Digital Circuits &

Systems Lab
(EC-407)

Ketan Sharma
82/EC/12

INDEX
S.N
o.
1a.
1b.
2.
3a.
3b.
3c.
4.
5.
6a.
6b.
7.
8.
9.
10.

Experiment
To design a 2x4 decoder in VHDL.
To design a 2x4 encoder in VHDL.
To design a 4-bit Binary to Gray code convertor.
To implement a Latch in VHDL.
To implement a Flip-Flop in VHDL.
To implement a Register in VHDL.
To implement a finite state machine in VHDL which
checks if the incoming sequence is divisible by five.
The sequence enters from the right (MSB first).
To implement a Traffic light controller in VHDL.
To implement a 3-bit binary counter in VHDL.
To implement a 2 digit BCD counter in VHDL.
To implement a 1x4 4-bit Data Demultiplexer in
VHDL. Data enters through a high-speed 4-bit input
port and is given into four 4-bit output lines.
To implement an 4-bit Serial-in-Parallel-out Shift
register in VHDL.
To implement a ALU unit in VHDL.
Characterisation of Logic Gates. Find out logic
threshold values & noise margins. Delay time
measurement of an Inverter using odd number of
inverting oscillators.

Signature

Experiment 1a
AIM: To design a 2x4 decoder in VHDL.
CODE:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity dec is
Port ( i : in STD_LOGIC_VECTOR (1 downto 0);
o : out STD_LOGIC_VECTOR (3 downto 0));
end dec;
architecture Behavioral of dec is
begin
process(i)
begin
case i is
when
when
when
when
when

"00" => o <= "0001";

"01" => o <= "0010";
"10" => o <= "0100";
"11" => o <= "1000";
others => o <= "0000";

end case;
end process;
end Behavioral;

OUTPUT:

Experiment 1b
AIM: To design a 2x4 Encoder in VHDL.
CODE:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity enc is
Port ( o : out STD_LOGIC_VECTOR (1 downto 0);
i : in STD_LOGIC_VECTOR (3 downto 0));
end enc;
architecture Behavioral of enc is
begin
process(i)
begin
if(i(0)='1') then o<="00";
elsif(i(1)='1') then o<="01";
elsif(i(2)='1') then o<="10";
elsif(i(3)='1') then o<="11";
end if;
end process;
end Behavioral;

OUTPUT:

Experiment 2
AIM: To design a 4-bit Binary to Gray Code convertor.
CODE:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity b2g is
Port ( o : out STD_LOGIC_VECTOR (2 downto 0);
i : in STD_LOGIC_VECTOR (2 downto 0));
end b2g;
architecture Behavioral of b2g is
begin
o(2) <= i(2);
o(1) <= i(2) xor i(1);
o(0) <= i(1) xor i(0);
end Behavioral;

OUTPUT:

Experiment 3a
AIM: To implement a Latch in VHDL.
CODE:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity latch is
Port ( o : out STD_LOGIC ;
i : in STD_LOGIC ;
clk : in STD_LOGIC;
rst : in STD_LOGIC);
end latch;
architecture Behavioral of latch is
begin
process(clk,i,rst)
begin
if(rst = '1') then
o<= '0';
elsif(clk = '1') then
o<=i;
end if;
end process;
end Behavioral;
OUTPUT:
6

Experiment 3b
AIM: To implement a Flip-Flop in VHDL.
CODE:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity dff is
Port ( q : out STD_LOGIC ;
q_nt : out STD_LOGIC;
d : in STD_LOGIC ;
clk : in STD_LOGIC;
rst : in STD_LOGIC);
end dff;
architecture Behavioral of dff is
begin
process(clk,d,rst)
begin
if(rst = '1') then
q<= '0';
q_nt<='1';
elsif(clk'event and clk = '1') then
q<=d;
q_nt<=not(d);
end if;
end process;
end Behavioral;

OUTPUT:
7

Experiment 3c
AIM: To implement a Register in VHDL.
CODE:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity reg is
Port ( o : inout STD_LOGIC_VECTOR (3 downto 0) ;
i : in STD_LOGIC ;
clk : in STD_LOGIC;
rst : in STD_LOGIC);
end reg;
architecture Behavioral of reg is
begin
process(clk,i,rst)
begin
if(rst = '1') then
o<= "0000";

elsif(clk'event and clk = '1') then

o(0) <= i;
o(1) <= o(0);
o(2) <= o(1);
o(3) <= o(2);
end if;
end process;
end Behavioral;

OUTPUT:

With synchronous reset:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity reg is
Port ( o : inout STD_LOGIC_VECTOR (3 downto 0) ;
i : in STD_LOGIC ;
clk : in STD_LOGIC;
rst : in STD_LOGIC);
end reg;
architecture Behavioral of reg is
begin
process(clk,i,rst)
begin

if(clk'event and clk = '1') then

if(rst = '1') then
o<= "0000";
else
o(0) <= i;
o(1) <= o(0);
o(2) <= o(1);
o(3) <= o(2);
end if;
end if;
end process;
10

end Behavioral;
OUTPUT:

Experiment 4

11

AIM: To implement a finite state machine in VHDL which checks if

the incoming sequence is divisible by five. The sequence enters
from the right (MSB first).
CODE:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity mod5fsm is
Port ( o : out STD_LOGIC ;
i : in STD_LOGIC ;
rst : in STD_LOGIC;
clk : in STD_LOGIC);
end mod5fsm;
architecture Behavioral of mod5fsm is
type state is (R0,R1,R2,R3,R4);
signal CS, NS: state;
begin
process(clk)
begin
if(rst = '1') then
CS<=R0;
elsif(clk='1' and clk'event) then
CS<=NS;
end if;
end process;
process(CS,i)
begin
case CS is
when R0 =>
o<= '1';
if(i='0') then
NS<=R0;
else
NS<=R1;
end if;

12

when R1=>
o <= '0';
if(i='0') then
NS<=R2;
else
NS<=R3;
end if;
when R2=>
o <= '0';
if(i='0') then
NS<=R4;
else
NS<=R0;
end if;
when R3=>
o <= '0';
if(i='0') then
NS<=R1;
else
NS<=R2;
end if;
when R4=>
o <= '0';
if(i='0') then
NS<=R3;
else
NS<=R4;
end if;
end case;

end process;
end Behavioral;
OUTPUT:

13

Experiment 5
AIM: To implement a Traffic light controller in VHDL.
14

CODE:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity traffic is
Port ( rst : in STD_LOGIC;
clk : in STD_LOGIC;
o : out STD_LOGIC_VECTOR (5 downto 0));
end traffic;
architecture Behavioral of traffic is
type state_type is (S0,S1,S2,S3);
signal state: state_type;
signal count: STD_LOGIC_VECTOR (3 downto 0):= "0000";
constant SEC1: STD_LOGIC_VECTOR (3 downto 0):= "0011";
constant SEC5: STD_LOGIC_VECTOR (3 downto 0):= "1111";
begin
process(clk,rst)
begin
if(rst = '1') then
state<=S0;
count<=X"0";
elsif(clk='1' and clk'event) then
case state is
when S0 =>
if count<SEC5 then
count <= count + 1;
else
state<=S1;
count<=X"0";
end if;
when S1=>
if count<SEC1 then
count<=count+1;
else
state<=S2;
15

count<=X"0";
end if;
when S2=>
if count<SEC5 then
count<= count+1;
else
state<=S3;
count<=X"0";
end if;
when S3=>
if count<SEC1 then
count<=count+1;
else
state<=S0;
count<=X"0";
end if;
end case;
end if;
end process;
process(state)
begin
case state is
when S0 =>
o <= "100001";
when S1 =>
o <= "110010";
when S2 =>
o <= "001100";
when S3 =>
o <= "010110";
end case;
end process;
end Behavioral;

16

OUTPUT:

Experiment 6a
AIM: To implement a 3-bit binary counter in VHDL.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

17

entity bin_cnt is
Port ( rst : in STD_LOGIC;
clk : in STD_LOGIC;
i : in STD_LOGIC;
o : out STD_LOGIC_VECTOR (2 downto 0));
end bin_cnt;
architecture Behavioral of bin_cnt is
type state_type is (S0,S1,S2,S3,S4,S5,S6,S7);
signal CS, NS: state_type;
--signal count: STD_LOGIC_VECTOR (3 downto 0):= "000";
begin
process(clk,rst)
begin
if(rst = '1') then
CS<=S0;
--count<="000";
elsif(clk='1' and clk'event) then
CS<=NS;
end if;
end process;
process(CS,i)
begin
case CS is
when S0 =>
o <= "000";
if i='1' then
NS<=S1;
else
NS<=S0;
end if;
when S1=>
o<="001";
if i='1' then
NS<=S2;
else
NS<=S1;
end if;
when S2=>
18

o<="010";
if i='1' then
NS<=S3;
else
NS<=S2;
end if;
when S3=>
o<="011";
if i='1' then
NS<=S4;
else
NS<=S3;
end if;
when S4=>
o<="100";
if i='1' then
NS<=S5;
else
NS<=S4;
end if;
when S5=>
o<="101";
if i='1' then
NS<=S6;
else
NS<=S5;
end if;
when S6=>
o<="110";
if i='1' then
NS<=S7;
else
NS<=S6;
end if;
when S7=>
o<="111";
if i='1' then
NS<=S0;
19

else
NS<=S7;
end if;
end case;
end process;
end Behavioral;
CODE:

20

OUTPUT:

Experiment 6b
AIM: To implement a 2-digit BCD counter in VHDL.
CODE:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity bcd is
Port ( rst : in STD_LOGIC;
clk : in STD_LOGIC;
i : in STD_LOGIC;
o1 : out STD_LOGIC_VECTOR (3 downto 0);
o2 : inout STD_LOGIC_VECTOR (3 downto 0):="0000");
end bcd;
architecture Behavioral of bcd is
type state_type is (S0,S1,S2,S3,S4,S5,S6,S7,S8,S9);
signal CS, NS: state_type;
signal i2: STD_LOGIC;
--signal count: STD_LOGIC_VECTOR (3 downto 0):= "000";
begin
process(clk,rst)
begin
if(rst = '1') then
CS<=S0;
--i2<='0';
--count<="000";
elsif(clk='1' and clk'event) then
CS<=NS;
end if;
end process;
process(CS,i)
begin
case CS is

21

when S0 =>
o1 <= "0000";
if(i2 = '1') then
if(o2<"1001") then
o2<=o2+1;
else
o2<="0000";
i2<='0';
end if;
end if;
if i='1' then
NS<=S1;
else
NS<=S0;
end if;
when S1=>
o1<="0001";
if i='1' then
NS<=S2;
else
NS<=S1;
end if;
when S2=>
o1<="0010";
if i='1' then
NS<=S3;
else
NS<=S2;
end if;
when S3=>
o1<="0011";
if i='1' then
NS<=S4;
else
NS<=S3;
end if;
when S4=>
o1<="0100";
if i='1' then
NS<=S5;
22

else
NS<=S4;
end if;
when S5=>
o1<="0101";
if i='1' then
NS<=S6;
else
NS<=S5;
end if;
when S6=>
o1<="0110";
if i='1' then
NS<=S7;
else
NS<=S6;
end if;
when S7=>
o1<="0111";
if i='1' then
NS<=S8;
else
NS<=S7;
end if;
when S8=>
o1<="1000";
if i='1' then
NS<=S9;
else
NS<=S8;
end if;
when S9=>
o1<="1001";
if i='1' then
i2 <= '1';
NS<=S0;
else
NS<=S9;
end if;
end case;
23

end process;
end Behavioral;

OUTPUT:

Experiment 7
24

AIM: To implement a 1x4 4-bit Data Demultiplexer in VHDL. Data

enters through a high-speed 4-bit input port and is given into
three 4-bit output lines.
CODE:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity demux is
Port ( rst : in STD_LOGIC;
clk : in STD_LOGIC;
i : in STD_LOGIC_VECTOR (3 downto 0);
--sel: in STD_LOGIC_VECTOR (1 downto 0);
o1 : out STD_LOGIC_VECTOR (3 downto 0);
o2 : out STD_LOGIC_VECTOR (3 downto 0);
o3 : inout STD_LOGIC_VECTOR (3 downto 0));
end demux;
architecture Behavioral of demux is
signal sel: STD_LOGIC_VECTOR (1 downto 0):="00";
begin
process(rst,clk)
variable tem1,tem2,tem3: STD_LOGIC_VECTOR (3 downto 0):="0000";
begin
if(rst = '1') then
o1<="0000";
o2<="0000";
o3<="0000";
sel<="00";
elsif(clk'event and clk = '1') then
case sel is
when "00" =>
tem1:=i;
o1<=i;
o2<=tem3;
o3<=tem2;
sel<=sel+1;
when "01" =>
tem2:=i;
o1<=tem2;
o2<=tem1;
25

o3<=tem3;
sel<=sel+1;
when others =>
tem3:=i;
o1<=tem3;
o2<=tem2;
o3<=tem1;
sel<="00";
end case;
end if;
end process;
end Behavioral;

OUTPUT:

Experiment 8
AIM: To implement an 4-bit Serial-in-Parallel-out Shift register in
VHDL.
26

CODE:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity reg is
Port ( o : inout STD_LOGIC_VECTOR (3 downto 0) ;
i : in STD_LOGIC ;
clk : in STD_LOGIC;
rst : in STD_LOGIC);
end reg;
architecture Behavioral of reg is
begin
process(clk,i,rst)
begin
if(rst = '1') then
o<= "0000";

elsif(clk'event and clk = '1') then

o(0) <= i;
o(1) <= o(0);
o(2) <= o(1);
o(3) <= o(2);
end if;
end process;
end Behavioral;

OUTPUT:

27

Experiment 9
AIM: To implement a ALU unit in VHDL.
CODE:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity alu1 is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
28

c : in STD_LOGIC;
co: out STD_LOGIC;
s : in STD_LOGIC_VECTOR (2 downto 0);
F : out STD_LOGIC);
end alu1;
architecture Behavioral of alu1 is
signal D: STD_LOGIC;
signal E: STD_LOGIC;
signal MD: STD_LOGIC;
begin
process(a,b,c,s)
begin
case s is
when "000" =>
MD<=b;
when "001" =>
MD <= not(b);
when "010" =>
MD <= '0';
when "011" =>
MD<='1';
----------when "100" =>
E<= a and b;
when "101" =>
E<= a or b;
when "110" =>
E<= a xor b;
when "111" =>
E<= not(a);
when others =>
E<='0';
----------end case;
end process;
process(E,MD)
29

begin
if s(2) = '0' then
D<=(a xor MD) xor c;
co<= (a and(MD or c)) or (MD and c);
F<=D;
else
F<=E;
end if;
end process;

end Behavioral;
end Behavioral;

OUTPUT:

Experiment 10
AIM: Characterization of Logic Gates. Find out threshold values & noise
margins. Delay time measurements of an inverter using odd number of
inverting oscillators. Fosc =1/(2nd); d is the inverter delay, n is the number
of inverter (need to be odd number) and Fosc is the resultant frequency of
operation. Measure Fosc and estimate d.
COMPONENTS:
IC7404 (Two), Bread Board, Digital Circuit Kit, Connecting Wires, DSO, Probes.

THEORY (Delay Time):

For any digital circuit as the number of gates n increases a delay is introduced in
the circuit.
Here, inverter circuits have been added in series to determine the delay in the
circuit.
The working equation is:
30

Fosc =1/(2nd)
PROCEDURE (Delay Time):
1. Place IC7404 on the bread board of the digital training kit.
2. Do necessary connections as per the circuit diagram & switch ON the
trainer.
3. Connect output of inverter to a DSO.
4. Measure time period of oscillation of the output wave.
5. Repeat above steps for the number of inverters as 3, 5 & 7.
6. Tabulate the readings and get the results.

THEORY (Logic Threshold Value):

For finding out the logic threshold values and the noise margins, we need to find
the transfer function of the inverter gates. The characteristics of inverter gives
the three regions, one is the logic HIGH for low values of input and a transition
state that has a steep slope. The difference in the level of +5V and the point of
slope in the noise margin for high.
There are two values of noise margin specified for a given logic circuit: the HIGH
level noise margin (VNH) and the low level noise margin (VNL). These parameters
are defined by the following equations:

VNH = VOH (min) VIH (min)

VNL = VIL (max) VOL (max)
PROCEDURE (Logic Threshold Value):
1. Place IC7404 on the bread board, do the necessary connections and switch
ON the trainer.
2. Using a multi-meter measure the input and output voltage values and
record in the table.
3. Vary the potentiometer from 0V to +5V. Record the input and the output
voltages.
4. Draw the graph using values in the table.
5. Measure logic threshold values & noise margins using the graph.

OBSERVATIONS & CALCULATIONS:

For Delay Time:
S.
No.

No. Of Inverters

Time Period
(ns)

Time Delay
(ns)

1.
2.
3.

3
5
7

62.5
104.29
146.1

10.42
10.43
10.43

For Logic Threshold Value:

S. No.

Vin (V)

Vo (V)
31

1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.

0.08 mV
73 mV
0.5
1.0
1.15
1.30
1.50
2.00
2.50
3.00
3.50
4.00
4.50
5.00

4.95
4.94
4.9
4.75
4.6
4.3
3.35
1.05
25 mV
12 mV
8.2 mV
6.8 mV
6.7 mV
6.6 mV

32