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A comparison between single data rate, double data rate, and quad data rate.
In computing, a computer bus operating with double data rate (DDR) transfers data on both the
rising and falling edges of the clock signal.[1][page needed] This is also known as double pumped, dualpumped, anddouble transition. The term toggle mode is used in the context of NAND flash
memory.
The simplest way to design a clocked electronic circuit is to make it perform one transfer per full
cycle (rise and fall) of a clock signal. This, however, requires that the clock signal changes twice per
transfer, while the data lines change at most once per transfer. When operating at a high
bandwidth, signal integrity limitations constrain the clock frequency. By using both edges of the
clock, the data signals operate with the same limiting frequency, thereby doubling the data
transmission rate.
This technique has been used for microprocessor front side busses, Ultra-3 SCSI, graphics RAM
(the AGP bus and GDDR), main memory (both RDRAM and DDR1 through DDR4), and
the HyperTransport bus onAMD's Athlon 64 processors. It is more recently being used for other
systems with high data transfer speed requirements as an example, for the output of analog-todigital converters (ADCs).[2]
DDR should not be confused with dual channel, in which each memory channel accesses two RAM
modules simultaneously. The two technologies are independent of each other and many
motherboards use both, by using DDR memory in a dual channel configuration.
An alternative to double or quad pumping is to make the link self-clocking. This tactic was chosen
by InfiniBand and PCI Express.
Memory Clock
Transfer Rate
Theoretical Bandwidth
DDR-200, PC-1600
100 MHz
100 MHz
0.2 GT/s
1.6 GB/s
DDR2-800, PC2-6400
200 MHz
400 MHz
0.8 GT/s
6.4 GB/s
DDR3-1600, PC3-12800
200 MHz
800 MHz
1.6 GT/s
12.8 GB/s
DDR4-3200, PC4-25600
400 MHz
1600 MHz
3.2 GT/s
25.6 GB/s
DDR SDRAM uses double-data-rate signalling only on the data lines. Address and control signals
are still sent to the DRAM once per clock cycle (to be precise, on the rising edge of the clock), and
timing parameters such as CAS latency are specified in clock cycles. Some less common DRAM
interfaces, notably LPDDR2, GDDR5 and XDR DRAM, send commands and addresses using
double data rate.
References[edit]
1.
2.
See also[edit]
Categories:
Digital electronics
Clock signal
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