Beruflich Dokumente
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OCTAL BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCLS269O DECEMBER 1995 REVISED JULY 2003
SN54AHCT541 . . . J OR W PACKAGE
SN74AHCT541 . . . DB, DGV, DW, N, NS, OR PW PACKAGE
(TOP VIEW)
OE1
A1
A2
A3
A4
A5
A6
A7
A8
GND
description/ordering information
The AHCT541 octal buffers/drivers are ideal for
driving bus lines or buffer memory address
registers. These devices feature inputs and
outputs on opposite sides of the package to
facilitate printed circuit board layout.
20
19
18
17
16
15
14
13
12
10
11
VCC
OE2
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
SN54AHCT541 . . . FK PACKAGE
(TOP VIEW)
A2
A1
OE1
VCC
A3
A4
A5
A6
A7
3 2 1 20 19
18
17
16
15
14
9 10 11 12 13
Y1
Y2
Y3
Y4
Y5
A8
GND
Y8
Y7
Y6
OE2
D
D
ORDERING INFORMATION
PDIP N
SN74AHCT541N
Tube
SN74AHCT541DW
SN74AHCT541DWR
SOP NS
SN74AHCT541NSR
AHCT541
SSOP DB
SN74AHCT541DBR
HB541
Tube
SN74AHCT541PW
SN74AHCT541PWR
TVSOP DGV
SN74AHCT541DGVR
HB541
CDIP J
Tube
SNJ54AHCT541J
SNJ54AHCT541J
CFP W
Tube
SNJ54AHCT541W
SNJ54AHCT541W
LCCC FK
Tube
SNJ54AHCT541FK
SNJ54AHCT541FK
TSSOP PW
55C to 125C
TOP-SIDE
MARKING
Tube
SOIC DW
40C to 85C
40C
ORDERABLE
PART NUMBER
PACKAGE
TA
SN74AHCT541N
AHCT541
HB541
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines
are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2003, Texas Instruments Incorporated
SN54AHCT541, SN74AHCT541
OCTAL BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCLS269O DECEMBER 1995 REVISED JULY 2003
FUNCTION TABLE
(each buffer/driver)
INPUTS
A
OUTPUT
Y
OE1
OE2
A1
1
19
18
Y1
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 7 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 7 V
Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to VCC + 0.5 V
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 mA
Package thermal impedance, JA (see Note 2): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70C/W
DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92C/W
DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58C/W
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69C/W
NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60C/W
PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65C to 150C
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
SN54AHCT541, SN74AHCT541
OCTAL BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCLS269O DECEMBER 1995 REVISED JULY 2003
SN74AHCT541
MIN
MAX
MIN
MAX
4.5
5.5
4.5
5.5
UNIT
VCC
VIH
Supply voltage
VIL
VI
0.8
Input voltage
5.5
5.5
VO
IOH
Output voltage
VCC
8
VCC
8
mA
IOL
t/v
mA
20
20
ns/V
2
0.8
V
V
TA
Operating free-air temperature
55
125
40
85
C
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
TEST CONDITIONS
VCC
VOH
IOH = 50 mA
IOH = 8 mA
45V
4.5
VOL
IOL = 50 mA
IOL = 8 mA
45V
4.5
II
IOZ
VI = 5.5 V or GND
VO = VCC or GND
ICC
VI = VCC or GND,
IO = 0
One input at 3.4 V,
Other inputs at VCC or GND
ICC
Ci
VI = VCC or GND
VO = VCC or GND
MIN
4.4
TA = 25C
TYP
MAX
4.5
3.94
SN54AHCT541
MIN
MAX
SN74AHCT541
MIN
4.4
4.4
3.8
3.8
MAX
UNIT
V
0.1
0.1
0.1
0.36
0.44
0.44
0 V to 5.5 V
0.1
1*
mA
5.5 V
0.25
2.5
2.5
mA
5.5 V
40
40
mA
5.5 V
1.35
1.5
1.5
mA
10
pF
5V
10
Co
5V
4
* On products compliant to MIL-PRF-38535, this parameter is not production tested at VCC = 0 V.
This is the increase in supply current for each input at one of the specified TTL voltage levels, rather than 0 V or VCC.
pF
SN54AHCT541, SN74AHCT541
OCTAL BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCLS269O DECEMBER 1995 REVISED JULY 2003
FROM
(INPUT)
TO
(OUTPUT)
LOAD
CAPACITANCE
tPLH
tPHL
CL = 15 pF
tPZH
tPZL
OE
CL = 15 pF
tPHZ
tPLZ
OE
CL = 15 pF
tPLH
tPHL
CL = 50 pF
tPZH
tPZL
OE
CL = 50 pF
tPHZ
tPLZ
OE
CL = 50 pF
MIN
TA = 25C
TYP
MAX
SN54AHCT541
SN74AHCT541
MIN
MAX
MIN
MAX
4.1*
6*
1*
6.5*
6.5
3.7*
5.5*
1*
6.5*
6.5
5*
7*
1*
8*
5*
7*
1*
8*
4.5*
7*
1*
8*
4.5*
7*
1*
8*
6.2
8.5
9.5
9.5
8.5
9.5
9.5
7.5
10
12
12
7.5
10
12
12
10
12
12
10
12
12
tsk(o)
CL = 50 pF
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
** On products compliant to MIL-PRF-38535, this parameter does not apply.
1**
UNIT
ns
ns
ns
ns
ns
ns
ns
TEST CONDITIONS
No load,
f = 1 MHz
TYP
12
UNIT
pF
SN54AHCT541, SN74AHCT541
OCTAL BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCLS269O DECEMBER 1995 REVISED JULY 2003
From Output
Under Test
RL = 1 k
From Output
Under Test
Test
Point
S1
VCC
Open
TEST
GND
CL
(see Note A)
CL
(see Note A)
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open Drain
Open
VCC
GND
VCC
3V
1.5 V
Timing Input
0V
tw
3V
1.5 V
Input
1.5 V
th
tsu
3V
1.5 V
Data Input
1.5 V
0V
0V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
3V
1.5 V
Input
1.5 V
0V
tPLH
In-Phase
Output
tPHL
50% VCC
tPHL
Out-of-Phase
Output
VOH
50% VCC
VOL
Output
Waveform 1
S1 at VCC
(see Note B)
VOH
50% VCC
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
1.5 V
1.5 V
0V
tPZL
tPLZ
VCC
50% VCC
tPZH
tPLH
50% VCC
3V
Output
Control
Output
Waveform 2
S1 at GND
(see Note B)
VOL + 0.3 V
VOL
tPHZ
50% VCC
VOH 0.3 V
VOH
0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
26-Sep-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
5962-9685801Q2A
ACTIVE
LCCC
FK
20
TBD
Call TI
Level-NC-NC-NC
5962-9685801QRA
ACTIVE
CDIP
20
TBD
Call TI
Level-NC-NC-NC
TBD
Call TI
Level-NC-NC-NC
TBD
Call TI
Call TI
Lead/Ball Finish
5962-9685801QSA
ACTIVE
CFP
20
SN74AHCT541DBLE
OBSOLETE
SSOP
DB
20
SN74AHCT541DBR
ACTIVE
SSOP
DB
20
CU NIPDAU
Level-1-260C-UNLIM
SN74AHCT541DBRE4
ACTIVE
SSOP
DB
20
CU NIPDAU
Level-1-260C-UNLIM
SN74AHCT541DW
ACTIVE
SOIC
DW
20
25
CU NIPDAU
Level-1-260C-UNLIM
SN74AHCT541DWE4
ACTIVE
SOIC
DW
20
25
CU NIPDAU
Level-1-260C-UNLIM
SN74AHCT541DWR
ACTIVE
SOIC
DW
20
CU NIPDAU
Level-1-260C-UNLIM
SN74AHCT541DWRE4
ACTIVE
SOIC
DW
20
CU NIPDAU
Level-1-260C-UNLIM
SN74AHCT541N
ACTIVE
PDIP
20
20
Pb-Free
(RoHS)
CU NIPDAU
Level-NC-NC-NC
SN74AHCT541NE4
ACTIVE
PDIP
20
20
Pb-Free
(RoHS)
CU NIPDAU
Level-NC-NC-NC
SN74AHCT541NSR
ACTIVE
SO
NS
20
CU NIPDAU
Level-1-260C-UNLIM
SN74AHCT541NSRE4
ACTIVE
SO
NS
20
CU NIPDAU
Level-1-260C-UNLIM
SN74AHCT541PW
ACTIVE
TSSOP
PW
20
70
CU NIPDAU
Level-1-260C-UNLIM
SN74AHCT541PWE4
ACTIVE
TSSOP
PW
20
70
CU NIPDAU
Level-1-260C-UNLIM
SN74AHCT541PWLE
OBSOLETE
TSSOP
PW
20
TBD
Call TI
SN74AHCT541PWR
ACTIVE
TSSOP
PW
20
CU NIPDAU
Level-1-260C-UNLIM
SN74AHCT541PWRE4
ACTIVE
TSSOP
PW
20
CU NIPDAU
Level-1-260C-UNLIM
SN74AHCT541PWRG4
ACTIVE
TSSOP
PW
20
CU NIPDAU
Level-1-260C-UNLIM
SNJ54AHCT541FK
ACTIVE
LCCC
FK
20
TBD
Call TI
Level-NC-NC-NC
SNJ54AHCT541J
ACTIVE
CDIP
20
TBD
Call TI
Level-NC-NC-NC
SNJ54AHCT541W
ACTIVE
CFP
20
TBD
Call TI
Level-NC-NC-NC
Call TI
(1)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS &
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Addendum-Page 1
no
Sb/Br)
please
check
26-Sep-2005
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
MECHANICAL DATA
MLCC006B OCTOBER 1996
FK (S-CQCC-N**)
28 TERMINAL SHOWN
18
17
16
15
14
13
NO. OF
TERMINALS
**
12
19
11
20
10
MIN
MAX
MIN
MAX
20
0.342
(8,69)
0.358
(9,09)
0.307
(7,80)
0.358
(9,09)
28
0.442
(11,23)
0.458
(11,63)
0.406
(10,31)
0.458
(11,63)
21
22
44
0.640
(16,26)
0.660
(16,76)
0.495
(12,58)
0.560
(14,22)
23
52
0.739
(18,78)
0.761
(19,32)
0.495
(12,58)
0.560
(14,22)
24
6
68
0.938
(23,83)
0.962
(24,43)
0.850
(21,6)
0.858
(21,8)
84
1.141
(28,99)
1.165
(29,59)
1.047
(26,6)
1.063
(27,0)
B SQ
A SQ
25
26
27
28
4
0.080 (2,03)
0.064 (1,63)
0.020 (0,51)
0.010 (0,25)
0.020 (0,51)
0.010 (0,25)
0.055 (1,40)
0.045 (1,14)
0.045 (1,14)
0.035 (0,89)
0.045 (1,14)
0.035 (0,89)
0.028 (0,71)
0.022 (0,54)
0.050 (1,27)
4040140 / D 10/96
NOTES: A.
B.
C.
D.
E.
MECHANICAL DATA
MSSO002E JANUARY 1995 REVISED DECEMBER 2001
DB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
28 PINS SHOWN
0,38
0,22
0,65
28
0,15 M
15
0,25
0,09
8,20
7,40
5,60
5,00
Gage Plane
1
14
0,25
08
0,95
0,55
Seating Plane
2,00 MAX
0,10
0,05 MIN
PINS **
14
16
20
24
28
30
38
A MAX
6,50
6,50
7,50
8,50
10,50
10,50
12,90
A MIN
5,90
5,90
6,90
7,90
9,90
9,90
12,30
DIM
4040065 /E 12/01
NOTES: A.
B.
C.
D.
MECHANICAL DATA
MTSS001C JANUARY 1995 REVISED FEBRUARY 1999
PW (R-PDSO-G**)
14 PINS SHOWN
0,30
0,19
0,65
14
0,10 M
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
7
0 8
A
0,75
0,50
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,10
14
16
20
24
28
A MAX
3,10
5,10
5,10
6,60
7,90
9,80
A MIN
2,90
4,90
4,90
6,40
7,70
9,60
DIM
4040064/F 01/97
NOTES: A.
B.
C.
D.
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