A HIGH DATA TRANSFER RATE FREQUENCY SHIFT KEYING

DEMODULATOR CHIP FOR THE WIRELESS BIOMEDICAL IMPLANTS

Mavsam Ghovanloo and Khalil Najafi
Center for Wireless Integrated Microsystems

University of Michigan, 1301 Beal Ave., Ann Arbor, Michigan 48109-2122, USA
Tel: (734) 763-6650, Fax: (734) 763-9324, maysamgh@,engin.umich.edu
ABSTRACT

So far, the amplitude shifl keying (ASK) data modulation

technique has been commonly used in the biomedical implants
because of its fairly simple modulation .and demodulation
circuitry However this method faces major limitations for high
bandwidth data transfer. Therefore, a novel high-rate data
transfer protocol and demodulator circuit has been proposed
based on the frequency shift keying (FSK) data modulation
technique for wirelessly operating the University of Michigan
micromachined 3D stimulating microprobes [I], shown in Fig. I ,
which are targeted at a 1024-site wireless stimulating
microsystem for visual and auditory prosthesis.

This paper describes a high-rate frequency shift keying

(FSK) data transfer protocol and demodulator circuit for
wirelessly operating biomedical implants in need of data transfer
rates above IMbitiSec. The demodulator circuit receives the
serial data bit stream from an FSK carrier signal in 2-2OMHz
range, which is used to power the implant through inductive
coupling. The circuitry has been desimed and fabricated in the
University of Michigans single metal, dual-poly 3-LIm CMOS
process and has been tested fully functional.

1. INTRODUCTION
Wireless operation is required for must of the biomedical
implantable circuits and many other emerging MEMS
applications to improve safety and enable stand-alone operation
for an unlimited time period. Many of these devices are powered
by inductive coupling in the centimeter range distance over the
skin barrier. Tne most convenient way to transfer data to these
devices is to combine it with the electromagnetic power carrier
signal. Some of the biomedical implants, particularly those who
are interfacing with the central nervous system like cochlear
implants, need to transfer large amount of data for real-time
signal processing and high quality sound perception. The visual
implant is another example, which needs even higher data rates
for transferring images with minimum reasonable resolution.
Therefore, a high data transfer rate interface circuitry that can
establish an efficient wireless link between the implant and the
external units is highly needed.

The FSK is one of the most useful modulation techniques

for digital communication, which simply means sending binary
data with two frequencies& andf,, representing digital 0 and
1 respectively. The resultant modulated signal can he regarded
as the sum oftwo amplitude modulated (AM) signals of different
carrier frequencies as shown in Fig. 2a:

/ ( 1 ) = ~ ~ ( t ) s i n ( 2 ~ ~ ~ + 8 ) + ~ ~ ( t ) s i n ((1)2 ~ ~ ~ + ~ )
!n the frequency domain, the signal power is centered at two
carrier frequencies,fo andf,, as shown in Fig. 2b. Since/o(tj and
f,(r) can have the same amplitude, an excellent characteristic of
the FSK modulation for wireless biomedical implants, which
should be powered as well as communicated with the same
electromagnetic field is that the transmitted power is always
constant at its maximum level irrespective of& andfi or the data
contents:

DigitalSigna

(b) Frequency Domain

Fig. 1 A 3D probe array of256 stimulating sites.

0-7803-7523-8/02/$I7.00 02002 lEEE

Fig. 1 Frequency shifl keying in time and frequency domains.

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This is a major advantage over the amplitude shift keyed (ASK)

signals where data bits can alter power transfer efficiency
parricularly when the modulation index is high as in suspended
carrier modulation [2].
Another difference between the FSK and ASK is that in the
ASK data transmission; the receiver tank circuit frequency
response should have a very high quality factor (Q),centered at
the carrier frequency to get enough amplitude variation for data
detection. However, in the FSK data transmission, the pass band
should be centered between fa and fi with a low Q to pass enough
power of both carrier frequencies. This is an advantage for the
FSK technique because in the biomedical implants application,
the quality factor of the receiver coil is generally low particularly
when the implant receiver coil is integrated and its high
resistivity is unavoidable [3].

f,

(a) PDFSK

Synchronization of the receiver with the transmitter is easier

though in the ASK systems. Because the receiver internal clock
signal can be directly derived by stepping down the constant
transmitter carrier frequency [4,5]. However, in the FSK data
transfer, the internal clock with constant frequency should be
derived from a combination of the two carrier frequencies
and
6)based on the data transfer protocol or synchronization
patterns.

vn

2. THE FSK DATA TRANSFER

PROTOCOL
The data rate in digital communication, so called FSK rate,
is hundreds oftimes slower thanf, or/,. This cannot he the case
if we want to surpass IMbiVSec baud rate in the wireless
biomedical implants where the carrier frequency is limited to tens
of MHz because of the incremental tissue loss and risk of tissue
damage at higher frequencies. For this kind of applications,
every dozen of carrier cycles should transfer at least one or even
more bits of data. Therefore a new method was devised for the
FSK data transfer with the FSK rate as high as fiwith j o twice as
f,. In this method, the digital bit I is transmitted by a single
cycle of the carrier/, and the digital bit 0 is transmitted by two
cycles of the carrier fo as shown in Fig. 2a. This leads to a
consistent data transfer rate of fi bits/Sec. The transminer
frequency switches at a small fraction of a cycle and only at zero
crossings. Obviously, any odd number of consecutive fa cycles
in this protocol is an indication of data transfer error.

3. DIFERRENTIAL FSK DEMODULATOR

The data detection technique used here for the FSK
demodulation is based on measuring the period of each received
carrier cycle. If the period is higher than a certain value, a digital
I bit is detected and otherwise a digital 0 is received. A
simple method for time measurement is charging a capacitor with
a constant current source and monitoring its voltage. Charging
and discharging of this capacitor should be synchronized with the
FSK carrier signal. If the capacitor voltage is higher than a
certain value, a digital 1 hit is detected and otherwise a digital
0 is received. This comparison can be done in two ways:
I- Fully differential FSK demodulator (FDFSK): Charging two
unequal capacitors with different currents and compare their
voltages with a hysteresis comparator as shown in Fig. 3a. This

(b) R D m K

Fig. 3 The FSK data detection techniques: (a) Fully Differential

FSK (b) Referenced Differential FSK.
is like comparing two capacitive timers with different time
constants.
2- Referenced differential FSK demodulator (RDFSK):
Generating a reference voltage and comparing it with a charging
capacitor voltage as shown in Fig.3b.

The FDFSK method is more robust against process

To
variations in expense of more power consumption.
experiment and compare both methods, we desigmd a circuit
based on the RDFSK method in the AMI 1Spm CMOS process
through the M O S S foundry. Another prototEe chip was
designed based on the FDFSK method, which is the main focus
of this paper and implemented in the UofM 3pm CMOS process
as shown in Fig. 4.
Fig. 5 shows a simplified schematic diagram of the FDFSK
demodulator. Both current sources and switches are controlled
by the input clock signal (CK.), which is directlyrecovered from
the FSK carrier by the clock recovery block. The clock recovery
circuit is a cross-coupled differential pair, which is directly
connected to the receiver coil and turns the sinusoidal FSK
carrier signal into a similar square waveform. When CK,, is low,
SL and SH switches are open and SLC and SHCare closed.
Therefore, the current sources lLand IH linearly charge CLand CH
up to VL and VH respectively. During a digital I long cycle,

Fig. 4 The FDFSK prototype chip and its floor plan

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a
Fig. 5 The FDFSK data detector simplified schematic diagram.
VLI and VHIare twice as V,O and VHOwhen a digital 0 short
cycle is being received because in our FSK protocol in Fig. 2, TI
is twice as To. A hesteresis comparator compares capacitor
voltages. The hysteresis window width, Why,,,is set somewhere
between VH,-VL,,andVHO-VLO.
Therefore, the comparator output
switches to highduring a digital 1 long cycle but not during a
distal 0 shoti cycle. SL and SH switches discharge the
capacitors in a fraction of the FSK 2& half cycle, when CK, is
high; meanwhile SU, and SHCswitches open to reduce power
consumption. CK, also resets the hysteresis comparator to
prepare it for dktecting the type of the next cycle.
The output of the FDFSK data detector circuit is only a
pulse, which discriminates between long and short FSK carrier
cycles, so it cannot be directly regarded as the received data bit
stream. These pulses are fed into a digital block along with CK,
to generate the serial data output (VOUT) and a constant
frequency output clock ( C L J .
Fig.6 shows the schematic
diagram of the digital block. On every rising edge of the CK,, a
2-bit shift register shifts in the data-detector block output. Every
2 successive short cycles should be regarded as a 0 bit on
DOUT and every single long cycle indicates a 1 bit. Any odd
number of short cycles is an indication of error according to the
FSK protocoland activates the error output signal. To generate a
constant frequency clock, a T flip-flop indicates the number of
successive zeros and another T flip-flop toggles an every long
CKj. cycle or two successive short CK,, cycles.

4. SIMULATION AND MEASUREMENT

RESULTS
To check the performance of the FDFSK demodulator, postlayout simulation was performed with choosing& andjo to be
2.5MHz and 5MHz respectively. The data hit stream of

-error
vout

ckout
Fig. 6 The FDFSK digital block schematic diagram.

n.nsUx 1

(b)
Fig. 7 The FDFSK data detector simulated waveforms.
001001 110101 changes to 000010000111001001 when it is
encoded to the FSK data transfer protocol. To test the error
detection circuitry two single zeros are added before the 121h and
I S h bits and finally a bit stream of0000100001 IQlOOlO0Ql is
fed into the FDFSK demodulator CK, input. Fig. 7a shows the
resulting simulation waveforms. From top to bottom, trace-I
shows the FSK detector output pulses, which indicate long period
pulses (2.5MHz) of the bottom trace, CK,. The inserted error
bits have been detected at t=3.2ks and t=5ps and shown on the
3rd trace. Ile constant frequency clock (CL,,) and data
(VOUT) outputs are shown on the 4Ih and 5h traces respectively.
Both rising and falling edges of the CG., indicate received data
bits on VOUT, which shows the original bit stream of
0010011lO101 without any errors. Fig. 7b shows CH and CL
capacitor voltages in a scaled portion of the simulation
waveforms.
The data detector, clock regenerator, and digital blocks were
tested both individually and together as an FSK data demodulator
chip. All of these circuits were functioning as expected from the
simulations up to IOOKbitisec, which was the highest FSK
modulation rate of our signal generator. Fig. 8 shows some of
the measured waveforms, whilefi andfo are set equal to lMHz
and 2MHz respectively. The lower trace in all sections is the
regenerated clock input (CK,). The upper traces in Fig. 8a and
8b are CL and CH capacitor voltages respectively. Fig. 8c shows
the FSK data detector output pulses which discriminates between
IMHz and 2MHz carrier cycles. The final demodulated data bit

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stream at IOOKbitkec is shown in Fig. 8d. Table 1 summarizes

some of the specifications of the FDFSK demodulator chip.

5. CONCLUSION

TABLE 1
SPECIFICATIONS OF THE FDFSK DEMODULATOR CHIP

Process technology
Die size

1 Uofh4 CMOS 3

~ m

I2mmx2mm

We have developed a high-rate FSK data transfer protocol

and demodulator circuit for wirelessly operating the University

I, and I.
Supply voltage

I 2OuA and 33uA

5v

7. REFERENCES
M. G. Gingench, J. F. Hetke, D. J. Anderson, and K. 0.
Wise, A 256-site 3 0 CMOS microelectrode anay for
multipoint stimulation and recording in the central nervous
system, The 11 International Conference on Solid-State
Sensors and Actuators (Transducers Ol), pp. 416419 June
2001.
P. R. Troyk and M. Edington, Inductive links and drivers
for remotely-powered telemetry systems, A n t e n n a arid
Propagarion Symposium, Volume 1, pp. 60-62,2000,
1. A. Von A r x and K. Najafi, On-chip coils with integrated
cores for remote inductive powering of integrated
microsystems, Transducers 97, pp.999-1002, lune 1997.
M . Ghovanloo, K. Beach, K. D. Wise, and K. Najafi, A
BiCMOS wirelcss interface chip for micromachined
stimulating microprobes, IEEE-EMBS Special Topic
ConJerence on Microtechnologies in Medicine and Biology
proceedings, pp 277-282, Madison-Wisconsin, May 2002
M. Ghovanloo and K. Najafi, Fully integrated power
supply design for wireless biomedical implants, IEEEEMBS Special Topic Conference on Microtechnologier in
Medicine and Biology proceedings, pp 414419, MadisonWisconsin, May 2002

Fig. 8 The prototype FDFSK measured waveforms withfi and

fo equal 10 lMHz and 2MHz respectively. (a) Larger capacitor,

CL, voltage, (b) Smaller capacitor, CH, voltage, (c) The FSK
data detector output, (d) The FSK demodulated data output

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