Lab Project 2: Sequence Detectors (phase 1)

201 3R .W. A l l ison

C ECS 301 CS ULB

Revision: Feb.11,2013

STUDENT
I am submitting my own work, and I understand penalties will
be assessed if I submit work for credit that is not my own.

Print Name

Estimated Work Hours

1

PointScale
4:Exemplary
3:Complete
2:Incomplete
1:Minoreffort
0:Notsubmitted

9 10

ID Number
5%will be deducted from total score

Sign Name

for each day late

Date

Score=Pointsawarded(Pts)xWeight(Wt)

GRADER
#

Demonstration

Wt

Demo working Sequence Detectors

Documentation / Source Code

Testbench / Simulation-Verification

Pts

Score

Grader Signature

Date

Days

TotalInLab
Score

Late

GeneralStatement: You are to design and implement a sequential

circuit (in verilog) that functions as a dual implementation nonoverlapping sequence detector. The sequence detector will have an
input X that will be used to detect the non-overlapping sequence of
101101. The output Z is to become 1 upon completion of the
correct input sequence, and is 0 otherwise. Your circuit will have a
both a Mealy implementation and a Moore implementation. A
"mode" input (M) specifies which type of sequence detector is
being exercised: If M = 0, exercise the Moore implementation; if
M = 1, switch to the Mealy implementation.
Clocking and I/O Specifications: The clock input to the sequence detector is to be provided by debounced
push-button switch (BTN0) developed in Lab 1 (clocked by a 500Hz clock). The reset input is to come from
another push button switch (BTN3). Input M is to come from slide switch SW7. Input X is to come from slide
switches SW0. The single output Z is to be displayed on LD0. Display the 3-bit present state (e.g. Q[2:0]) for the
respective sequence detector on LD7..LD5.
Top Level Specifications: You are to create a schematic diagram (see next page) that instantiates the clock
divider module, the debounce module and the sequence detector, connecting them to the input (X) and output
(Z), the 50MHz board clock and reset, including appropriate BUFG for high speed inputs (e.g. 50 MHz clock).
The verilog module that implements the sequence detector must be a structural implementation that
instantiates the necessary D flip flops and assigns (using verilog assign statements) the inputs to each flip flop
with the outputs of appropriate combinational logic for the next state. The Z output is also to be assigned
according to the appropriate combinational logic.

DueDate:Monday,February18,2013

{Monday of Week 5}

301 Lab Assignment 2 Page 1

Lab Project 2: Sequence Detectors (phase 1)

Revision: Feb.11,2013

201 3R .W. A l l ison

C ECS 301 CS ULB

Simulation/Verification: The simulation of the sequence detector module is to be according to a verilog

testbench module (see p. 3) that will instantiate the sequence detector and feed it with the appropriate test
sequence. In Xilinx ISE, a verilog testbench module is created by right clicking on the appropriate module in
the Sources windows, specifying New Source, and then selecting Verilog Test Fixture. Once you have
typed in the verilog code for the testbench module (copied from page 3) you invoke the ISE simulator by
selecting the testbench file while in the Simulation section in Hierarchy window pane and then double
clicking on the Simulate Behavioral Model in the Processes window pane. Note: it is very important that
you have the `timescaledirective on the first line of the testbench!

Deliverables: Your must turn in (1) these specification sheets, followed by (2) a printout of your schematic, (3)
the state diagram and state table for the Moore implementation, (4) K-maps and derivations for your state and
output equations for the Moore implementation, (5) the state diagram and state table for the Mealy
implementation, (6) K-maps and derivations for your state and output equations for the Mealy implementation,
(7) printouts of the verilog files for the sequence detector module and the verilog testbench module, and (8) the
printouts of both "simulation" waveforms (i.e. the results of the verilog testbench) that show all functions work
correctly.

301 Lab Assignment 2 Page 2

Lab Project 2: Sequence Detectors (phase 1)

201 3R .W. A l l ison

C ECS 301 CS ULB

Revision: Feb.11,2013

`timescale 1ps / 100fs

module testbench();
//
//
//
//
//
//

DATE:
AUTHOR:
MODULE:
FILENAME:
PROJECT:
VERSION:

Mon Aug 24 09:44:44 2012

Your_Name
sequence_detector_101101
sequence_detector_101101
301_lab2
Version 2.0

// Inputs
reg clk, reset, X, M;
// Outputs
wire
Z;
wire [2:0] Q;
// Local Declarations
reg [44:1] sequence_pattern;
integer
i;
// Instantiate the Unit Under Test
sequence_detector_101101 uut (
.clk(clk), .reset(reset),
.X(X),
.M(M),
.Z(Z)
.Q(Q) );

Youllhavetoeditthispart,dependingonthe
nameofyoursequencedetectormodule,and
theorderandnameofyourinputs,outputs.

// Generate 10 ps Clock
always
#5 clk = ~clk;
// Initialize Inputs
initial begin
$timeformat(-12, 1, " ps", 8);
clk = 0; reset = 0; X = 0; M = 0;
sequence_pattern = 44'b01100010101101011011111001011011011011101010;
@(negedge clk)
reset = 1;
@(negedge clk)
reset = 0;
M = 0;
// Mealy implementation (M=0); to simulate the
//
Moore implementation, set M = 1 and run the simulation again
// this loop will "feed" the sequence detector with the
// test sequence pattern from MSB to LSB
for (i=44; i > 0; i=i-1) begin
// change inputs on negative edge of clock
@(negedge clk)
X = sequence_pattern[i];
// display outputs after the positive clock
@(posedge clk)
#1 $display("Time=%t X=%b Q=%b Z=%b", $time, X, Q, Z);
end
$stop;
end
endmodule
301 Lab Assignment 2 Page 3