Processor

8085 MICROPROCESSOR
INTRODUCTION TO 8085
INTEL 8085 is one of the most popular 8-bit microprocessor capable of addressing 64 KB of
memory and its architecture is simple. The device has 40 pins, requires +5 V power supply and
can operate with 3MHz single phase clock.
ALU (Arithmetic Logic Unit):
The 8085A has a simple 8-bit ALU and it works in coordination with the accumulator,
temporary registers, 5 flags and arithmetic and logic circuits. ALU has the capability of
performing several mathematical and logical operations. The temporary registers are used to hold
the data during an arithmetic and logic operation. The result is stored in the accumulator and the
flags are set or reset according to the result of the operation. The flags are affected by the
arithmetic and logic operation. They are as follows:
Sign flag: After the execution of the arithmetic - logic operation if the bit D7 of the result is 1,
the sign flag is set. This flag is used with signed numbers. If it is 1, it is a negative number and if
it is 0, it is a positive number.
Zero flag: The zero flag is set if the ALU operation results in zero. This flag is modified by the
result in the accumulator as well as in other registers.
Auxillary carry flag: In an arithmetic operation when a carry is generated by digit D3 and
passed on to D4, the auxillary flag is set.
Parity flag: After arithmetic logic operation, if the result has an even number of 1s the flag is
set. If it has odd number of 1s it is reset.
Carry flag: If an arithmetic operation results in a carry, the carry flag is set. The carry flag also
serves as a borrow flag for subtraction.
Timing and control unit:
This unit synchronizes all the microprocessor operation with a clock and generates the control
signals necessary for communication between the microprocessor and peripherals. The control
signals RD (read) and WR (write) indicate the availability of data on the data bus.
Instruction register and decoder
The instruction register and decoder are part of the ALU. When an instruction is fetched from
memory it is loaded in the instruction register. The decoder decodes the instruction and
establishes the sequence of events to follow.
Register array
The 8085 has six general purpose registers to store 8-bit data during program execution. These
registers are identified as B, C, D, E, H and L. they can be combined as BC, DE and HL to
perform 16-bit operation.
Accumulator
Accumulator is an 8-bit register that is part of the ALU. This register is used to store 8-bit data
and to perform arithmetic and logic operation. The result of an operation is stored in the
accumulator.
Program counter
The program counter is a 16-bit register used to point to the memory address of the next
instruction to be executed.
Stack pointer
It is a 16-bit register which points to the memory location in R/W memory, called the Stack.
Communication lines
8085 microprocessor performs data transfer operations using three communication lines called
buses. They are address bus, data bus and control bus.
Address bus it is a group of 16-bit lines generally identified as A 0 A15. The

address bus is unidirectional i.e., the bits flow in one direction from
microprocessor to the peripheral devices. It is capable of addressing 2 16 memory
locations.
Data bus it is a group of 8 lines used for data flow and it is bidirectional. The
data ranges from 00 FF.
Control bus it consist of various single lines that carry synchronizing signals.
The microprocessor uses such signals for timing purpose.
Ex.no:1
Date:
8 BIT ADDITION & SUBTRACTON
AIM:
a) To write an Assembly Language program to add two 8 bit numbers and store sum at
memory location 4500 and carry at 4501.
b) To write an Assembly Language program to Subtract two 8 bit numbers and store
difference at memory location 4500 and carry at 4501.
APPARATUS REQUIRED:
1. Microprocessor kit 8085
2. Power Supply(+ 5V)
ALGORITHM:
1.
2.
3.
4.
5.
6.
7.
8.
9.
Clear D register for Carry.

Load the data to be loaded and added to A register and B register.
Add B register data with accumulator.
If carry exists increment carry registers D.
Store added output at 4500.
Move carry to accumulator and store the carry at 4501.
Halt the operation.
In case of subtraction,subtract A data with B.
Store difference output at 4500.
FLOW CHART:
ADDRESS
4100
MNEMONICS
LABEL
MVI C,00
OPCODE
COMMENTS
0E,00
Move the data 00 into reg C
4102
MVI A,09
3E,09
Move 09 into accumulator.
4104
MVI B,05
06,05
Move 05 into register B.
4106
ADD B/SUB B
80/90
Do ADD/SUB b/w A & B reg
4107
JNC Loop
D2,0B,41
Jump to 410B , if there is no carry
410A
INR C
0C
carry.
Increment
reg C
STA 4500
32,00,45
Store [A] into 4500
410E
MOV A,C
79
Move [C] into [A]
410F
STA 4501
32,01,45
Store [A] into 4501
4112
HLT
76
Stop the Execution
410B
Loop
PROGRAM:
PROGRAM:
OUTPUT
Data : A = 09
B = 05
Result :
Addition=0E
5
Subtraction=04
RESULT:
a)Thus an ALP was written to add 8 bit numbers and output was stored stored at 4500 &
carry at 4501.
b) Thus an ALP was written to Subtract two 8 bit numbers and output was stored stored
at 4500 & carry at 4501.
Ex.no:1
Date:
8 BIT MULTIPLICATION
AIM:
To write an Assembly Language program to multiply two 8 bit numbers store at
consecutive memory locations.
APPARATUS REQUIRED:
ALGORITHM:
LOGIC: Multiplication can be done by repeated addition.
1. Clear Register A.
2. Load the datas to multiplied to B register and C register.
3. Clear the D register for carry.
4. Add B register data with A.
5. If no carry exists decrement C else increment D and do steps in sequence.
6. If C is not equal to zero do repeat addition else store output at 1000.
7. If carry exists move D to A and store at 1001.
8. Halt the operation.
FLOW CHART:
PROGRAM:
ADDRESS
MNEMONICS
OPCODE
COMMENTS
MVI C,00
0E,00
Move immediate data 00 to C
8002
MVI A,00
3E,00
register
Move immediate data 00 to A reg
8004
MVI B,05
06,05
Move immediate data 05 to B reg
8006
MVI D,04
16,04
Move immediate data 04 to D reg
ADD D
82
Add content of D with A.
8009
JNC L1
D2,0D,80
Jump if no carry to L1
800C
INR C
0C
Increment Cregister
DCR B
05
Decrement B register
800E
JNZ L2
C2,08,80
Jump if no zero to L2
8011
STA 1000
32,00,C0
Store Accumulator content to 1000
8014
MOV A,C
79
Move content of C reg to A register
8015
STA 1001
32,01,C0
Store Accumulator content to 1001
8000
8008
800D
LABEL
L2
L1
8018
HLT
76
Halt the operation
OUTPUT
Data : B = 05, D=04,

Result : 05 x 04=20
RESULT:
Thus an ALP was written to multiply two 8 bit data and output was stored at 1000 and
carry at 1001.
Ex.no:1
8 BIT DIVISION
Date:
AIM:
To write an ALP to divide two 8-bit datas numbers and store the result in memory.
APPARATUS REQUIRED:
ALGORITHM:
LOGIC: Division is done using the method Repeated subtraction.
1. Clear the carry register D.
2. Load the data to be divided to A and B register.
3. Compare B register data with A.
4. If carry exists increment carry register H.Subtract B with A and do successive steps
and jump to 8006.
5. Else store output at 8700.
6. Move carry into B to A and store at 8701.
FLOWCHART:
8
PROGRAM:
ADDRES
MNEMONICS
OPCODE
COMMENTS
8000
MVI H,00
26,00
Move immediate data 00 to H reg.
8002
MVI A,08
3E,08
Move immediate data 08 to A reg
8004
MVI B,02
06,02
Move immediate data 02 to B reg
CMP B
B8
Compare content of A with B reg.
8007
JC L1
DA,0F,80
Jump if there exist carry to L1
800A
SUB B
90
Subtract B from A register
800B
INR H
24
Increment Hregister.
800C
JMP L2
C3,06,80
Jump to L2.
STA A010
32,10,A0
Store the accumulator content to A010
MOV A,H
7C
Move content of H to Aregister
8006
800F
8012
L2
L1
8013
STA A011
32,11,A0
Store the accmulator content to A011
8016
HLT
76
Halt the operation
OUTPUT
Data : (4150) = 08 - Divisor

(4151) = 02 - Dividend.
Result : ( A011)= 00 - Remainder
(A010) = 04 - Quotient.
RESULT:
Thus an ALP was written to divide two 8-bit datas using repeated subtraction method
and executed using 8085 p kits and the output was stored at 8010 and carry at A011.
Ex.no:2
16 BIT ADDITION & 16 BIT SUBTRACTION
Date:
AIM:
a) To write an Assembly Language program to Perform 16 bit addition and store output
and carry.
b) To write an Assembly Language program to Perform 16 bit Subtraction and store output
and carry.
APPARATUS REQUIRED:
ALGORITHM:
a) ADDITION (16 bit)
10
1.
2.
3.
4.
5.
Clear D register for Carry and load 16 bit data to HL and BCregister pair.
And perform addition.
If no carry store output at 9000,9002.
If carry exist increment carry then store the output and carry.
Halt the operation.
b) SUBTRACTION (16 bit)

1.
2.
3.
4.
5.
Clear H register for Carry and get 16 bit data at BC and DEregister pair .
And perform addition.
If no carry store output at 9000,9002.
If carry exist increment carry then store the output and carry.
Halt the operation.
FLOW CHART:
PROGRAM:
16-Bit Addition
ADDRESS
MNEMONICS
OPCODE
COMMENTS
16,00
Clear D register for carry.
8000
MVI D,00
8002
LXI H,0502
21,02,05
Load 16 bit data to HL reg pair
8005
LXI B,0704
01,04,07
Load next 16 bit data BC reg pair
8008
DAD B
09
Do addition process
8009
JNC L1
D2,0D,80
Jump if no carry to 800D
800C
INR D
14
Increment Carry.
11
800D
L1
SHLD 9000
22,00,90
Store HL at 9000
8010
MOV A,D
7A
Move the content of D reg to A
8011
STA 9002
32,02,90
Store Carry at 9002.
76
Halt the operation
OPCODE
COMMENTS
8014
OUTPUT
HLT
Data : HL= 0502
BC=0704
Result : HL=0C06
PROGRAM:
16-Bit Subtraction:
ADDRESS
MNEMONICS
12
8000
MVI H,00
26,00
Clear H register for carry.
8002
LXI B,0502
01,02,05
Load 16 bit data to BC reg pair
8005
LXI D,0301
11,03,01
Load next 16 bit data DE reg pair
8008
MOV A,C
79
Move the content of C reg to A reg
8009
SUB E
93
Subtract A reg with E reg.
800A
STA 9000
32,00,90
Store A reg at 9000
800D
MOV A,B
78
Move B to A
800E
SBB D
9A
Subtract D,A,CY
800F
JNC L1
D2,13,80
Jump if C0 to 8013
8012
INR H
24
Increment H Register
STA 9001
32,01,90
Store A to 9001
8016
MOV A,H
7C
Move the Content of H reg to A reg
8017
STA 9002
32,02,90
Store Carry at 9002.
801A
HLT
76
Halt the operation
8013
L1
OUTPUT
Data : BC= 0502
DE=0301
Result : 9000=01
9002=02
RESULT:
a)Thus an ALP program was written to perform 16-bit addition and executed in 8085p
using special instructions and output was stored.
b)Thus an ALP program was written to perform 16-bit Subtraction and executed in
instructionsELEMENTS
and output was
stored.
Ex.8085p
no: 3 using special LARGEST
IN AN
ARRAY &
SMALLEST NUMBER IN AN ARRAY
Date:
AIM:
To write an ALP to find largest element and smallest element in an array.
APPARATUS REQUIRED:
13

ALGORITHM:
1. Set a counter register to load data and initialize starting address.
2. Move memory to A and increment H.
3. Get next data to B and compare withy A
4. Use JNC for biggest and JC for smallest.
5. Accordingly decrement D else move M to A.
6. If D 0 get next data else store output .
7. Store output at 9000.
FLOW CHART:
14
PROGRAM:
15
ADDRESS
MNEMONICS
OPCODE
COMMENTS
16,03
Set a counter register D
8000
MVI D,04
8002
LXI H,8500
21,00,85
Initialize address to load data
8005
MOV A,M
7E
Move M to A
INX H
23
Increment H reg
8007
MOV B,M
46
Move M to B
8008
CMP B
B8
Compare B with A
8009
JNC L1(Largest
D2,0D,80
Jump if no carry to 800D or
JC L1(Smallest No)
DA,0D,80
Jump if carry to 800D
MOV A,M
7E
Move memory to A
DCR D
15
Decrement D reg
800E
JNZ L2
C2,06,80
Jump if no zero to 8006
8011
STA 9000
32,00,90
Store largest/smallest Number at 9000
8014
HLT
76
Halt the operation
8006
L2
800C
800D
L1
OUTPUT
Data : (4150) = 05 - No. of elements,

(4151) = 67 - Array starts, (4152) = 79, (4153) = 15, (4154) = E3, (4155) = 72
Result : (4156) = E3.
RESULT:
Thus the largest number in the given array is found out.
Ex.no:3(A)
SMALLEST ELEMENT IN AN ARRAY
Date: 23-12-2011
AIM:
To find the smallest element in an array.
ALGORITHM:
16
1. Place all the elements of an array in the consecutive memory locations.

2. Fetch the first element from the memory location and load it in the accumulator.
3. Initialize a counter (register) with the total number of elements in an array.
4. Decrement the counter by 1.
5. Increment the memory pointer to point to the next element.
6. Compare the accumulator content with the memory content (next element).
7. If the accumulator content is smaller, then move the memory content (largest element) to
the accumulator. Else continue.
8. Decrement the counter by 1.
9. Repeat steps 5 to 8 until the counter reaches zero
10. Store the result (accumulator content) START
in the specified memory location.
[HL]
[8100H]
[B] 04H
[A] [HL]
[HL [HL] + 1
IS[A] <
[HL]?
[A] [HL]
FLOW CHART:
[B] [B]-1
IS[B] =
0?
17 [A]
[8105]
STOP
PROGRAM:
ADDRESS
OPCODE
8001
21
LABEL
MNEMONICS
OPERAND
LXI
H,8100
8002
COMMENTS
Initialize HL reg. to
8100H
8003
18
8004
06
MVI
B,04
Initialize B reg with

no. of comparisons(n1)
8006
7E
MOV
A,M
Transfer first data to

acc.
8007
23
INX
Increment HL reg. to
point next memory
location
8008
8E
CMP
Compare M & A
8009
DA
JC
LOOP
If A is lesser than M
then go to loop
800C
7E
MOV
A,M
Transfer data from M

to A reg
800D
05
DCR
800E
C2
JNZ
LOOP1
32
STA
8105
76
HLT
8005
LOOP1
800A
800B
LOOP
800F
Decrement B reg
If B is not Zero go to
loop1
8010
8011
8012
Store the result in a

memory location.
8013
8014
Stop the program
19
OUTPUT
Data : (4150) = 05 - No. of elements,

(4151) = 67 - Array starts
(4152) = 79,
(4153) = 15,
(4154) = E3,
(4155) = 72
Result : (4156) = E3.
RESULT:
Thus the smallest number in the given array is found out.
Ex.no:4
ASCENDING ORDER
Date: 23-12-2011
AIM:
To sort the given number in the ascending order using 8085 microprocessor.
ALGORITHM:
1. Get the numbers to be sorted from the memory locations.
20
2. Compare the first two numbers and if the first number is larger than second then I
interchange the number.
3. If the first number is smaller, go to step 4
4. Repeat steps 2 and 3 until the numbers are in required order
START
[B] 04H
[HL]
[8100H]
[C] 04H
[A] [HL]
[HL [HL] + 1
IS [A] <
[HL]?
[D] [HL]
FLOWCHART:
[HL] [A]
[HL] [HL] - 1
[HL] [D]
[HL] [HL] + 1
[C] [C] 01 H
21
A
IS[C] =
0?
[B] [B]-1
IS[B] =
0?
STOP
22
PROGRAM:
ADDRESS
OPCODE
8000
06
LABEL
MNEMONICS
OPERAND
MVI
B,04
Initialize B reg with

number of
comparisons (n-1)
LXI
H,8100
Initialize HL reg. to
8001
8002
21
LOOP 3
23
COMMENTS
8003
8100H
8004
8005
0E
MVI
C,04
Initialize C reg with

no. of comparisons(n1)
MOV
A,M
Transfer first data to

acc.
8006
8007
7C
LOOP2
8008
23
INX
Increment HL reg. to
point next memory
location
8009
8E
CMP
Compare M & A
800A
DA
JC
LOOP1
If A is less than M
then go to loop1
800D
56
MOV
D,M
Transfer data from M

to D reg
800E
77
MOV
M,A
Transfer data from acc

to M
800F
28
DCX
8010
72
MOV
M,D
8011
23
INX
Increment HL pair
8012
0D
DCR
Decrement C reg
8013
C2
JNZ
LOOP2
8016
05
DCR
8017
C2
JNZ
LOOP3
800B
800C
LOOP1
8014
Decrement HL pair
Transfer data from D
to M
If C is not zero go to
loop2
8015
8018
24
Decrement B reg
If B is not Zero go to
loop3
8019
801A
76
HLT
Stop the program
OUTPUT:
Data : (4150) = 06 - No. of elements.

(4151) = 2A - Array starts.
(4152) = B5
(4153) = 60
(4154) = 3F
(4155) = D1
(4156) = 19
Result : (4151) = 19
(4152) = 2A
(4153) = 3F
(4154) = 60
(4155) = B5
(4156) = D1
RESULT:
Thus the ascending order program is executed and thus the numbers are arranged in
ascending order.
Ex.no:4(A)
Date: 23-12-2011
DESCENDING ORDER
AIM:
To sort the given number in the descending order using 8085 microprocessor.
ALGORITHM:
1. Get the numbers to be sorted from the memory locations.
2. Compare the first two numbers and if the first number is smaller than second then I
interchange the number.
3. If the first number is larger, go to step 4
4. Repeat steps 2 and 3 until the numbers are in required order
25
FLOWCHART:
26
PROGRAM:
MEMORY ADDRES
OPCODES
LABEL
MNEMONICS
OPERANDS
START
MVI
B,00
LXI
H,4150
sssssssS
4100
06
4101
00
4102
21
4103
50
4104
41
4105
4E
MOV
C,M
4106
0D
DCR
27
4107
23
INX
4108
7E
LOOP
MOV
A,M
4100
06
START
MVI
B,00
4101
00
4102
21
LXI
H,4150
4103
50
4104
41
4105
4E
MOV
C,M
4106
0D
DCR
4107
23
INX
4108
7E
LOOP
MOV
A,M
4100
06
START
MVI
B,00
4101
00
4102
21
LXI
H,4150
4103
50
4104
41
4105
4E
MOV
C,M
4106
0D
DCR
4107
23
INX
4108
7E
MOV
A,M
LOOP
4109
23
INX
410A
BE
CMP
410B
D2
JNZ
28
LOOP1
410C
15
410D
41
410E
56
MOV
410F
77
MOV
M,A
4110
2B
DCX
4111
72
MOV
M,D
4112
23
INX
4113
06
MVI
B,01H
4114
01
4115
0D
4116
C2
4117
08
4118
41
4119
05
DCR
411A
CA
JZ
411B
00
411C
41
411D
76
HLT
4109
23
INX
410A
BE
CMP
410B
D2
JNZ
410C
15
410D
41
410E
56
MOV
410F
77
MOV
M,A
4110
2B
DCX
4111
72
MOV
M,D
4112
23
INX
LOOP1
DCR
JNZ
29
D,M
C
LOOP
B
START
LOOP1
D,M
4113
06
MVI
4114
01
4115
0D
4116
C2
4117
08
4118
41
4119
05
DCR
411A
CA
JZ
411B
00
411C
41
411D
76
LOOP1
B,01H
DCR
JNZ
LOOP
B
START
HLT
OUTPUT:
Data : (4150) = 06 - No. of elements.

(4151) = 2A - Array starts.
(4152) = B5
(4153) = 60
(4154) = 3F
(4155) = D1
(4156) = 19
Result : (4151) = D1, (4152) = B5,(4153) = 60, (4154) = 3F,(4155) = 2A, (4156) = 19
RESULT:
Thus the descending order program is executed and thus the numbers are arranged in descending
order.
Ex. no: 5
Parallel communication between 2 p Kits using 8255
Date: 27-12-2011
AIM
To write an ALP to Interface parallel communication between two micro processor kits
using 8255.
ALGORITHM
30
1. Take two 8086 microprocessor kits.

2. Enter the transmitter program in transmitter kit.
3. Enter the receiver program in receiver kit.
4. Interface the two kits with 26-core cable on PPI-1.
5. Execute the receiver kit.
6. Execute the transmitter kit.
7. Go and see the memory location 4500 in receiver your getting 8 same data.
8. Data is available in transmitter kit the memory location is 4500f.
9. We will change the data & execute the following procedure & get the result in receiver kit.
PROGRAM: TRANSMITTER
MEMORY
OPCODES LABEL
ADDRESS
4100
4101
4102
4103
4104
4105
3E
82
D3
43
3E
3F
31
MNEMONICS
OPERANDS
MVI
A,82H
OUT
43H
MVI
A,3FH
4106
4107
4108
4109
410A
410B
410C
410D
410E
410F
4110
4111
4112
4113
4114
4115
4116
4117
4118
4119
411A
411B
411C
411D
411E
411F
4120
4121
4122
4123
4124
4125
4126
4127
4128
4129
412A
412B
412C
412D
D3
40
DB
41
D6
3F
C2
08
41
42
08
21
00
45
7E
D3
40
CD
20
41
23
41
C2
14
41
CF
06
05
1E
FF
1D
C2
24
41
FE
CB
C2
22
41
C9
LOOP
OUT
40H
IN
41
SU
I 3FH
JNZ
LOOP
MVI
C,08H
LXI
H,4500
MOV
OUT
A,M
40H
CALL
INX
DELAY
H
DCR
JNZ
RST 1
DELAY
MVI
B,05H
D1
MVI
E,0FFH
D2
DCR
JNZ
SD2
D1
DCR
JNZ
D2
RET
RECEIVER
MEMORY OPCODES
ADDRESS
4100
3E
LABEL
MNEMONICS
MVI
32
OPERANDS
A,90H
4101
4102
4103
4104
4105
4106
4107
4108
4109
410A
410B
410C
410D
410E
410F
4110
4111
4112
4113
4114
4115
4116
4117
4118
4119
411A
411B
411C
411D
411E
411F
4120
4121
4122
4123
4124
4125
4126
4127
4128
4129
412A
412B
412C
412D
412E
90
D3
43
DB
40
D6
3F
C2
04
41
3E
3F
D3
41
42
08
CD
23
41
21
00
45
DB
40
77
CD
23
41
23
41
C2
17
41
43
06
05
1E
FF
1D
C2
27
41
05
C2
25
41
CHECK:
L1:
OUT
43H
IN
40H
SUI
3FH
JNZ
CHECK
MVI
A,3FH
OUT
41H
MVI
C,08H
CALL
DELAY
LXI
H,4500H
IN
40H
MVI
CALL
INX
M,A
DELAY
H
DCR
JNZ L1
DELAY:
RST 1
MVI
B,05H
D1:
MVI
E,FFH
D2:
DCR
JNZ
E
D2
DCR
JNZ
B
D1
33
412F
4130
C9
C9
RET
RET
RESULT:
Thus a parallel communication between two microprocessor kits is obtained.
Ex. no: 6
Serial communication between 2 p Kits using 8251
Date: 27-12-2011
AIM
To write an ALP to Interface parallel communication between two micro processor kits
using 8255.
ALGORITHM
34
1. Take two 8086 microprocessor kits.

2. Enter the transmitter program in transmitter kit.
3. Enter the receiver program in receiver kit.
4. Interface the two kits with 26-core cable on PPI-1.
5. Execute the receiver kit.
6. Execute the transmitter kit.
7. Go and see the memory location 1200 in receiver ur getting 8 same datas.
8. Data is available in transmitter kit the memory location is 100f.
9. We will change the data & execute the following procedure & get the result in receiver kit.
PROGERAM:
SERIAL TRANSMISSION USING 8085:
TRANSMITTER:
MEMORY
OPCODES MNEMONICS
ADDRESS
4100
21
LXI
4101
00
4102
45
4103
3E
MVI
4104
36
35
OPERANDS
H,4500
A,36
4105
4106
4107
4108
4109
410A
410B
410C
410D
410E
410F
410A
4111
4112
4113
4114
4115
4116
4117
4118
4119
411A
411B
411C
411D
411E
411F
4120
4121
4122
4123
4124
4125
D3
0B
3E
40
D3
08
3E
01
D3
08
0E
05
DB
05
E6
04
CA
11
41
7E
D3
04
23
FE
3F
C2
0F
41
0D
C2
11
41
CF
OUT
0B
MVI
A,40
OUT
08
MVI
A,01
OUT
08
MVI
C,05
IN
05
ANI
04
JZ
4111
MOV
OUT
A,M
04
INX
CPI
H
3F
JNZ
410F
DCR
JNZ
C
4111
RST 1
RECEIVER:
MEMORY
ADDRESS
4100
4101
4102
4103
4104
4105
OPCODES
21
00
45
3E
36
D3
MNEMONICS
OPERANDS
LXI
H,4500
MVI
A,36
OUT
0B
36
4106
4107
4108
4109
410A
410B
410C
410D
410E
410F
4110
4111
4112
4113
4114
4115
4116
4117
4118
4119
411A
411B
411C
412D
411E
412F
4120
4121
4122
4123
4124
4125
4126
0B
3E
40
D3
08
3E
01
D3
08
0E
05
DB
05
E6
02
CA
11
41
DB
04
77
23
FE
3F
C2
0F
41
0D
C2
11
41
CF
CF
MVI
A,40
OUT
08
MVI
A,01
OUT
08
MVI
C,05
IN
05
ANI
02
JZ
4111
IN
04
MOV
INX
CPI
M,A
H
3F
JNZ
410F
DCR
JNZ
C
4111
RST 1
RST 1
RESULT:
Thus a serial communication between two micro processor kit is obtained.
37
8085 INTERFACING
KEYBOARD AND DISPLAY
CONTROLLER - 8279
KEYBOARD AND DISPLAY CONTROLLER - 8279

INTRODUCTION:
The Intel 8279 is responsible for debouncing of the keys, coding of the keypad matrix and
refreshing of the display elements in a Microprocessor based development system. Its main
features are:
1) Simultaneous Keyboard and Display operation.
38
2) Three Input modes such as Scanned Keyboard Mode, Scanned Sensor Mode and Strobed
Input Entry Mode.
3) Two Output modes such as 8 or 16 character multiplexed displays, right entry or left entry
display formats.
4) Clock Prescaler.
5) Programmable Scan Timing.
6) 2 Key lockout or N-key Roll-over with contact debounce.
7) Auto Increment facility for easy programming.
CIRCUIT DESCRIPTION:
The keyboard section consists of 16 keys, besides two keys for CNTL (Control) and
SHFT (Shift). The keyboard is arranged as two rows of eight keys each. With this keyboard it is
possible to enter 64 different key codes.
Keyboard and display is configured in the encoded mode. In the encoded mode, a binary
count sequence is put on the scan lines SL0-SL3. These lines must be externally decoded to
provide the scan lines for keyboard and display. A 3 to 8 decoder 74LS138 (U3) is provided for
this purpose. The S0-S1 output lines of this decoder are connected to the two rows of the
keyboard.
RL0-RL7 lines connect to the 8 columns of the keyboard matrix.
Display is a 6 digit, multiplexed display. The decoded outputs S0-S5 of the 74LS138
(U3) are used to drive the cathodes of the seven segment display. The output port lines A0-A3,
B0-B3 drive the anodes of the seven segment display.
___
IRQ output line is connected to RST 5.5 of 8085.
The 8279 is designed specifically to connect to any 8 bit microprocessor bus directly.
This allows the CPU to do some other work other than scanning the keyboard and refreshing the
display. The CPU can program the operating modes for 8279. 8279 uses the CS, A0, RD and
WR lines to control data flow to and from various internal registers and buffers, as given in the
following table.
39
Segment Definition:
Segment definitions of the seven segment display are shown below:
Table below shows the correspondence between the data bus and output port bits of 8279. Also,
the segment relationship with these are given:
D0 bit of the byte sent to the display RAM corresponds to B0 and D7 of the byte sent to the
display RAM corresponds A3. In order to light up a segment the corresponding bit of data
written into the display RAM should be a "0".
Ex. no: 1
Date: 3-1-2012
DISPLAY DATA "A"
AIM:
To initialize 8279 controller and to display the character "A" in the first digit of the
display.
ALGORITHM:
40
1. Display/Keyboard mode set word and clear word take care of basic initialization of 8279.
2. However, before sending codes to the display RAM, a write display RAM control word
should be sent.
3. Then, write the data to be displayed, to the data register.
PROGRAM:
ADDRESS
OPCODE
MNEMONICS OPERAND
COMMENT
4100
3E
MVI
A,00
Mode &
display set
4101
00
4102
D3
OUT
4103
C2
CNT
4104
3E
MVI
A,CC
Clear display
4105
CC
4106
D3
OUT
4107
C2
CNT
4108
3E
MVI
A,90
Write display
RAM
4109
90
410A
D3
OUT
410B
C2
CNT
410C
3E
MVI
A,88
Display "A"
410D
88
410E
D3
OUT
411F
C0
DAT
4110
3E
MVI
A,FF
Blank the rest

of the Display
4111
FF
4112
D3
OUT
4113
C0
DAT
4114
D3
OUT
4115
C0
DAT
4116
D3
OUT
4117
C0
DAT
4118
D3
OUT
4119
C0
DAT
411A
D3
OUT
41
411B
C0
DAT
411C
76
HLT
RESULT:
The above programs from the address specified and execute it.
Ex.no:1(A)
Date: 3-1-2012
ROLLING DISPLAY
AIM:
To display the rolling message 'HELP US' in the display using 8279 microcontroller .
ALGOROTHM:
1. The initialization of 8279
2. Then, the data is fetched from address 412CH and displayed in the first digit of the
display.
42
3. The next data is displayed in the second digit of the display, since in the command word
for 'write display RAM' the Auto Increment flag is set.
4. A time delay is given between successive digits for a lively display.
FLOWCHART:
SET UP
POINTER
INITIALIZE THE COUNTER
SET 8279 FOR 8-DIGIT CHARACTER

DISPLAY
SET 8279 FOR CLEARING THE
DISPLAY
WRITE THE COMMAND TO DISPLAY
LOAD THE CHARACTER INTO
ACCUMULATOR AND DISPLAY
DELAY
PROGRAM:
ADDRESS OPCODE LABEL MNEMONICS OPERAND COMMENT
4100
21
START LXI
H,POINTER Set pointer =
412CH
4101
4102
4103
2C
41
16
4104
4105
4106
4107
0F
3E
10
D3
MVI
D,0FH
MVI
A,10H
OUT
43
Initialize
counter
Set mode and
display
4108
4109
410A
410B
410C
410D
410E
410F
4110
4111
4112
4113
4114
4115
4116
4117
C2
3E
CC
D3
C2
3E
90
D3
C2
7E
D3
C0
CD
1F
41
23
4118
LOP
CNT
MVI
A,OCCH
OUT
CNT
MVI
A,90H
OUT
CNT
MOV
OUT
DAT
CALL
DELAY
A,M
INX
15
DCR
4119
C2
JNZ
LOP
411A
411B
411C
411D
411E
411F
4120
4121
4122
4123
4124
4125
4126
4127
4128
4129
412A
11
41
C3
00
41
O6
A0
OE
FF
0D
C2
23
41
05
C2
21
41
JMP
START
DELAY MVI
B,OAOH
LOP1
MVI
C,OFFH
LOP2
JNZ
DCR
LOP
C
2
B
LOP1
DCR
JNZ
44
Write display
Increment the
pointer
Decrement the
counter
Jump if nonzero to display
the next chr.
412B
C9
RET
OUTPUT:
4400
4404
4408
440C
FF
FF
98
FF
FF
FF
68
IC
FF
FF
7C
29
FF
FF
C8
FF
DELAY SUBROUTINE
4500
4502
4504
4505
4507
4509
7C
7D
00
DD
DC
22
A0
FF
FD
F9
MOV R4,#A0
LOOP2 : MOV R5,#FF
LOOP1 : NOP
DJNZ R5,LOOP1
DJNZ R4,LOOP2
RET
RESULT:
45
8255 INTERFACE BOARD

INTRODUCTION
The 8255 has been designed as general purpose programmable I/O device, compatible with Intel
Microprocessors. It contains three 8 bit ports which can be configured by software means to
provide any one of the three programmable data transfer modes available with 8255.
The block diagram shows two 8 bit ports (A and B), two 4 bit ports (PC0 - PC3 and PC4 - PC7),
the data bus buffer, group control the read/write control logic. The function of each of the block
is given below.
PORT A: One 8-bit data output latch/buffer and one 8-bit data input latch. Port A can function as
input or output port in three modes. The details are given in the following sections.
46
PORT B: One 8-bit data output latch/buffer and one 8-bit data input buffer. Port B can function
as input or output port in two modes.
PORT C: One 8-bit output latch/buffer and one 8-bit data input buffer (no latch for input). Port
C can function as a simple input or output port. This port can be divided into two 4-bit ports,
which in turn can function as simple input or output port. In addition the port C lines can be used
for the control signal outputs and status signal inputs in conjunction with port A and Port B.
GROUP A AND GROUP B CONTROLS
The three ports of 8255 have been divided into two groups: Group A and Group B.
Group A contains port A (PA0 - PA7) and port C higher order lines (PC4 - PC7).
Group B contains Port B (PB0 - PB7) and port C lower order lines (PC0 - PC3).
The ports are configured as input or output by the command word.
CIRCUIT IMPLEMENTAYION
The 24 I/O lines of the 8255 are terminated at a 26 pin header. This is our standard
Dio-bus.
The design provides all the hardware needed to configure 8255 in mode-0, mode-1 and
mode-2. Eight to configure 8255 in mode-0, mode-1 and 8 bit data set by the SPDT
switches, can be read by the CPU through the port A.
Eight LEDs are connected to port B configuring it as an output port. The output operation
of 8255 can be explained using these 8 LEDs in detail. Port C has multiacting as STB,
IBF, OBF and INTR lines in mode-1 and 2. In our circuit design, 5 LEDs are connected
to PC0, PC1, PC3, PC5, PC4 and PC6.
Ex. no:3
Date:3.1.2012
8255
FOR PORT-A AS INPUT PORT IN MODE-1
AIM:
The process involving INTR & RD signals will be explained later in the chapter
"Experimenting with 8255".
ALGORITHM:
1. With this configuration, PC4 of port C acts as strobe input and PC5 acts as IBFA output.
47
2. Referring to Figure 2-1C, it can be seen that, on giving a strobe pulse (STBA), the IBFA
goes high.
3. This can be explained with the following simple program.
PROGRAM:
ADDRESS OPCODE LABEL
MNEMONICS OPERAND COMMENT
4100
3E
MVI
4101
B0
4102
D3
OUT
4103
C6
0C6H
4104
76
HLT
START
A,B0
Initialize port
as Input port in
mode-1
RESULT:
Ex. no:3A
Date:3.1.12
8255
FOR PORT-B AS OUTPUT PORT IN MODE-2
AIM:
To initialize Port A as an Input port in mode-0, and port B as output port in Mode-1.
ALGORITHM:
1. In this configuration, the lines PC2 of port C acts as STBB input and PCI acts as IBFB
output.
48
2. From the following example, it can be seen that on applying a STBB signal, the IBFB
goes high.
3. Press the Int 0 switch which generates STBB signal. See the IBFB control signal going
high visually (The corresponding LED glows).
PROGRAM:
4100
3E
START
4101
4102
4103
4104
C0
D3
C6
3E
4105
4106
4107
4108
45
D3
C0
76

Port A as
MVI
A,C0
Output
OUT
0C6H
Port in mode-2.
MVI
A,45
Write Data 45
to Port B
OUT
0C0H
HLT
RESULT:
49
8-BIT DIGITAL TO
ANALOG CONVERTER
INTERFACE
8-BIT DIGITAL TO ANALOG CONVERTER INTERFACE

INTRODUCTION
In order to control medical instruments or automobiles or the machines in electronics factory,
with a microprocessor based system, we need to determine the values of physical quantities such
as temperature, pressure etc. These are represented by equivalent electrical quantities by means
of transducers. These signals are called analog signals. Even though an analog signal may
represent a real physical parameter with accuracy, it is difficult to process or store the analog
signal for later use without introducing considerable error. Therefore in a microprocessor based
control system, it is necessary to translate an analog signal into digital signal and vice versa. The
electronic circuit that translates an analog signal into a digital signal is called an Analog-toDigital or A/D Converter (ADC). Similarly the circuit that translates digital information to
analog signal is called Digital-to-Analog converter or D/A Converter (DAC).
50
VBMB-002 contains two D/A converters using DAC0800. Using this add-on card you can learn
in detail how to interface D/A converters with microprocessors. This card also consists of a
comparator which can be used along with the D/A converter.
Ex.no:4
Date: 7-1-2012
8-BIT DIGITAL TO ANALOG CONVERTER

INTERFACE
AIM:
To generate square-wave at the DAC2 output.

ALGORITHM:
1. The basic idea behind the generation of waveforms is the continuous generation of analog
output of DAC.
51
2. With 00 (Hex) as input to DAC 2, the analog output is -5V. Similarly with FF (Hex) as
input the output is +5V.
3. Outputting digital data 00 and FF at regular intervals, to DAC2, results in a square wave
of amplitude 15 Volts.
PROGRAM:
ADDRESS
4100
4101
4102
4103
4104
4105
4106
4107
4108
4109
410A
410B
410C
410D
410E
410F
4110
4111
4112
4113
4114
4115
4116
4117
4118
4119
411A
411B
411C
411D
OPCODE
3E
00
D3
C8
CD
11
41
3E
FF
D3
C8
CD
11
41
C3
00
11
06
05
0E
FF
0D
C2
15
41
05
C2
13
41
C9
LABEL
START
MNEMONICS OPERAND
MVI
A,00H
OUT
0C8H
CALL
DELAY
MVI
A,0FF
OUT
0C8H
CALL
DELAY
JMP
START
MVI
B,05
MVI
C,0FF
DCR
JNZ
C
L2
DCR
JNZ
B
L1
RET
52
RESULT:
Execute the program and using a CRO, verify that the waveform at the
DAC2 output is a square-wave. Modify the frequency of the square-wave,
by varying the time delay.
53
16 CHANNEL 8-BIT ADC

INTERFACE
16 CHANNEL 8-BIT ADC INTERFACE

INTRODUCTION
Microprocessors are Digital logic devices that can process only digital signals that are in binary
form logic levels (either 0 or 1 or 0 volts or 5 volts), But most industrial applications involve
physical variables such as temperature, pressure etc, which are continuously (varying voltage)
when converted to analog signal by transducers & signal condition, unlike digital signals having
either a low or high state. In most cases we want to control these signals electronically. This
automatic control can be achieved using a microprocessor. But microprocessor can understand
only digital language. Then how can it control these parameters? So there should be some
translater who can translate these analog signals to a digital form which the Microprocessor
considers formal. This is the place where an Analog to Digital Converter (ADC) comes into the
54
picture. Thus an Analog to Digital Converter is an electronic circuit that converts the analog or
continuous signal to digital or discrete form.
This manual explains about our add-on card VBMB-003. This card consists of a 16 Channel A to
D converter using two ADC 0809 ICs form National Semiconductor Devices FAC. Following
chapters will acquaint you with the basic principles of A to D converters, the IC ADC 0809,
interfacing ADC 0809 with Microprocessor.
Ex.no:3
Date: 7-1-2012
16 - CHANNEL 8 - BIT ADC INTERFACE
AIM:
Initiating the analog to digital conversion process by means of software.
ALGORITHM:
1.
2.
3.
4.
Place jumper J2 in A position.

Enter and execute the program.
Vary the analog input (using trimpot) and view the corresponding digital value in
the LED display.
55
PROGRAM:
ADDRESS OPCODE LABEL MNEMONICS OPERAND COMMENT
Select Channel
4100
3E
START MVI
A,10
0 and Make
4101
4102
4103
4104
10
D3
C8
3E
4105
4106
4107
4108
18
D3
C8
3E
OUT
0C8H
ALE Low
MVI
A,18
Make ALE
High
OUT
0C8H
MVI
A,01
56
SOC Signal
High
4109
410A
410B
410C
410D
410E
411F
01
D3
D0
AF
AF
AF
3E
4110
4111
4112
4113
00
D3
D0
76
OUT
0D0H
XRA
XRA
XRA
MVI
A
A
A
A,00
OUT
0D0H
DELAY
SOC Signal
Low
HLT
RESULT:
which converts the analog input at Channel 0 and displays the output with the
LEDs.
Ex. no: 4(A)
ADC CONVERTER
Date:7-1-2012
AIM:
The following programs initiate the conversion process, checks the EOC pin of ADC
0809 as to whether the conversion is over and then inputs the data to the processor
ALGORITHM:
1.
2.
3.
4.

Enter and execute the program.
Vary the analog input (using trimpot) and verify the digital data displayed with
that data stored in memory location 4150h..
PROGRAM:

57
4100
3E
4101
4102
4103
4104
10
D3
C8
3E
4105
4106
4107
4108
18
D3
C8
3E
4109
410A
410B
410C
410D
410E
410F
01
D3
D0
AF
AF
AF
3E
4110
4111
4112
4113
00
D3
D0
DB
4114
4115
4116
4117
4118
4119
411A
411B
411C
D8
E6
01
FE
01
C2
13
41
DB
411D
411E
411F
C0
32
50
START
LOP
MVI
A,10
Select
Channel
0and Make
OUT
0C8H
ALE Low
MVI
A,18
MAHE ALE
HIGH
OUT
0C8H
MVI
A,01
OUT
0D0H
XRA
XRA
XRA
MVI
A
A
A
A,00
OUT
0D0H
IN
0D8H
ANI
01
CPI
01
JNZ
LOP
IN
0C0H
STA
4150H
58
SOC Signal
High
DELAY
SOC Signal
Low
Check
EOC
for
Read
Data
From ADC
4120
4121
41
76
HLT
RESULT:
59
8259 INTERRUPT

INTRODUCTION:
The VBMB - 007 comprises of the Programmable Interrupt Controller Intel 8259. The
Programmable Interrupt Controller (PIC) Functions as an overall manager in an interrupt driven
system environment. It accepts requests from the peripheral equipment, determines which of the
incoming requests is of the highest importance (priority) , ascertains whether the incoming
request has a higher priority value than the level currently being serviced and issues an interrupt
to the CPU based on this determination.
The special features of 8259 are,
1) Eight level priority controller
2) Expandable to 64 levels
3) Programmable interrupt modes
4) Individual request mask capability
60
The 8259 is designed to minimize the software and real time overhead in handling
multilevel priority interrupts. It has several modes, permitting optimization for a variety of
system requirements.
CIRCUIT IMPLEMENTATION:
Design of this interrupt controller interface is quite simple. The 8259 interacts with the CPU by
D0-D7 , , , ,A0 ,I CS RD WR NT, INTA. Description of the rest of pins of 8259 are given below.
-CASO-CAS2 - Cascade lines (pin 12, pin 13 and pin 15).
-Private 8259 bus to control a multiple 8259 structure. These pins are left free.
-SP/EN - Slave program/Enable buffer (Pin 16).
-In buffered mode , it can be used to control buffer transceivers (EN) . In other modes, indicates
whether a master (SP=1) or a slave (SP=0) 8259. It is pulled high using a 3.3 k resistor.
-IRO-IR& - INTERRUPT REQUESTS.
In VBMB-007 these pins are connected to the switch settings so that interrupt requests can be
given manually. These interrupt request are also terminated at a 10 pin connector.
A latch 74LS273 (U3) is provided on-board, which transfers the status of the data bus to glow the
LEDS. This is meant for demonstration purposes.
Ex. no: 5
Date: 7-1-2012
8259 INTERRUPT
AIM:
To initialize 8259 with the following specifications.
ALGORITHM:
* ICW4 needed
* Single 8259
* Interval of 4
* Edge triggered mode
* A7 A6 A5 = 0 0 0
* Interrupt service routine address for IRO:5000H
61
* 8085 mode
* Normal EOI
* Non buffered mode (Since we are not using buffers)
* Not special fully nested mode
* Mask all interrupts except IR0
PROGRAM:
62
ADDRESS
4100
4101
4102
4103
4104
4105
4106
4107
4108
4109
410A
410B
410C
410D
410E
410F
4110
OPCODE LABEL
3E
START
17
D3
C0
3E
50
D3
C2
3E
00
D3
C2
3E
FE
D3
C2
76
MNEMONICS OPERAND
MVI
A,17
OUT
0C0H
MVI
A,50
OUT
0C2H
MVI
A,00
OUT
0C2H
MVI
A,FE
OUT
0C2H
HLT
RESULT:
63
8259 INTERRUPT
Ex.no:5(A)
Date: 7-1-2012
AIM:
To program the 8259 in special mask mode.
ALGORITHM:
1. The CPU jumps to 5000H and executes the program there.
2. Normally, since no EOI command is given 8259 will not accept further interrupts.
3. However due to special mask mode 8259 will accept interrupt only at IR1, since only IR1
is enabled at that location.
4. You may verify this.
PROGRAM:
ADDRESS
4100
4101
4102
4103
4104
4105
4106
4107
4108
4109
410A
410B
410C
410D
410E
411F
4110
4111
4112
OPCODE
3E
17
D3
C0
3E
50
D3
C2
3E
00
D3
C2
3E
00
D3
C2
3E
68
D3
LABEL
START
64
MNEMONICS OPERAND
MVI
A,17
OUT
0C0H
MVI
A,50
OUT
0C2H
MVI
A,00
OUT
0C2H
MVI
A,00
OUT
0C2H
MVI
A,68
OUT
0C0H
4113
4114
C0
76
HLT
RESULT:
65
8253 & 8251

INTERFACE BOARD
PROGRAMMABLE INTERVAL TIMER - IC 8253

66
The timer section contains only the chip 8253. The main features of the timer Intel 8253 are as
follows:
1. Three independent 16-bit counters
2. Input clock from DC to 2 MHz
3. Programmable counter modes
4. Count binary or BCD
The control signals with which the 8253 interfaces with the CPU are CS, RD, WR, A1, A2. The
basic operations performed by 8253 are determined by these control signals and are illustrated
in the table given below.
CIRCUIT IMPLEMENTATION FOR TIMER SECTION:

As in the circuit diagram CLK 0 can be connected to either Pclk (1.5 MHz clock available at the
VXT-BUS) or to the debounce circuit. Using this debounce circuit you can generate a pulse and
clock the timer. Similarly CLK 1 may be connected to Pclk and CLK 2 can be connected to
either Pclk or OUT 0. The usefulness of these settings will become evident when you go through
the software examples in the following sections.
PROGRAMMABLE COMMUNICATION INTERFACE - IC 8251:

The
RS232C
interface
of
VBMB-004
comprises
of
the
universal
synchronous/asynchronous Receiver / Transmitter 8251 (USART), RS232C driver (MC 1488)
and RS232C receiver (MC 1489).
The 8251A is used here as a peripheral device for serial communication and is
programmed by the CPU to operate using virtually any serial data transmission technique. The
USART accepts data characters from the CPU in parallel format and then converts them into a
67
continuous serial data stream for transmission. Simultaneously, it can receive serial data streams
and convert the minto parallel data characters for the CPU. The CPU can read the status of the
USART at any time. These include data transmission errors and control signals.
The main features of 8251A are,
1. Both Synchronous and Asynchronous operation,
2. False Start Bit Detection,
3. Automatic Break Detect and Handling,
4. Clock rate - 1, 16 or 64 times Baud rate,
5. Error Detection - Parity, Overrun and Framing Errors,
6. Break Character Generation.
The control pins with which the 8251A communicates with the CPU are the RESET, CLK,
WR, RD, CS, C/D, DO-D7.
CIRCUIT IMPLEMENTATION FOR USART:

The baud rate generation for USART is done by the timer 8253. The transmitter clock
and receiver clock are tied together, and connected to OUT 0 of 8253. This may also
be connected to OUT 1 or OUT 2.
The RTS (Pin 23) and TXD (Pin 19) of 8251 are connected to MC1488. CTS (Pin 17)
and RXD (Pin 3) are connected to MC1489. Refer the circuit diagram which is
given in Appendix-A.
Two LEDs are connected at TXD and RXD, to indicate the transmission and the
reception of serial data.
Jumper settings are provided so that you can connect the RTS with CTS (J5) and the
TXD with RXD (J4). This is a way to "loop.back", i.e., to send the data serially through
8251 and receive it back.
The receiver ready (Pin 14) of 8251 may be connected to RST 5.5 or RST 6.5 or RST 7.5.
Thus interrupt controlled I/O transfer is also possible.
Regarding chip selection, a 3 to 8 decoder 74LS138 (U7) is employed to select 8251 and
8253.
8253 & 8251 INTERFACE PROGRAM

68
Ex. no: 6
Date: 11-1-2012
HARDWARE TRIGGERED STROBE
AIM:
The program that follows initializes channel 0 in mode 5 and also triggers GATE 0.
Connect CLK 0 to debounce circuit.
ALGORITHM:
1. After giving six clock pulses, you can see using CRO.
2. The initially high output goes low.
4. The output (OUT 0 pin) goes high on the next clock pulse.
PROGRAM:
4100
4101
4102
4103
4104
3E
1A
D3
CE
3E
MVI
A,1A
OUT
0CE
MVI
A,05
4105
4106
4107
4108
4109
410A
05
D3
C8
D3
D0
76
OUT
OC8
OUT
0D0
HLT
RESULT:
Ex.no:6
8253 & 8251 INTERFACE

69
8253 in mode 5
Load LSB of
count
Trigger Gate 0
Date:11-1-2012
AIM:
To initiate 8253 and 8251 and to check the transmission and reception of a character.
ALGORITHM:
1. The program first initializes.
2. The 8253 to give an output clock frequency of 150 KHz at channel 0 which will give a
9600 baud rate of 8251.
3. Then the 8251 is also initialized with data 4E and 37.
PROGRAM:
4100
3E
START
4101
4102
4103
4104
4105
4106
4107
4108
4109
410A
410B
410C
410D
410E
410F
4110
4111
4112
4113
4114
4115
36
D3
CE
3E
0A
D3
C8
3E
00
D3
C2
3E
4E
D3
C2
3E
37
D3
C2
3E
41

Mode set for
MVI
A,36
8253
OUT
0CEH
MVI
A,OA
OUT
0C8H
MVI
A,00
OUT
0C8H
MVI
A,4E
OUT
0C2H
MVI
A,37
Command
OUT
0C2H
Instruction
MVI
A,41
send the data
70
Mode for 8251
4116
4117
4118
D3
C0
CF
OUT
0C0H
RST
OUTPUT:
4200
4202
4205
DB
32
CF
C0
50
IN
41
0C0H
STA 4150
RST 1
RESULT:
71
STEPPER MOTOR
&
DC MOTOR INTERFACE
72
STEPPER MOTOR INTERFACE BOARD

INTRODUCTION
We have introduced a series of Microprocessor Trainers based on different
microprocessors such as 8085A, Z-80, 6502, 8086, 8088, 8097, 8031 and we provide sufficient
software and hardware experiments. Also we have a range of add-on-boards.
These add-on-boards are meant for beginners who desire to get into hardware interfacing
and hardware oriented software.
This board supports stepper motor, ranging from 2 to 20Kg with operating voltages 6, 12
& 24V. The supply can be given externally. Two stepper motors of different voltages can be
connected to this board. The following sections cover the details of stepper motors, hardware
descriptions of this board and software listing for doing experiments in any of our
microprocessor kits. This board can be interfaced to any computer using our PC-Add-on-card
VAD-107.
HARDWARE DESCRIPTION
Among the Vi range of add-on-cards, the VBMB-13A supports the stepper motor interface. This
board can be plugged into the VXT Bus in any EB kits using 50 core cable and into the VME
Bus of any other kits using our VXT Bus extender. This board consists of 3 sections as
following.
1. Address decoding.
2. Stepper motor driving circuitry.
3. Operating voltage selections.
73
Ex.no:7
Date: 11-1-2012
STEPPER MOTOR INTERFACES
AIM:
To run a stepper motor at different speed in two directions.
ALGORITHM:
1. A motor in which the rotor is able to assume only discrete stationary angular position is a
stepper motor.
2. The rotary motion occurs in a stepwise manner from one equilibrium position to the next.
PROGRAM:
ADDRESS
4100
4101
4102
4103
4104
4105
4106
4107
4108
4109
410A
410B
410C
410D
410E
410F
4110
4111
4112
4113
4114
4115
4116
OPCODE
21
1A
41
06
04
7E
D3
C0
11
03
03
00
1B
7B
B2
C2
0B
41
23
05
CZ
05
41
LABEL
START
REPT
DELAY
74
MNEMONICS
LXI
OPERAND
H,LOOK UP
MVI
B,04
MOV
OUT
A,M
0C0H
LXI
D,0303H
NOP
DCX
MOV
ORA
JNZ
D
A,E
D
DELAY
INX
DCR
JNZ
H
B
REPT
4117
4118
4119
411A
411B
411C
411D
C3
00
41
09
03
06
0C
JMP
LOOK UP DB
START
09 05 06 0A
RESULT:
The stepper motor rotates. Speed can be varied by varying the count at DE pair. Direction
can be varied by entering the data in the look-up table in the reverse order.
75
Ex.no:7(A) STEPPER MOTOR IN BOTH FORWARD AND REVERSE DIRECTION

Date: 11-1-2012
WITH DELAY
AIM:
To run Stepper Motor in both Forward and Reverse directions with delay.
ALGORITHM:
1) Enter the above program starting from location 1000 onwards.
2) Execute the program after connecting the stepper motor in port 1.
3) Now you can see that the stepper motor runs in forward and reverse direction
continuously with a delay.

FLOWCHART:
START
INTIALIZE COUNTER FOR LOOK UP TABLE
GET THE FIRST DATA FROM THE ACCUMULATOR
MOVE DATA INTO THE ACCUMULATOR
DRIVE THE MOTOR

CIRCUITARY
DELAY
DECREMENT COUNTER
YES
NO
IS B =
0 ?
GET THE DATA FROM LOOK UP TABLE
76
PROGRAM:
77
ADDRESS
4100
4101
4102
4103
4104
4105
4106
4107
4108
4109
410A
410B
410C
410D
410E
410F
4110
4111
4112
4113
4114
4115
4116
4117
4118
4119
411A
411B
411C
411D
411E
411F
4120
4121
4122
4123
4124
4125
4126
4127
4128
4129
412A
412B
412C
412D
OPCODE
0E
20
21
3F
41
CD
21
41
0D
C2
02
41
CD
35
41
0E
20
21
43
41
CD
21
41
0D
C2
11
41
CD
35
41
C3
00
41
06
04
7E
D3
C0
11
03
03
1B
7B
B2
C2
29
LABEL
START
MNEMONICS OPERAND
MVI
C,20H
FORWARD LXI
H,FORLOOK
CALL
RATATE
DCR
JNZ
C
FORWARD
CALL
STOP
MVI
C,20H
LXI
H,REVLOOK
CALL
ROTATE
DCR
JNZ
C
REVES
CALL
STOP
JMP
START
ROTATE
MVI
B,04H
REPT
MOV
OUT
A,M
0C0H
LXI
D,0303H
DCX
MOV
ORA
JNZ
D
A,E
D
LOOP1
REVES
LOOP1
78
RESULT:
Execute the program. Now you can see that the stepper motor runs in forward direction
and reverse direction continuously with a delay.
SPEED OF DC MOTOR
Ex. no: 8
Date: 24-1-2012
AIM:
To set the speed of DC motor and read the count value from channel 0 of the counter.
ALGORITHM;
1.
2.
3.
4.
5.
6.
Set DC motor speed

Set control word and initialize the counter
Enable the counter gate
Apply delay for one second(rps)
Disable the counter gate.
Read the counter value.
PROGRAM:
ADDRESS
4100
4101
4102
4103
4104
4105
4106
LABEL
MNEMONIC OPERAND
MVI
A,0FFH
OUT
0C0H
MVI
OUT
0D8H
4108
CALL
DELAY
4109
410A
410B
MVI
A,3OH
4107
410C
79
HEX CODE COMMENTS

3E
FIX DAC
VALUE
FF
MAX DATA
D3
DAC VALUE
CO
3E
00
D3
INITIALIZE
GATE AS LOW
D8
INITIALISING
TIMER&LOAD
FOR
MAX.VALUE
CD
DELAY FOR
STABLE
RUNNING
2B
41
3E
MODE AS
INTERRUPT
ON
TERMINAL
COUNT
30
410D
410E
410F
4110
4111
4112
4113
OUT
0CEH
MVI
A,0FFH
OUT
0C8H
CE
3E
FF
D3
0C8H
C8
D3
OUT
4114
D3
C8
4115
4116
4117
4118
4119
411A
411B
411C
411D
411E
411F
4120
4121
4122
MVI
A,00
OUT
0D00H
3E
00
D3
CALL
DELAY
D0
CD
MVI
A,00
OUT
0D8H
2B
41
3E
00
D3
IN
0C8H
D8
DB
MEMI
C8
32
STA
4123
4124
4125
4126
4127
4128
4129
412A
MVI
A,00
STA
MEMI+1
HLT
00
45
3E
00
32
01
45
76
.ONE SECOND DELAY ROUTING.

412B
DELAY
MVI
C,03
80
0E
TIMER
CONTROL
PORT
MAX DATA
TIMER CHO
PORT(LSB)
TIMER CHO
PORT(MSB)
ENABLING
GATE FOR 1
SECOND
MAKE GATE
HIGH
DELAY FOR
ONE SECOND
MAKE GATE
LOW
DATA INPUT
DATA IN
FROM CHO
DATA STORED
ON MEMI
412C
412D
412E
412F
4130
4131
4132
4133
4134
4135
4136
4137
4138
4139
413A
413B
LO2
LXI
H,0A3C3H
LOOP
DCX
MVI
ORA
JNZ
H
A,L
H
LOOP
DCR
JNZ
C
LO2
RET
END
03
21
C3
A3
2B
7D
B4
C2
30
41
0D
C2
2D
41
C9
RESULT:
The decremented value is stored in memory location 4500H and 4501H.
81
8086 PROGRAMMING
82
Introduction to 8086
The 8086 is a 16-bit microprocessor chip designed by Intel between early 1976
and mid-1978, when it was released. The 8086 gave rise to the x86 architecture of Intel's future
processors. The Intel 8088, released in 1979, was a slightly modified chip with an external 8-bit
data bus.
8086 has a 20 bit address bus can access up to 220 memory locations ( 1 MB) . It can
support up to 64K I/O ports. It provides 14, 16-bit registers. It has multiplexed address and data
bus AD0- AD15 and A16 A19. It requires single phase clock with 33% duty cycle to provide
internal timing. 8086 is designed to operate in two modes, Minimum and Maximum. It can
prefetches up to 6 instruction bytes from memory and queues them in order to speed up
instruction execution. It requires +5V power supply. A 40 pin dual in line package.
Minimum and Maximum Modes:
The minimum mode is selected by applying logic 1 to the MN / MX# input pin. This is a single
microprocessor configuration.
The maximum mode is selected by applying logic 0 to the MN / MX# input pin. This is a multi
micro processors configuration.
Internal Registers of 8086:
The 8086 has four groups of the user accessible internal registers. They are the instruction
pointer, four data registers, four pointer and index register, four segment registers.
The 8086 has a total of fourteen 16-bit registers including a 16 bit register called the status
register, with 9 of bits implemented for status and control flags. Most of the registers contain
data/instruction offsets within 64 KB memory segment. There are four different 64 KB segments
for instructions, stack, data and extra data. To specify where in 1 MB of processor memory these
4 segments are located the processor uses four segment registers:
Code segment:
It is a 16-bit register containing address of 64 KB segment with processor instructions. The
processor uses CS segment for all accesses to instructions referenced by instruction pointer (IP)
register. CS register cannot be changed directly. The CS register is automatically updated during
far jump, far call and far return instructions.
Stack segment:
It is a 16-bit register containing address of 64KB segment with program stack. By default, the
Processor assumes that all data referenced by the stack pointer (SP) and base pointer (BP)
registers is located in the stack segment. SS register can be changed directly using POP
instruction.
Data segment
It is a 16-bit register containing address of 64KB segment with program data. By default, the
Processor assumes that all data referenced by general registers (AX, BX, CX, DX) and index
register (SI, DI) is located in the data segment. DS register can be changed
directly using POP and LDS instructions.
83
Extra segment:
It is a 16-bit register containing address of 64KB segment, usually with program data.
By default, the processor assumes that the DI register references the ES segment in string
manipulation instructions. ES register can be changed directly using POP and LES instructions.
It is possible to change default segments used by general and index registers by prefixing
instructions with a CS, SS, DS or ES prefix.
General Registers of the 8086 Microprocessor:
It can be used for arithmetic and logic operations. The general registers are:
Accumulator:
This register consists of two 8-bit registers AL and AH, which can be combined together
and used as a 16- bit register AX. AL in this case contains the low-order byte of the word, and
AH contains the high-order byte. Accumulator can be used for I/O operations and string
manipulation.
Base register:
It consists of two 8-bit registers BL and BH, which can be combined together and used as
a 16-bit register BX. BL in this case contains the low-order byte of the word, and BH contains
the high-order byte. BX register usually contains a data pointer used for based, based indexed or
register indirect addressing.
Count register:
It consists of two 8-bit registers CL and CH, which can be combined together and used as
a 16-bit register CX. When combined, CL register contains the low-order byte of the word, and
CH contains the high order byte. Count register can be used in Loop, shift/rotate instructions and
as a counter in string manipulation,.
Data register:
It consists of two 8-bit registers DL and DH, which can be combined together and used as a
16-bit register DX. When combined, DL register contains the low-order byte of the word, and
DH contains the high order byte. Data register can be used as a port number in I/O operations. In
integer 32-bit multiply and divide instruction the DX register contains high-order word of the
initial or resulting number.
Stack Pointer
It is a 16-bit register pointing to program stack
.
Base Pointer:
It is a 16-bit register pointing to data in stack segment. BP register is usually used for
based, based indexed or register indirect addressing.
Source Index:
It is a 16-bit register. SI is used for indexed, based indexed and register indirect addressing,
as well as a source data addresses in string manipulation instructions.
Internal
Destination Index:
It is a 16-bit register. DI is used for indexed, based indexed and register indirect addressing,
a well as a destination data address in string manipulation instructions.
84
Other registers:
Instruction Pointer (IP) is a 16-bit register.
Flags are a 16-bit register containing 9 one bit flags.
Overflow Flag (OF) - set if the result is too large positive number, or is too small negative
number to fit into destination operand.
Direction Flag - if set then string manipulation instructions will auto-decrement index
registers. If cleared then the index registers will be auto-incremented.
Interrupt-enable Flag (IF) - setting this bit enables maskable interrupts.
Single-step Flag (TF) - if set then single-step interrupt will occur after the next instruction.
Sign Flag (SF) - set if the most significant bit of the result is set.
Zero Flag (ZF) - set if the result is zero.
Auxiliary carry Flag (AF) - set if there was a carry from or borrow to bits 0-3 in the AL
register.
Parity Flag (PF) - set if parity (the number of "1" bits) in the low-order byte of the result is
even.
Carry Flag (CF) - set if there was a carry from or borrow to the most significant bit during
last result calculation.
Addressing Modes:
Implied - the data value/data address is implicitly associated with the instruction.
Register - references the data in a register or in a register pair.
Immediate - the data is provided in the instruction.
Direct - the instruction operand specifies the memory address where data is located.
Register indirect - instruction specifies a register containing an address, where data is located.
Indexed:- 8-bit or 16-bit instruction operand is added to the contents of an index register (SI or
DI), the resulting value is a pointer to location where data resides.
Based Indexed:- the contents of a base register (BX or BP) is added to the contents of an index
register (SI or DI), the resulting value is a pointer to location where data resides.
Based Indexed with displacement:- 8-bit or 16-bit instruction operand is added to the contents
of a base register (BX or BP) and index register (SI or DI), the resulting value is a pointer to
location where data resides.
85
ADDITION
Ex. no: 1(A)

Date: 31-1-2012
AIM:
To write an Assembly Language Program (ALP) for performing the addition operation of
two byte numbers.
ALGORITHM:
a)
a)
b)
c)
d)
e)
Initialize the MSBs of sum to 0

Get the first number.
Add the second number to the first number.
If there is any carry, increment MSBs of sum by 1.
Store LSBs of sum.
Store MSBs of sum.
PROGRAM:
MEMORY
ADDRESS
OPCODES
1000
1001
1002
1003
1004
1005
1006
1007
1008
1009
100A
100B
100C
MNEMONICS OPERANDS
8B
06
00
11
03
06
02
11
89
06
00
12
F4
MOV
AX,[1100]
ADD
AX,[1102]
MOV
[1200],AX
HLT
OUTPUT:
Data-1: 1100 = 1234
Data-2: 1102 = 5678
Result: 1200 = 68AC
RESULT:
Thus the 8086 assembly language program to add two 16 bit numbers was successfully
executed and verified
86
Ex. no: 1(B)

Date: 31-1-2012
SUBTRACTION
AIM:
To write an Assembly Language Program (ALP) for performing the subtraction operation
of two byte numbers.
ALGORITHM:
1.
2.
3.
4.
5.
6.
Initialize the MSBs of sum to 0

Get the first number.
Add the second number to the first number.
If there is any carry, increment MSBs of sum by 1.
Store LSBs of sum.
Store MSBs of sum.
PROGRAM:
MEMORY
ADDRESS
1000
1001
1002
1003
1004
1005
1006
1007
1008
1009
100A
100B
100C
OPCODES
MNEMONICS
8B
06
00
11
03
06
02
11
89
06
00
12
F4
OPERANDS
MOV
AX,[1100]
SUB
AX,[1102]
MOV
[1200],AX
HLT
OUTPUT:
Data-1: 1100 = 4343
Data-2: 1102 = 2121
Result:
1200 =.2222
RESULT:
Thus the 8086 assembly language program to subtract two 16 bit numbers was
successfully executed and verified
87
Ex. no: 1(C)

Date: 31-1-2012
MULTIPLICATION
AIM:
To write an Assembly Language Program (ALP) for performing the multiplication
operation of 16-bit numbers.
ALGORITHM:
a)
b)
c)
d)
e)
f)
Get the multiplier.

Get the multiplicand
Initialize the product to 0.
Product = product + multiplicand
Decrement the multiplier by 1
If multiplicand is not equal to 0,repeat from step (d) otherwise store the product.
PROGRAM:
MEMORY
ADDRESS
1000
1001
1002
1003
1004
1005
1006
1007
1008
1009
100A
100B
100C
100D
100E
100F
1010
1011
1012
OPCODES
MNEMONICS
8B
06
00
11
8B
1E
02
11
F7
E3
89
16
00
12
89
06
02
12
F4
MOV
AX,[1100]
MOV
BX,[1102]
MUL
BX
MOV
[1200],DX
MOV
[1202],AX
HLT
88
OPERANDS
OUTPUT:
Data-1: 1100 = FEDC
Data-2: 1102 = BA98
Result: 1200 = B9C3
1202 = 2AA0
RESULT:
Thus the 8086 assembly language program to multiplication of two 16 bit numbers was
successfully executed and verified.
89
DIVISION
Ex. no: 1(D)

Date: 31-1-2012
AIM:
To write an Assembly Language Program (ALP) for performing the division operation of 16-bit
numbers
ALGORITHM:
1.
2.
3.
4.
5.
6.
7.
Get the dividend

Get the divisor
Initialize the quotient to 0.
Dividend = dividend divisor
If the divisor is greater, store the quotient. Go to step g.
If dividend is greater, quotient = quotient + 1. Repeat from step
Store the dividend value as remainder.
PROGRAM:
MEMORY
ADDRESS
1000
1001
1002
1003
1004
1005
1006
1007
1008
1009
100A
100B
100C
100D
100E
100F
1010
1011
1012
1013
1014
1015
OPCODES
MNEMONICS
8B
16
00
11
8B
06
02
11
8B
0E
04
11
F7
F1
89
06
00
12
89
16
02
12
90
OPERANDS
MOV
DX,[1100]
MOV
AX,[1102]
MOV
CX,[1104]
DIV
CX
MOV
[1200],AX
MOV
[1202],DX
1016
OUTPUT:
Dividend:
Divisor:
Result:
F4
HLT
1100 = 0000
1102 = FFFF
1104 = FFFF
1200 = 0001
1202 = 0000.
RESULT:
Thus the 8086 assembly language program to division of two 16 bit numbers was
successfully executed and verified
91
Ex. no: 2
Date: 7-2-2012
LINEAR SEARCH
AIM:
To write 8086 ALP to find the desired (enter) element in the array starting from 1200H.
ALGORITHM:
1.
2.
3.
4.
5.
Clear the data segment register.

Load the data in to AL,BL register pair.
Find the desired element you enter.
Store the element in corresponding memory location
Stop the program.
PROGRAM
MEMORY
ADDRESS
1000
1001
1002
1003
1004
1005
1006
1007
1008
1009
100A
100B
100C
100D
100E
100F
1010
1011
1012
1013
1014
1015
1016
1017
1018
1019
OPCODE
BE
00
12
BF
00
15
8A
0C
46
8A
04
46
3A
04
74
09
46
FE
C9
75
F7
B0
FF
88
04
8A
MNEMONICS
MOV SI,1200H
MOV DI,1500H
MOV CL,[SI]
INC SI
MOV AL,[SI]
LOOP:
INC SI
CMP AL,[SI]
JZ END
INC SI
DEC CL
JNZ LOOP
MOV AL,0FFH
MOV [SI],AL
END:
92
MOV BL,[SI]
101A
101B
101C
101D
101E
101F
1C
88
1D
CD
02
F4
MOV [DI],BL
INT 02H
HLT
OUTPUT:
1200 = 04H (LENGTH 0F ARRAY)
1201 = 35H
1202 = 18H
1203 = 36H
1204 = 54H
1205 = 72H
Note: The element which one we want to search is stored at location 1201h & The number of
elements in an array is stored at location 1200h.
Result:
1. If the elment which one we want to search is in an array, then it will be store at the
location [1500H] i.e 35 is stored
2. If the element which one we want of search is not in an array, then FFFFH will be
stored at location 1500h to indicate ERROR condition.
RESULT:
93
Thus the program finding the desired element using 8086 was executed and verified.
Ex. no: 3(A)
ASCENDING ORDER
Date: 7-2-2012
AIM:
To write an Assembly Language Program (ALP) to sort a given array in ascending
order.
ALGORITHM:
1. Load the array count in two registers C1 and C2.
2. Get the first two numbers.
3. Compare the numbers and exchange if necessary so that the two numbers are in
ascending order.
4. Decrement C2.
5. Get the third number from the array and repeat the process until C2 is 0.
6. Decrement C1 and repeat the process until C1 is 0.
PROGRAM:
INSERTION SORT: (ASCENDING)
MEMORY
ADDRESS
1000
1001
1002
1003
1004
1005
1006
1007
1008
1009
100A
100B
100C
100D
100E
100F
1010
1011
1012
1013
OPCODES LABEL
B3
00
BE
00
12
8A
0C
FE
C9
46
8A
04
46
3A
04
72
0A
8A
14
88
04
MNEMONICS OPERANDS
START
94
MOV
BL,00
MOV
SI,1200H
MOV
CL,[SI]
DEC
CL
INC SI
MOV
AL,[SI]
INC
CMP
SI
AL,[SI]
JC
LOOP1
MOV
DL,[SI]
MOV
[SI],AL
1015
1016
1017
1018
1019
101A
101B
101C
101D
101E
101F
1020
1021
1022
1023
4E
88
14
46
B3
01
FE
C9
75
EB
FE
CB
74
DD
F4
DEC
MOV
SI
[SI],DL
INC
MOV
SI
BL,01
DEC
CL
JNZ
LOOP
ZEC
JZ
START
HLT
OUTPUT:
1200 = 05 (LENGTH 0F ARRAY)
1201 = 2A
1202 = B5
1203 = FF
1204 = 34
1205 = D1
Result:
1200 = 2A
1201 = 34
1202 = B5
1203 = D1
1204 = FF.
RESULT
Thus the program for arranging the number in ascending order using 8086 was executed
and verified
95
Ex. no: 3(B)

Date: 7-2-2012
DESCENDING ORDER
AIM:
To write an Assembly Language Program (ALP) to sort a given array in descending
order.
ALGORITHM:
a. Load the array count in two registers C1 and C2.
b. Get the first two numbers.
c. Compare the numbers and exchange if necessary so that the two numbers are in descending
order.
d. Decrement C2.
e. Get the third number from the array and repeat the process until C2 is 0.
f. Decrement C1 and repeat the process until C1 is 0.
PROGRAM
SELECTION SORT
MEMORY ADDRESS
1000
1002
1005
1007
1009
100A
100C
100D
100F
1011
1013
1015
1016
1018
1019
LABEL
START:
OPCODES
B3
00
BE
00
12
8A
0C
FE
C9
46
8A
04
46
3A
04
73
0A
8A
14
88
04
4E
88
14
46
B3
96
MNEMONICS
MOV
OPERANDS
BL,00
MOV
SI,1200H
MOV
CL,[SI]
DEC
CL
INC
MOV
SI
AL,[SI]
INC
CMP
SI
AL,[SI]
JNC
LOOP1
MOV
DL,[SI]
MOV
[SI],AL
DEC
MOV
SI
[SI],DL
INC
MOV
SI
BL,01
101B
LOOP1:
101D
101F
1021
1023
01
FE
C9
75
EB
FE
CB
74
DD
F4
DEC
CL
JNZ
LOOP
DEC
BL
JZ
START
HLT
OUTPUT:
1200 = 05 (LENGTH 0F ARRAY)
1201 = 2A
1202 = B5
1203 = FF
1204 = 34
1205 = D1
Result:
1200 = FF
1201 = D1
1202 = B5
1203 = 34
1204 = 2A.
RESULT
Thus the program for arranging the number in descending order using 8086 was executed
and verified
Ex. no: 4
STRING MANIPULATION
97
Date: 7-2-2012
COMPARE STRING PROGRAM
AIM:
To write an ALP to compare two strings using 8086 microcontroller kit.
ALGORITHM
1. Clear the data segment register.
2. Load the data in to the register.
3. Compare the value in the register.
4. Store the result in the corresponding memory location.
5. Stop the program.
PROGRAM
COMPARE STRING PROGRAM
ORG 1000H
LEA SI,[1200]
LEA DI,[1300]
MOV CX,0003H
CLD
REPE CMPSB
JNZ NOTEQUAL
MOV AL,01
MOV [1400],AL
HLT
NOTEQUAL: MOV AL,00
MOV [1400],AL
HLT
OUTPUT:
CONDITION 1: (SAME STRING IN DATA1 AND DATA2)
1ST INPUT
1200:11
1201:22
1202:33
2ND INPUT
1300:11
1301:22
1302:33
OUTPUT:
1400:01
CONDITION 2: (DIFFERENT STRING IN DATA1 AND DATA2)
98
1ST INPUT:
1200:11
1201:22
1202:33
2ND INPUT:
1300:44
1301:55
1302:66
OUTPUT:
1400:00
RESULT:
Thus the program to perform string manipulation by using 8086 was executed and
verified.
99
Ex. no: 5
Date: 14-2-2012
DIGITAL CLOCKS AND STOP WATCH
AIM:
To write the program to display 24 hours digital clock in serial mode. Execute the
program from 1000H to change MIN, HOURS. Change the data in location 1009H & 1007H
respectively by using 8086.
DIGITAL CLOCK PROGRAM FOR MICRO-86/88LCD R:2 KIT:
store time value in memory location 1500- SECONDS
1501- MINUTES
1502- HOURS
MEMORY
ADDRESS
1000
1003
1006
1006
1008
100A
100C
100C
100E
1010
1012
1014
1014
1015
1016
1017
1018
101A
101C
101E
1020
1022
1024
1026
1029
102B
102D
OPCODE
MNEMONICS
E8 0060
E8 0051
START:
CALL
CALL
CONVERT
DISPLAY
MOV
OUT
MOV
AL,0B0H
16H,AL
CL,07H
MOV
OUT
MOV
OUT
AL,88H
14H,AL
AL,80H
14H,AL
MOV
OUT
AL,80H
16H,AL
DELAY:
B0 B0
E6 16
B1 07
S2:
B0 88
E6 14
B0 80
E6 14
S1:
90
90
90
90
E4 14
8A D0
E4 14
0A C2
75 F2
FE C9
75 E6
BE 1500
8A 04
FE C0
88 04
;
;
NOP
NOP
NOP
NOP
IN AL,14H
MOV
DL,AL
IN AL,14H
OR AL,DL
JNZ S1
DEC
CL
JNZ S2
MOV
SI,1500H
MOV
AL,[SI]
INC AL
MOV
[SI],AL
100
102F
1031
1033
1035
1037
1038
103A
103C
103E
1040
1042
1044
1046
1047
1049
104B
104D
104F
1051
1053
1055
1057
1057
1059
105C
105E
1060
1062
1063
1063
1066
1069
106B
106D
106F
1071
1073
1075
1078
1079
107B
107C
107E
3C 3C
75 CD
B0 00
88 04
46
8A 04
FE C0
88 04
3C 3C
75 BE
B0 00
88 04
46
8A 04
FE C0
88 04
3C 18
75 AF
B0 00
88 04
EB A9
CMP
AL,3CH
JNZ START
MOV
AL,00H
MOV
[SI],AL
INC
SI
MOV
AL,[SI]
INC AL
MOV
[SI],AL
CMP
AL,3CH
JNZ START
MOV
AL,0
MOV
[SI],AL
INC
SI
MOV
AL,[SI]
INC AL
MOV
[SI],AL
CMP
AL,18H
JNZ START
MOV
AL,0
MOV
[SI],AL
JMP START
DISPLAY:
B4 06
BA 1600
B5 01
B1 00
CD 05
C3
MOV
MOV
MOV
MOV
INT 5
RET
AH,06H
DX,1600H
CH,01H
CL,0H
BE 1500
BB 1608
B0 24
88 07
MOV
MOV
MOV
MOV
SI,1500H
BX,1608H
AL,24H
[BX],AL
8A 04
B4 00
B6 0A
F6 F6
80 C4 30
4B
88 27
4B
04 30
88 07
MOV
MOV
MOV
DIV DH
ADD
DEC
MOV
DEC
ADD
MOV
AL,[SI]
AH,0
DH,0AH
CONVERT:
101
AH,30H
BX
[BX],AH
BX
AL,30H
[BX],AL
;SECONDS
1080
1081
1083
1085
4B
B0 3A
88 07
4B
DEC
MOV
MOV
DEC
BX
AL,3AH
[BX],AL
BX
1086
1087
1089
108B
108D
108F
1092
1094
1095
1097
1099
109A
109C
109E
46
8A 04
B4 00
B6 0A
F6 F6
80 C4 30
88 27
4B
04 30
88 07
4B
B0 3A
88 07
4B
INC
MOV
MOV
MOV
DIV DH
ADD
MOV
DEC
ADD
MOV
DEC
MOV
MOV
DEC
SI
;MINUTES
AL,[SI]
AH,0
DH,0AH
109F
10A0
10A2
10A4
10A6
10A8
10AB
10AD
10AE
10B0
10B2
10B3
10B3
10B5
10B7
10B9
46
8A 04
B4 00
B6 0A
F6 F6
80 C4 30
88 27
4B
04 30
88 07
C3
INC
MOV
MOV
MOV
DIV DH
ADD
MOV
DEC
ADD
MOV
RET
SI
;HOURS
AL,[SI]
AH,0
DH,0AH
AH,30H
[BX],AH
BX
AL,30H
[BX],AL
BX
AL,3AH
[BX],AL
BX
AH,30H
[BX],AH
BX
AL,30H
[BX],AL
GETC:
E4 02
24 FF
3C F0
75 F8
IN AL,02H
AND AL,0FFH
CMP AL,0F0H
JNE GETC
RESULT
Thus the program was executed and displayed 24 hours digital clock. The minutes and
hours could be changed
102
8051 -MICRO
CONTROLLER
INTRODUCTION
103
INTEL MCS-51 FAMILY:

Intel has introduced a family of Microcontrollers called the MCS-51. This family comprises the
8031, 8051, 8052, 8751 and 8752 Microcontrollers. Our trainer kit supports all these
microcontrollers. 8051, an 8-bit Single chip Microcontroller has got a powerful CPU optimised
for control applications, 64K Program Memory address space, 64K Data Memory address space,
4K bytes of on-chip ROM (Read Only Memory), 128 bytes of on-chip RAM (Read/Write
Memory), Four 8-bit bidirectional Parallel ports, one full-duplex (it can transmit and receive
simultaneously) Serial port, two 16-bit timer/counters and an extensive interrupt structure.
The Major Features of 8051 Are:
* 8-bit CPU optimised for control applications.
* Extensive Boolean processing (single-bit logic) capabilities.
* 64K Program Memory address space.
* 64K Data Memory address space.
* 4K bytes of on-chip Program Memory (in 8051 and 8751 only).
* 128 bytes of on-chip Data RAM.
* 32 bi-directional and individually addressable I/O lines.
* Two 16-bit Timer / Counters.
* Full Duplex UART (Universal Asynchronous Receiver / Transmitter).
* 6-source / 5-vector interrupt structure with two priority levels.
* On-chip Oscillator and Clock circuitry.
Simplified diagram of 8051

THE 8051 MICROCONTROLLER ARCHITECTURE
The architecture of the 8051 family of microcontrollers is referred to as the MCS-51 architecture
(Micro Controller Series-51), or sometimes simply as MCS-51.The microcontrollers have an 8bit data bus. They are capable of addressing 64K of program memory and a separate 64K of data
memory. The block diagram of 8051 microcontroller is shown below.
104
The 8051 have 4K of code memory implemented as on-chip Read Only Memory (ROM). The
8051 have 128 bytes of internal Random Access Memory (RAM). The 8051 has two
timer/counters, a serial port, 4 general purpose parallel input/output ports, and interrupt control
logic with five sources of interrupts. Besides internal RAM, the 8051 have various Special
Function Registers (SFR), which are the control and data registers for on-chip facilities. The
SFRs also include the accumulator, the B register, and the Program Status Word (PSW), which
contains the CPU flags. Programming the various internal hardware facilities of the 8051 is
achieved by placing the appropriate control words into the corresponding SFRs.
8051 PROGRAMMING
105
8 BIT ADDITION
Ex. no: 1(A)

Date: 14-2-2012
AIM:
To write a program to add two 8-bit numbers using 8051 microcontroller.
ALGORITHM:
1. Clear Program Status Word.
2. Select Register bank by giving proper values to RS1 & RS0 of PSW.
3. Load accumulator A with any desired 8-bit data.
4. Load the register R 0 with the second 8- bit data.
5. Add these two 8-bit numbers.
6. Store the result.
7. Stop the program.
FLOW CHART:
START
Clear PSW
Select Register
Bank
Load A and R 0
with 8- bit
datas
Add A & R 0
Store the sum
STOP
PROGRAM
106
8 Bit Addition (Immediate Addressing)

ADDRESS
4100
CLR
HEX
CODE
C3
4101
MOV
A, data1
74,data1
4103
ADDC
A, # data 2
24,data2
4105
MOV
90,45,00
4108
MOVX
DPTR, #
4500H
@ DPTR, A
SJMP
L1
80,FE
4109
LABEL
L1
MNEMONIC OPERAND
F0
COMMENTS
Get the data1 in

Accumulator
Add the data1 with
data2
Initialize the
memory location
Store the result in
memory location
Stop the program
Clear CY Flag
RESULT:
Thus the 8051 ALP for addition of two 8 bit numbers is executed.
Ex. no: 1(B)
8 BIT SUBTRACTION
107
Date: 14-2-2012
AIM:
To perform subtraction of two 8 bit data and store the result in memory.
ALGORITHM:
a.
b.
c.
d.
e.
f.
Clear the carry flag.

Initialize the register for borrow.
Get the first operand into the accumulator.
Subtract the second operand from the accumulator.
If a borrow results increment the carry register.
Store the result in memory.
FLOWCHART:
START
CLEAR CARRY
FLAG
GET IST
OPERAND IN
ACCR
SUBTRACT THE
2ND OPERAND
FROM ACCR
N
IS
CF=1
Y
INCREMENT
THE BORROW
REGISTER
STORE
RESULT IN
MEMORY
STOP
108
PROGRAM
8 Bit Subtraction (Immediate Addressing)
ADDRESS
MNEMONIC
OPERAND
COMMENTS
HEX
CODE
C3
4100
CLR
4101
MOV
A, # data1
74, data1
4103
SUBB
A, # data2
94,data2
4105
MOV
DPTR, # 4500
90,45,00
4108
MOVX
@ DPTR, A
F0
SJMP
L1
80,FE
Store data1 in
accumulator
Subtract data2 from
data1
Initialize memory
location
Store the difference
in memory location
Stop
4109
LABEL
L1
RESULT:
Thus the 8051 ALP for subtraction of two 8 bit numbers is executed.
109
Clear CY flag
Ex. no: 1(C)

Date: 18-2-2012
8 BIT MULTIPLICATION
AIM:
To perform multiplication of two 8 bit data and store the result in memory.
ALGORITHM:
a.
b.
c.
d.
Get the multiplier in the accumulator.

Get the multiplicand in the B register.
Multiply A with B.
Store the product in memory.
FLOWCHART:
START
GET MULTIPLIER IN
ACCR
GET MULTIPLICAND IN B
REG
MULTIPLY A WITH B
STORE RESULT IN
MEMORY
STOP
PROGRAM
110
8 Bit Multiplication
MEMORY ADDRESS
4100
4102
4105
4106
4109
410A
410B
410D
410E
OPCODES
74 0A
75 F0 88
A4
90 45 00
F0
A3
E5 F0
F0
80 FE
MNEMONICS
MOV A,#0A
MOV B,#88
MUL AB
MOV DPTR,#4500
MOVX @DPTR,A
INC DPTR
MOV A,B
MOVX @DPTR,A
HERE: SJMP HERE
INPUT:
4101 = 0A
4104 = 88
RESULT:
4500 = 50 (LSB)
4501 = 05 (MSB)
RESULT
Thus the 8051 ALP for multiplication of two 8 bit numbers is executed.
Ex. no: 1(D)
8 BIT DIVISION
111
Date: 18-2-2012
AIM:
To perform division of two 8 bit data and store the result in memory.
ALGORITHM:
1.
2.
3.
4.
Get the Dividend in the accumulator.

Get the Divisor in the B register.
Divide A by B.
Store the Quotient and Remainder in memory.
FLOWCHART:
START
GET DIVIDEND IN
ACCR
GET DIVISOR IN B
REG
DIVIDE A BY B
STORE
QUOTIENT &
REMAINDER IN
MEMORY
STOP
112
PROGRAM
8 Bit Division
ADDRESS LABEL MNEMONIC
OPERAND
4100
MOV
A, # data1
HEX
CODE
74,data1
COMMENTS
4102
MOV
B, # data2
75,data2
Store data1 in
accumulator
Store data2 in B reg
4104
DIV
A,B
84
Divide
4015
MOV
DPTR, # 4500H
90,45,00
4018
MOVX
@ DPTR, A
F0
Initialize memory
location
Store remainder
4109
INC
DPTR
A3
410A
MOV
A,B
E5,F0
Go to next memory
location
Store quotient
410C
410D
STOP
MOV
@ DPTR, A
F0
SJMP
STOP
80,FE
RESULT:
113
Stop
Thus the 8051 ALP for division of two 8 bit numbers is executed.
Ex. no: 1(E)
Date: 18-2-2012
LOGICAL AND BIT MANIPULATION
AIM:
To write an ALP to perform logical and bit manipulation operations using 8051 microcontroller.
ALGORITHM:
1.
2.
3.
4.
5.
6.
7.
8.
Initialize content of accumulator as FFH

Set carry flag (cy = 1).
AND bit 7 of accumulator with cy and store PSW format.
OR bit 6 of PSW and store the PSW format.
Set bit 5 of SCON.
Clear bit 1 of SCON.
Move SCON.1 to carry register.
Stop the execution of program.
PROGRAM
1. SETTING BITS IN AN 8-BIT NUMBER:
MEMORY
ADDRESS
4100
4102
4104
4107
4108
OPCODES
MNEMONICS
74 2F
44 45
90 45 00
F0
80 FE
MOV A,#2FH
ORL A,#45H
MOV DPTR,#4500H
MOVX @DPTR,A
HERE: SJMP HERE
INPUT:
4101 = 2F
4103 = 45
RESULT:
4500 = 6F.
114
MASKING BITS IN AN 8-BIT NUMBER:

MEMORY
ADDRESS
4100
4102
4104
4107
4108
OPCODES
MNEMONICS
74 87
54 7E
90 45 00
F0
80 FE
MOV A,#87H
ANL A,#7EH
MOV DPTR,#4500H
MOVX @DPTR,A
HERE: SJMP HERE
INPUT:
4101 = 87
4103 = 7E
Result:
4500 = 06.
RESULT:
115
Thus the bit manipulation operation is done in 8051 microcontroller.

Ex. no: 2
Date: 18-2-2012
PROGRAMS TO VERIFY TIMER, INTERRUPTS &

UART OPERATIONS IN 8051 MICROCONTROLLER
AIM
To verify the Timer, Interrupts & UART operations using 8051.
ON BOARD TIMER AND INTERRUPT USING MICRO-51EB
TIMER OVERFLOW
4100
75
89
20
MOV TMOD,#10H; TIMER 1 MODE 0
4103
75
A8
88
MOV IE,#88H;
TIMER1 OVERFLOW
4106
76
8D
00
MOV TH1,#00H;
INTERRUPT IS ENABLED
4109
75
8B
00
MOV TL1,#00H;
410C
D2
8E
4111
30
8F
4113
C2
8E
SETB TR1;
FD L1:JNB TF1,L1;
CLR TR1;
4115
START THE TIMER

CHECK THE TIMER OVERFLOW
CLEAR THE TIMER CONTROL BIT
L2:SJMP L2;
INTERRUPT SERVICE ROUTINE

THE VECTOR ADDRESS FOR TIMER OVERFLOW INTERRUPT IS 001b ; IN OUR KIT
INE JUMP LOCATION [5030H] GIVEN IN THAT VECTOR ADDRESS
5030
74
12
MOV A,#12H
5032
24
12
ADD A,#12H
5035
90
45
5038
F0
5039
80
00
MOV DPTR,#4500H
MOVX @DPTR,A
FE
HLT: SJMP HLT
116
ON BOARD UART PROGRAM USING MICRO 51 EB

4100
75
89
00
MOV TMOD,#20h
4103
75
8D
FD
MOV TH1,#FD h
4106
75
8b
00
MOV TL1,#00h
4109
75
88
40
MOV TCON,#40h
410C
75
98
58
MOV SCON,#58h
410F
75
99
54
MOV SBUF,#54h
4112
30
98
FD
4115
C2
98
CLR SCON.0
4117
E5
99
MOV A,SBUF
4119
90
45
4122
F0
411C
80
00
repeat: JNB SCON.0,repeat
MOV DPTR,#4500h
MOVX @DPTR,A
FE
HLT: SJMP HLT
RESULT:
Thus the program to verify Timer, Interrupts & UART operations in 8051 microcontroller
was successfully executed.
117
COMMUNICATIONS BETWEEN 8051 MICROCONTROLLER

Date: 21-2-2012
KIT & PC
Ex. no: 3
AIM:
To write an ALP for interfacing with pc by using 8051
ALGORITHM:
1.
2.
3.
4.
5.
6.
7.
DIP switch 1&4 is ON in 8051 microcontroller.

Assemble - > check -> enter the program.
Dissemble the program entered in memory location of 8051.
Upload the program and save it as file name add: hex.
Download the program to 8051 kit.
Enter the program in 8051.
Stop the Execution.
PROGRAM:
ADDRESS
4100
CLR
HEX
CODE
C3
4101
MOV
A, data1
74,data1
4103
ADDC
A, # data 2
24,data2
4105
MOV
90,45,00
4108
MOVX
DPTR, #
4500H
@ DPTR, A
SJMP
L1
80,FE
4109
LABEL
L1
MNEMONIC OPERAND
F0
COMMENTS
Get the data1 in

Accumulator
Add the data1 with
data2
Initialize the
memory location
Store the result in
memory location
Stop the program
Clear CY Flag
RESULT:
Thus the program for interfacing with pc by using 8051 was successfully executed and
verified.
118
EXTRA PROGRAMS
USING 8085, 8086, 8051
119
TRAFFIC LIGHT CONTROL using 8085
Ex. no: 1
Date:28.2.12
AIM:
To stimulate the blinking of the signaling lights or ON-OFF control of light emitting
diodes.
ALGORITHM:
The board has green, red and yellow LEDs

The green, orange, red signals are actual systems
Twelve LEDs are used on the board
In addition eight dual color LEDs are used
PROGRAM:
ADDRESS
4100
4101
4102
4103
4104
4105
4106
4107
4108
4109
410A
410B
410C
410D
410E
410F
4110
4111
4112
4113
4114
4115
4116
LABEL
START
LOOP1
MNEMONIC
LXI
OPERAND
H,DATA
MVI
C,OC
MOV
OUT
A,M
CNT
INX
MOV
OUT
H
A,M
APRT
INX
MOV
OUT
H
A,M
BART
CALL
DELAY
INX
DCR
JMP
H
C
LOOP1
120
HEX CODE
21
00
45
0E
0C
23
D3
0F
23
7E
D3
0C
23
7E
D3
0D
CD
1B
41
23
OD
C2
09
4117
4118
4119
411A
411B
411C
411D
411E
411F
4120
4121
4122
4123
4124
4125
4126
4127
4128
4129
412A
412B
412C
JMP
START
DELAY
PUSH
MVI
B
A,0A
LOOP3
LXI
D,FFFFF
LOOP2
DCX
MOV
ORA
JNZ
D
A,D
E
LOOP2
DCR
JNZ
C
LOOP3
POP
RET
121
41
C3
00
41
C5
0E
0A
11
FF
FF
1B
7A
B3
C2
21
41
0D
C2
1E
41
C1
C9
RESULT:
The outputs are the inputs to buffers 7406 whose outputs drive the LEDs.
LCD INTERFACING WITH 8051

INTRODUCTION
1. The declining prices of LCD.
2. The ability to display numbers, characters, and graphics.
3. Incorporation of a refreshing controller into the LCD, thereby
relieving the CPU of the task of refreshing the LCD.
4. Ease of programming for characters and Graphics.
122
123
Ex. no:2
Date: 28.2.12
DISPLAY THE LETTERS M, D, E IN LCD
124
AIM
To interface a LCD with 8051 micro controller to send letters M, D, and E to the
LCD using C
PROGRAM
#include <reg51.h>
sfr ldata = 0x90; //P1=LCD data pins
sbit rs = P2^0;
sbit rw = P2^1;
sbit en = P2^2;
sbit busy = P1^7;
void main(){
lcdcmd(0x38);
lcdcmd(0x0E);
lcdcmd(0x01);
lcdcmd(0x06);
lcdcmd(0x86); //line 1, position 6
lcdcmd(M);
lcdcmd(D);
lcdcmd(E);
}
RESULT:
Thus the LCD interface with 8051 is obtained.
Ex. no: 3
Date:28-2-2012
8086/88 INTERFACING WITH STEPPER MOTOR
125
AIM:
To run a stepper motor for required angle within 460, which is equivalent to 256 steps.
PROGRAM:
PORT1
1000
1000
1000 B3 45
1002 BF 1B 10
1005 B1 04
1007 8A 05
1009 E6 C0
100B FE CB
100D 74 0B
100F BA 1010
1012 4A
1013 75 FD
1015 47
1016 E2 EF
1018 EB E8
101A F4
101B
101B 09 05 06 0A
EQU
ORG
0C0H
1000H
BEGIN:
MOV BL,45H
START: MOV DI,OFFSET TABLE
MOV CL,04
REPT: MOV AL,[DI]
OUT PORT1,AL
DEC BL
JZ END
MOV DX,1010H
DELAY: DEC DX
JNZ DELAY
INC DI
LOOP REPT
JMP START
END: HLT
TABLE:
DB
9.5,6,0AH
RESULT:
Enter the above program and execute it. By converting the required step in decimal to hex
and entering the hex data at 1001 the motor rotates for so much steps and then stops.
Ex. no:4
Date:28-2-2012
THROW OF A DICE
126
AIM:
To simulate THROW OF A DICE using 8085 interrupts.
ALGORITHM:
STEP 1: Initialize the interrupt system by proper data.
STEP 2: Write the interrupt service routine at proper location (memory location)
STEP 3: Interrupt service routine is a program for dice simulation (counting from 0-6).
STEP 4: Loop the program control in a continuous mode.
STEP 5: Terminating point.
PROGRAM:
START: MVI A,0BH
SIM
EI
CAR: MVI A,01H
RPT: INR A
CPI 06H
JNZ RPT
JMP CAR
INRTS: DI
PUSH PSW
CALL UPDDT
POP PSW
EI
RETRN: RET
FFB1: C3 0F F0
RESULT
Press the Vect intr button in the keyboard, for each pressing a display will be there in
the display field (data field). I t displays from 00 to 06.
127
VIVA QUESTIONS
128
EC1304-Microprocessor And
Microcontroller
Laboratory
VIVA QUESTIONS
1.What is Microprocessor ?
It is a program controlled semiconductor device (IC}, which fetches, decode and
executes instructions.
2. What are the basic units of a microprocessor ?
The basic units or blocks of a microprocessor are ALU, an array of registers and control unit.
3.What is Software and Hardware?
The Software is a set of instructions or commands needed for performing a specific task by a
programmable device or a computing machine.
The Hardware refers to the components or devices used to form computing machine in which
the software can be run and tested. Without software the Hardware is an idle machine.
4. What is assembly language?
The language in which the mnemonics (short -hand form of instructions) are used to write a
program is called assembly language. The manufacturers of microprocessor give the mnemonics.
5. What are machine language and assembly language programs?
The software developed using 1's and 0's are called machine language, programs. The
software developed using mnemonics are called assembly language programs.
6. What is the drawback in machine language and assembly language, programs?
The machine language and assembly language programs are machine dependent. The
programs developed using these languages for a particular machine cannot be directly run on
another machine .
7. Define bit, byte and word.
A digit of the binary number or code is called bit. Also, the bit is the fundamental storage unit
of computer memory. The 8-bit (8-digit) binary number or code is called byte and 16-bit
binary number or code is called word.
8. What is a bus?
Bus is a group of conducting lines that carries data, address and control signals.
9. Why data bus is bi-directional?
The microprocessor has to fetch (read) the data from memory or input device for
processing and after processing, it has to store the data to memory or output device. Hence the
data bus is bi-directional.
129
10. Why address bus is unidirectional?

The address is an identification number used by the microprocessor to identify or access a
memory location or I / O device. It is an output signal from the processor. Hence the address bus
is unidirectional.
11. What is the function of microprocessor in a system?
The microprocessor is the master in the system, which controls all the activity of the
system. It issues address and control signals and fetches the instruction and data from memory.
Then it executes the instruction to take appropriate action.
12. What are the modes in which 8086 can operate?
The 8086 can operate in two modes and they are minimum (or uniprocessor) mode and
maximum ( or multiprocessor) mode.
13. What is the data and address size in 8086?
The 8086 can operate on either 8-bit or 16-bit data. The 8086 uses 20 bit address to access
memory and 16-bit address to access 1/0 devices.
14. Explain the function of M/IO in 8086.
The signal M/IO is used to differentiate memory address and 1/0 address When the
processor is accessing memory locations MI 10 is asserted high and when it is accessing 1/0
mapped devices it is asserted low.
15. Write the flags of 8086.
The 8086 has nine flags and they are
1. Carry Flag (CF)
2. Parity Flag (PF)
3. Auxiliary carry Flag (AF)
4. Zero Flag (ZF)
5. Sign Flag (SF)
6. Overflow Flag (OF)

7. Trace Flag (TF)
8. Interrupt Flag (IF)
9. Direction Flag (DF)
16. What are the interrupts of 8086?

The interrupts of 8085 are INTR and NMI. The INTR is general maskable interrupt
and NMI is non-maskable interrupt.
17. How clock signal is generated in 8086? What is the maximum internal clock frequency of
8086?
The 8086 does not have on-chip clock generation circuit. Hence the clock generator chip,
8284 is connected to the CLK pin of8086. The clock signal supplied by 8284 is divided by three
for internal use. The maximum internal clock frequency of8086 is 5MHz.
18. Write the special functions carried by the general purpose registers of 8086.
The special functions carried by the registers of 8086 are the following.
Register Special function
1. AX 16-bit Accumulator
130
2. AL 8-bit Accumulator
3. BX Base Register
4. CX Count Register
5. DX .Data Register
19. What is pipelined architecture?
In pipelined architecture the processor will have number of functional units and the execution
time of functional units are overlapped. Each functional unit works independently most of the
time.
20. What are the functional units available in 8086 architecture?
The bus interface unit and execution unit are the two functional units available in 8086
architecture.
21. List the segment registers of 8086.
The segment registers of 8086 are Code segment, Data segment, Stack segment and Extra
segment registers.
22. Define machine cycle.
Machine cycle is defined as the time required to complete one operation of accessing
memory, I/O, or acknowledging an external request. This cycle may consist of three to six Tstates.
23. Define T-State.
T-State is defined as one subdivision of the operation performed in one clock period.
These subdivisions are internal states synchronized with the system clock, and each T-State is
precisely equal to one clock period.
24. List the components of microprocessor (single board microcomputer) based system.
The microprocessor based system consist of microprocessor as CPU, semiconductor
memories like EPROM and RAM, input device, output device and interfacing devices.
25. Why interfacing is needed for 1/0 devices?
Generally I/O devices are slow devices. Therefore the speed of I/O devices does not
match with the speed of microprocessor. And so an interface is provided between system bus and
I/O devices.
26. What is the difference between CPU bus and system bus?
The CPU bus has multiplexed lines but the system bus has separate lines for each signal.
27..What does memory-mapping mean?
The memory mapping is the process of interfacing memories to microprocessor and
allocating addresses to each memory locations.
28..What is interrupt 1/0?
131
If the 1/0 device initiate the data transfer through interrupt then the 1/0 is called interrupt
driven 1/0.
29. Why EPROM is mapped at the beginning of memory space in 8085 system?
In 8085 microprocessor, after a reset, the program counter will have OOOOH address. If
the monitor program is stored from this address then after a reset, it will be executed
automatically. The monitor program is a permanent program and stored in EPROM memory. If
EPROM memory is mapped at the beginning of memory space, i.e., at OOOOH, then the
monitor program will be executed automatically after a reset.
30. What is the need for system clock and how it is generated in 8085?
The system clock is necessary for synchronizing various internal operations or devices
in the microprocessor and to synchronize the microprocessor with other peripherals in the
system.
31.What is DMA?
The direct data transfer between I/O device and memory is called DMA.
32. What is the need for Port?
The I/O devices are generally slow devices and their timing characteristics do not match
with processor timings. Hence the I/O devices are connected to system bus through the ports.
33.What is a port?
The port is a buffered I/O, which is used to hold the data transmitted from the microprocessor to
I/O device or vice-versa.
34.Give some examples of port devices used in 8085 microprocessor based system?
The various INTEL I/O port devices used in 8085 microprocessor based system are 8212, 8155,
8156, 8255, 8355 and 8755.
35. Write a short note on INTEL 8255?
The INTEL 8255 is a I/O port device consisting of 3 numbers of 8 bit parallel I/O ports. The
ports can be programmed to function either as a input port or as a output port in different
operating modes. It requires 4 internal addresses and has one logic LOW chip select pin.
36.What is the drawback in memory mapped I/0?
When I/O devices are memory mapped, some of the addresses are allotted to I/O devices and so
the full address space cannot be used for addressing memory (i.e., physical memory address
space will be reduced). Hence memory mapping is useful only for small systems, where the
memory requirement is less.
37. How DMA is initiated?
When the I/O device needs a DMA transfer, it will send a DMA request signal to DMA
controller. The DMA controller in turn sends a HOLD request to the processor. When the
processor receives a HOLD request, it will drive its tri-stated pins to high impedance state at the
end of current instruction execution and send an acknowledge signal to DMA controller. Now the
DMA controller will perform DMA transfer.
132
38. What is processor cycle (Machine cycle)?

The processor cycle or machine cycle is the basic operation performed by the processor. To
execute an instruction, the processor will run one or more machine cycles in a particular order.
39. What is Instruction cycle?
The sequence of operations that a processor has to carry out while executing the instruction is
called Instruction cycle. Each instruction cycle of a processor indium consists of a number of
machine cycles.
40. What is fetch and execute cycle?
In general, the instruction cycle of an instruction can be divided into fetch and execute cycles.
The fetch cycle is executed to fetch the opcode from memory. The execute cycle is executed to
decode the instruction and to perform the work instructed by the instruction.
41.What is Block and Demand transfer mode DMA?
In Block transfer mode, the DMA controller will transfer a block of data and relieve the bus
for processor. After sometime another block of data is transferred by DMA and so on. In Demand
transfer mode the DMA controller will complete the entire .data transfer at a stretch and then
relieve the bus to processor.
42. What is the need for timing diagram?
The timing diagram provides information regarding the status of various signals, when a
machine cycle is executed. The knowledge of timing diagram is essential for system designer to
select matched peripheral devices like memories, latches, ports, etc., to form a microprocessor
system.
43. How many machine cycles constitute one instruction cycle in 8085?
Each instruction of the 8085 processor consists of one to five machine cycles
.
44. Define opcode and operand.
Opcode (Operation code) is the part of an instruction / directive that identifies a specific
operation. Operand is a part of an instruction / directive that represents a value on which the
instruction acts.
45. What is opcode fetch cycle?
The opcode fetch cycle is a machine cycle executed to fetch the opcode of an instruction
stored in memory. Every instruction starts with opcode fetch machine cycle.
46. What operation is performed during first T -state of every machine cycle in 8085 ?
In 8085, during the first T -state of every machine cycle the low byte address is latched into
an external latch using ALE signal.
47. Why status signals are provided in microprocessor?
133
The status signals can be used by the system designer to track the internal operations of the
processor. Also, it can be used for memory expansion (by providing separate memory banks for
program & data and selecting the bank using status signals).
48. How the 8085 processor differentiates a memory access (read/write) and 1/0 access
(read/write)?
The memory access and 1/0 access is differentiated using 10 I M signal. The 8085
processor asserts 10 I M low for memory read/write operation and 10 I M is asserted high for 1/0
read/write operation.
49. When the 8085 processor checks for an interrupt?
In the second T -state of the last machine cycle of every instruction, the 8085 processor
checks whether an interrupt request is made or not.
50. What is interrupt acknowledge cycle?
The interrupt acknowledge cycle is a machine cycle executed by 8085 processor to get the
address of the interrupt service routine in-order to service the interrupt device.
51. How the interrupts are affected by system reset?
Whenever the processor or system is resetted , all the interrupts except TRAP are disabled.
fu order to enable the interrupts, El instruction has to be executed after a reset.
52. What is Software interrupts?
The Software interrupts are program instructions. These instructions are inserted at
desired locations in a program. While running a program, if software interrupt instruction is
encountered then the processor executes an interrupt service routine.
53. What is Hardware interrupt?
If an interrupt is initiated in a processor by an appropriate signal at the interrupt pin, then
the interrupt is called Hardware interrupt.
54. What is the difference between Hardware and Software interrupt?
The Software interrupt is initiated by the main program, but the Hardware interrupt is
initiated by an external device. In 8085, the Software interrupt cannot be disabled or masked but
the Hardware interrupt except TRAP can be disabled or masked.
55. What is Vectored and Non- Vectored interrupt?
When an interrupt is accepted, if the processor control branches to a specific address defined
by the manufacturer then the interrupt is called vectored interrupt. In Non-vectored interrupt
there is no specific address for storing the interrupt service routine. Hence the interrupted device
should give the address of the interrupt service routine.
56. List the Software and Hardware interrupts of 8085?
Software interrupts: RST 0, RSTl, RST 2, RST 3, RST 4, RST 5, RST 6 and RST 7.
Hardware interrupts: TRAP, RST 7.5, RST 6.5, RST 5.5 and INTR.
57. What is TRAP?
134
The TRAP is non-maskable interrupt of8085. It is not disabled by processor reset or after
reorganization of interrupt.
58. Whether HOLD has higher priority than TRAP or not?
The interrupts including TRAP are recognized only if the HOLD is not valid, hence
TRAP has lower priority than HOLD.
59. What is masking and why it is required?
Masking is preventing the interrupt from disturbing the current program execution. When
the processor is performing an important job (process) and if the process should not be
interrupted then all the interrupts should be masked or disabled. In processor with multiple
'interrupts, the lower priority interrupt can be masked so as to prevent it from interrupting, the
execution of interrupt service routine of higher priority interrupt.
60. When the 8085 processor accept hardware interrupt?
The processor keeps on checking the interrupt pins at the second T-state of last Machine
cycle of every instruction. If the processor finds a valid interrupt signal and if the interrupt is
unmasked and enabled then the processor accepts the interrupt. The acceptance of the interrupt is
acknowledged by sending an OOA signal to the interrupted device.
61. When the 8085 processor will disable the interrupt system?
The interrupts of 8085 except TRAP are disabled after anyone of the following operations
1. Executing El instruction.
2. System or processor reset.
3. After reorganization (acceptance) of an interrupt.
62. What is the function performed by Dl instruction?
The function of Dl instruction is to enable the disabled interrupt system.
63. What is the function performed by El instruction?
The El instruction can be used to enable the interrupts after disabling.
64. How the vector address is generated for the INTR interrupt of 8085?
For the interrupt INTR, the interrupting device has to place either RST opcode or CALL
opcode followed by l6-bit address. I~RST opcode is placed then the corresponding vector
address is generated by the processor. In case of CALL opcode the given l6-bit address will be
the vector address.
65. How clock signals are generated in 8085 and what is the frequency of the internal clock?
The 8085 has the clock generation circuit on the chip but an external quartz crystal or L C
circuit or RC circuit should be connected at the pins XI and X2. The maximum internal clock
frequency of 8085A is 3.03 MHz.
66. What happens to the 8085 processor when it is resetted?
When the 8085 processor is resetted it execute the first instruction at the OOOOH location.
The 8085 resets (clears) instruction register, interrupt mask bits and other registers.
135
67. What are the operations performed by ALU of 8085?

The operations performed by ALU of 8085 are Addition, Subtraction, Logical AND,
OR, Exclusive OR, Compare Complement, Increment, Decrement and Left & Right shift.
68. What is a flag?
Flag is a flip flop used to store the information about the status of the processor and the
status of the instruction executed most recently.
69. List the flags of 8085
There are five flags in 8085. They are sign flag, zero flag, Auxiliary carry flag, parity flag
and carry flag.
70. What is the Hardware interrupts of 8085?
The hardware interrupts in 8085 are TRAP, RST 7.5, RST 6.5 and RST 5,5. 41.
71.Which interrupt has highest priority in 8085? What is the priority of other interrupts?
The TRAP has the highest priority, followed by RST 7.5, RST 6.5, RST 5.5 and INTR.
72 What is an ALE?
The ALE (Address Latch Enable) is a signal used to demultiplex the address and data
lines, using an external latch. It is used to enable the external latch.
73. Explain the function of IO/M in 8085.
The IO/M is used to differentiate memory access and I/O access. For IN and OUT
instruction it is high. For memory reference instructions it is low.
74. Where is the READY signal used?
READY is an input signal to the processor, used by the memory or I/O devices to get
extra time for data transfer or to introduce wait states in the bus cycles.
75. What is HOLD and HLDA and how it is used?
Hold and hold acknowledge signals are used for the Direct Memory Access (DMA) type
of data transfer. The DMA controller place a high on HOLD pin in order to take control of the
system bus. The HOLD request is acknowledged by the 8085 by driving all its tristated pins to
high impedance state and asserting HLDA signal high.
76.What is Polling?
Polling is a scheme or an algorithm to identify the devices interrupting the processor.
Polling is employed when multiple devices interrupt the processor through one interrupt pin of
the processor.
77. What are the different types of Polling?
The polling can be classified into software and hardware polling. In software
polling the entire polling process is govern by a prograrn.1n hardware polling, the hardware
takes care of checking the status of interrupting devices and allowing one by one to the
processor.
136
78.What is the need for interrupt controller?

The interrupt controller is employed to expand the interrupt inputs. It can handle the
interrupt request from various devices and allow one by one to the processor.
79. List some of the features of INTEL 8259 (Programmable InterruptController)
1. It manage eight interrupt request
2. The interrupt vector addresses are programmable.
3. The priorities of interrupts are programmable.
4. The interrupt can be masked or unmasked individually.
80. What is a programmable peripheral device ?
If the functions performed by a peripheral device can be altered or changed by a
program instruction then the peripheral device is called programmable device. Usually the
programmable devices will have control registers. The device can be programmed by sending
control word in the prescribed format to the control register.
81. What is synchronous data transfer scheme?
For synchronous data transfer scheme, the processor does not check the readiness of the
device after a command have been issued for read/write operation. fu this scheme the processor
will request the device to get ready and then read/W1.ite to the device immediately
after the request. In some synchronous schemes a small delay is allowed after the request.
82. What is asynchronous data transfer scheme?
In asynchronous data transfer scheme, first the processor sends a request to the device
for read/write operation. Then the processor keeps on polling the status of the device. Once the
device is ready, the processor execute a data transfer instruction to complete the process.
83. What are the operating modes of 8212?
The 8212 can be hardwired to work either as a latch or tri-state buffer. If mode (MD) pin is
tied HIGH then it will work as a latch and so it can be used as output port. If mode (MD) pin is
tied LOW then it work as tri- state buffer and so it can be used as input port.
84. Explain the working of a handshake output port
In handshake output operation, the processor will load a data to port. When the port
receives the data, it will inform the output device to collect the data. Once the output device
accepts the data, the port will inform the processor that it is empty. Now the processor can load
another data to port and the above process is repeated.
85.What are the internal devices of 8255 ?
The internal devices of 8255 are port-A, port-B and port-C. The ports can be programmed
for either input or output function in different operating modes.
86. What is baud rate?
The baud rate is the rate at which the serial data are transmitted. Baud rate is defined as l /
(The time for a bit cell). In some systems one bit cell has one data bit, then the baud rate and
bits/sec are same.
87. What is USART?
137
The device which can be programmed to perform Synchronous or Asynchronous

serial communication is called USART (Universal Synchronous Asynchronous Receiver
Transmitter). The INTEL 8251A is an example of USART.
88. What are the functions performed by INTEL 8251A?
The INTEL 825lA is used for converting parallel data to serial or vice versa. The data
transmission or reception can be either asynchronously or synchronously. The 8251A can be used
to interface MODEM and establish serial communication through MODEM over telephone lines.
89. What is an Interrupt?
Interrupt is a signal send by an external device to the processor so as to request the
processor to perform a particular task or work.
90. What are the control words of 8251A and what are its functions ?
The control words of 8251A are Mode word and Command word. The mode word
informs 8251 about the baud rate, character length, parity and stop bits. The command word can
be send to enable the data transmission and reception.
91. What are the information that can be obtained from the status word of 8251 ?
The status word can be read by the CPU to check the readiness of the transmitter or receiver
and to check the character synchronization in synchronous reception. It also provides
information regarding various errors in the data received. The various error conditions that can
be checked from the status word are parity error, overrun error andframing error.
92. Give some examples of input devices to microprocessor-based system.
The input devices used in the microprocessor-based system are Keyboards, DIP switches,
ADC, Floppy disc, etc.
93. What are the tasks involved in keyboard interface?
The task involved in keyboard interfacing are sensing a key actuation, Debouncing the key
and Generating key codes (Decoding the key). These task are performed software if the keyboard
is interfaced through ports and they are performed by hardware if the keyboard is
interfaced through 8279.
94. How a keyboard matrix is formed in keyboard interface using 8279?
The return lines, RLo to RL7 of 8279 are used to form the columns of keyboard matrix. In
decoded scan the scan lines SLo to SL3 of 8279 are used to form the rows of keyboard matrix. In
encoded scan mode, the output lines of external decoder are used as rows of keyboard
matrix.
95. What is scanning in keyboard and what is scan time?
The process of sending a zero to each row of a keyboard matrix and reading the columns
for key actuation is called scanning. The scan time is the time taken by the processor to scan all
the rows one by one starting from first row and coming back to the first row again.
96. What is scanning in display and what is the scan time?
138
In display devices, the process of sending display codes to 7 segment LEDs to display the
LEDs one by one is called scanning ( or multiplexed display). The scan time is the time taken to
display all the 7-segment LEDs one by one, starting from first LED and coming back
to the first LED again.
97. What are the internal devices of a typical DAC?
The internal devices of a DAC are R/2R resistive network, an internal latch and current to
voltage converting amplifier.
98. What is settling or conversion time in DAC?
The time taken by the DAC to convert a given digital data to corresponding analog signal is
called conversion time.
99. What are the different types of ADC?
The different types of ADC are successive approximation ADC, counter type ADC flash
type ADC, integrator converters and voltageto- frequency converters.
100. Define stack
Stack is a sequence of RAM memory locations defined by the programmer.
101. What is program counter? How is it useful in program execution?
The program counter keeps track of program execution. To execute a program the starting
address of the program is loaded in program counter. The PC sends out an address to fetch a byte
of instruction from memory and increments its content automatically.
102. How the microprocessor is synchronized with peripherals?
The timing and control unit synchronizes all the microprocessor operations with clock
and generates control signals necessary for communication between the microprocessor and
peripherals.
103. What is a minimum system and how it is formed in 8085?
A minimum system is one which is formed using minimum number of IC chips, The 8085
based minimum system is formed using 8155,8355 and 8755.
104. What is mean by microcontroller
A device which contains the microprocessor with integrated peripherals like memory,
serial ports, parallel ports, timer/counter, interrupt controller, data acquisition interfaces like
ADC,DAC is called microcontroller.
105.List the features of 8051 microcontroller?
The features are
*single_supply +5 volt operation using HMOS technology.
*4096 bytes program memory on chip(not on 8031)
*128 data memory on chip.
*Four register banks.
*Two multiple mode,16-bit timer/counter.
*Extensive boolean processing capabilities.
139
*64 KB external RAM size

*32 bidirectional individually addressible I/O lines.
*8 bit CPU optimized for control applications.
106.Explain the operating mode0 of 8051 serial ports?
In this mode serial enters &exits through RXD, TXD outputs the shift clock.8 bits are
transmitted/received:8 data bits(LSB first).The baud rate is fixed at 1/12 the oscillator frequency.
107 Explain the operating mode2 of 8051 serial ports?
In this mode 11 bits are transmitted(through TXD)or received (through RXD):a start bit(0),
8 data bits(LSB first),a programmable 9th data bit ,& a stop bit(1).ON transmit the 9th data bit
(TB* in SCON)can be assigned the value of 0 or 1.Or for eg:, the parity bit(P, in the PSW)could
be moved into TB8.On receive the 9th data bit go in to the RB8 in Special Function Register
SCON, while the stop bit is ignored. The baud rate is programmable to either 1/32or1/64 the
oscillator frequency.
108. Explain the mode3 of 8051 serial ports?
In this mode,11 bits are transmitted(through TXD)or received(through RXD):a start bit(0),
8 data bits(LSB first),a programmable 9th data bit ,& a stop bit(1).In fact ,Mode3 is the same as
Mode2 in all respects except the baud rate. The baud rate in Mode3 is variable. In all the four
modes, transmission is initiated by any instruction that uses SBUF as a destination register.
Reception is initiated in Mode0 by the condition RI=0&REN=1.Reception is initiated in other
modes by the incoming start bit if REN=1.
109.Explain the interrupts of 8051 microcontroller?
The interrupts are:
Vector address
External interrupt 0 : IE0 : 0003H
Timer interrupt 0 : TF0 : 000BH
External interrupt 1 : IE1 : 0013H
Timer Interrupt 1 : TF1 : 001BH
Serial Interrupt
Receive interrupt : RI : 0023H
Transmit interrupt: TI : 0023H
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8085 MICROPROCESSOR

Address bus it is a group of 16-bit lines generally identified as A 0 A15. The

8 BIT ADDITION & SUBTRACTON

Clear D register for Carry.

Move the data 00 into reg C

Move 09 into accumulator.

Move 05 into register B.

Do ADD/SUB b/w A & B reg

Jump to 410B , if there is no carry

Store [A] into 4500

Move [C] into [A]

Store [A] into 4501

Stop the Execution

Move immediate data 00 to C

Move immediate data 05 to B reg

Move immediate data 04 to D reg

Add content of D with A.

Store Accumulator content to 1000

Move content of C reg to A register

Store Accumulator content to 1001

Halt the operation

Data : B = 05, D=04,

Move immediate data 00 to H reg.

Move immediate data 08 to A reg

Move immediate data 02 to B reg

Compare content of A with B reg.

Jump if there exist carry to L1

Subtract B from A register

Store the accumulator content to A010

Move content of H to Aregister

Store the accmulator content to A011

Halt the operation

Data : (4150) = 08 - Divisor

16 BIT ADDITION & 16 BIT SUBTRACTION

b) SUBTRACTION (16 bit)

Clear D register for carry.

Load 16 bit data to HL reg pair

Load next 16 bit data BC reg pair

Jump if no carry to 800D

Move the content of D reg to A

Store Carry at 9002.

Halt the operation

Clear H register for carry.

Load 16 bit data to BC reg pair

Load next 16 bit data DE reg pair

Move the content of C reg to A reg

Subtract A reg with E reg.

Store A reg at 9000

Move the Content of H reg to A reg

Store Carry at 9002.

Halt the operation

1. Microprocessor kit 8085

Set a counter register D

Initialize address to load data

Jump if no carry to 800D or

Jump if carry to 800D

Jump if no zero to 8006

Store largest/smallest Number at 9000

Halt the operation

Data : (4150) = 05 - No. of elements,

SMALLEST ELEMENT IN AN ARRAY

1. Place all the elements of an array in the consecutive memory locations.