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Sub-20nm CMOS FinFET Technologies

Yang-Kyu Choi, Nick Lindert, Peiqi Xuan, Stephen Tang*, Daewon Ha, Erik Anderson',
Tsu-Jae King, Jeffrey Bokor, and Chenming Hu
Department of Electrical Engineering and Computer Sciences
University of California, Berkeley, CA 94720, USA
*Intel, Hillsboro, OR 97 124
'Lawrence Berkeley National Laboratory, Berkeley, CA
E-mail:ykchoi@eecs.berkeley.edu, Tel:+l-5 10-643-2558, Fax:+l-5 10-643-2636
a pad oxide was thermally grown to a thickness of 4nm to
relieve
the stress between the ensuing nitride hard mask and
Abstract
the Si. Silicon nitride was deposited to a thickness of 50nm
A simplified fabrication process for sub-2Onm
on the pad oxide, to serve as a hard mask to protect the SiCMOS double-gate FinFETs is reported. It is a more
fin during the subsequent poly-SiGe gate etch. For the
manufacturable process and has less overlap capacitance
spacer FinFET, a 200nm-thick sacrificial layer of Sio.4Geo.6
compared to the previous FinFET [1][2]. Two different
was
deposited by low pressure chemical vapor deposition
patterning approaches: e-beam lithography and spacer
(LPCVD)
onto the nitride hard mask and patterned (to
lithography, are developed. Selective Ge by LPCVD is
support the spacers used to define the Si fin) with optical
utilized to fabricate raised S/D structures which minimize
lithography and plasma etching. Afterwards, phosphoparasitic series resistance and improves drive current.
silicate glass (PSG) was deposited and etched
Introduction
anisotropically, and the sacrificial Sio.4Ge~.6
layer was then
Sub-1OOnm NMOS [ l ] and PMOS [2] FinFETs have
removed using H20: H202:NH40H(5:l:l) at 75OC [5]. The
previously been separately reported. These double-gate
PSG spacers are subsequently used as a hard mask to define
MOSFET structures were demonstrated to be robust against
the narrow Si fins. Note that the PSG thickness determines
short-channel effects, but they required a complicated
the fin width. For a given lithography pitch, the fin density is
fabrication process which yielded large overlap capacitance
doubled, resulting in twice the drive current as shown in Fig.
between the gate and source/drain (S/D) regions. A simpler,
1. In principle, a FinFET fabricated using this process
more manufacturable process similar to a conventional SO1
produces four times the drive current of a conventional bulkCMOS process was recently developed for a quasi- planar
CMOS device: a factor of two comes from the doubled fin
FinFET structure with much less gate-to-S/D overlap [3].
density, and another factor of two comes from the doubleWe report here sub-2Onm gate-length CMOS
gate structure. Fig. 2 shows the spacer FinFET structure.
FinFETs. Novel process technologies -- fin formation by
The Si fins are defined by the PSG spacers, while the SID
spacer lithography and raised S/D by selective Ge deposition
contact areas are defined using photoresist, which can also
-- for nanoscale CMOS are demonstrated. Spacer FinFETs be used to define much wider fins. The ring-like PSG profile
achieve twice the drive current within a given pitch (limited
is not transferred to the nitride/oxide/Si-substrate (Fig. 3).
by optical or e-beam lithography), more uniform fin width,
One drawback of a spacer lithography technology is that it
and ultimately narrower fins, beyond the lithographic limit.
provides only one line width [6]. But by combining the
Standard FinFETs fabricated by e-beam lithography, which
spacer process with a conventional photoresist masking
is more straightforward than spacer lithography, are also
process, we overcome this limitation. After Si patterning,
demonstrated. Various gate materials are used to study gate
2.5nm thermal oxide (Tax) was grown and undoped Si0.6Ge0.4
work function engineering for threshold voltage control.
was deposited. The Sio.6Geo.4layer was then doped with P or
Rapid thermal annealing (RTA) before gate oxidation is
B implantation and planarized with chemical mechanical
used to reduce the density of interface traps along the etched
polishing (CMP). The planarized gate provides wider
fin sidewalls for better performance [4]. The dependence of
process windows for lithography (depth-of-focus) and gate
drive current on fin S/D extension length is investigated.
etch (margin for eliminating stringers). Fig. 4 shows an SEM
Selective deposition of Ge is demonstrated to be effective
profile of Si fins (Wfm=40nm)defined by PSG spacers and
for reducing the series resistance of the S/D extensions.
planarized gate electrode (Lg=6Onm). As can be seen from
Good CMOS performance is achieved by spacer FinFETs
the Figure, the gate p0ly-Si~,6Ge~,~
was completely removed
and standard FinFETs.
without any stringers and residues. To investigate the drive
Device Fabrication and Characterization
current dependence on extension length (SI and S2 in Fig. 4),
Boron-doped ( 1 ~ 1 0 ' ~ c m(100)
- ~ ) SO1 wafers served intentional offsets were designed into the mask set. Source
as the starting material. N-type body doping (1~10''cm-~
or and drain regions were doped by masked 5~10'~cm-'
3OkeV
2~10'~crn")
was achieved with P implantation. The SO1 film P implantation for NMOS and 5~10'~cm-'lOKeV B
was reduced from lOOnm to 50nm by thermal oxidation and

0-7803-7050-3/01/$10.00 02001 IEEE

19.1.I

IEDM 0 1-421

implantation for PMOS after gate sidewall spacer formation. effects are clearly improved as fin width is narrowed as
RTA (900C, lmin) was used to activate the dopants, and expected. V, is less sensitive to body type and doping
was followed by a forming gas anneal (400C, 30min). No concentration with Ar RTA(90O0C, lmin) prior to gate
silicidation or metallization was used for the devices oxidation as shown in Fig. 16 . Ar RTA after Si-fin
reported here. Fig. 5 shows the TEM cross-section
formation and before gate oxidation returns V, to the
40nm-wide fin defined by PSG spacer technology.
predicted value because Ar annealing reduces interface trap
A standard FinFET using e-beam lithography for fin density. Fig. 17 shows that drive current is strongly affected
patterning is more straightforward. Body doping (2~1O~cm by extension resistance. Silicidation and/or a raised S/D
3, was achieved with P implantation. The overall process
process is necessary to improve drive current. With selective
flow was the same except that Si-fins were defined not by Ge raised S/D [lo] for standard FinFET, 28% drive current
spacer lithography but by e-beam lithography and CMP for improvement was observed as shown in Fig. 18.
gate planarization was not used. Fig.6 shows a schematic
Summary
diagram of a standard FinFET with selective Ge on the S/D
Sub-2Onm gate length CMOS FinFETs are
Si-fin. Fig. 7 shows SEM picture of a lOnm Si-fin and 20nm demonstrated and novel technologies including spacer
gate. Even though the gate length in the top view of SEM lithography and selective Ge raised S/D are developed. The
photograph (Fig. 7) is 20nm, the real gate length on the spacer lithography technology was developed for better
channel is shorter than 20nm because of T-shaped gate uniformity of fins and higher device density producing more
profile, which is generated in the over etch step. Sub-lOnm drive current. Threshold voltage (V,) is less sensitive to body
Si-fins were patterned with e-beam lithography and doping type and concentration compared to bulk-CMOS and
subsequent ashing-trimming [7]. 2.lnm gate oxide (T0J was more strongly controlled by gate work function. Measured
thermally grown and in-situ boron-doped Sio6Geo.4 was drive current is strongly affected by the S/D extension
deposited to form the gate stack. Fig. 8 shows cross- resistance. Selective Ge deposition for raised S/D is used to
sectional TEM picture of selective Ge raised S/D on the S/D reduce this extension resistance and results in 28%
extension.
improvement of drive current.
NMOS drive current of the standard FinFET
Acknowledgement
(Lg=20nm, Wfm=lOnm, T0,=2.1nm) is 365pNpm and
The authors would ldce to thank the University of
PMOS drive current is 270pA/pm at IVg-V,I=lV and Vd=lv. California-BerkeleyMicrolab staffs for their supports in
Selective Ge for raised S/D was not used for this wafer. Off- device fabrication. This research was sponored by SRC
state current at the intersection of NMOS and PMOS current under Contract 2000-NJ-850 and MARC0 contract 2001is 70nA/pm as shown in Fig. 9. The relatively low drive MT-887.
current is due to the relatively thick To, and higher S/D
References
extension resistance of the narrow fin. For the spacer [ l ] D. Hisamoto, W.-C. Lee, et. al., FinFET-A Self-Aligned Double-Gate
FinFET, NMOS drive current for Lg=60nm, Wf,=40nm, and MOSFET Scalable to 20nm, IEEE Trans. Electron Devices, vo1.47,
p.2320-2325,2000.
T0,=2.1nm is 500pNpm and PMOS is 380pA/pm at IV,[2] X. Huang, W.-C. Lee, C. Kuo, D. Hisamoto, L. Cang, J. Kedzierski, E.
V,I=1V and Vd=lv. Drive current is normalized with twice Anderson,
H. Takeuchi, Y.-K. Choi, K. Asano, V. Subramanian, T.-J.
the fin height (2*TS1),which is a conservative definition of King, J. Bokor, C. Hu, Sub 50-nm FinFET : PMOS, IEDM Tech. Dig.,
channel width in the double-gate structure. With the p.67-70, 1999.
conventional definition of channel width in double-gate, [3] N. Lindert, Y.-K. Choi, L. Chang, E. Anderson, W. Lee, and T.-J.
King, J. Bokor, C. Hu,Quasi-Planar NMOS FinFETs with Sub-100nm
NMOS current is 1000pA/pm and PMOS current is Gate Lengths, 5ghDevice Research Conference, p.26-27,2001.
760pNpm. We speculate that the low NMOS drive current [4] H. Fukuda, M. Yasuda, T. Iwabuchi, S. Kaneko, T. Ueno, I. Ohdomari,
is due to degraded electron mobility caused by sidewall Process dependence of the Si02/Si(100) interface trap density of ultrathin
roughness of the Si-fin, which is generated by the dry etch SiOz films, Journal ofApplied Physics, 72, p. 1906-1 1, 1992.
[5] F.S. Johnson, D.S. Miles, D.T. Grider, J.J. Wortman, Selective
process. Hole mobility is more immune to these surface Chemical Etching of Polycrystalline SiGe Alloys with Respect to Si and
roughness effects [8]. Off-state current of the spacer FinFET Si02, Journal ofthe Electronic Materials, v01.21, p.805-810, 1992.
is less than lnA/um at the intersection of NMOS and PMOS [6] J.T. Horstmann, U. Hilleringmann, K.F. Goser, Matching Analysis
current as shown in Fig. 11. The higher drive current despite of Deposition Defined 50-nm MOSFETs, IEEE Trans. Electron
Devices, vo1.45, p.299-306, 1998.
thicker To, of the spacer FinFET is due to the wider fin [7] K. Asano, Y.-K. Choi, T.-J. King, C. Hu, Patterning sub-30-nm
width (40nm). Figs. 13, 14, and 15 show V, roll-off, MOSFET gate with i-line lithography, IEEE Trans. Electron Devices,
subthreshold swing, and DIBL for various fin widths, ~01.48,p.1004-6, 2001
respectively. These excellent short channel effects even with [8] C. J. Petti, J. P. McVittie, J. D. Plummer, Characterization of Surface
Mobility on the
Sidewalls of Dry-Etched Trenches, IEDM Tech. Dig.,
relatively thick gate oxide (2.1 nm) come from the fact that p.104-107, 1988
extending sidewalls (undercut as shown in Fig. 5) of the gate [9] J.-T. Park, J.-P. Colinge, C.H. Diaz, Pi-Gate SO1 MOSFET, IEEE
ElecfronDevice Leffers,v01.22, p.405-406, 2001.
poly- Sio,6Geo.4
in the buried oxide shields the back of the
[IO] Y.-K. Choi, D. Ha, T.-J. King, C. Hu, Ultra-Thin Body
channel region from electric fields from the drain [9]. The
PMOSFETs with Selectively Deposited Ge Source/Drain, 200f Symp.
relatively poorer short channel effects in PMOS are caused on VLSI Tech., p. 19,2001.
by hgher B diffusivity than P in the S/D. Short-channel

422-IEDM 01

19.1.2

Optical or e-beam
lithography pitch

Optical or e-beam

Removal of dummy
and SI-fin etch

Fig. 1 Comparison of tin density between conventional


lithography and spacer lithography technology. The spacer
lithography technology produces twice the density of a
conventional lithographic technology

Fig. 3 SEM photograph of


patterned photo resist profile for
S / D contact pads and PSG spacers
for narrow Si-fins, respectively.

Oxide hard

Fig. 2 Schematic diagram of spacer FinFET.

Fig. 4 SEM photograph of spacer


FinFET. S I and Sz denotes
intentional offset to investigate
drive current dependence on fin
series resistance. Planarized gate
was
achieved
with
CMP.
(Wfm=40nm,Lg=60nm)

Fig. 5 TEM photograph (x-x


cross-section in Fig. 2) of Si-fin by
spacer lithography. (Wfm=40nm,
Tsi=SOm)

mask: 50nm

Si,,Ge,,: 250nrn-r

Cross-section of z-z direction

Fig. 6 Schematic diagram of a


standard FinFET.

Fig. 7 SEM photograph of Si-fin


and gate profile (Standard
FinFET)

19.1.3

Fig. 8 TEM cross-section (z-z


direction in Fig. 6) of selective
Ge raised S/D. Top portion of the
fin was recessed during spacer
etch.

IEDM 0 1-423

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-1.5-1.2-0.9 -0.6-0.3 0.0 0.3 0.6 0.9 1.2 1.5

2.0

Drain Voltage, V, M
Fig. 10 I d - V d characteristics of Lg=20nm, wfi,=lonm,
and ToX=2.1nm (Standard FinFET). Current is
normalized with 2*Tsi

Gate Voltage, V, [VI

Fig. 9 Subthreshold I d - v , characteristics of L,= :20nm,


Wfi,=lOnm, and T0,=2. lnm (Standard FinFET).

700,

;i

600

600

500

500

400

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300

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zoo

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.-c
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Gate Voltage, VB[VI

Fig. 11 Subthreshold I d - v , characteristics of


Lg=60nm, Wfm=40nm, and TOx=2.5nm (Spacer
FinFET).
1.4I
1.2>- 1.0d 0.8:
m
= 0.6- 0.4:

Drain Voltage, V, [VI

Fig. 12 I d - V d characteristics of Lg=6Onm, Wfm=40nm,


and TOx=2.5nm(Spacer FinFET). Current is normalized
with 2*Tsi.

a W,=lOnm

W,=34nm
W,=42nm

90

WRn=lOnm
WCn=26nm

$ 0.0
O
-100
-120

PMOS
-140
-160
0 20 40 60 80 100120140160

0 10 20 30 40 50 60 70 80
Gate Length, L, [nm]

Fig. 13 Threshold voltage rolloff characteristics for various


Wfm(Standard FinFET).

2x10tm3 tx10cm~

>-

-02

a Ar (900C,lmin)
0

-o.
0

-E

Fig. 15 Drain induced barrier


lowering (DIBL) for various Wrm
5$Standard
0
FinFET).
450: - - - - Before Selective

.
O

Fig. 16 Threshold voltage


dependence on body type (N-type
vs.
P-type)
and
doping
concentration for N+Sio.6Geo.4
gate and Ar ayealing effect.

Gate Length, L, [nm]

NoAr

-0.30 20 40 60 80 1001201401

Fig.14 Subthreshold swing for


various Wfm(Standard FinFET)

Gate Length, L, [nm]

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Gap. S, [nml

Fig. 17 Measured drive current


dependence on extension length
between gate edge and S/D pads.

19.1.4

0.0

0.3

0.6

0.9

1.2

1.5

M
Fig. 18 Comparison of dnve
current before and after selective
Ge deposition for raised S/D.
Drain Voltage, V,

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