Beruflich Dokumente
Kultur Dokumente
1. A two stage CMOS op-amp is found to have a capacitance between the output
mode and ground of 1 pf. If it is desired to have a unity gain bandwidth ft of 100
MHz with a phase margin of 750C, what must be gm6. Assume the compensation
capacitor Cc and adjusted to place the transmission zuo at infinity. What is the R
value? If first state is operated at (V0v) = 0.2v, what is the structures. If the first
stage bias connect I=200 μ A , What is the required CC?
3.a] Design a switched capacitor first-order circuit that has a low frequency gain as 10
and a-3dB frequency of 1 KHz. Given the value of the capacitor ratios α1 and
α 2 , use clock frequency of 100 KHz.
b] An inventing switching capacitor integrator is shown below. If the gain of the op-
amp is A0, find the z-domain transfer function of this integrator.
4.a] What are the basic differences between buffered and unbuffered CMOS devices?
b] Why is ECL called a non-saturating logic? What is the main advantage of this
ECL logic? With the help of a relevant circuit briefly describe the operation of
ECL or/NOR logic.
5.a] Write a VHDL code to model a 4-bit carry look ahead adder circuit in Behavioral
model.
b] Model a decade counter using dataflow model in VHDL. Draw the timing wave
form.
Cont…2
Code No: A5505 ::2::
7.a] Briefly describe the principle operation of a simultaneous or flash type A/D
converter. What are the merits and demerits of this type of converter.
b] A certain 12-bit successive approximation type A/D converter has a full scale
input as 10v. It operates at a clock frequency of 1 MHz. Determine the conversion
time for input of 7.5v.
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