IEEE TRANSACTIONS ON NANOTECHNOLOGY, VOL. 1, NO.

4, DECEMBER 2002

233

Electrical Characteristics of FinFET With Vertically

Nonuniform Source/Drain Doping Profile
Dong-Soo Woo, Jong-Ho Lee, Woo Young Choi, Byung-Yong Choi, Young-Jin Choi, Jong Duk Lee, Member, IEEE,
and Byung-Gook Park, Member, IEEE

AbstractThe effects of a nonuniform source/drain (S/D)

doping profile on the FinFET characteristics are investigated
using three-dimensional device simulation. With a fixed S/D
doping profile, larger silicon-on-insulator (SOI) thickness can
suppress short-channel effects due to the coexistence of longer
channel regions. There can be some design margin in the channel
thickness due to this reduced short-channel effect. Drain saturation current in FinFET is proportional to the effective device
width and SOI thickness.
To determine the appropriate SOI thickness of FinFET, alternating current (ac) characteristics are investigated. Device capacitance increases with SOI thickness, but this is not for the gate delay,
as the drive current also increases and compensates for the increase
of capacitance. When driving a constant capacitance load such as
interconnect, devices with larger drain current or thicker SOI are
more favorable for the fixed S/D doping condition.
Index TermsDouble-gate, FinFET, nonuniform source/drain
(S/D), silicon-on-insulator (SOI).

I. INTRODUCTION

S CMOS dimensions shrink down into a few tens of

nanometer regime, double-gate (DG) MOSFETs attract
much attention due to their robustness to the short-channel
effect. Among DG CMOS devices, the FinFET [1] reported
by Hisamoto et al., is considered to be the most promising
candidate due to its simple process, which is compatible with
the conventional planar process.
There have been many simulation studies on the DG
MOSFET [2], but those studies were performed using the
two-dimensional (2-D) device simulation. That was reasonable,
as the FinFET with a vertically uniform source/drain (S/D)
doping profile has no 3-D structural issue. The first FinFET
[1] structure has highly doped polysilicon as an S/D pad.
However, to dope the S/D region of FinFET for CMOS, ion implantation is necessary. Recent researches on FinFET reported
by Choi [3] and Kedzierski [4] used an ion-implantation process
to dope the S/D region. A vertically uniform S/D doping profile
can be obtained in a single-fin device through a tilted extension
implant. There are, however, some cases in which a uniform
S/D doping profile cannot be easily obtained. For example,
Manuscript received June 8, 2002; revised October 9, 2002. This work was
supported by the BK21 Program, by the National Research Laboratory Project
of Ministry of Science and Technology, Korea, and by the Collaborative Project
for Excellence in Basic System IC Technology. This paper was presented in part
at the 2002 IEEE Silicon Nanoelectronics Workshop, Honolulu, HI, June 910,
2002.
The authors are with the Interuniversity Semiconductor Research Center
(ISRC) and School of Electrical Engineering, Seoul National University, Seoul
151-742, Korea (e-mail: woods@smdl.snu.ac.kr; bgpark@snu.ac.kr).
Digital Object Identifier 10.1109/TNANO.2002.807373

Fig. 1. Device structure used in this study. Two gates are located at both sides
of an ultra-thin channel. As S/D doping is performed vertically (y direction)
nonuniformly, device channel length (L ) varies along the device width
direction (y direction). S/D is located at the far end of channel direction (x
direction).

if the S/D regions fan out right at the channel edge, tilted
implantation would not be very useful. Another example would
be a multifin device with high aspect ratio fins. Tilted extension
implants may not be adequate, due to shadow effect. Besides,
zero or small-angle implant is simpler and easier in terms of
fabrication, as long as the device characteristics do not show
degradation.
In this paper, we have studied the effects of a nonuniform
doping profile along the device width direction on the device
characteristics using analytical profiles. Following that, the
behavior of the devices electrical characteristics is discussed.
Finally, we present the device design guidelines for those
device geometrical parameters such as silicon-on-insulator
(SOI) thickness, using real doping profiles obtained from the
2-D process simulation.
II. SIMULATION SCHEME
The device used in this study is shown in Fig. 1. Two gates are
located at both sides of an ultra-thin channel. As S/D doping is
performed vertically ( direction) nonuniformly, device channel
) varies along the device width direction ( direclength (
tion). S/D is located at the end of channel direction ( direction).
In this paper, S/D doping profile is invariant along the direction. To investigate electrical characteristics of the device,
a 2-D doping profile is enough. A simple analytical profile is
shown in Fig. 2. Dopant concentration of the uniform region
was 3 10 cm and it decays with a Gaussian tail outside
the uniform region. The characteristic length of the Gaussian
tail is fixed to 4 nm in this paper, and the junction abruptness
was about 2.5 nm/decade along the channel length direction.
The latter part of this paper treats real doping profiles obtained
from ion implantation and thermal annealing. In that case, 2-D
doping profiles were obtained from the 2-D process simulation.

1536-125X/02$17.00 2002 IEEE

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IEEE TRANSACTIONS ON NANOTECHNOLOGY, VOL. 1, NO. 4, DECEMBER 2002

Fig. 2. S/D doping profile used in this study. Doping level of the uniform
region is 3 10 cm , and that in the nonuniform region decays with a
Gaussian tail whose characteristic length of 4 nm and the junction abruptness
was about 2.5 nm/decade. The effective device width is defined as the length
of junction which is controlled by the gate.

(a)

To investigate the device short-channel effect, a simple driftdiffusion model is used as it is enough for our purpose. This
model is also enough for studying the trend of the device current.
The gate voltage, which results in 0.1 A per unit-device
width in micrometers, was chosen to be the threshold voltage
of the device. We used twice the SOI thickness as the device
width, which is generally the case in FinFET. We adjusted the
V to be 0.2 V by
threshold voltage of FinFET at
varying the gate workfunction, and this is consistent with the
previous study reported by Chang [2]. Doping level of boron
doped p-type channel was 1 10 cm , and the gate oxide
was 2 nm.
In this paper, short-channel effect was evaluated using draininduced barrier lowering (DIBL) as a major parameter. DIBL
was obtained from the change of threshold voltage as drain bias
changes 1 V. Drain saturation current was the current when
V. Total currents of the devices with different SOI thicknesses were compared, and they were not divided by the channel width. We took this approach, since the
important factor in the very large scale integration (VLSI) application is a planar active area of the device, and the drive current can be controlled by the number of fins, not necessarily by
the variation of device width [6].
III. SIMULATION RESULTS
Fig. 3 shows DIBL and drain saturation current characteristics of the simulated devices. The effect of the increase of
) with fixed uniform doping profile depth
SOI thickness (
) is shown in Fig. 3(a), and that of the increase of doping
(
of 50 nm is shown in Fig. 3(b).
profile depth at fixed
fixed at 30 nm,
varied from
In the device with
3080 nm. In this case, DIBL reduces and drain saturation cur) increases, with an increase of
. For the same
rent (
, smaller
causes reduced DIBL and smaller drain
saturation current.
To investigate the origin of reduced DIBL, we obtained the
potential profiles of each device along the vertical or the width
) just bedirection ( direction) at the channel center (
nm) from
neath the gate oxide, and channel interface (
the Si/SiO interface. This is shown in Fig. 4(a).
For a 30-nm device, channel potential has a uniform profile, but the 50- and 70-nm devices show nonuniform potential
profiles along the vertical direction ( direction). This implies
that there exists a vertical electric field from the shorter channel
) region to the longer region. In Fig. 4(b), potential
length (

(b)
Fig. 3. DIBL and drain saturation current characteristics of various devices
with a nonuniform S/D doping profile. (a) T
30 nm. (b) T
50 nm.
In both cases, L
36 nm, T
2 nm.

profiles along the channel direction ( direction) for the 70-nm

is fixed to 30 nm, potential proSOI device are shown. As
0 nm and
10 nm show no difference. At
30
files at
nm, the potential is lower than that of the upper region, and its
minimum point moves to drain, which means the reduced lateral electric field at that region. The junction crosses the gate
46 nm when
30 nm, potentials below this
edge at
point become smaller as the depth increases, and there also exists a lateral electric field. For the 30-nm SOI device, the lateral
30 nm is the same as those of the upper
electric field near
region.
Hence, the reduction of DIBL can be explained by Fig. 5.
) than the
Channel region I has a shorter channel length (
other regions (II and III), and has a higher channel potential due
to the applied drain bias. Due to the difference in channel potential, a vertical electric field is generated from the shorter
region to the longer region, as shown in Fig. 5. This vertical electric field reduces the lateral electric field at the smaller channel
region according to Gauss law, and causes smaller DIBL. This
phenomenon is similar to the Pi-gate MOSFET proposed by
Park [5]. According to Gauss law, the lateral electric field at the
longer channel region can also be explained.
Drain saturation current becomes larger for the device with
thicker SOI. In Fig. 3(a), this may be caused by the increase of
the current path in the channel region, not by the increase of effective device width as the doping profile is fixed. The term effective device width is arbitrarily defined as the junction length
which overlaps with the gate. The increase of current path in the

WOO et al.: ELECTRICAL CHARACTERISTICS OF FINFET WITH VSOURCE/DRAIN PROFILE

(a)

235

Fig. 6. DIBL and drain saturation current of the devices with T

30, 50, and 70 nm, and S/D doped by As ion implantation at the dose
of 5 10 cm . Implantation energy was varied to be 10, 15, 20, 25,
and 30 keV.

(b)

Fig. 4. (a) Vertical channel potential of the devices with T

30 nm and
T
30, 50, and 70 nm. (b) Lateral channel potential of 70-nm T
device
at various points (y 0, 10, 30, 40, 50, and 70 nm).

Fig. 5. Schematic diagram which explains the reduction of DIBL for the
device with a vertically nonuniform S/D doping profile. Channel region I has
a shorter channel length (L ) than the other regions (II, III), and has higher
channel potential due to the drain bias. This difference in potential causes the
vertical electric field to be generated from the shorter L
region (region I) to
longer regions (region II, III).

channel region can be verified by the lateral electrical field in the

longer channel region shown in Fig. 4(b). The result of effective
,
device width change is shown in Fig. 3(b). By increasing
we can increase effective device width, and the current stops increasing until the effective device width reaches maximum. In
) is
Fig. 3(b), the depth of the uniform doping region (
45 nm, and the point where the junction profile crosses the gate
edge is 49 nm. This is where effective device width is maximum
at the device with an SOI thickness of 50 nm.
In the previous section, we discussed the reason for the
reduction of DIBL. The main reason was interaction between

channel potentials with different channel lengths (

s). In
the next section, we will investigate the effect of a nonuniform
S/D doping profile using the ion-implanted doping profiles
obtained from the 2-D process simulation. Oxide spacers
with a width of 50 nm were formed at each side of the gate
to prevent the S/D profiles merging. For the MOSFET, As ,
5 10 cm was implanted with various energies, followed
by a 1000 C, 10-s annealing process. Implantation energies
were 10, 15, 20, 25, and 30 keV. When obtaining an S/D doping
profile, the transient-enhanced diffusion (TED) model was
ignored as the accurate profile was not necessary.
Fig. 6 shows the DIBL and drain saturation current of the
devices. As mentioned previously, drain saturation current inincreases for the same S/D doping condition.
creases as
This can be explained by the increase of current path. For the
, drain saturation current increases until some implansame
tation energy and it decreases for the further increase of implantation energy. The energies were 20, 25, and 30 keV for the 30,
, respectively. This can be explained by the
50, and 70 nm
change of effective device width, as it depends on the SOI thickness and implantation energy.
In the fabrication of FinFET, the channel thickness is the critical dimension. This is the limiting factor in the scaling down
of FinFET. Using a vertically nonuniform S/D doping profile,
the short-channel effect can be reduced to some extent. For the
devices with ion-implantation doped S/D, there would be some
margin in the design of FinFET. Fig. 7 shows the maximum al) of the FinFET which satisfies
lowable channel thickness (
the DIBL constraint of 100 mV/V. For the same S/D doping pro.
file, a thicker SOI device allows larger
For the fixed S/D doping geometry, the device with a larger
shows larger drain saturation current and smaller DIBL.
can result in large capacitance. In
However, an increase of
FinFET, the main component is gate capacitance. The junction
capacitance of FinFET can be ignored as the device is built on
thick buried oxide. To evaluate the ac characteristics of FinFET,
V and
V was obgate capacitance at
tained by applying a small signal to the gate and extracting the
change of gate charge. Signal frequency was 1 MHz. Each device has a different channel thickness obtained in Fig. 7, and this
means there are no differences in short-channel effect. Using the

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IEEE TRANSACTIONS ON NANOTECHNOLOGY, VOL. 1, NO. 4, DECEMBER 2002

REFERENCES

Fig. 7. Maximum allowable channel thickness (W

constraints (< 100 mV/V) only.

) considering DIBL

[1] D. Hisamoto, W.-C. Lee, J. Kedzierski, H. Takeuchi, K. Asano, C. Kuo,

E. Anderson, T.-J. King, J. Bokor, and C. Hu, FinFETA self-aligned
double-gate MOSFET scalable to 20 nm, IEEE Trans. Electron Devices, vol. 47, pp. 23202325, Dec. 2000.
[2] L. Chang, S. Tang, T.-J. King, J. Bokor, and C. Hu, Gate length scaling
and threshold voltage control of double-gate MOSFETs, in Tech. Dig.
IEDM, 2000, pp. 719722.
[3] Y.-K. Choi, N. Lindert, P. Xuan, S. Tang, D. Ha, E. Anderson, T.-J. King,
J. Bokor, and C. Hu, Sub-20 nm CMOS FinFET technologies, in Tech.
Dig. IEDM, 2001, pp. 421424.
[4] J. Kedzierski and H. -S. Philip Wong, High-performance symmetric-gate and CMOS-compatible V asymmetric-gate FinFET
devices, Tech. Dig. IEDM, pp. 437440, 2001.
[5] J.-T. Park, J.-P. Colinge, and C. H. Diaz, Pi-Gate SOI MOSFET, IEEE
Electron Device Lett., vol. 22, pp. 405406, Aug. 2001.
[6] S. H. Tang, L. Chang, N. Lindert, Y.-K. Choi, W.-C. Lee, X. Huang, V.
Subramanian, J. Bokor, T.-J. King, and C. Hu, FinFET-a quasi-planar
double-gate MOSFET, in Proc. IEEE Int. Solid State Circuits Conf.,
2001, pp. 118119.

Dong-Soo Woo received the B.S. and M.S. degrees

from the School of Electrical Engineering, Seoul National University, Seoul, Korea, in 1996 and 1998, respectively. Since 1998, he has been working toward
the Ph.D. degree at the same university.
His current research interests are nanoscale CMOS
device modeling, characterization, and fabrication.
Fig. 8. Calculated C V =I gate delay (t ). Capacitance is the gate capacitance.
V
1:0 V, V
V
= 0:8 V, and the maximum channel thickness
(W ) was chosen from Fig. 7.

gate capacitance,
gate delay was calculated and shown in
gate delay shows no dependency on the drain
Fig. 8. Each
saturation current. This is because the capacitance also changes
with SOI thickness and the channel thickness. Anyway, there is
so small a difference in gate delay, less than 6% in its value, despite about 230% difference in SOI thickness.
Moreover, there can be a case when the device drives a constant capacitance load, such as an interconnect. In that case, the
device with larger drain saturation current is better, as the delay
is inversely proportional to the drain saturation current. Hence,
should be determined considering system dethe optimum
tails.
IV. CONCLUSION
The effects of a nonuniform S/D doping profile on the FinFET
characteristics were investigated using a 3-D device simulation.
With a fixed S/D doping profile, larger SOI thickness can suppress short-channel effect due to the effect of a longer channel
region. So, there can be some design margin in the channel
thickness, due to this reduced short-channel effect. Drain saturation current in FinFET is proportional to the effective device
width and SOI thickness.
To determine the optimum SOI thickness of FinFET, ac characteristics are also investigated. Device capacitance increases
with SOI thickness, but this is not necessarily the case for the
gate delay, as the drive current also increases and compensates
for the increase of capacitance. When driving a constant capacitance load such as interconnect, devices with larger drain current
or thicker SOI are more favorable.

Jong-Ho Lee received the B.S. degree in electronic

engineering from Kyungpook National University,
Taegu, Korea, in 1987. He received the M.S. and
Ph.D. degrees from Seoul National University,
Seoul, Korea, in 1989 and 1993, respectively, both
in electronic engineering.
In 1983, he worked on advanced BiCMOS process
development at the Interuniversity Semiconductor
Research Center (ISRC), Seoul National University,
as an Engineer. From 1994 to 2001, he was a faculty
member of Wonkwang University, Iksan, Korea.
In 2002, he joined the School of Electronics and Electrical Engineering,
Kyungpook National University, Daegu, Korea. From 1994 to 1998, he
was with ETRI as an Invited Member of Technical Staff, working on deep
submicrometer SOI devices, device isolation, 1/f noise, and device mismatch
characterization. From August 1998 to July 1999, he was with the Massachusetts Institute of Technology (MIT), Cambridge, as a Postdoctoral Researcher,
where he was engaged in research on sub-100nm double-gate CMOS devices.
His research interests include sub-100nm CMOS technologies, SiGe HBT,
high-performance IC design, and microsystems.

Woo Young Choi received the B.S. and M.S. degrees

from the School of Electrical Engineering, Seoul National University, Seoul, Korea, in 2000 and 2002, respectively. Since 2002, he has been working toward
the Ph.D. degree at the same university.
His current research interests are nanoscale CMOS
device modeling, characterization, and fabrication.

WOO et al.: ELECTRICAL CHARACTERISTICS OF FINFET WITH VSOURCE/DRAIN PROFILE

Byung-Yong Choi received the B.S. degree in

electronic engineering from Kyungpook National
University, Taegu, Korea, in 1998. He received
the M.S. degree from the School of Electrical
Engineering, Seoul National University, Seoul,
Korea, in 2000. Since 2000, he has been working
toward the Ph.D. degree at the same university.
His current research interests are nanoscale CMOS
device modeling, characterization, and fabrication.

Young-Jin Choi received the B.S. and M.S. degrees

from the School of Electrical Engineering, Seoul National University, Seoul, Korea, in 1994 and 1996, respectively. Since 1996, he has been working toward
the Ph.D. degree at the same university.
His current research interests are nanoscale CMOS
device modeling, characterization, and fabrication.

Jong Duk Lee (M79) received the B.S. degree

in physics from Seoul National University, Seoul,
Korea, in 1966 and the Ph.D. degree from the Department of Physics, University of North Carolina,
Chapel Hill, in 1975.
He was an Assistant Professor in the Department of
Electronics Engineering, Kyungpook National University, Taegu, Korea, from 1975 to 1978. In 1978,
he studied microelectric technology in HP-ICL, Palo
Alto, CA and soon afterwards, worked for the Korea
Institute of Electronic Technology (KIET) as the Director of the Semiconductor Division. He established the KIET Kumi Facility
and introduced the first polysilicon gate technology in Korea by developing 4K
SRAM, 32K and 64K Mask ROMs, and one-chip 8-bit microcomputers. In July
1983, he moved to the Department of Electronics Engineering, Seoul National
University, as an Associate Professor, where he has been Professor since 1988.
He established the Interuniversity Semiconductor Research Center (ISRC) in

237

1985 and served as the Director until 1989. He served as the Chairman of the
Electronics Engineering Department from 1994 to 1996. He was with Samsung
Display Devices Co., Ltd., as the Head of Display R&D Center in 1996, on leave
from Seoul National University. He concentrated his study on the image sensors
such as Vidicon type, MOS type, and also CCDs, for Samsung Display Devices
Co. and Samsung Electronics Co. from 1984 to 1991. His current research interests include sub-0.1-m CMOS structure and technology, FEDs, CMOS image
sensor, and high-speed SRAM design. He has published over 130 papers in the
major international scientific journals, including over 65 SCI papers. He has
presented more than 180 papers, including 80 international conference papers.
He also has registered 11 U.S., three Japanese, and eight Korean patents.
Dr. Lee is a member of the Steering Committees for IVMC (International
Vacuum Microelectronics Conference) and KCS (Korean Conference on Semiconductors). He was the Conference Chairman of IVMC97 and KCS98 who
led the IVMC97 and the KCS98. He was also a member of the IEDM (International Electron Devices Meeting) Subcommittee on Detectors, Sensors, and
Displays, IEEE Electron Devices Society, from 1998 to 1999. In June 1999, he
was elected First President of the Korean Information Display Society.

Byung-Gook Park (M96) received the B.S. and

M.S. degrees in electronics engineering from Seoul
National University, Seoul, Korea, in 1982 and
1984, respectively, and the Ph.D. degree in electrical
engineering from Stanford University, Stanford, CA,
in 1990.
From 1990 to 1993, he was with AT&T Bell Laboratories, Murray Hill, NJ, where he contributed to the
development of 0.1-m CMOS and its characterization. From 1993 to 1994, he was with Texas Instruments, Dallas, TX, developing 0.25-m CMOS. In
1994, he joined the School of Electrical Engineering, Seoul National University,
as an Assistant Professor, and he is currently an Associate Professor. His current research interests are nanoscale CMOS devices, Si single-electron devices,
organic electroluminescent display, and scanning probe microscopy systems.
Dr. Park was a member of the IEDM (International Electron Devices Meeting)
Subcommittee on Solid State Devices, IEEE Electron Devices Society, from
2001 to 2002.