ST.

ANNS COLLEGE OF ENGINEERING & TECHNOLOGY

CHIRALA
( Accredited by NBA(twice) , IE (I) &NAAC with A Grade)
( Approved by AICTE & Permanently Affiliated to JNTUK)

A project report on

32-BIT VEDIC MULTIPLIER

Undertheesteemedguidanceof

FIROZE BASHA SHAIK M.Tech

SUBMITTED BY

Shaik Meerabi (12F01A04E8)

MVN Sai Kumar (13F05A0422)
Ubba Aditya Kiran (12F01A04G6)
Shaik Muhammad Nawaz Shariff (13F05A0434)
DEPARTMENT OF ELECTRONICS AND COMMUNICATION
ENGINEERING
ST.ANNS COLLEGE OF ENGINEERING & TECHNOLOGY ,CHIRALA.

ABSTRACT
Binary multipliers and addresses are used in the design and development of
Arithmetic Logic Unit (ALU), Digital Signal Processing (DSP) Processors,

Multiply and Accumulate (MAC).The objective of this paper is to implement digital

multipliers based on the concept of Vedic mathematics. In order to develop a digital
multiplier, Urdhva-tiryakbyham sutra of Vedic mathematics is used to implement
vertical and cross wise operations. In this project 32-bit vedic multiplier is designed
and simulated in Xilinx ISE 13.4 and has been compared with a 32-bit binary
multiplier.
The multipliers are used in our daily life for various applications. So to make
the multiplier faster, power efficient and to fit in lesser area we are going to use an
oldest technique known as Vedic mathematics. The main objective of the paper is to
develop binary multipliers i.e. multipliers designed to find the product of two n-bit
binary numbers and then implement it. Binary multipliers of 32x32 have been
compared with conventional multipliers based on their summary obtained at the end
after the implementation.
The code for implementing binary multipliers has been written in VHDL
language for both the multipliers. The "Urdhva-tiryakbyham" sutra is based on
"vertical and crosswise.
The simulation of the 32-bit Vedic multiplier is carried out by creating a test
bench file which consists of all the input combinations and mapping process. This
test bench files have been simulated in behavioral and the outputs obtained. The
proposed multiplier of 32-bit is implemented on a Spartan.

http://www.vedicmathsofindia.com/tag/vedic-mathematics-sutra-no-1-ekadhikenapurvena/#Division

2014 IEEE International Conference on Advanced Communication Control and Computing Technologies (lCACCCT)

Comparison ofa 32-Bit Vedic Multiplier With A Conventional

Binary Multiplier
l

Abhyarthana Bisoyi , Mitu Barat , Manoja Kumar Senapati

1,2,3Dept.

3
l

of Electronics and Communication,National Institute of Science and Technology,Berhampur, India abhyabisoyi@gmail.com,

mitubaral@gmail.com, s.manojakumar@yahoo.com
a!. [5] focused on the DSP application in VLSI by designing a MAC unit

Abstract- Binary multipliers and addresses are used in the design and development
of Arithmetic Logic Unit (ALU), Digital Signal Processing (DSP) Processors, Multiply
and Accumulate (MAC).The objective of this paper is to implement digital multipliers

based on Vedic mathematics. In 2011, lM. Rudagi, et al. [6] extended the
applications in DSP by focusing on convolution, FFT, etc and applied on
Computation Intensive Arithmetic Functions. In 2012, A. Haveliya [7]

based on the concept of Vedic mathematics. In order to develop a digital multiplier,

used overlap add method and overlap save method in order to develop a

Urdhva-tiryakbyham sutra of Vedic mathematics is used to implement vertical and

Vedic multiplier. In 2013, A. K. Itawadiya, et al. [8] approached to

cross wise operations. Since these are digital multipliers, they are implemented on

implement convolution as well as correlation which was different in

FPGA board and are tested through the 8 LED

application and was innovative idea. In 2013, L. Sriraman, et al. [9]

proposed an 8, 16, 32 bit squarer and implemented on Cyclone III

(s) in FPGA (Nexys 3). A 32-bit Vedic multiplier has been simulated in Xilinx ISE 13.4

FPGAEP3C 16F484C6.

and has been compared with a 32-bit binary multiplier.

The main objective of the paper is to develop binary multipliers i.e.

Keywords-Vedic mathematics; FPGA; binary nmltipliers, Xilinx ISE

multipliers designed to find the product of two n-bit binary numbers and
then implement it on a Nexys 3, Spartan 6 FPGA board. Binary
I.

multipliers of 32x32 have been compared with conventional multipliers

INTRODUCTION

In today's era more emphasis is given on the signal processing

based on their summary obtained at the end after the implementation.

applications in VLSI. Since last two decades, papers on MAC have been
written in order to improve the multiplication techniques and when we talk
of multiplication the first thing that strikes is "Mathematics". Researchers
or readers prefer the ancient methodology for any mathematical
application where sutras are used i.e. "Vedic Mathematics". Vedic
Mathematics is based on 16 sutras (aphorisms) namely (Anurupye)
Shunyamanyat,

Chalana-Kalanabyham,

Ekadhikina

Dashatahm,

described in Section III. The simulation results along with discussions on

it are presented in Section IV. The paper has been concluded in Section
V.

Purvena,

Ekanyunena Purvena,Gunakasamuchyah, Gunitasamuchyah, Nikhilam

Navatashcaramam

Rest of the paper is organized as; the proposed work has been
discussed in Section II. Algorithm for the Vedic multiplier has been

ParaavartyaYojayet,

Puranapuranabyham, Sankalana vyavakalanabhyam, Shesanyankena

Charamena, Shunyam Saamyasamuccaye, Sopaantyadvayamantyam,
Urdhva tiryakbyham, Vyashtisamanstih and Yaavadunam [2]. Each of

AI.

PROPOSED WORK

The code for implementing binary multipliers has been written in

Verilog language for both the multipliers. The whole program has been
written in Xilinx 13.4 ISE environment.

these sutras is used for specific application, for example Nikhilam sutra is
used to find the square of a number. Using the concept of Vedic
Mathematics any mathematical operation can be done.

In 2007, S. Akhter, [1] has developed a technique for NxN

multipliers based on add and shift instead of vertical and crosswise
multiplication. In 2008, H.D. Tiwari, et al. [2] implemented multipliers that
were developed based on Vedic mathematics on a ALTERA Cyclone -II
FPGA which was faster than array multiplier and Boot multiplier. In 2009,
P. Mehta, et a!. [3] compared the conventional multipliers with the Vedic
multipliers by implementing on the Xilinx FPGA device, Virtex XCV 300

IMPLEMENTATION

-6PQ240. In 2011, P. Saha, et a1. [4] developed a design for high speed
complex multiplier based on the 16 sutras of ancient mathematics. In
2009, D. laina, et

Figure I. Work flow diagram

ISBN No. 978-1-4799-3914-5/14/$31.00

2014 IEEEEEE International Conference on Advanced Communication Control and Computing Technologies (lCACCCT)
Step 2
The "Urdhva-tiryakbyham" sutra is based on "vertical and crosswise"
[2] calculations and hence this sutra amongst all other sutras has been

10

used for designing the binary multipliers.

6\

11
The flow of the work is given in figure 1. After writing the verilog code for

Product=

(Ixl)

(IxO)

1+0=1,

Final

Result=Product+ Previous carry=1 +0=1 So,

Final Result=l, Carry=O

II

a binary multiplier, it is very important to simulate the code before

implementing it on the board. Simulation has been done in Xilinx

Step 3

environment by writing test bench file and then the simulation results has
been verified with actual results. The simulation is followed by synthesis

process which is another important step and if the code is not synthesizable
then it will not work on the FPGA board also. After synthesis, the code is
ready to be implemented in hardware but before that it has to undergo place
and route. Once place and route is over a bit is generated in Xilinx which is
downloaded on the FPGA board and then the code is implementation
process starts.

Product=( 1x 1 )+( 1xO )+( 1xO)= 1+0+0= 1,

Final Result= 1+0=1
Final Result=l, Carry=O

III
Product= (Ixl) + (OxO) + (Ixl) + (Ixl) = 1+0+ 1+
Step 4

1=11, Final Result= 11+0= 11 Final Result=l,

Carry=1

BI.

ALGORITHM

The Urdhva-tiryakbyham sutra deals with vertical and crosswise

that can be seen from the line diagram. So an algorithm is developed

1111

based on a line diagram described in section A and the steps are

Product= (Ixl) + (IxO) + (IxO)

explained with an example in section B.

1+0+0=1, Final Result= 1+ 1=10

Step 5

Final Result=O, Carry=1

A.

Line diagram

011 II
Product= (Ixl) + (IxO) = 1+0=1,
Step 6

Final Result= 1+1=10

Final Result=O, Carry=1

1011

0011 II

Product= (Ixl) = 1,
Final Result= 1+ 1 =10

Step 7

Final Result=O, Carry=1

1011

IV. RESULTS AND DISUSSION

10

100011 II
The results are obtained from two parts i.e. simulation part and
implementation part. The simulation results are shown in section A and
section B discusses about the implementation results.

A.

B.

Example with steps

An example of the above pin diagram is demonstrated in this

section. The pin diagram is for two 4-bit numbers, Bitl= "lOll"

The simulation of the 32-bit Vedic multiplier is carried out by

creating a test bench file which consists of all the input combinations
and mapping process. This test bench files have been simulated in
behavioral and the outputs obtained are shown in figure 2 and3.

Bit2= "1101"
Step!
101

Simulation results

In figure2, the inputs are taken as,

Bit1= "11111111111111111111111111100001" Bit2=
Product= 1 x 1 = 1,

"10000111111111111111111111111111"
In figure 3, the inputs are taken as,

1101

So, Result= 1, Carry=O

Bitl= "11111111111111111111111111111111" Bit2=

"11111111111111111111111111111111"

1758
4 IEEE International Conference on Advanced Communication Control and Computing Technologies (lCACCCT)
The slice distribution summary table of a Vedic Multiplier has been shown in
table number II, where the utilization of unused flip flop is 100% and utilization of
other parameters was 0% i.e. they were not used.

TABLE lIl.

Description

Figure 2. Simulation result-I of two 32 bit numbers

I/O UTILIZATION

Used

Number of 1I0s

128

Number
IIOs

128

of bonded

Available

232

Utilization

(%)

55

The 110 utilization summary table of a Vedic Multiplier

has been shown in table number III, where the utilization of
bonded 1I0s was 55%.
TABLE IV.

SPECIAL FEATURE unLiZA nON

Description
Used
Number
DSP48AIs

of

32

Available
32

Utilization

(%)

100

Figure 3. Simulation result-2 of two 32 bit numbers

B.

Comparison on basis of synthesis report

The slice logic utilization, slice logic distribution, 110 utilization and special feature utilization table of a 32-bit Vedic multiplier are given in table

number I, II, III and IV respectively.

TABLE I.

SLICE LOGIC UTILIZATION

Description
Number
LUTs

Used

of

slice

Number
used
logic gates

Available

Utilization

(%)

3356

9112

36

3356

9112

36

as

The slice logic utilization summary table of a Vedic Multiplier has been shown in table number I, where the utilization of slice LUTs and logic gates
are 36%.
TABLE II.

SLICE LOGIC DISTRIBUTION

Table Head

Used

Available

Utilization

(%)

Number of LUT Flip Flop

3356

pairs used
Number
Flip Flop

with

Number
LUT

with

Number
of
LUT-FF pairs

unused

an

3356

3356

100

3356

3356

unused

an

fully

used

Number of unique control

sets

The special feature utilization summary table of a Vedic Multiplier has been shown in table number IV, where the utilization of DSP48Als was 100%.

The 110 utilization and special feature utilization table of a 32-bit conventional multiplier are given in table number V and VI respectively. The other
two utilization reports have 0% utilization and hence are not mentioned in tabular format.
TABLE V.

Description

110 UTILIZATION

Used

Number of 1I0s

128

Number of bonded
IIOs

128

Available

232

Utilization

(%)

55

The 110 utilization summary table of a 32-bit Conventional Multiplier has been shown in table number V, where the utilization of bonded 1I0s was
55% which is same % as Vedic Multiplier.

TABLE VI.

SPECIAL FEATURE unLiZA nON

Description
Used
Number
DSP48AIs

of

Available
32

Utilization

(%)
12

The special feature utilization summary table of a Vedic Multiplier has been shown in table number IV, where the utilization of DSP48Als was
12% which is very less in % as compared to Vedic Multiplier tabulation results.

2014 IEEE Iernational Conference on Advanced Communication Control and Computing Technologies (lCACCCT)
C.

1)

Comparison on basis of delay

In Vedic multiplier of 32-bit operation, the delay obtained is as follows,
168.430ns (40.043ns logic, 128.387ns route)
(23.8% logic, 76.2% route)
2) In a conventional multiplier of 32-bit operation, the delay obtained is
as follows,

19.286ns (15.993ns logic, 3.293ns route) (82.9% logic,

17.1 % route)
D. Advantages and disadvantages of Vedic multipliers
After comparing the 32x32 Vedic multiplier with a conventional 32-bit
binary multiplier, it has been observed that there are many disadvantages
in Vedic multipliers but still have various applications in DSP. So the
various advantages and disadvantages are listed as follows:

1)

Advantages: Vedic multipliers are based on one of the 16 sutras

of Vedic Mathematics which is "Vertical - crosswise". From the algorithm

[4] P. Saha, A Banerjee, P. Bhattacharyya, A Dandapat, "High speed ASIC design

of complex multiplier using Vedic Mathematics", IEEE Students' Technology
Symposium , pp. 237-241, Jan 2011
doi: 10.1109fTECHSYM.2011.5783852
[5]
D. Jaina, K. Sethi, R. Panda, "Vedic Mathematics Based Multiply
Accumulate Unit", International Conference on Computational Intelligence
and Communication Networks, pp. 754-757, Oct 2011
doi: 10.1l09fCICN.2011.167
[6]
J.M. Rudagi, Vishwanath Ambli, Vishwanath Munavalli, Ravindra Patil,
Vinaykumar Sajjan, "Design and implementation of efficient multiplier using
Vedic Mathematics", 3rd International Conference on Advances in Recent
Technologies in Communication and Computing, pp. 162-166, Nov 2011
doi: 10.1 049fic.20 11.0071
[7] A Haveliya, "FPGA implementation of a Vedic convolution algorithm",
International journal of engineering research and applications, Vol. 2, issue
I, pp. 678-684, Feb 2012
[8] AK. ltawadiya, R. Mahle, and V. Patel, D. Kumar, "Design a DSP operations
using Vedic mathematics", International Conference on Communications
and Signal Processing, pp. 897-902, Apr 2013
doi: 10.1109ficcsp.2013.6577186
[9] L. Srirarnan, K. Kumar, T.N. Saravana, Prabakar, "Design and FPGA
implementation of binary squarer using Vedic mathematics", Fourth
International Conference on Computing, Communications and Networking
Technologies, pp. 1-5, July 2013

explained in the previous section, it can be clearly seen that the Vedic
multiplier is based on MAC i.e. Multiply and Accumulate. So, these have

doi: 10.11 09f1CCCNT.20 13.6726607

got wide applications in DSP.

2) Disadvantages: The major disadvantage of Vedic multipliers is the

utilization of LUTs, lOBs, etc. The conventional multipliers do not have
much utilization of these components.

V.

CONCLUSION

From the utilization summary obtained after implementation, it has been observed that the nwnber 1I0s needed for 32-bit Vedic multiplier and
conventional binary multiplier are 128 out of 232 because of which the utilization becomes 55% for both of the multipliers. In the specific feature
utilization table, the number of DSP48Als used is 32, and 4, so the utilization is 100% and 12% respectively. On observing these results, the
disadvantages of Vedic Multipliers can be seen over binary multipliers. The delay difference is more but is in the range of nano seconds and hence
does not affect much in the circuit. Further, 64x64 multiplier can be implemented which will reduce the delay by 50%. Various applications such as
convolution, correlation, FFT, etc. can be implemented in order to extend the application of DSP in VLSI. The Texas has their own DSP Processors
where they emphasize on discrete time signal applications and we should also implement it.

REFERENCES
[I]
S. Akhter, "VHDL implementation of fast NxN multiplier based on Vedic mathematic", 18th European Conference on Circuit Theory and Design, pp.
472-475, Aug 2007
doi: 10. I 109fECCTD.2007.4529635
[2] H.D. Tiwari, G. Gankhuyag, Chan-Mo Kim, Yong Beom Cho, "Multiplier design based on ancient Indian Vedic Mathematics", International SoC Design
Conference, Vol. 2, pp. 65-68, Nov 2008
doi: 10.1I 09fSOCDC.2008.48I 5685
[3] P. Mehta and D. Gawali, "Conventional versus Vedic Mathematical Method for Hardware Implementation of a Multiplier", International Conference on Advances in
Computing, Control & Telecommunication Technologies, pp. 640-642, Dec 2009
doi: 10.1l09fACT.2009.162