2) Verify the behavior of logic gates using truth

tables(AND,OR,NOT,XOR,NAND,NOR,XNOR)

AND:

entity and123 is
Port ( x : in STD_LOGIC;
y : in STD_LOGIC;
z : out STD_LOGIC);
end and123;
architecture Behavioral of and123 is
begin
process (x, y)
begin
if (x='1' and y='1') then

-- Compare with truth table

Z <= '1';
else
Z <= '0';
end if;
end process;
end Behavioral;

0R:
entity or123 is
Port ( x : in
STD_LOGIC;
y : in
STD_LOGIC;
z : out
STD_LOGIC);
end or123;
architecture Behavioral of or123 is
begin
process (x, y)
begin
if (x='0' and y='0') then -Compare with truth table
Z <= '0';
else
Z<= '1';
end if;
end process;
end Behavioral;

NOT:
entity not123 is
Port ( x : in STD_LOGIC;
z : out STD_LOGIC);
end not123;
architecture Behavioral of not123 is
begin
process (X)
begin
if (x='0') then -- Compare with truth table
Z <= '1';
else
Z<= '0';
end if;
end process;
end Behavioral;
NAND:
entity nand123 is
Port ( x : in STD_LOGIC;
y : in STD_LOGIC;
z : out STD_LOGIC);
end nand123;
architecture Behavioral of nand123 is
begin
Process (x, y) Begin
If (x='1' and y='1') then -- Compare with truth table
Z <= '0';
else
Z <= '1';
end if;
end process;
end Behavioral;
NOR:
entity nor123 is
Port ( x : in STD_LOGIC;
y : in STD_LOGIC;
z : out STD_LOGIC);
end nor123;
architecture Behavioral of nor123 is
begin
process (x, y)
begin
If (x='0' and y='0') then -- Compare with truth table
Z <= '1';
else
Z <= '0';
end if;
end process;
end Behavioral;

XOR:

entity xor123 is
Port ( x : in STD_LOGIC;
y : in STD_LOGIC;
z : out STD_LOGIC);
end xor123;
architecture Behavioral of xor123 is
begin
process (x, y)
begin
If (x/=y) then -- Compare with truth table
Z <= '1';
else
Z<= '0';
end if;
end process;
end Behavioral;
XNOR:
entity xnor123 is
Port ( x : in STD_LOGIC;
y : in STD_LOGIC;
z : out STD_LOGIC);
end xnor123;
architecture Behavioral of xnor123 is
begin
process (x, y)
begin
If (x=y) then -- Compare with truth table
Z <= '1';
else
Z<= '0';
end if;
end process;
end Behavioral;

3)Implementing HALF ADDER, FULL ADDER using basic logic gates

FULL ADDER:
entity fa is
Port ( a : in STD_LOGIC_VECTOR (2 downto 0);
s : out STD_LOGIC;
ca : out STD_LOGIC);
end fa;
architecture Behavioral of fa is
begin
process(a)
begin
if a="000" then s<='0';ca<='0';
elsif a="001" then s<='1';ca<='0';
elsif a="010" then s<='1';ca<='0';
elsif a="011" then s<='0';ca<='1';
elsif a="100" then s<='1';ca<='0';
elsif a="101" then s<='0';ca<='1';
elsif a="110" then s<='0';ca<='1';
else s<='1';ca<='1';
end if;
end process;
end Behavioral;

HALF ADDER:
entity HA123 is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
s : out STD_LOGIC;
c : out STD_LOGIC);
end HA123;
architecture Behavioral of HA123 is
begin
s <=a xor b;
c <=a and b;
end Behavioral;

4) Implementing Binary -to -Gray, Gray -to -Binary code conversions.

Binary -to Gray:
entity bg123 is
Port ( b : in STD_LOGIC_VECTOR (3 downto 0);
g : out STD_LOGIC_VECTOR (3 downto 0));
end bg123;
architecture Behavioral of bg123 is
begin
g(3)<=b(3);
g(2)<=b(3) xor b(2);
g(1)<=b(2) xor b(1);
g(0)<=b(1) xor B(0);
end Behavioral;

GRAY TO BINARY CODE CONVERSION .

entity gtb is
Port ( g : inout STD_LOGIC_VECTOR (4 downto 0);
b : inout STD_LOGIC_VECTOR (4 downto 0));
end gtb;
architecture Behavioral of gtb is
begin
b(3)<=g(3);
b(2)<=b(3) xor g(2);
b(1)<=b(2) xor g(1);
b(0)<=b(1) xor g(0);
end Behavioral;

5) Implementing 3-8 line DECODER.

entity DEC123 is
Port ( w : in STD_LOGIC_VECTOR (2 downto 0);
e : in STD_LOGIC;
y : out STD_LOGIC_VECTOR (7 downto 0));
end DEC123;
architecture Behavioral of DEC123 is
begin
y<="10000000" when (w="000" and e='1')else
"01000000" when (w="001" and e='1')else
"00100000" when (w="010" and e='1')else
"00010000" when (w="011" and e='1')else
"00001000" when (w="100" and e='1')else
"00000100" when (w="101" and e='1')else
"00000010" when (w="110" and e='1')else
"00000001" when (w="111" and e='1')else
"00000000" when e='0';
end Behavioral;

6) Implementing 4x1 and 8x1 MULTIPLEXERS.

8x1MUX:
entity mux8x1 is
Port ( I : in STD_LOGIC_VECTOR (7 downto 0);
S : in STD_LOGIC_VECTOR (2 downto 0);
en_1 : in STD_LOGIC;
Y : out STD_LOGIC);
end mux8x1;
architecture Behavioral of mux4x1 is
begin
process (I,S,en_1)
begin
if en_1='0' then case s is
when "000" => y <= I(0);
when "001" => y <= I(1);
when "010" => y <= I(2);
when "011" => y <= I(3);
when "100" => y <= I(4);
when "101" => y <= I(5);
when "110" => y <= I(6);
when "111" => y <= I(7);
when others=>null;
end case;
else y <= '0'; --y=0 when en_l=1
end if;
end process;
end Behavioral;

7) Verify the excitation tables of various FLIP-FLOPS.

1) D-FLIP FLOP:

entity ffd1 is
Port ( d : in STD_LOGIC;
clk : in STD_LOGIC;
q : out STD_LOGIC;
qbar : out STD_LOGIC);
end ffd1;
architecture Behavioral of ffd1 is
begin
process(clk,d)
begin
if clk='1'then q<=d;
qbar<= not d;
end if;
end process;
end Behavioral;

2)T-FlipFlop:
entity tff123 is
Port ( clk : in STD_LOGIC;
t : in STD_LOGIC;
q : inout STD_LOGIC:='0');
end tff123;
architecture Behavioral of tff123 is
begin
process(clk)
begin
if (clk' event and clk='1') then
if(t='1') then
q<= not q;
else
q<=q;
end if;

end if;
end process;
end Behavioral;

9) Design of an 8-bit ARITHMETIC LOGIC UNIT.

entity alu is
Port ( a : in STD_LOGIC_VECTOR (3 downto 0);
b : in STD_LOGIC_VECTOR (3 downto 0);
s : in STD_LOGIC_VECTOR (2 downto 0);
y : out STD_LOGIC_VECTOR (3 downto 0));
end alu;
architecture Behavioral of alu is
begin
process(a,b,s)
begin
case s is
when "001"=>y<="0000";
when"101"=>y<=a xor b;
when"110"=>y<=a or b;
when"111"=>y<=a and b;
when "000"=>y<=a xnor b;
when others =>y<="0001";
end case;
end process;
end Behavioral;