Weekly course progress table for FPGA-based Systems Design, Spring 2016

Class ID: 63247

Class on Monday, Friday
SNo

Date

Contents + Comments

1.

18 Jan, 2016

Introduction
Hardware vs Software
Hardware device technologies and their comparison
(Textbook Section 1.2, Complete section)
System Representation
(Textbook Section 1.3, Complete section)

2.

22 Jan, 2016

Marks Distribution
Google Drive http://tinyurl.com/jyhzx5p
Levels of Abstraction
o (Textbook Section 1.4)
Quick revision of Digital Logic fundamentals
Combinational vs Sequential circuits
Latch vs Flip flop. Timing diagram. Level triggered
vs Edge triggered. Synchronous and Asynchronous
clear signals
SOP expression, POS expressions, their mapping
on Truth table.
Number Representation. Signed magnitude form,
1s complement, 2s complement.
Half adder, Full adder, 4-bit adder

3.

25 Jan, 2016

Basic VHDL Concept Via an Example

(Text book Section 2.2, without testbench)
Even Parity truth table
VHDL code of even parity detector with SOP
architecture
Entity declaration, Architecture declaration,
Introduction to concurrent (parallel) statements
After clause
VHDL code of even parity detector with XOR
architecture
VHDL code of even parity detector using structural
description of XOR architecture.
Introduction to processes, Concurrent vs sequential
execution of VHDL (no example studied so far)

4.

29 Jan, 2016

No class due to PAF-KIET closed.

01 Feb, 2016

No class due to instructor unavailability

05 Feb, 2016

No class due to Kashmir Day Holiday.

Quiz + Assignment

08 Feb, 2016

Introduction to test benches. Output visualization using

waveform, manually assigning values through force feed-back,
Automatic assignment of values through test. Test vectors were
generation and output of even detector is compared with the
expected output in test vector verification process. (Text book
Section 2.2)
VHDL code of Even Detector simulated on ModelSim by forcing
the inputs, we can see output waveform changes. (Displayed
using projector)
Uses of HDL program
Data-Flow VHDL
Simple concurrent signal assignments (Section 4.1,
4.2 Complete sections)
Conditional Signal assignment statement (Section
4.3, Complete section)
Selected signal assignment statement (Section 4.4,
Complete section)
Conditional signal vs Selected Signal assignment
statement (Section 4.5, Complete section)

12 Feb, 2016

VHDL Process (Section 5.1, 5.2, Complete section)

Variable Assignment (Section 5.3, Complete section)
(Class terminated early due to PEC visit)

15 Feb, 2016

10

19 Feb, 2016

DFF with enable (Section 8.5.1)

Arbitrary sequence counter (Section 8.5.3)
Binary counter (Section 8.5.4)
Decade counter (Section 8.5.5)
Programmable mod-m counter (Section 8.5.6)
Gray code incrementor (Section 7.5.1)
Gray counter (Section 9.2.1)
LFSR (Section 9.2.3)
Timing Analysis Basics and D-FF Timing Parameters (Section
8.1.2)

11

22 Feb, 2016

Timing Analysis of Synchronous Sequential Circuits (Section

8.6)
Setup Time violations and maximal clock rate
Clock rate examples,
Hold time violations

IF Statement (Section 5.4, Complete section)

CASE Statement (Section 5.5, Complete section)
Simple FOR loop (Section 5.6, Complete section)
Sequential vs Combinational circuits (Section 8.1.1)
Basic Memory elements (Section 8.1.2)
Basic Model of Synchronous circuit (Section 8.2.1, Complete
section)
D Latch (Section 8.4.1)
DFF (Section 8.4.2)

Assignment 1
(given today)
Due date 15 Feb,
2016 before start of
class

Quiz-1 Taken today

Assignment 2
(given today)
Due date 29 Feb,
2016 before start of
class

 Output related timing considerations

Input related timing considerations
Introduction to Operator Sharing (Section 7.2)
12

26 Feb, 2016

Explanation of both versions of Quiz-1

Operator Sharing (Section 7.2, Complete section)

13

29 Feb, 2016

14

04 Mar, 2016

15

07 Mar, 2016

16

11 Mar, 2016