VLSI Lab Manual

SRINIVASAN ENGINEERING COLLEGE
DEPT OF ELECTRONICS AND COMMUNICATION ENGINEERING

ANNA UNIVERSITY CHENNAI
REGULATION 2009
I YEAR/ II SEMESTER
VL 9225 - VLSI DESIGN LABORATORY II

LAB MANUAL
ISSUE: 01 REVISION: 00
APPROVED BY
Prof. B. REVATHI
HOD/ECE
PREPARED BY
K.VIJAYA KANTH, Assistant Professor.
VLSI DESIGN LAB-II MANUAL

SRINIVASAN ENGINEERING COLLEGE, PERAMBALUR
I YEAR
VLSI
Preface
This laboratory manual is prepared by the Department of Electronics and Communication
engineering for VLSI Design Laboratory II (VL-9225). This lab manual can be used as instructional
book for students, staff and instructors to assist in performing and understanding the experiments. In
the first part of the manual, experiments as per syllabus are described and in the second part of the
manual, experiments that are beyond the syllabus but expected for university laboratory examination
are displayed. This manual will be available in electronic form from Colleges official website, for
the betterment of students.
Acknowledgement
We would like to express our profound gratitude and deep regards to the support offered
by the Chairman Shri. A.Srinivasan. We also take this opportunity to express a deep sense of
gratitude to our Principal Dr.B.Karthikeyan,M.E, Ph.D, for his valuable information and
guidance, which helped us in completing this task through various stages. We extend our hearty
thanks to our head of the department Mrs.B.Revathi M.E, (Ph.D), for her constant
encouragement and constructive comments.
Finally the valuable comments from fellow faculty and assistance provided by the
department are highly acknowledged.

I YEAR
VLSI
SYLLABUS
VL 9255 VLSI DESIGN LABORATORY II
LIST OF EXPERIMENTS
1. Implementation of 8 Bit ALU in FPGA / CPLD.

2. Implementation of 4 Bit Sliced processor in FPGA / CPLD.
3. Implementation of Elevator controller using embedded microcontroller.
4. Implementation of Alarm clock controller using embedded microcontroller.
5. Implementation of model train controller using embedded microcontroller.
6. System design using PLL

I YEAR
VLSI
CONTENTS
S.No
TOPIC
PAGE
NO
4
5
1. Syllabus
2. Requirements
3. Experiments
IMPLEMENTATION OF 8-BIT ALU IN FPGA/CPLD
1
2
IMPLEMENTATION OF 4-BIT SLICED PROCESSOR IN
FPGA/CPLD
IMPLEMENTATION OF ELEVATOR CONTROLLER
3
USING 8051 MICROCONTROLLER
9
15
28
LIFT1 MOVES FROM GROUND FLOOR TO FOURTH FLOOR

35
LIFT1 MOVES FROM FOURTH FLOOR TO GROUND FLOOR

41

47
IMPLEMENTATION OF ALARM CLOCK

CONTROLLER USING EMBEDDED
MICROCONTROLLER TRAINER
IMPLEMENTATION OF MODEL TRAIN CONTROLLER
53
64
USING EMBEDDED MICROCONTROLLER TRAINER

ROTATE ONLY

71
STATION 1 TO STATION 2

10
I YEAR
VLSI
82

FORWARD AND REVERSE DIRECTION
11
4
WORKING OF A PLL SYNTHESIZING OSCILLATOR
University Model Question Paper
100
105

I YEAR
VLSI
REQUIREMENTS
HARDWARE REQUIREMENTS
Spartan 3e trainer kit
8 bit microcontroller kit
Elevator interface board
Universal PIC embedded trainer
Model train interface board
VCT-57
CRO
SOFTWARE REQUIREMENTS
XILINX ISE 9.2i
MPLAB IDE V7.41

I YEAR
VLSI
LAB COURSE HANDOUT

Subject code
: VL 9255
Subject Title
: VLSI Design Lab II
Staff name
: K.VIJAYA KANTH
Scope and Objective of the Subject:

The objective of this course is to introduce the fundamental techniques in which highperformance is based on micro controllers.
To study synthesis, simulation and schematic of various alu and sliced processor using
CPLD on Xilinx simulator.
To study about the PLL.
Course Plan / Schedule:
S.No
Topics to be covered
Learning objectives
Page
No*
No. of
hours
Implementation Of 8-Bit ALU In

FPGA/CPLD
Students will be able to learn

about ALU and CPLD devices
6 hrs
Implementation Of 4-Bit Sliced Processor

In FPGA/CPLD

about sliced processor and
CPLD devices
15
6hrs
28
6hrs
Lift moves from ground floor to fourth

floor and fourth to ground

about elevator controller by
moving the lift from one floor to
another
Implementation Of Alarm Clock

Controller Using Embedded
Microcontroller Trainer

about alarm clock in embedded
trainer
53
6hrs
Implementation Of Model Train

about train controller in
embedded trainer
64
6hrs
100
6hrs
Implementation of elevator controller

using 8051 microcontroller
Controller Using Embedded

Microcontroller Trainer
6
Working Of A PLL Synthesizing

Oscillator

about PLL
*-As in Lab Manual


I YEAR
VLSI
Evaluation scheme Internal Assessment

EC
No.
Evaluation
Components
Duration
Weightage
Observation
Continuous
20%
Record
Continuous
30%
Attendance
Continuous
30%
Model lab
3hr
20%
Timings for chamber consultation: Students should contact the Course Instructor in her/his
chamber during lunch break.
STUDENTS GUIDELINES
There are 3 hours allocated to a laboratory session in VLSI DESIGN LAB. It is a necessary part
of the course at which attendance is compulsory.
Here are some guidelines to help you perform the Programs and to submit the reports:
1. Read all instructions carefully and proceed according to that.

2. Ask the faculty if you are unsure of anything program or any concept.
3. Execute the programs and save the results. If any unexpected or wrong results are
appeared check the program or else you can raise the same error to the faculty.
4. Write up full and suitable conclusions for each experiment.
5. After completing the experiment complete the observation and get signature from the
staff.
6. Before coming to next lab make sure that you complete the record and get sign from the
faculty.
STAFF SIGNATURE
HOD

I YEAR
VLSI
EX NO: 1
DATE :
IMPLEMENTATION OF 8-BIT ALU IN FPGA/CPLD
AIM:
To implement an 8-bit ALU in FPGA/CPLD.
SOFTWARE USED:
Xilinx ISE 9.2i
APPARATUS REQUIRED:
Spartan 3E trainer kit
Power Chord
Interfacing cable
PROCEDURE:
Open Xilinx 9.2i software to write a program for 8-bit ALU.
Declare input and output in entity.
To represent the arithmetic, logical and shifting operations in architecture.
Then save the program and check the syntax.
Assign the package pins for input and output which is mentioned in entity.
Configuring the impact in generating programming to download the program.
Then check the result in FPGA kit

I YEAR
VLSI
THEORY:
The arithmetic logic unit (ALU) is the brawn of the computer, the device that performs
the arithmetic operations like addition and subtraction or logical operations like AND and
OR.ALU was designed to perform arithmetic and logical operations for controller. Arithmetic
operations performed are 8-bit addition and subtraction. Logical operations performed are AND,
OR, XOR and NOT. ALU also calculates 1s and 2s complement for the 8-bit input and
compares the two inputs using 8-bit comparator. ALU also consist of two input 8-bit registers to
hold that data during operation and output register to hold result of operation. Fig. 1 shows the
entity for ALU.
An ALU must process numbers using the same format as the rest of the digital circuit.
The format of modern processors is almost always the two's complement binary number
representation. Early computers used a wide variety of number systems, including Ones
complement, Two's complement, sign-magnitude format, and even true decimal systems, with
various representation of the digits. ALUs for each one of these that makes it easier for the ALUs
to calculate additions and subtractions. The ones complement and two's complement number
systems allow for subtraction to be accomplished by adding the negative of a number in a very
simple way which negates the need for specialized circuits to do subtraction; however,
calculating the negative in two's complement requires adding a one to the low order bit and
propagating the carry.
An alternative way to do two's complement subtraction of AB is to present a one to the
carry input of the adder and use B rather than B as the second input. The arithmetic, logic and
shift circuits introduced in previous sections can be combined into one ALU with common
selection.
A. Design of 8-bit Adder and Subtractor
8-bit adder and subtractor was implemented using fast adder based on the principle of
carry look ahead. The mode control signal was used to decide on the operation of addition and
subtraction. The mode control signal performs 2s complement operation during subtraction
only.
10

I YEAR
VLSI
B. Design of 8-bit Logical block

8-bit logical operations were performed on the data bitwise. This block simply consists of
parallel gates connected to perform desired operation.
C. Design of comparator
8-bitcomparator compares the two inputs and generates the high signal for A greater than
B, A equal to B and A less than B.
CPLD:
A complex programmable logic device (CPLD) is a programmable logic device with
complexity between that of PALs and FPGAs, and architectural features of both. The building
block of a CPLD is the macro cell, which contains logic implementing disjunctive normal form
expressions and more specialized logic operations. The main distinction between FPGA and
CPLD device architectures is that FPGAs are internally based on look-up tables (LUTs) while
CPLDs form the logic functions with sea-of-gates.
PROGRAM:
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.math_complex.all;
use ieee.math_real.all;
use ieee.std_logic_misc.all;
entity alu is
port (a,b : inout std_logic_vector (7 downto 0);
sel : in bit_vector (3 downto 0);
o : out std_logic_vector (7 downto 0);
o1 : inout std_logic_vector (15 downto 0));
11

I YEAR
VLSI
end alu;
architecture alu1 of alu is
begin
process (a,b,sel)
begin
case sel is
when 0000=>
o<= a;
when 0001=>
o<= not(a);
when 0010=>
o<= a + 1;
when 0011=>
o<= a 1;
when 0100=>
o<= a and b;
when 0101=>
o<= a or b;
when 0110=>
o<= a nand b;
when 0111=>
o<= a nor b;
when 1000=>
o<= a xor b;
when 1001=>
o<= not( a xor b);
when 1010 =>
o<= a + b;
when 1011=>
o<= a b;
12

I YEAR
VLSI
when 1100=>
o1<= a * b;
when 1101=>
o<= a (6 downto 0) & a (7);
when 1110=>
o<= a (0) & a (7 downto 1);
when 1111=>
o<= a (6 downto 0) & 0;
when others =>
end case;
end process;
end alu1;
RESULT:
Thus 8-bit ALU was implemented using FPGA/CPLD.
13

I YEAR
VLSI
VIVA QUESTIONS:
1. What are the types of operations which can be done by ALU?
Fixed-Point Operations
Floating Point Operations
2. What are the applications of FPGA?
Aerospace and Defense
ASIC Prototyping
Broadcast
Consumer Electronics Video & Image Processing
Medical
3. Which is better CPLD or FPGA?
CPLD
CPLDs are available in a range of densities, scaling from the simplest logic design to the
most complex that integrate logic, high-performance multiport and FIFO memory, and a
SERDES for demanding communications designs. CPLDs are cheap too.
4. Can we perform logarithm in ALUs?
NO. only arithmetic and logical operations can be done by ALUs.
5. In which applications ALUs are used?
The ALU is responsible for complex mathematical calculations, such as floating point math.
It does not have any specific additional use as related to databases, except to say that the
database, as any other software, uses the ALU to perform sums, averages, and so on during
queries.
14

EX NO: 2
I YEAR
VLSI
IMPLEMENTATION OF 4-BIT SLICED PROCESSOR IN
DATE :
FPGA/CPLD
AIM:
To implement a 4-bit sliced processor in FPGA/CPLD
SOFTWARE USED:
XILINX ISE 9.2i
APPARATUS REQUIRED:
SPARTAN 3E trainer kit
Power chord
PROCEDURE:
Open Xilinx 9.2i software to write a program for 8-bit ALU.
Declare input and output in entity.
Output is feedback to input to obtain the solution.
Then save the program and check the syntax.
Assign the package pins for input and output which is mentioned in entity.
Configuring the impact in generating programming to download the program.
Then check the result in FPGA kit
15

I YEAR
VLSI
THEORY:
CPLD:
A complex programmable logic device (CPLD) is a programmable logic device with
complexity between that of PALs and FPGAs, and architectural features of both. The building
block of a CPLD is the macro cell, which contains logic implementing disjunctive normal form
expressions and more specialized logic operations. The main distinction between FPGA and
CPLD device architectures is that FPGAs are internally based on look-up tables (LUTs) while
CPLDs form the logic functions with sea-of-gates.
INSTRUCTION FORMAT AND CONTROLS OF AMD2901
A Address B Address
I8 I7 I6
I5 I4 I3
I2
I1
I0
I2 I1 I0
Ci
16

I5
I4
I3
ALU
FUNCTIONS
R+S+Ci
S-R-Ci
R-S-Ci
I8
I7
I6
RAM
F>Q
F>B
F>B
F/2>B
F/2>B
2 F>B
2Q>Q
2F>B
I YEAR
VLSI
Q/2>Q
17

In/Out
A Address
Write Enable
R3
RAM Shift. R0
In/Out
Q3
In/Out
Q Shift.
Q0
I YEAR
VLSI
In/Out
Q Register
Two port RAM

Port A: Read only
Port B: Read/Write
B Address
16*4
Ext. Input
0000
A Latches
B Latches A
B
0
R-MUX
S-MUX
R
Cin
CN+4
8 Functions High Speed
F3
ALU
Out-MUX
F
OE
Out-Buffer
Y(4 bits)
Output data
18

I YEAR
VLSI
CONTROLS OF AMD2909
ADDRESS SELECTION
S1
S2
SOURCE FOR Y OUTPUT
Micro program counter
Register(R)
Push pull stack(STKO)
Direct input(D)
STACK SELECTION
FE
PUP
STACK CHANGE
No change
Increment stack pointer then

increment current pc onto
STKO
Decrement stack pointer
19

I YEAR
VLSI
OUTPUT CONTROL
ORi
ZERO
OE
Yi
Hi-Zi
0
1
Sources selected by s1,s0
PROGRAM:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--use work.TYPES.all;
--use work.MVL7_functions.all; -- some MVL7 functions
--use work.synthesis_types.all; -- some data types ( hints for synthesis)
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity bitslice2 is
Port ( I : in STD_LOGIC_VECTOR(8 downto 0);
--Aadd : in integer range 0 to 15;
--Badd : in integer range 0 to 15;
Aadd : in STD_LOGIC_VECTOR(3 downto 0);
Badd : in STD_LOGIC_VECTOR(3 downto 0);
D : in STD_LOGIC_VECTOR(3 downto 0);
CLK : in STD_LOGIC;
C0 : in STD_LOGIC;
20

I YEAR
VLSI
OEBAR : in STD_LOGIC;
RAM0 : inout STD_LOGIC;
RAM3 : inout STD_LOGIC;
Q0 : inout STD_LOGIC;
Q3 : inout STD_LOGIC;
Y : out STD_LOGIC_vector(3 downto 0);
C4 : out STD_LOGIC;
Gbar : out STD_LOGIC;
Pbar : out STD_LOGIC;
OVR : out STD_LOGIC;
F3 : out STD_LOGIC;
F30 : out STD_LOGIC);
-- ram_result : out-- std_logic_vector(3 downto 0));
end bitslice2;
architecture Behavioral of bitslice2 is
begin
process
variable A,B : std_logic_vector(3 downto 0);
variable RAM : std_logic_vector(15 downto 0);
variable Q : std_logic_vector(3 downto 0);
variable RE,S : std_logic_vector(3 downto 0);
variable F : std_logic_vector(3 downto 0);
variable dout : std_logic_vector(3 downto 0);
variable R_ext, S_ext, result : std_logic_vector(4 downto 0);
variable temp_p, temp_g : std_logic_vector(3 downto 0);
begin
wait until ( (clk = '0') and (not clk'stable) );
A := Aadd; -- RAM OUTPUTS ( ADDRESSED BY Aadd AND Badd ) ARE
B := Badd; -- MADE AVAILABLE TO ALU SOURCE SELECTOR
-- SELECT THE SOURCE OPERANDS FOR ALU. SELECTED OPERANDS ARE "RE"
AND "S".
case I(2 downto 0) is
when "000" =>
RE := A;
21

I YEAR
VLSI
S := Q;
when "001" =>
RE := A;
S := B;
when "010" =>
RE := "0000";
S := Q;
when "011" =>
RE := "0000";
S := B;
when "100" =>
RE := "0000";
S := A;
when "101" =>
RE := D;
S := A;
when "110" =>
RE := D;
S := Q;
when "111" =>
RE := D;
S := "0000";
when others =>
end case;
-- SELECT THE FUNCTION FOR ALU.
-- TO FACILITATE COMPUTATION OF CARRY-OUT "C4", WE EXTEND THE CHOSEN
-- ALU OPERANDS "RE" AND "S" (4 BIT OPERANDS) BY 1 BIT IN THE MSB
POSITION.
-- THUS THE EXTENDED OPERANDS "R_EXT" AND "S_EXT" (5 BIT OPERANDS)
ARE
-- FORMED AND ARE USED IN THE ALU OPERATION. THE EXTRA BIT IS SET TO '0'
-- INITIALLY. THE ALU'S EXTENDED OUTPUT ( 5 BITS LONG) IS "result".
22

I YEAR
VLSI
-- IN THE ADD/SUBTRACT OPERATIONS, THE CARRY-INPUT "C0" (1 BIT) IS

EXTENDED
-- BY 4 BITS ( ALL '0') IN THE MORE SIGNIFICANT BITS TO MATCH ITS LENGTH TO
-- THAT OF "R_ext" AND "S_ext". THEN, THESE THREE OPERANDS ARE ADDED.
-- ADD/SUBTRACT OPERATIONS ARE DONE ON 2'S COMPLEMENT OPERANDS.
when "000" =>
R_ext := '0' & RE;
S_ext := '0' & S;
result := R_ext + S_ext + ("0000" & C0);
when "001" =>
R_ext := '0' & not(RE);
S_ext := '0' & S;
result := S_ext - R_ext - ("0000" & not (C0));
when "010" =>
R_ext := '0' & RE;
S_ext := '0' & not(S);
result := R_ext - S_ext - ("0000" & not (C0));
when "011" =>
R_ext := '0' & RE;
S_ext := '0' & S;
result := R_ext or S_ext;
when "100" =>
R_ext := '0' & RE;
S_ext := '0' & S;
result := R_ext and S_ext;
when "101" =>
R_ext := '0' & RE;
S_ext := '0' & S;
result := (not R_ext) and S_ext;
when "110" =>
R_ext := '0' & RE;
S_ext := '0' & S;
result := R_ext xor S_ext;
when "111" =>
R_ext := '0' & RE;
23

I YEAR
VLSI
S_ext := '0' & S;

result := R_ext xnor S_ext;
when others =>
end case;
-- EVALUATE OTHER ALU OUTPUTS.

-- FROM EXTENDED OUTPUT "result" ( 5 BITS), WE OBTAIN THE NORMAL ALU
OUTPUT,
-- "F" (4 BITS) BY LEAVING OUT THE MSB ( WHICH CORRESPONDS TO CARRY-OUT
-- "C4").
-- TO FACILITATE COMPUTATION OF CARRY LOOKAHEAD TERMS "Pbar" AND
"Gbar", WE
-- COMPUTE INTERMEDIATE TERMS "temp_p" AND "temp_g".
C4 <= result(4) ;
OVR <= not ((R_ext(3) xor S_ext(3)) and
(R_ext(3) xor result(3))) ;
F := result(3 downto 0) ;
temp_p := R_ext(3 downto 0) or S_ext(3 downto 0);
temp_g := R_ext(3 downto 0) and S_ext(3 downto 0);
Pbar <= not( temp_p(0) and temp_p(1) and temp_p(2) and temp_p(3) ) ;
Gbar <= not( temp_g(3) or
( temp_p(3) and temp_g(2) ) or
(temp_p(3) and temp_p(2) and temp_g(1) ) or
(temp_p(3) and temp_p(2) and temp_p(1) and temp_g(0) )
);
F3 <= result(3) ;
F30 <= not ( result(3) or result(2) or result(1) or result(0) ) ;
-- GENERATE INTERMEDIATE OUTPUT "dout" AND BIDIRECTIONAL SHIFTER

SIGNALS.
-- WRITE TO DESTINATION(S) WITH/WITHOUT SHIFTING. RAM DESTINATIONS ARE
-- ADDRESSED BY "Badd".
when "000" =>
dout := F;
-- INTERMEDIATE OUTPUT
24

Q := F;
I YEAR
VLSI
-- WRITE TO
DESTINATION
Q0 <= 'Z';
Q3 <= 'Z';
RAM0 <= 'Z';
RAM3 <= 'Z';
when "001" =>
dout := F;
Q0 <= 'Z';
Q3 <= 'Z';
RAM0 <= 'Z';
RAM3 <= 'Z';
when "010" =>
dout := A;
Q0 <= 'Z';
RAM(3 downto 0) := F;
Q3 <= 'Z';
RAM0 <= 'Z';
RAM3 <= 'Z';
when "011" =>
dout := F;
RAM(3 downto 0) := F;
Q0 <= 'Z';
Q3 <= 'Z';
RAM0 <= 'Z';
RAM3 <= 'Z';
when "100" =>
dout := F;
RAM(3 downto 0) := RAM3 & F (3
downto 1);
Q := Q3 & Q(3 downto 1);
Q3 <= 'Z';
RAM3 <= 'Z';
RAM0 <= F(0) ;
-- SHIFTER
SIGNALS
Q0 <= Q(0) ;
when "101" =>
dout := F;
RAM(3 downto 0) := RAM3 & F (3
downto 1);
25

I YEAR
VLSI
Q0 <= 'Z';
Q3 <= 'Z';
RAM3 <= 'Z';
RAM0 <= F(0) ;
when "110" =>
dout := F;
RAM(3 downto 0) := F (2 downto 0)
& RAM0;
Q := Q(2 downto 0) & Q0;
Q0 <= 'Z';
RAM0 <= 'Z';
RAM3 <= F(3) ;
Q3 <= Q(3) ;
when "111" =>
dout := F;
RAM(3 downto 0) := F (2 downto 0)
& RAM0;
Q0 <= 'Z';
Q3 <= 'Z';
RAM0 <= 'Z';
RAM3 <= F(3) ;
when others =>
end case;
-- GENERATE DATA OUTPUT "Y" FROM INTERMEDIATE OUTPUT "dout".
if (OEbar = '0') then
Y <= dout;
else
Y <= "ZZZZ";
end if;
end process;
end Behavioral;
RESULT:
Thus the program for 4-bit sliced processor was implemented using FPGA/CPLD.
26

I YEAR
VLSI
VIVA QUESTIONS:
1. What is bit slicing?
Bit slicing is a technique for constructing a processor from modules of smaller bit width.
Each of these components processes one bit field or "slice" of an operand. The grouped
processing components would then have the capability to process the chosen full word-length
of a particular software design.
2. What are the differences between FPGA and CPLD?
Elements inside CPLDs are Macro cells (combinational + sequential).Currently CPLDs have
maximum of 1024 Macro cells( see Lattice semiconductor make).
Most of them are flash based and are reprogrammable.
Elements inside FPGAs are combinational cell and sequential cells. The Actel FPGAs
are available as one time programmable and flash based reprogrammable also. The Xilinx
and Altera FPGAs are S-RAM based. The currently available FPGAs have about 2 million
gates capacity.
3. What are the differences between sliced processors and other processors?
ALU's can be attached together in horizontal configurations to create computers that can
handle very large chunks of data at a time.
Advantage of the Bit-slice design is the fact that the two chip design allowed the
chips
to use bipolar chip technology
4. What is the expansion of CPLD?
Complex Programmable Logic Device.
5. What is the basic block of CPLD and FPGA?
CPLD Macro cell
FPGA combinational or sequential cells
27

EX NO: 3
DATE :
I YEAR
VLSI
IMPLEMENTATION OF ELEVATOR CONTROLLER USING 8051

MICROCONTROLLER
[LIFT1 MOVES FROM GROUND FLOOR TO FOURTH FLOOR]
AIM:
To implement elevator controller to show that lift1 moves from ground floor to fourth
floor then produce beep sound using embedded microcontroller.
APPARATUS REQUIRED:
PROCEDURE:
Connect VBMB-022 board to microcontroller trainer kit.
Enter the following program from user RAM address 4100H.
After checking the program and execute the same.
We can see the movement of lift1 from ground floor to 4th floor.
THEORY:
Microcontroller 8051 architecture
It is 8-bit microcontroller, means MC 8051 can Read, Write and Process 8 bit data. This
is mostly used microcontroller in the robotics, home appliances like mp3 player, washing
machines, electronic iron and industries.
128 Byte RAM for Data Storage
MC 8051 has 128 byte Random Access memory for data storage. Random access
memory is non volatile memory. During execution for storing the data the RAM is used. RAM
28

I YEAR
VLSI
consists of the register banks, stack for temporary data storage. It also consists of some special
function register (SFR) which are used for some specific purpose like timer, input output ports
etc. Normally microcontroller has 256 byte RAM in which 128 byte is used for user space which
is normally Register banks and stack. But other 128 byte RAM which consists of SFRs. We will
discuss the RAM in detail in next section. Now what is the meaning of 128 byte RAM. What are
address range which is provided for data storage.
Since 27 bytes so last 7 bits can be changed so total locations are from 00H to 7F H. This
procedure of calculating the memory address is called as memory mapping. We can save data
on memory locations from 00H to 7FH. Means total 128 byte space from 00H to 7FH is provided
for data storage.
4KB ROM
In 8051, 4KB read only memory (ROM) is available for program storage. This is used for
permanent data storage. Or the data which is not changed during the processing like the program
or algorithm for specific applications. This is volatile memory; the data saved in this memory
does not disappear after power failure. We can interface up to 64KB ROM memory externally if
the application is large. These sizes are specified different by their companies.
Address Range of PC
Address range of PC means program counter (which points the next instruction to be
executing) can be moved between these locations or we can save the program from this location
to this location. The address range can be calculated in the same way just like the RAM
which is discussed in previous section. Address range of PC is 0000H to 0FFFH means total
4KB locations are available from 0000H to 0FFFH. At which we can save the program.
Timers and Counters
Timer means which can give the delay of particular time between some events. For
example on or off the lights after every 2 sec. This delay can be provided through some assembly
program but in microcontroller two hardware pins are available for delay generation. These
hardware pins can be also used for counting some external events. How much times a number is
repeated in the given table is calculated by the counter. In MC8051, two timer pins are available
T0 and T1, by these timers we can give the delay of particular time if we use these in timer
mode. We can count external pulses at these pins if we use these pins in counter mode. 16 bits
29

I YEAR
VLSI
timers are available. Means we can generate delay between 0000H to FFFFH. Two special
function registers are available. If we want to load T0 with 16 bit data then we can load separate
lower 8 bit in TL0 and higher 8 bit in TH0. In the same way for T1. TMOD, TCON registers are
used for controlling timer operation.
Serial Port
There are two pins available for serial communication TXD and RXD. Normally TXD is
used for transmitting serial data which is in SBUF register, RXD is used for receiving the serial
data. SCON register is used for controlling the operation. There are four modes of serial
communication which has been discussed in next chapter.
Input Output Ports
There are four input output ports available P0, P1, P2, P3.Each port is 8 bit wide and has
special function register P0, P1, P2, P3 which are bit addressable means each bit can be set or
reset by the Bit instructions (SETB for high, CLR for low) independently. The data at any port
which is transmitting or receiving is in these registers. The port 0 can perform dual works. It is
also used as Lower order address bus (A0 to A7) multiplexed with 8 bit data bus P0.0 to P0.7 is
AD0 to AD7 respectively the address bus and data bus is demultiplex by the ALE signal and
latch which is further discussed in details. Port 2 can be used as I/O port as well as higher order
address bus A8 to A15. Port 3 also have dual functions it can be worked as I/O as well as each
pin of P3 has specific function. P3.0 RXD {Serial I / P for Asynchronous communication
Serial O / P for synchronous communication.
P3.1 TXD Serial data transmit.
P3.2 INT0 External Interrupt 0.
P3.4 T0 Clock input for counter 0.
P3.6 WR Signal for writing to external memory.
P3.7 RD Signal for reading from external memory.
30

I YEAR
VLSI
When external memory is interfaced with 8051 then P0 and P2 cant be worked as I/O
port they works as address bus and data bus, otherwise they can be accessed as I/O ports.
Oscillator
It is used for providing the clock to MC8051 which decides the speed or baud rate of
MC.We use crystal which frequency vary from 4MHz to 30 MHz, normally we use 11.0592
MHz frequency.
Interrupts
Interrupts are defined as requests because they can be refused (masked) if they are not
used, that is when an interrupt is acknowledged. A special set of events or routines are followed
to handle the interrupts. These special routines are known as interrupt handler or interrupt service
routines (ISR). These are located at a special location in memory. INT0 and INT1 are the pins
for external interrupts.
PROGRAM:
ADDRESS
OPCODE
4100
MNEMONICS
COMMENTS
START:
4100
74 03
4102
90 FF CC
4105
F0
4106
12 41 41
4109
74 02
410B
F0
410C
74 80
410E
90 FF C0
MOV a,#03h
MOV dptr,#stat_0u
Default open doors of lift 1 and lift

2
MOVX @dptr,a
Call delay
MOV a,#02h
Close door of lift1
MOVX @ dptr,a
MOV @,#80h
MOV dptr,#lift1
Indicates lift1 is in ground floor
31

4111
F0
4112
74 01
4114
90 FF C4
MOV dptr,#lift 2
4117
F0
MOVX @dptr,a
4118
12 41 41
Call delay
411B
90 FF C0
MOV dptr,#lift 1
411E
74 40
4120
F0
4121
12 41 41
4124
74 20
4126
F0
4127
12 41 41
412A
74 10
412C
F0
412D
12 41 41
4130
74 08
4132
F0
4133
74 0B
I YEAR
VLSI
MOVX @dptr,a
MOV a,#01h
Indicates lift 1 is in fourth floor
MOV a,#40h
MOVX @dptr,a
Call delay
MOV a,#20h
MOVX @dptr,a
Call delay
MOV a,#10h
MOVX @dptr,a
Call delay
MOV a,#08h
MOVX @dptr,a
MOV a,#0Bh
Beep for door open
32

ADDRESS
OPCODE
4165
30 8D FD
MNEMONICS
Jnb tf0,$
I YEAR
VLSI
COMMENTS
0FFFF-(16 BIT TIMER
VALVE)+1
4168
C2 8C
Clr tr0
416A
C2 8D
Clr tf0
416C
22
ret
1 stop the timer 0

1 clear timer flag 0
Return from subroutine
end
RESULT:
Thus elevator controller which moving a lift1 from ground floor to fourth floor was
implemented using embedded micro controller
33

I YEAR
VLSI
VIVA QUESTIONS:
1. What is the expansion PIC?

PIC Peripheral Interface Controller
2. What is the Address space in 8051?
Address range of PC is 0000H to 0FFFH means total 4KB locations are available from
0000H to 0FFFH. At which we can save the program.
3. What is the available ROM size in 8051?
Available ROM size in 8051 4KB.
4. What are the timer registers in 8051?
TMOD and TCON
5. What is the size of the 8051 micro controller?
8051 is an 8 bit micro controller.
34

EX NO: 4
I YEAR
VLSI

MICROCONTROLLER
DATE :
AIM:
To implement elevator controller to show that lift1 moves from fourth floor to ground
floor then produce beep sound using 8051 microcontroller.
APPARATUS REQUIRED:
PROCEDURE:
35

I YEAR
VLSI
THEORY:
for data storage.
4KB ROM
Address Range of PC
36

I YEAR
VLSI
Timers and Counters

Serial Port
Input Output Ports
37

I YEAR
VLSI

Oscillator
MHz frequency.
Interrupts
PROGRAM:
ADDRESS
OPCODE
4100
MNEMONICS
COMMENTS
START:
4100
74 03
4102
90 FF CC
4105
F0
MOV a,#03h
MOV dptr,#stat_0u

2
MOVX @dptr,a
38

4106
12 41 41
4109
74 02
410B
F0
410C
74 08
410E
90 FF C0
MOV dptr,#lift1
4111
F0
MOVX @dptr,a
4112
74 01
4114
90 FF C4
MOV dptr,#lift 2
4117
F0
MOVX @dptr,a
4118
12 41 41
Call delay
411B
90 FF C0
MOV dptr,#lift 1
411E
74 10
4120
F0
4121
12 41 41
4124
74 20
4126
F0
4127
12 41 41
412A
74 40
412C
F0
412D
12 41 41
Call delay
I YEAR
VLSI
Close door of lift1
MOV a,#02h
MOVX @ dptr,a
MOV @,#80h
Indicates lift1 is in fourth floor
Indicates lift 1 is in ground floor
MOV a,#01h
MOV a,#40h
MOVX @dptr,a
Call delay
MOV a,#20h
MOVX @dptr,a
Call delay
MOV a,#10h
MOVX @dptr,a
Call delay
39

4130
74 80
4132
F0
4133
74 0B
ADDRESS
OPCODE
4165
30 8D FD
I YEAR
VLSI
MOV a,#08h
MOVX @dptr,a
Beep for door open
MOV a,#0Bh
MNEMONICS
Jnb tf0,$
COMMENTS
0FFFF-(16 BIT TIMER
VALVE)+1
4168
C2 8C
Clr tr0
416A
C2 8D
Clr tf0
416C
22
ret
1 stop the timer 0

RESULT:
Thus elevator controller which moving a lift1 from fourth floor to ground floor was
implemented using embedded micro controller
40

EX NO: 5
I YEAR
VLSI

MICROCONTROLLER
DATE :
AIM:
To implement elevator to show that lift1 moves from ground floor to fourth floor then
produce beep sound controller using embedded microcontroller.
APPARATUS REQUIRED:
PROCEDURE:
THEORY:
41

I YEAR
VLSI
for data storage.
4KB ROM
Address Range of PC
Timers and Counters
42

I YEAR
VLSI
Serial Port
Input Output Ports

43

I YEAR
VLSI
Oscillator
MHz frequency.
Interrupts
PROGRAM:
ADDRESS
OPCODE
4100
MNEMONICS
COMMENTS
START:
4100
74 03
4102
90 FF CC
4105
F0
4106
12 41 41
4109
74 02
410B
F0
410C
74 80
410E
90 FF C4
MOV a,#03h
MOV dptr,#stat_0u

2
MOVX @dptr,a
Call delay
MOV a,#02h
Close door of lift1
MOVX @ dptr,a
MOV @,#80h
MOV dptr,#lift1
44

4111
F0
4112
74 01
4114
90 FF C0
MOV dptr,#lift 2
4117
F0
MOVX @dptr,a
4118
12 41 41
Call delay
411B
90 FF C4
MOV dptr,#lift 1
411E
74 40
4120
F0
4121
12 41 41
4124
74 20
4126
F0
4127
12 41 41
412A
74 10
412C
F0
412D
12 41 41
4130
74 08
4132
F0
4133
74 0B
I YEAR
VLSI
MOVX @dptr,a
MOV a,#01h
Indicates lift2 is in seventh floor
MOV a,#40h
MOVX @dptr,a
Call delay
MOV a,#20h
MOVX @dptr,a
Call delay
MOV a,#10h
MOVX @dptr,a
Call delay
MOV a,#08h
MOVX @dptr,a
MOV a,#0Bh
Beep for door open
45

ADDRESS
OPCODE
4165
30 8D FD
MNEMONICS
Jnb tf0,$
I YEAR
VLSI
COMMENTS
0FFFF-(16 BIT TIMER
VALVE)+1
4168
C2 8C
Clr tr0
416A
C2 8D
Clr tf0
416C
22
ret
1 stop the timer 0

RESULT:
Thus elevator controller which moving a lift2 from ground floor to fourth floor was
implemented was implemented using embedded micro controller
46

EX NO: 6
I YEAR
VLSI

MICROCONTROLLER
DATE :
AIM:
To implement elevator controller to show that lift2 moves from fourth floor to ground
floor then produce beep sound using embedded microcontroller.
APPARATUS REQUIRED:
PROCEDURE:
THEORY:
47

I YEAR
VLSI
for data storage.
4KB ROM
Address Range of PC
Timers and Counters
48

I YEAR
VLSI
Serial Port
Input Output Ports
49

I YEAR
VLSI
Oscillator
MHz frequency.
Interrupts
PROGRAM:
ADDRESS
OPCODE
4100
MNEMONICS
COMMENTS
START:
4100
74 03
4102
90 FF CC
4105
F0
4106
12 41 41
4109
74 02
410B
F0
410C
74 08
410E
90 FF C4
MOV dptr,#lift1
4111
F0
MOVX @dptr,a
4112
74 01
MOV a,#03h
MOV dptr,#stat_0u

2
MOVX @dptr,a
Call delay
MOV a,#02h
Close door of lift2
MOVX @ dptr,a
MOV @,#80h
MOV a,#01h
Indicates lift2 is in fourth floor
50

4114
90 FF C0
MOV dptr,#lift 2
4117
F0
MOVX @dptr,a
4118
12 41 41
Call delay
411B
90 FF C4
MOV dptr,#lift 1
411E
74 10
4120
F0
4121
12 41 41
4124
74 20
4126
F0
4127
12 41 41
412A
74 40
412C
F0
412D
12 41 41
4130
74 80
4132
F0
4133
74 0B
I YEAR
VLSI
MOV a,#40h
MOVX @dptr,a
Call delay
MOV a,#20h
MOVX @dptr,a
Call delay
MOV a,#10h
MOVX @dptr,a
Call delay
MOV a,#08h
MOVX @dptr,a
MOV a,#0Bh
Beep for door open
51

ADDRESS
OPCODE
4165
30 8D FD
MNEMONICS
Jnb tf0,$
I YEAR
VLSI
COMMENTS
0FFFF-(16 BIT TIMER
VALVE)+1
4168
C2 8C
Clr tr0
416A
C2 8D
Clr tf0
416C
22
ret
1 stop the timer 0

RESULT:
Thus elevator controller which moving a lift2 from fourth floor to ground floor was
implemented using embedded micro controller.
52

EX NO: 7
I YEAR
VLSI
IMPLEMENTATION OF ALARM CLOCK CONTROLLER USING

EMBEDDED MICROCONTROLLER TRAINER
DATE :
AIM:
To implement an alarm clock controller that rotates using embedded microcontroller
trainer.
SOFTWARE REQUIRED:
MPLAB IDE V7.41
PIC ISP
HARDWARE REQUIRED:
Interfacing cable
PROCEDURE:
Open MAT lab software, select the project wizard select 16f877 controller and select
the CCS compiler tool suite for PIC family.
Type the program in the program window and save it with .c extension.
Add the source file and compile the program by using CCS compiler.
Open PIC ISP tool and download the program to microcontroller then enter the reset
to run the program.
THEORY:
PIC is a family of modified Harvard architecture microcontrollers made by Microchip
Technology, derived from the PIC1650[1][2][3] originally developed by General Instrument's
Microelectronics Division. The name PIC initially referred to "Peripheral Interface
Controller".[4][5]
53

I YEAR
VLSI
PICs are popular with both industrial developers and hobbyists alike due to their low
cost, wide availability, large user base, extensive collection of application notes, availability of
low cost or free development tools, and serial programming (and re-programming with flash
memory) capability. They are also commonly used in educational programming as they often
come with the easy to use 'pic logicator' software.
The PIC architecture is characterized by its multiple attributes:
Separate code and data spaces (Harvard architecture).
A small number of fixed length instructions
Most instructions are single cycle execution (2 clock cycles, or 4 clock cycles in 8-bit
models), with one delay cycle on branches and skips
One accumulator (W0), the use of which (as source operand) is implied (i.e. is not
encoded in the opcode)
All RAM locations function as registers as both source and/or destination of math and
other functions.[6]
A hardware stack for storing return addresses
A fairly small amount of addressable data space (typically 256 bytes), extended through
banking
Data space mapped CPU, port, and peripheral registers
The program counter is also mapped into the data space and writable (this is used to
implement indirect jumps).
There is no distinction between memory space and register space because the RAM
serves the job of both memory and registers, and the RAM is usually just referred to as the
register file or simply as the registers.
Data space (RAM)
PICs have a set of registers that function as general purpose RAM. Special purpose
control registers for on-chip hardware resources are also mapped into the data space. The
addressability of memory varies depending on device series, and all PIC devices have some
54

I YEAR
VLSI
banking mechanism to extend addressing to additional memory. Later series of devices feature
move instructions which can cover the whole addressable space, independent of the selected
bank. In earlier devices, any register move had to be achieved via the accumulator.
To implement indirect addressing, a "file select register" (FSR) and "indirect register"
(INDF) are used. A register number is written to the FSR, after which reads from or writes to
INDF will actually be to or from the register pointed to by FSR. Later devices extended this
concept with post- and pre- increment/decrement for greater efficiency in accessing sequentially
stored data. This also allows FSR to be treated almost like a stack pointer (SP).
External data memory is not directly addressable except in some high pin count PIC18
devices.
Code space
The code space is generally implemented as ROM, EPROM or flash ROM. In general,
external code memory is not directly addressable due to the lack of an external memory
interface. The exceptions are PIC17 and select high pin count PIC18 devices
Word size
All PICs handle (and address) data in 8-bit chunks. However, the unit of addressability of
the code space is not generally the same as the data space. For example, PICs in the baseline
(PIC12) and mid-range (PIC16) families have program memory addressable in the same
wordsize as the instruction width, i.e. 12 or 14 bits respectively. In contrast, in the PIC18 series,
the program memory is addressed in 8-bit increments (bytes), which differs from the instruction
width of 16 bits.
In order to be clear, the program memory capacity is usually stated in number of (single
word) instructions, rather than in bytes.
55

I YEAR
VLSI
Stacks
PICs have a hardware call stack, which is used to save return addresses. The hardware
stack is not software accessible on earlier devices, but this changed with the 18 series devices.
Hardware support for a general purpose parameter stack was lacking in early series, but
this greatly improved in the 18 series, making the 18 series architecture more friendly to high
level language compilers.
Instruction set
A PIC's instructions vary from about 35 instructions for the low-end PICs to over 80
instructions for the high-end PICs. The instruction set includes instructions to perform a variety
of operations on registers directly, the accumulator and a literal constant or the accumulator and
a register, as well as for conditional execution, and program branching.
Some operations, such as bit setting and testing, can be performed on any numbered
register, but bi-operand arithmetic operations always involve W (the accumulator), writing the
result back to either W or the other operand register. To load a constant, it is necessary to load it
into W before it can be moved into another register. On the older cores, all register moves
needed to pass through W, but this changed on the "high end" cores.
PIC cores have skip instructions which are used for conditional execution and branching.
The skip instructions are 'skip if bit set' and 'skip if bit not set'. Because cores before PIC18 had
only unconditional branch instructions, conditional jumps are implemented by a conditional skip
(with the opposite condition) followed by an unconditional branch. Skips are also of utility for
conditional execution of any immediate single following instruction.
The 18 series implemented shadow registers which save several important registers
during an interrupt, providing hardware support for automatically saving processor state when
servicing interrupts.
56

I YEAR
VLSI
PROGRAM:
#include <16F877.H>
#use delay(clock=20000000)
#use rs232(baud=19200, xmit=PIN_C6, rcv=PIN_C7)
#use I2C(MASTER,sda=PIN_C4,scl=PIN_C3)
unsigned int time[]={0x05,0x57};
unsigned int readtime[0x02];
unsigned long int second,second1,minute,minute1;
unsigned int a,b,a1,b1,c1,d1,dat;
int i,j;
unsigned char array[10]={0x3f,0x06,0x5b,0x4f,0x66,0x6d,0x7d,0x07,0x7f,0x67};
void set_rtc_time()
{
for (i=2;i<=3;i++)
{
i2c_start();
i2c_write(0xa0 | 0x00);
i2c_write(i);
i2c_write(time[(i-2)]);
i2c_stop();
}
}
void get_rtc_time()
{
for (i=2;i<=3;i++)
{
delay_ms(5);
57

I YEAR
VLSI
i2c_start();
i2c_write(0xa0);
i2c_write(i);
i2c_start();
i2c_write(0xa0 | 0x01);
readtime[(i-2)]= i2c_read(0);
i2c_stop();
}
}
void display_sec0()
{
delay_ms(5);
i2c_start();
i2c_write(0x44);
i2c_write(0x00);
i2c_write(array[a1]);
i2c_write(0xf7);
i2c_stop();
}
void display_sec1()
{
delay_ms(5);
i2c_start();
i2c_write(0x44);
i2c_write(0x00);
i2c_write(array[b1]);
i2c_write(0xfb);
i2c_stop();
58

I YEAR
VLSI
void display_min0()
{
delay_ms(5);
i2c_start();
i2c_write(0x44);
i2c_write(0x00);
i2c_write(array[c1]);
i2c_write(0xfd);
i2c_stop();
}
void display_min1()
{
delay_ms(5);
i2c_start();
i2c_write(0x44);
i2c_write(0x00);
i2c_write(array[d1]);
i2c_write(0xfe);
i2c_stop();
}
void IC_Config()
{
delay_us(1000);
i2c_start();
59

I YEAR
VLSI
i2c_write(0x44);
i2c_write(0x04);
i2c_write(0x00);
i2c_write(0x00);
i2c_stop();
delay_us(1000);
i2c_start();
i2c_write(0x44);
i2c_write(0x06);
i2c_write(0x00);
i2c_write(0x00);
i2c_stop();
delay_us(1000);
i2c_start();
i2c_write(0x44);
i2c_write(0x0a);
i2c_write(0x01);
i2c_write(0x01);
i2c_stop();
delay_us(1000);
}
void alarm_set()
{
output_b(0xff);
if(minute==0x57)
60

I YEAR
VLSI
{
if((second>=0x10)&&(second<=0x14))
{
output_high(PIN_B0);
delay_ms(10);
output_low(PIN_B0);
delay_ms(10);
}
}
void main()
{
IC_Config();
set_rtc_time();
while(1)
{
get_rtc_time();
second = readtime[0];
minute = readtime[1];
printf(" Time : %x : %x \n\r",readtime[1],readtime[0]);
a1 = (second & 0x0f);

b1 = (second & 0xf0);
b1 = b1>>0x04;
61

I YEAR
VLSI
c1 = (minute & 0x0f);

d1 = (minute & 0xf0);
d1 = d1>>0x04;
display_sec0();
display_sec1();
delay_us(50);
display_min0();
display_min1();
alarm_set();
delay_us(500);
}
}
RESULT:
Thus the alarm clock controller was implemented using embedded microcontroller
trainer.
62

I YEAR
VLSI
VIVA QUESTIONS:
1. What is the use of stack in PIC?

PICs have a hardware call stack, which is used to save return addresses.
2. What is size of Data in PIC?
All PICs handle data in form of 8bit chunks.
3. What is the type of architecture used in PIC controller?
PIC uses Harvard architecture instead of von Neumann architecture.
4. How many instructions are used in PIC?
In the range of 35 instructions.
5. What is the use of INDF and FSR?
(INDF) are used.
63

EX NO: 8
I YEAR
VLSI
IMPLEMENTATION OF MODEL TRAIN CONTROLLER USING

DATE :
[ROTATE ONLY]
AIM:
To rotate a model train controller in clockwise direction using embedded microcontroller
trainer.
SOFTWARE REQUIRED:
MPLAB IDE V7.41
PIC ISP
HARDWARE REQUIRED:
Model train interface board
Interfacing cables
PROCEDURE:
to rotate the model train.
THEORY:
Technology, derived from the PIC1650 originally developed by General Instrument's
64

I YEAR
VLSI

Controller".
other functions
banking
65

I YEAR
VLSI
Data space (RAM)

devices.
Code space
interface. The exceptions are PIC17 and select high pin count PIC18 devices.
Word size
width of 16 bits.
66

I YEAR
VLSI
Stacks
Instruction set
67

I YEAR
VLSI
PROGRAM:
#include <16F877.H>
unsigned char data,a,b,c;
int i,j,i1,k=0x15;
unsigned char ls0[]={0x55,0x54,0x50,0x40,0x00,0x00,0x01,0x05,0x15,0x55};
//led0-led3 selector for forward direction.
unsigned char sel[]={0x0c0,0x0c2,0xc4,0xc6,0xc8,0xca,0xcc,0xce,0x0c0};
void init();
void initbuf();
void sensor();
void main()
{
init();
initbuf();
while(1)
{
start1:
for(j=0x00;j<0x09;j++)
{
i1=0x05;
for(i=0x00;i<0x09;i++)
{
68

I YEAR
VLSI
start:
if(i<=0x04)
{
i2c_start();
i2c_write(sel[j]);
i2c_write(k);
i2c_write(ls0[i]);
i2c_write(ls0[i1]);
i1++;
}
if(j==0x08)
goto start1;
if(i>=0x05)
{
i2c_start();
i2c_write(sel[j]);
i2c_write(k+1);
i2c_write(ls0[i-0x04]);
i2c_stop();
i2c_start();
i2c_write(sel[j+1]);
i2c_write(k);
i2c_write(ls0[i1-0x04]);
i1++;
}
if(i != 0x08)
delay_ms(300);
}
}
}
69

I YEAR
VLSI
void init()
{
for(i=0;i<0x08;i++)
{
i2c_start();
i2c_write(sel[i]);
i2c_write(0x15);
i2c_write(0x00);
i2c_write(0x00);
i2c_stop();
}
}
void initbuf()
{
output_d(0x00);
output_low(PIN_E1);
output_high(PIN_E1);
output_d(0x00);
output_low(PIN_E2);
output_d(0x00);
output_low(PIN_B1);
}
RESULT:
Thus the model train controller was rotated in clockwise direction using embedded
microcontroller trainer.
70

EX NO: 9
I YEAR
VLSI

DATE :
[STATION 1 TO STATION 2]
AIM:
To rotate a model train controller from station1 to station 2 using embedded microcontroller
trainer.
SOFTWARE REQUIRED:
MPLAB IDEV7.41
PIC ISP
HARDWARE REQUIRED:
UNIVERSAL PIC EMBEDDED TRAINER
MODEL TRAIN INTERFACE BOARD
INTERFACING CABLES
PROCEDURE:
to rotate the model train from station 1 to station 2.
THEORY:
Technology, derived from the PIC1650 originally developed by General Instrument's
71

I YEAR
VLSI

Controller".
other functions
banking
72

I YEAR
VLSI
Data space (RAM)

devices.
Code space
Word size
width of 16 bits.
73

I YEAR
VLSI
Stacks
Instruction set
74

I YEAR
VLSI
PROGRAM:
#include <16F877.H>

int i,j,i1,k=0x15,j1,j2;
//led0-led3 selector for forward direction.
unsigned char sel[]={0x0c0,0x0c2,0xc4,0xc6,0xc8,0xca,0x0c0};
unsigned char sel1[]={0x0c0,0x0c2,0xc4,0xc6,0xc8,0xca,0xcc,0xce};
void init();
void initbuf();
void sensor();
void station2forward();
void crossingon();
void crossingoff();
void main()
{
init();
initbuf();
while(1)
75

I YEAR
VLSI
{
start1:
for(j=0X00;j<0X07;j++)
{
i1=0x05;
for(i=0x00;i<0x09;i++)
{
start:
if(i<=0x04)
{
i2c_start();
i2c_write(sel[j]);
i2c_write(k);
i2c_write(ls0[i]);
i2c_write(ls0[i1]);
i1++;
}
if((j == 0x05) && (i >= 0x00))
station2forward();
sensor();
if((b != 0x0))
goto start;
start3:
if(i>=0x05)
{
i2c_start();
i2c_write(sel[j]);
i2c_write(k+1);
76

I YEAR
VLSI
i2c_stop();
i2c_start();
i2c_write(k);
i1++;
}
if((j == 0x05) && (i == 0x04))
goto start3;
sensor();
if((b != 0x0))
goto start;
if(i != 0x08)
delay_ms(200);
}
}
}
}
void init()
{
for(i=0;i<0x08;i++)
{
i2c_start();
i2c_write(sel1[i]);
i2c_write(0x15);
i2c_write(0x00);
77

I YEAR
VLSI
i2c_write(0x00);
i2c_stop();
}
}
void initbuf()
{
output_d(0x00);
output_low(PIN_E1);
output_d(0x00);
output_low(PIN_E2);
output_d(0x00);
output_low(PIN_B1);
}
void station2forward()
{
output_d(0x08);
output_low(PIN_E2);
delay_ms(600);
station1.
}
78

I YEAR
VLSI
void sensor()
{
output_low(PIN_B4);
a=input_d();
b = a;
b = b & 0x04;
if(b != 0x04)
crossingon();
b = a;
b = b & 0x08;
if(b != 0x08)
crossingoff();
b=a;
b= b & 0x40;
}
void crossingon()
{
output_d(0xF0);
output_low(PIN_E2);
output_d(0xFF);
output_low(PIN_B1);
output_low(PIN_E0);
79

I YEAR
VLSI
void crossingoff()
{
output_d(0x00);
output_low(PIN_E2);
output_d(0x00);
output_low(PIN_B1);
}
RESULT:
Thus the model train controller was rotated from station1 to station 2 using embedded
80

I YEAR
VLSI
VIVA QUESTIONS:
1. What are the directions of train in your experiment?
2. Can we implement model train controller using any other types of controllers? Why?
3. What is the clock speed of PIC controller?
4. Can we implement an alarm clock without a micro controller? Why?
5. What is the use of INDF and FSR?
81

EX NO:10
I YEAR
VLSI

DATE :
[FORWARD AND REVERSE DIRECTION]
AIM:
To rotate a model train controller in both forward and reverse direction using embedded
SOFTWARE REQUIRED:
MPLAB IDEV7.41
PIC ISP
HARDWARE REQUIRED:
UNIVERSAL PIC EMBEDDED TRAINER
MODEL TRAIN INTERFACE BOARD
INTERFACING CABLES
PROCEDURE:
to rotate the model train in forward direction.
Change the switch position in model train interface board then enter the reset to rotate
the model train in reverse direction.
82

I YEAR
VLSI
THEORY:
Technology, derived from the PIC1650[1][2][3] originally developed by General Instrument's
Controller".
other functions.[6]
banking
83

I YEAR
VLSI
Data space (RAM)
devices.
Code space
Word size
84

I YEAR
VLSI
width of 16 bits.
Stacks
Instruction set
85

I YEAR
VLSI
PROGRAM:
#include <16F877.H>

//unsigned char ls1[]={0x00,0x01,0x05,0x15,0x55};
unsigned char sel[]={0x0c0,0x0c2,0xc4,0xc6,0xc8,0xca,0xcc,0xce,0x0c0};
unsigned char sel1[]={0x0ce,0xcc,0xca,0xc8,0xc6,0xc4,0xc2,0x0c0,0xce};
//unsigned char sig[]={0x01,0x02,0x04,0x08,0x10,0x20,0x40,0x80};
unsigned char i,i1,j,k=0x15,senout=0x00,senout1=0x00,senout2,senout3;
void crossingon();
void crossingoff();
void init();
void initbuf();
void sensor();
void sensor1();
86

I YEAR
VLSI
void station1reverse();
void station2reverse();
void sw();
void sw1();
void reverse();
void forward();
void main()
{
init();
initbuf();
while(1)
{
start1:
for(j=0x00;j<0x09;j++)
{
i1=0x05;
for(i=0x00;i<0x09;i++)
{
start:
if(i<=0x04)
{
i2c_start();
i2c_write(sel[j]);
i2c_write(k);
i2c_write(ls0[i]);
i2c_write(ls0[i1]);
i1++;
}
87

I YEAR
VLSI
if(j==0x08)
goto start1;
sw();
if((b != 0x0))
goto start;
if(i>=0x05)
{
i2c_start();
i2c_write(sel[j]);
i2c_write(k+1);
i2c_stop();
i2c_start();
i2c_write(k);
i1++;
}
i2c_stop();
sw();
if((b != 0x0))
goto start;
sensor();
if(senout == 0x00)
goto stop1;
senout++;
if(senout < 0x05)
delay_ms(200);
else if(senout == 0x05)
{
88

I YEAR
VLSI
delay_ms(0x2000);
output_d(0x10);
output_low(PIN_E1);
delay_ms(1000);
output_d(0x08);
output_low(PIN_E1);
delay_ms(100);
}
if((senout > 0x05) && (senout <=0x09))
delay_ms(200);
stop1:
if(senout1 == 0x00)
goto stop2;
senout1++;
if(senout1 < 0x05)
delay_ms(200);
else if(senout1 == 0x05)
{
delay_ms(0x2000);
output_d(0x04);
output_low(PIN_E2);
delay_ms(1000);
output_d(0x02);
output_low(PIN_E2);
delay_ms(100);
}
89

I YEAR
VLSI
if((senout1 > 0x05) && (senout1 <=0x09))

delay_ms(200);
stop2:
if(i != 0x08)
delay_ms(200);
}
}
}
}
void init()
{
for(i=0;i<0x08;i++)
{
i2c_start();
i2c_write(sel[i]);
i2c_write(0x15);
i2c_write(0x00);
i2c_write(0x00);
i2c_stop();
}
}
void sensor()
{
output_low(PIN_B4);
a=input_d();
b = a;
b = b & 0x04;
90

I YEAR
VLSI
if(b != 0x04)
{
output_d(0x0);
output_low(PIN_E1);
crossingon();
}
b = a;
b = b & 0x08;
if(b != 0x08)
crossingoff();
b = a;
b = b & 0x10;
if(b != 0x10)
station2forward();
b = a;
b = b & 0x01;
if(b != 0x01)
station1forward();
}
void crossingon()
{
output_d(0xF0);
output_low(PIN_E2);
output_d(0xFF);
output_low(PIN_B1);
output_low(PIN_E0);
91

I YEAR
VLSI
void crossingoff()
{
output_d(0x00);
output_low(PIN_E2);
output_d(0x00);
output_low(PIN_B1);
{
output_d(0x00);
output_low(PIN_E2);
output_d(0x20);
output_low(PIN_E1);
delay_ms(100);
output_low(PIN_B4);
a=input_d();
b=a;
b= b & 0x01;
if(b == 0x01)
senout=0x01;
92

I YEAR
VLSI
{
output_d(0x08);
output_low(PIN_E2);
delay_ms(100);
output_low(PIN_B4);
a=input_d();
b = a;
b = b & 0x10;
if(b == 0x10)
senout1=0x01;
}
void sw()
{
output_low(PIN_B4);
a=input_d();
b=a;
b= b & 0x40;
c=a;
c= c & 0x80;
if((b == 0x0) &&(c == 0x80))
reverse();
}
93

I YEAR
VLSI
void reverse()
{
init();
initbuf();
while(1)
{
start3:
for(j=0x00;j<0x09;j++)
{
i1=0x05;
for(i=0x00;i<0x09;i++)
{
start4:
if(i<=0x04)
{
i2c_start();
i2c_write(sel1[j]);
i2c_write(0x06);
i2c_write(ls1[i]);
i2c_start();
i2c_write(sel1[j]);
i2c_write(0x05);
i2c_write(ls1[i1]);
i1++;
}
if(j==0x08)
goto start3;
sw1();
if((b != 0x0))
goto start4;
94

I YEAR
VLSI
if(i>=0x05)
{
i2c_start();
i2c_write(sel1[j]);
i2c_write(0x05);
i2c_stop();
i2c_start();
i2c_write(sel1[j+1]);
i2c_write(0x06);
i1++;
}
sw1();
if((b != 0x0))
goto start4;
sensor1();
senout2++;
if(senout2 < 0x05)
delay_ms(200);
{
delay_ms(0x2000);
initbuf();
output_d(0x80);
output_low(PIN_E1);
delay_ms(1000);
initbuf();
output_d(0x40);
95

I YEAR
VLSI
output_low(PIN_E1);
delay_ms(100);
}
delay_ms(200);
senout3++;
if(senout3 < 0x05)
delay_ms(200);
{
delay_ms(0x2000);
initbuf();
output_d(0x02);
output_low(PIN_E1);
delay_ms(1000);
initbuf();
output_d(0x01);
output_low(PIN_E1);
delay_ms(100);
}
delay_ms(200);
if(i != 0x08)
delay_ms(200);
}
}
}
96

I YEAR
VLSI
void sensor1()
{
output_low(PIN_B4);
a=input_d();
b = a;
b = b & 0x20;
if(b != 0x20)
{
output_d(0x00);
output_low(PIN_E1);
station2reverse();
}
b = a;
b = b & 0x04;
if(b != 0x04)
crossingoff();
b = a;
b = b & 0x08;
if(b != 0x08)
crossingon();
b = a;
b = b & 0x02;
if(b != 0x02)
station1reverse();
}
97

I YEAR
VLSI
void station1reverse()
{
initbuf();
output_d(0x04);
output_low(PIN_E1);
delay_ms(100);
output_low(PIN_B4);
a=input_d();
b=a;
b= b & 0x02;
if(b == 0x02)
senout3=0x01;
}
void station2reverse()
{
initbuf();
output_d(0x01);
output_low(PIN_E2);
delay_ms(100);
output_low(PIN_B4);
a=input_d();
b = a;
b = b & 0x20;
if(b == 0x20)
98

I YEAR
VLSI
senout2=0x01;
}
void sw1()
{
output_low(PIN_B4);
a=input_d();
b=a;
b= b & 0x40;
c=a;
c= c & 0x80;
}
void initbuf()
{
output_d(0x00);
output_low(PIN_E1);
output_d(0x00);
output_low(PIN_E2);
output_d(0x00);
output_low(PIN_B1);
}
RESULT:
Thus the model train controller was rotated in both forward and reverse direction using
embedded microcontroller trainer kit.
99

I YEAR
VLSI
EX NO: 11
WORKING OF A PLL SYNTHESIZING OSCILLATOR

DATE :
AIM:
To study the working of a PLL synthesizing oscillator.
APPARATUS REQUIRED:
VCT-57
CRO
Patch Chords
CRO Probe
PROCEDURE:
Switch ON the trainer.
Remove the jumper pin between the points P1 & P2.
Measure the VCO output frequency.
Insert the jumper pin between the points P1 & P2.
Set the frequency divider ratio 1 by press the switch SW1.
Measure the PLL synthesized output frequency at test point P7.
Increase the frequency divider ratio(N) by pressing the switches (SW1, SW2, SW3).
Tabulate the readings.
Repeat steps (6-8) to obtain more values of VCO output frequency (f) & frequency divider
ratio (N).
From the readings tabulated make sure that the VCO output frequency is multiplied N times
with respect to its original 1KHZ reference signal.
100

I YEAR
VLSI
THEORY:
A phase locked loop, PLL, is basically of form of servo loop. Although a PLL performs
its actions on a radio frequency signal, all the basic criteria for loop stability and other
parameters are the same.
A basic phase locked loop, PLL, consists of three basic elements:
Phase comparator: As the name implies, this circuit block within the PLL compares the
phase of two signals and generates a voltage according to the phase difference between
the two signals.
Loop filter: This filter is used to filter the output from the phase comparator in the PLL.
It is used to remove any components of the signals of which the phase is being compared
from the VCO line. It also governs many of the characteristics of the loop and its
stability.
Voltage controlled oscillator (VCO):
The voltage controlled oscillator is the circuit
block that generates the output radio frequency signal. Its frequency can be controlled
and swung over the operational frequency band for the loop.
Phase locked loop operation

The concept of the operation of the PLL is relatively simple, although the mathematical
analysis can become more complicated
The Voltage Controlled Oscillator, VCO, within the PLL produces a signal which enters
the phase detector. Here the phase of the signals from the VCO and the incoming reference
signal are compared and a resulting difference or error voltage is produced. This corresponds to
the phase difference between the two signals.
101

I YEAR
VLSI
Block diagram of a basic phase locked loop (PLL)

The error signal from the phase detector in the PLL passes through a low pass filter
which governs many of the properties of the loop and removes any high frequency elements on
the signal. Once through the filter the error signal is applied to the control terminal of the VCO
as its tuning voltage. The sense of any change in this voltage is such that it tries to reduce the
phase difference and hence the frequency between the two signals. Initially the loop will be out
of lock, and the error voltage will pull the frequency of the VCO towards that of the reference,
until it cannot reduce the error any further and the loop is locked.
When the PLL is in lock a steady state error voltage is produced. By using an amplifier
between the phase detector and the VCO, the actual error between the signals can be reduced to
very small levels. However some voltage must always be present at the control terminal of the
VCO as this is what puts onto the correct frequency.
The fact that a steady error voltage is present means that the phase difference between the
reference signal and the VCO is not changing. As the phase between these two signals is not
changing means that the two signals are on exactly the same frequency.
TABULATION FOR INPUT:

Amplitude (volts)
Time period (ms)
1.2
102

I YEAR
VLSI
TABULATION FOR OUTPUT:
BCD COUNTER
BCD COUNTER
X100(SW3)
BCD COUNTER
X10(SW2)
FREQUENCY
X1(SW1)
DIVIDER
AMPLITUDE
(volts)
TIME
PERIOD
L12
L11
L10
L9
L8
L7
L6
L5
L4
L3
L2
L1
RATIO
(ms)
1.2
1.2
0.6
0.4
0.3
0.24
0.2
0.16
0.14
0.12
10
0.12
11
0.16
12
0.1
RESULT:
Thus the working of a PLL synthesizing oscillator was studied.
103

I YEAR
VLSI
VIVA QUESTIONS:
1. What is the expansions of PLL?

2. What are the blocks available in PLL?
3. What for VCO is used?
4. What is the purpose of loop filter?
5. What are the applications of PLL?
104

I YEAR
VLSI
1. Write a Hardware Description language to develop a package of arithmetic operations for

IEEE single precision floating point numbers represented as bit vectors. The package should
include addition , subtraction, multiplication, division, square root operations and conversion
function to convert between bit vector and real values. Implement the package using a
suitable Complex Programmable Logic Device
2. Write a structural Hardware Description language to implement an 8 bit ALU with minimum
number of configurable logic blocks using a suitable FPGA device.
3. Write a HDL program to implement an 8 bit ALU using structural as well as Behavioural
modelling. Implement the ALU in any suitable FPGA device
4. Write a Hardware Description Language program to implement an 16 bit ALU using
dataflow modelling. Implement the ALU in any suitable CPLD device
5. Write a behavioural model for a digital integrator that has a clock input of type bit and data
input and output each of type real. The integrator maintains the sum of successive data input
values. When the clock input changes from 0 to1 the integrator should add the current data
input to the sum and provide the new sum on the output. Implement the above scheme using
a CPLD
6. Write and implement a Data flow model of an averaging module that calculates the average
of batches of 16 real numbers. The module has clock and data input and a data output. The
module accepts the next input numbers when the clock changes to 1. After 16 numbers have
been accepted, the module places their average on the output port, then repeats the process
for the next batch using a suitable FPGA.
7. Write and implement a Data flow model of an averaging module that calculates the average
of batches of 16 real numbers. The module has clock and data input and a data output. The
module accepts the next input numbers when the clock changes to 1. After 16 numbers have
been accepted, the module places their average on the output port, then repeats the process
for the next batch using a suitable FPGA.
8. A binary to BCD converter is to be designed using CPLD. Assume the binary data is shifted
in serially, LSB first, into the converter; the conversion process begins when a complete
binary word has been shifted. The BCD data is shifted out of the converter with least
significant bit first. Use minimum no. of Function Blocks and implement the logics using any
suitable CPLD.
9. Write a Hardware Description Language program to developed 4-bit ALUs arranged side by
side, with control lines between them, to form an 8-bit Processor. The Processor should
perform all the arithmetic and Logical operations. Implement the bit sliced processor in real
time and demonstrate it using any suitable complex programmable logic devices.
10. Write a Hardware Description Language program to develope a 4-bit ALU with control lines
to form an 32-bit Processor. Implement the bit sliced processor in real time and demonstrate
it using any suitable FPGA.
105

I YEAR
VLSI
11. Design and implement a low cost and compact dedicated controller for Elevator using a
suitable microcontroller. The scheme for the elevator Controller device is to indicate the
direction of the motion, and the present floor level. The controller must take the lift motion
by means of accepting the floor level as input and generate control signals (for control the lift
motion) as output.
12. Design and implement a compact dedicated controller for Elevator using a microcontroller.
The scheme for the elevator Controller device is to indicate the direction of the motion, and
the present floor level. The controller must recognize the power crisis, under emergency and
power crisis the elevator must be stopped at the nearest floor and elevator door should be
opened with minimal delay time.
13. Design and implement a compact dedicated controller using Selective down algorithm for an
Elevator using a microcontroller. The scheme is used during Down Peak mode, elevator is
sent away from the ground floor towards the highest floor served, after which it commence
running down the floors in response to calls placed by passengers wishing to leave the
building. The commencement of Selective down algorithm may be triggered by a time clock.
14. Develop and implement automatic control logic for a model electric traction using a suitable
microcontroller.
15. Design and implement a compact and dedicated controller for a train using microcontroller.
Run the train with half the rated speed of the drive and also employ the regenerative braking.
16. Design and implement a compact and dedicated controller for the railway automatic gate
opening and closing using microcontroller.
17. Design an alarm clock using six 7-segment display to display the time in HH-MM-SS format
using a micro controller. use I2c communication and the following alarm set and format : 12
hour format with PM led indicator and Alarm set (hh/mm/ss)+/- with snooze 5 mins facility
18. Design an alarm clock to display the time in HH-MM-SS format using a micro controller. use
serial communication protocol and the following alarm set and format : Set hours/min/secs /
Pm /Am with +/- switches, Alarm set (hh/mm/ss)+/- with snooze 10 mins facility
19. Design an alarm clock using LCD display to display the time in HH-MM-SS format using a
micro controller. Use I2c communication and the following alarm set and format : 24 hour
format led indicator, 12hrs with AM/PM and Alarm set (hh/mm/ss)+/- with snooze 1 mins.
facility
20. Design and implement a PLL for the following : A DAC require a high-speed Master Clock
to clock their digital filters and modulators. This Master Clock is typically required to be
synchronous to the left-right (frame or word) clock in order to maintain sample alignment in
the digital filters, state machines, modulator.
21. Design and implement a digital phase locked loop to generate internal clock at a specified
frequency using a suitable microcontroller.
22. Design and implement a clock generator using phase locked loop to perform frequency
synthesis and frequency divider operation.
106

VLSI Lab Manual

Hochgeladen von

Dokumentinformationen

Copyright

Verfügbare Formate

Dieses Dokument teilen

Dokument teilen oder einbetten

Freigabeoptionen

Stufen Sie dieses Dokument als nützlich ein?

Sind diese Inhalte unangemessen?

Copyright:

Verfügbare Formate

VLSI Lab Manual

Hochgeladen von

Copyright:

Verfügbare Formate

SRINIVASAN ENGINEERING COLLEGE

DEPT OF ELECTRONICS AND COMMUNICATION ENGINEERING

VL 9225 - VLSI DESIGN LABORATORY II

VLSI DESIGN LAB-II MANUAL

VLSI DESIGN LAB-II MANUAL

1. Implementation of 8 Bit ALU in FPGA / CPLD.

VLSI DESIGN LAB-II MANUAL

LIFT1 MOVES FROM GROUND FLOOR TO FOURTH FLOOR

IMPLEMENTATION OF ELEVATOR CONTROLLER

LIFT1 MOVES FROM FOURTH FLOOR TO GROUND FLOOR

IMPLEMENTATION OF ELEVATOR CONTROLLER

LIFT2 MOVES FROM GROUND FLOOR TO FOURTH FLOOR

IMPLEMENTATION OF ELEVATOR CONTROLLER

LIFT2 MOVES FROM FOURTH FLOOR TO GROUND FLOOR

IMPLEMENTATION OF ALARM CLOCK

USING EMBEDDED MICROCONTROLLER TRAINER

IMPLEMENTATION OF MODEL TRAIN CONTROLLER

VLSI DESIGN LAB-II MANUAL

IMPLEMENTATION OF MODEL TRAIN CONTROLLER

USING EMBEDDED MICROCONTROLLER TRAINER

WORKING OF A PLL SYNTHESIZING OSCILLATOR

University Model Question Paper

VLSI DESIGN LAB-II MANUAL

VLSI DESIGN LAB-II MANUAL

LAB COURSE HANDOUT

: VLSI Design Lab II

Scope and Objective of the Subject:

Implementation Of 8-Bit ALU In

Students will be able to learn

Implementation Of 4-Bit Sliced Processor

Students will be able to learn

Lift moves from ground floor to fourth

Students will be able to learn

Implementation Of Alarm Clock

Students will be able to learn

Implementation Of Model Train

Students will be able to learn

Implementation of elevator controller

Controller Using Embedded

Working Of A PLL Synthesizing

Students will be able to learn

*-As in Lab Manual

VLSI DESIGN LAB-II MANUAL

Evaluation scheme Internal Assessment

1. Read all instructions carefully and proceed according to that.

VLSI DESIGN LAB-II MANUAL

IMPLEMENTATION OF 8-BIT ALU IN FPGA/CPLD

Spartan 3E trainer kit

Declare input and output in entity.

To represent the arithmetic, logical and shifting operations in architecture.

Then save the program and check the syntax.

Configuring the impact in generating programming to download the program.

Then check the result in FPGA kit

VLSI DESIGN LAB-II MANUAL

VLSI DESIGN LAB-II MANUAL

B. Design of 8-bit Logical block

VLSI DESIGN LAB-II MANUAL

VLSI DESIGN LAB-II MANUAL

VLSI DESIGN LAB-II MANUAL

VLSI DESIGN LAB-II MANUAL

IMPLEMENTATION OF 4-BIT SLICED PROCESSOR IN

Declare input and output in entity.

Output is feedback to input to obtain the solution.

Then save the program and check the syntax.