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I. I NTRODUCTION
F SYNTHESIS has generally shied away from ring oscillators due to their much more severe phase noise-power
trade-offs than those of LC topologies. Todays multiband,
multimode radios, however, require a number of synthesizers
and can greatly benefit from compact, flexible implementations
afforded by ring oscillators.
This paper proposes a phase-locked loop (PLL) architecture
that can achieve a wide loop bandwidth, thus suppressing the
voltage-controlled oscillator (VCO) phase noise and allowing
the use of a ring topology. An integer-N synthesizer based on
this architecture also incorporates harmonic traps on the VCO
control line to reduce the output sidebands [1]. Most of the concepts introduced here are applicable to other PLL and oscillator
topologies as well. Implemented in the TSMC 45 nm digital
CMOS technology, an experimental prototype exhibits a phase
noise of 114 dBc/Hz up to 10 MHz offset with a spur level
of 65 dBc.
Section II provides the motivation for this work and reviews
the bandwidth limitations of traditional PLLs. Section III
describes the evolution of the proposed synthesizer architecture. Section IV deals with phase noise considerations, and
Section V is concerned with spur reduction. Section VI presents
the experimental results.
Manuscript received August 24, 2015; revised December 14, 2015; accepted
December 17, 2015. This paper was approved by Associate Editor Waleed
Khalil. This work was supported in part by the Qualcomm Innovation
Fellowship Program, in part by the Broadcom Fellowship Program, and in part
by Realtek Semiconductor.
The authors are with the Department of Electrical Engineering, University of
California, Los Angeles, CA 90095-1594 USA (e-mail: razavi@ee.ucla.edu).
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/JSSC.2015.2511157
II. BACKGROUND
A. General Considerations
The need for LC oscillators in RF synthesis has been solidified by various studies revealing that the white-noise-induced
phase noise of ring oscillators trades primarily with the power
consumption [2], [3] and is relatively independent of the number of stages. However, ring oscillators do present compelling
advantages. 1) They occupy a smaller area and can be readily
placed within a transceiver layout with less serious concerns
regarding proximity effects. 2) They entail much less coupling
to and from other circuits. 3) They achieve a wider tuning range
and can be multiplexed to cover decades of frequencies. 4) They
readily generate multiple phases.
That the phase noise of ring oscillators is difficult to improve
at the circuit level forces us to higher levels of abstraction. For
example, [4] processes the signals in an RF receiver (RX) so as
to suppress the phase noise in reciprocal mixing. This approach,
however, does not correct for the effect of phase noise on the
received signal constellation and the error vector magnitude
(EVM) (e.g., in the absence of a blocker), nor is it applicable to
the transmitter (TX). It is interesting to note that 1) applications
entailing significant reciprocal mixing, e.g., GSM, actually
place tighter requirements on the TX phase noise, and 2) applications specifying the phase noise by the EVM, e.g., IEEE
802.11 a/b/g, impose equally stringent phase noise constraints
on RX and TX. In other words, the TX phase noise is at least
as critical as the RX phase noise in most systems. It is therefore
desirable to seek a solution that can be applied to both.
B. PLL Bandwidth Limitations
Another level of abstraction at which phase noise reduction can be considered is the synthesizer architecture. The loop
bandwidth is generally constrained by three factors: 1) the PLL
reference frequency, f REF ; for example, in a mobile phone environment, only a crystal oscillator around 20 MHz is available;
2) the PLL stability limit, often called Gardners Limit, and
generally accepted to be around fREF /10 for type-II topologies;
and 3) the ripple amplitude on the VCO control line and hence
the output spur level. In the presence of charge pump (CP) nonidealities, the loop bandwidth is reduced to typically fREF /20
or less if spurs lower than 60 dBc are required [5][9].
It is helpful to briefly review the different bandwidths
encountered in PLL analysis: 1) the inputoutput transfer function has a certain 3 dB bandwidth, which we call the PLL
bandwidth fBW in this paper; 2) the loop transmission has
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2
Fig. 1. (a) Traditional type-I PLL architecture. (b) Settling behavior with bandwidth of 5.6 MHz.
(1)
(2)
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KONG AND RAZAVI: A 2.4 GHz 4 mW INTEGER-N INDUCTORLESS RF SYNTHESIZER
Fig. 3. (a) Type-I PLL with traditional sampling filter. (b) Time-domain operation.
n
j2f TCK /2 sin f TCK
X f
Y (f ) = e
. (4)
f TCK n=
TCK
sin f TCK
X(f ).
f TCK
(5)
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4
1
KPD KVCO
N
j
1
sin f TREF
ejf TREF
C2
f TREF
1+
j
C1 fREF
(7)
where KPD is the phase detector (PD) gain (chosen approximately equal to 2.2 V/rad so as to provide the desired
bandwidth). We have approximated the MSSF sampling rate
by fREF . To determine the phase margin, we must examine
H(j) at the unity-gain bandwidth fUGB , i.e., the frequency
at which |H(j)| drops to unity. To this end, we make two
approximations. 1) As explained in Section III-B, C1 C2 and
hence the fraction 1/[1 + C2 j/(C1 fREF )] contributes negligibly to H and |H|. 2) Predicting that fUGB < fREF /2, we also
neglect the effect of the sinc on |H|. It follows that |H(j)|
KPD KVCO /(N ) and 2fUGB KPD KVCO /N . The phase
contains a 90 contribution by the VCO and f TREF by
the MSSF, H(j) /2 f TREF . The phase margin +
H(j2fUGB ) is thus equal to
PM =
KPD KVCO
fUGB TREF =
TREF .
2
2
2N
(8)
out
N H(j)
.
(j) =
in
1 + H(jw)
sin f TCK
1
ejf TCK
.
C2
f TCK
1+
j
C1 fCK
(6)
(9)
1 + ( 1)2 + 3 /6
(10)
2fBW 2 3fREF
(11)
+ 1 ( + 1)2 3 /6
(12)
2fn, VCO 2 3fREF
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KONG AND RAZAVI: A 2.4 GHz 4 mW INTEGER-N INDUCTORLESS RF SYNTHESIZER
not lead to lock. Since the free-running VCO range lies well in
the acquisition range, no frequency acquisition aid is necessary
in our prototype. Circuit simulations confirm these predictions.
IV. P HASE N OISE C ONSIDERATIONS
The phase noise of the proposed PLL arises from three building blocks, namely the VCO, the XOR gate, and the sampling
filter. We wish to design the VCO according to the overall phase
noise specification and reduce to negligible levels the XOR and
filter contributions.
A. VCO Phase Noise
(13)
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Fig. 9. (a) Proposed PLL in open-loop configuration. (b) Simulated control voltage waveform.
Fig. 11. VCO phase noise in free-running mode and in type-II and proposed
PLLs.
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KONG AND RAZAVI: A 2.4 GHz 4 mW INTEGER-N INDUCTORLESS RF SYNTHESIZER
Fig. 13. (a) Harmonic trap implementation. (b) Magnitude of gyrator input impedance.
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Fig. 18. Simulated PLL phase noise before and after harmonic traps are ON.
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KONG AND RAZAVI: A 2.4 GHz 4 mW INTEGER-N INDUCTORLESS RF SYNTHESIZER
TABLE I
P ERFORMANCE SUMMARY
mW
FoM1 =10log10 [( jitter
)2 (1power
)]FoM2 =10 log10 [(fOSC
)2( 1power
)] Phase Noise
1s
mW
f
(dBc/Hz)
Fig. 21. Measured output spectrum with harmonic traps turned OFF (top) and
turned ON (bottom).
VII. C ONCLUSION
This paper presents an inductorless type-I synthesizer architecture for 2.4 GHz RF applications. A spur reduction approach
based on harmonic traps is also introduced that measures the
ripple on the control voltage by means of a modulator and,
using a three-point algorithm, forces the ripple to minimum.
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10
ACKNOWLEDGMENT
The authors would like to thank the TSMC University Shuttle
Program for chip fabrication.
A PPENDIX I
In this appendix, we use the approximation [KPD KVCO /
(N j)] exp (jf TREF ) to determine the closed-loop bandwidth. From (9), we denote KPD KVCO by K and write
out
K/
in (j) =
K
1 + jN exp (jf TREF )
(14)
K/
=
.
N 2 2 2KN sin f T + K 2
Equating the square of this quantity to N 2 /2 yields the 3 dB
bandwidth
BW TREF
2 2
(15)
N BW 2KN BW sin
K 2 = 0.
2
3
)/24
Since sin 3 /6 for 1 rad, (KN TREF
4
2
+ (N 2 KN TREF )BW
K 2 = 0. We also denote
BW
by
,
KT /N = KPD KVCO /(N fREF ) = 2fUGB /fREF
obtaining (10).
We should mention that the VCO noise transfer function is
obtained as
jN
out
(j) =
. (16)
VCO
j[N K sin f TREF ] + K cos f TREF
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Long Kong (S15) received the B.E. degree in microelectronics from Shanghai Jiao Tong University,
Shanghai, China, in 2011, and the M.S. degree
in electrical engineering from the University of
California (UCLA), Los Angeles, CA, USA, in 2013.
He is pursuing the Ph.D. degree at UCLA, where he is
developing high-performance frequency synthesizer
architectures.
Mr. Kong is the recipient of the Qualcomm
Innovation Fellowship (20132014), the Analog
Devices Outstanding Student Designer Award (2015),
and the Broadcom Fellowship (20152016).