COMP ENG 2DP4

Memory devices
All main memory and cache devices are
one of two basic types:

Read-Only Memory (ROM)

eg. PROM, EPROM, EEPROM, Flash

or

Read/Write Memory (RAM)

eg. SRAM, DRAM, NVRAM, VRAM, EDORAM
COMP ENG 2DP4

Dr. D. Capson, Electrical & Computer Engineering

Organization vs Capacity
The organization of a memory device
specifies its logical operation (but not
necessarily its internal architecture).
For example: 2k x n or 64K x 8 for
k=16, n=8.
The capacity of a memory device is
the total number of bits of storage.
For example, for k=16, n=8, the
capacity is: 219 bits.
COMP ENG 2DP4

Dr. D. Capson
Electrical and Computer Engineering

Dr. D. Capson, Electrical & Computer Engineering

COMP ENG 2DP4

Logical representation
of memory devices

Notes:
(1) sometimes there is more than one chip select in which case they operate as an AND function
(2) sometimes CS is named CE (chip enable)
(3) lower case and upper case (cs, CS, ce, CE) are used interchangeably
(4) CS (or CE) also controls the tri-state buffers of the data output
(5) for the SRAM, WE = 0 means write, WE = 1 means read

COMP ENG 2DP4

Dr. D. Capson, Electrical & Computer Engineering

For larger memory systems, devices

must be combined to construct larger
capacities or different organizations.
Example 1

Construct a 4K x 8 RAM system using 1K x

8 devices.

Example 2

Construct a 1K x 16 RAM system using 1K

x 8 devices.
COMP ENG 2DP4

Dr. D. Capson
Electrical and Computer Engineering

Dr. D. Capson, Electrical & Computer Engineering

COMP ENG 2DP4

ROM internal structures

64x1 = 64 bit Memory

COMP ENG 2DP4

Dr. D. Capson, Electrical & Computer Engineering

ROM internal structures

8x8 = 64 bits

64x1 = 64 bits with

two-level decoding
COMP ENG 2DP4

Dr. D. Capson
Electrical and Computer Engineering

Dr. D. Capson, Electrical & Computer Engineering

COMP ENG 2DP4

ROM internal structures

16x4 = 64 bit Memory with two-level
decoding

COMP ENG 2DP4

Dr. D. Capson, Electrical & Computer Engineering

ROM internal structures

For larger memory capacities,
how can we build large decoders
and MUXs ? Eg. 9-to-512 ?
A decoder can be used as a
MUX by adding transmision
gates on the outputs
COMP ENG 2DP4

Dr. D. Capson
Electrical and Computer Engineering

Dr. D. Capson, Electrical & Computer Engineering

COMP ENG 2DP4

Design for a 6-to-64 decoder

COMP ENG 2DP4

Dr. D. Capson, Electrical & Computer Engineering

Design for a 64-to-1 MUX

COMP ENG 2DP4

Dr. D. Capson
Electrical and Computer Engineering

Dr. D. Capson, Electrical & Computer Engineering

10

COMP ENG 2DP4

ROM internal structures

32Kx1 = 32 Kbit
memory with
two-level
decoding

COMP ENG 2DP4

Dr. D. Capson, Electrical & Computer Engineering

11

32Kx8 = 256 Kbit memory with

two-level decoding

COMP ENG 2DP4

Dr. D. Capson
Electrical and Computer Engineering

Dr. D. Capson, Electrical & Computer Engineering

12

COMP ENG 2DP4

32Kx8 = 256 Kbit memory with twolevel decoding and output control logic

COMP ENG 2DP4

Dr. D. Capson, Electrical & Computer Engineering

13

Read-Write Memory (RAM)

By far, the market is dominated by
dynamic RAM. When we refer to the
PC memory, usually we mean DRAM.
But, the fastest memory is static
RAM (SRAM). The problem is that it
takes much more physical space, consumes
much more power than DRAM, and costs
much more than DRAM (per bit).
COMP ENG 2DP4

Dr. D. Capson
Electrical and Computer Engineering

Dr. D. Capson, Electrical & Computer Engineering

14

COMP ENG 2DP4

Static RAM (SRAM)

One bit of SRAM
memory is based
on back-to-back
inverters.

This is constructed
electronically with 6
CMOS transistors
and is known as the
6T cell
COMP ENG 2DP4

Dr. D. Capson, Electrical & Computer Engineering

15

Dynamic RAM (DRAM)

One-bit of DRAM
memory requires only a
single transistor and a
small capacitor
So, it is physically smaller than SRAM and
consumes less power. But, the drawback is that it
only stores a bit for a few milliseconds ! This
requires a refreshing strategy.
COMP ENG 2DP4

Dr. D. Capson
Electrical and Computer Engineering

Dr. D. Capson, Electrical & Computer Engineering

16

COMP ENG 2DP4

SRAM internal structures

A one-bit SRAM memory cell logic

Note: Latch is used, not a flip flop !
COMP ENG 2DP4

Dr. D. Capson, Electrical & Computer Engineering

17

SRAM internal structures

A 4x4
SRAM
memory

COMP ENG 2DP4

Dr. D. Capson
Electrical and Computer Engineering

Dr. D. Capson, Electrical & Computer Engineering

18

COMP ENG 2DP4

SRAM internal structures

Rows are selected

simultaneously
COMP ENG 2DP4

Dr. D. Capson, Electrical & Computer Engineering

19

SRAM internal structures

4x4
SRAM
memory
with
separate
lines for
input and
output

COMP ENG 2DP4

Dr. D. Capson
Electrical and Computer Engineering

Dr. D. Capson, Electrical & Computer Engineering

20

10

COMP ENG 2DP4

4 x 4
SRAM

bidirectional
IO bus
COMP ENG 2DP4

Dr. D. Capson, Electrical & Computer Engineering

21

Memory Timing

COMP ENG 2DP4

Dr. D. Capson
Electrical and Computer Engineering

Dr. D. Capson, Electrical & Computer Engineering

22

11

COMP ENG 2DP4

Memory Timing

COMP ENG 2DP4

Dr. D. Capson, Electrical & Computer Engineering

23

Memory Timing

COMP ENG 2DP4

Dr. D. Capson
Electrical and Computer Engineering

Dr. D. Capson, Electrical & Computer Engineering

24

12

COMP ENG 2DP4

Microprocessor Bus Interface

COMP ENG 2DP4

Dr. D. Capson, Electrical & Computer Engineering

25

Basic READ Machine Cycle

COMP ENG 2DP4

Dr. D. Capson
Electrical and Computer Engineering

Dr. D. Capson, Electrical & Computer Engineering

26

13

COMP ENG 2DP4

Basic WRITE Machine Cycle

COMP ENG 2DP4

Dr. D. Capson, Electrical & Computer Engineering

27

COMP ENG 2DP4

Dr. D. Capson, Electrical & Computer Engineering

28

Simple
Memory
Maps

Dr. D. Capson
Electrical and Computer Engineering

14

COMP ENG 2DP4

Generalized Memory Map

COMP ENG 2DP4

Dr. D. Capson, Electrical & Computer Engineering

29

A simple address decode example

COMP ENG 2DP4

Dr. D. Capson
Electrical and Computer Engineering

Dr. D. Capson, Electrical & Computer Engineering

30

15

COMP ENG 2DP4

Address decoding using decoder

COMP ENG 2DP4

Dr. D. Capson, Electrical & Computer Engineering

31

Now, add the memory devices

COMP ENG 2DP4

Dr. D. Capson
Electrical and Computer Engineering

Dr. D. Capson, Electrical & Computer Engineering

32

16

COMP ENG 2DP4

Where is A12 ???

COMP ENG 2DP4

Dr. D. Capson, Electrical & Computer Engineering

33

Decoder enables can eliminate

sections of the memory map

COMP ENG 2DP4

Dr. D. Capson
Electrical and Computer Engineering

Dr. D. Capson, Electrical & Computer Engineering

34

17

COMP ENG 2DP4

A15 and A14 both used as

decoder enables

COMP ENG 2DP4

Dr. D. Capson
Electrical and Computer Engineering

Dr. D. Capson, Electrical & Computer Engineering

35

18