CS221:

VHDLIntroduction
Dr.A.Sahu
Dept of Comp. Sc. & Engg.
DeptofComp.Sc.&Engg.
IndianInstituteofTechnologyGuwahati
1

Outline
RequirementofVHDL
Model:Entity&Architecture
VHDL
Basiclanguageconcepts,designmethodology

OnlineDemoinClass
Examples,GHDL,GTKWAVE
l

VHDL Tutorial
VHDLTutorial
Forwarded
ForwardedByFrankVahid:DigitalDesign
By Frank Vahid: Digital Design
http://esd.cs.ucr.edu/labs/tutorial/
Google
Googlesearch
search VHDL
VHDLTutorial:Learnby
Tutorial: Learn by
Example

Requirement of HDL
RequirementofHDL
Time
howthebehaviorofthesystemchangeswithtime
y
g
creatingwaveforms

PeriodicSignals:Clocks
Concurrency:Specify:ProcessesP1andP2executein
parallel

x=x+1
P1

y=a b
P2

Structure,CompositionandInterconnection:
Structure Composition and Interconnection:
BlockAconsistsoftwoblocks:X1andY1
BlockXisduplicated
p
A
WireWconnectsAandB
W
X1

Y1

B
X2

Requirement of HDL
RequirementofHDL
ElectricalCharacteristics
CurrentLevels,
Current Levels Tri
Tristating
stating
Sensitivity:Risingedge/fallingedge

Otherprogrammingconstructs
Other programming constructs
TextandFileI/O,usefulinsimulation/debugging

Bittruedatatypes
it true data types
NotsoimportantinSW,ImportantinHW
int<6:0>
var; Specify
the bitwidth
of variables
int 6:0 var;
Specifythebit
widthofvariables

ModulesandInterfaces: Ports
Input Port P
InputPortP
InputPortQ
InputPortR

out Port W
outPortW
Inout PortX

Fundamental VHDL Objects

FundamentalVHDLObjects
Entity
and Architecture Pair
EntityandArchitecturePair
Entity
VHDLModel
Consistsof
TwoParts

EntityRepresent
y p
ExternalInterface

ArchRepresent
Architecture Contents/Function
Architecture
ality

VHDL: Entity
VHDL:Entity
Entity
: Represent External Interface
Entity:RepresentExternalInterface
A
Y
B

Entityhas
Interface:No
y
functionality

PortName

ENTITY and_gate
IS
PORT (A:INBIT;
( A IN BIT
B:INBIT;
Y:OUTBIT
);
END and_gate;

Model
Name
Port Type
PortType
Port
P
Direction7

VHDL:Architecture,Specifying
f
functionality
l
ARCHITECTURE
C
C
d
data_flow
fl OF
O and_gate
d
ISS
BEGIN
y<=aAND b;
END data_flow;

Mayhavemultiplearchitecturesfor
givenentity
i
i
differentviews
differentlevelsofdetail
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Specifying Concurrency
SpecifyingConcurrency
ConcurrentSignalAssignments
Ci
Ai
Bi

Sii

Co
ARCHITECTURE data_flow
data flow OF full_adder
full adder IS
BEGIN
si<=aiXOR biXOR ci;
co <= (ai AND bi)OR
co<=(ai
bi) OR (biAND
(bi AND ci)OR
ci) OR (ai AND ci);
END data_flow;
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Order of Execution
OrderofExecution
ExecutionindependentofSpecification
ARCHITECTURE data_flow OF full_adder IS
BEGIN
si<=aiXOR biXOR ci;
co<=(ai AND bi)OR (biAND ci)OR (ai AND ci);
END data_flow;

ARCHITECTURE data_flow
data flow OF full_adder
full adder IS
BEGIN
co<=(ai AND bi)OR (biAND ci)OR (ai AND ci);
si<=aiXOR biXOR ci;
ENDdata_flow;
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Modelling CombinationalLogic
Combinational Logic
Oneconcurrentassignmentforeachoutput

i1
i2
i3
i4

o1
o2
o3
o4

ARCHITECTURE data_flow
OF comb_logic
g IS
BEGIN
o1<=i1and i2;
o2 <= (i2 or i3)xor
o2<=(i2or
i3) xor (i1and
(i1 and i4);
o3<=...;
o4<=...;
END data_flow;

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When Logic Complexity Increase

WhenLogicComplexityIncrease
TemporarySIGNALSneeded
Temporary SIGNALS needed
Avoidredundantevaluations

Y=g(f(x))

h
Ports:X,Y,Z

Z=h(f(x))

t=f(x)

g
h

Y=g(t)

Z=h(t)

Signal:t
Signal : t
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SIGNALS
Representintermediatewires/storage
Internal
visible outside entity
Internal not
notvisibleoutsideentity
ENTITY comb_logic IS
PORT (i1,i2,i3,i4:INBIT;
(i1 i2 i3 i4: IN BIT;
o1,o2:OUTBIT);
END comb_logic;
ARCHITECTURE data_flow
OF comb_logic IS
BEGIN
o1<=(i1and i2and i3)xor i2;
o2 <=(i1andi2andi3)or
o2<
(i1 and i2 and i3) or i4;
END data_flow;

ENTITY comb_logic IS
PORT (i1,i2,i3,i4:INBIT;
o1 o2: OUT BIT);
o1,o2:OUTBIT);
END comb_logic;
ARCHITECTURE data_flow1
d t fl 1
OF comb_logic IS
SIGNAL temp:BIT;
BEGIN
temp<=(i1and i2and i3);
o1 <=tempxor
o1<
temp xor i2;
o2<=tempori4;
END data_flow;

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SIGNALS
executed
when i1 i2
executedwheni1,i2,
ori3changes
executedwhentemp
executed when temp
ori2changes
SIGNALSare
SIGNALS are
associatedwith
/
time/waveforms
PORTisaspecialtype
ofSIGNAL

ARCHITECTURE data_flow1
OF comb_logic IS
SIGNAL temp:BIT;
temp: BIT;
BEGIN
temp<=(i1and i2and i3);
o1 <= temp xor i2;
o1<=tempxor
o2<=tempori4;
END data_flow;
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Modelling Delays:inertialdelay
Delays: inertial delay
Modelsactualhardware
Spikessuppressed
yy<<=INERTIALNOTaAFTER
INERTIAL NOT a AFTER 10ns;
10 ns;
y<=NOTaAFTER 10ns; inertialdelayisdefault
A

Y
0 10

12

22

30

35

Modelling Delays:transportdelay
Delays: transport delay
Modelswires/transmissionlines
usedinmoreabstractmodelling

Spikespropagated
y<=TRANSPORTNOTaAFTER 10ns;
A

Y
0 10

12

22

32

35

40

45
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Describing Behavior: Processes

DescribingBehavior:Processes
Signal
SignalassignmentstatementsOKforsimple
assignment statements OK for simple
behavior
Complexbehaviorrequiresmoreconstructs
Complex behavior requires more constructs
conditionals(IF,CASE)
loops(FOR,WHILE)
l
(FOR WHILE)

UseVHDLPROCESS

17

VHDLPROCESS
ARCHITECTURE xof aIS
BEGIN

PROCESSissequential
q
Processesareconcurrent
w.r.t eachother
Signalassignmentisasimple
specialcase
Architectureconsistsofaset
A hit t
it f
t
ofProcesses(andsignal
assignments)attoplevel
g
)
p
Processescommunicate
usingsignals

f <= g+ 1;
f<=g+1;
p1:PROCESS
BEGIN
GIN
IF (x)THEN ...
ELSE ...;...
END PROCESS;
ENDPROCESS;
p2:PROCESS
BEGIN
FOR i in 1TO 5LOOP
a(i)<=0;
ENDL LOOP;
ENDLLOOP;...
ENDPROCESS;
END x;
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PROCESS Execution Semantics

PROCESSExecutionSemantics
NeedtodefinewhenProcessisexecuted
Need to define when Process is executed
suspending/resumingexecution
morecomplexthansignalassignment
more complex than signal assignment

(evaluatewhenanysignalonRHSchanges)
Nonotionofcompletionofexecution
needstoemulatehardware

19

Process Sensitivity List

ProcessSensitivityList

ProcessissensitivetosignalsonSensitivityList
Allprocessesexecutedonceattime=0
ll
d
Suspendedatendofprocess
Reactivatedwheneventoccursonanysignalin
y
sensitivitylist
Sensitivity List = a b
SensitivityList=a,b
PROCESS ((a,b)
, )
BEGIN
c<=aAND b;
ENDPROCESS;
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ProcessandSignalAssignment
g
g
ARCHITECTURE xof yIS
BEGIN
PROCESS (a,b)
BEGIN
c<=aAND b;
ENDPROCESS;
END x;

ARCHITECTURE xof yyIS

BEGIN
c<=aAND b;
END x;

Identical
NeednotusePROCESSformodelling
N d t
PROCESS f
d lli
simplecombinationalbehaviour

21

Process Synchronization
ProcessSynchronization

Sensitivitylistisoptional
waitisgeneralsynchronizationmechanism
Implicitinfiniteloopinprocess
p
p p
Executioncontinuesuntilsuspendedbywait
statement PROCESS
BEGIN
waitona,b;
c<=aand b;
ENDPROCESS;

PROCESS(a,b)
BEGIN
c < a and b;
c<=aand
b
ENDPROCESS;

Identical

22

Synchronization with WAITs

SynchronizationwithWAITs
Synchronisation withwaitmoreflexible
with wait more flexible
Bothsensitivitylistandwaitnotallowedin
same process
sameprocess
processcanhaveanynumberofwaits

Forcombinationallogic,placeALLinput
signalsinsensitivitylist
Forsequentiallogic,usewaitsappropriately

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WAITExamples
PROCESS
BEGIN
wait for 10 ns;
waitfor10ns;
outp <=inp;
ENDPROCESS
Sample input every 10ns
Sampleinputevery10ns

PROCESS
BEGIN
waituntil
i
il clkevent
lk
and
d clk=1;
lk
d<=q;
ENDPROCESS
EdgeTriggeredDFlipFlop

PROCESS (clk,reset)
BEGIN
IF resetTHEN
q<=0;
ELSIFclkevent and clk=1
d<=q;
END IF;
ENDIF;
ENDPROCESS
FlipFlop withReset

PROCESS
BEGIN
outp <=inp;
ENDPROCESS
Error!(nowaits)(Comparesignal
assignmentatarchitecturelevel)

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Process
Variables
ProcessVariables
Variablesusedforlocal
computations
i
PROCESS
VARIABLEresult:BIT;
BEGIN
Notassociatedwith waituntilclkevent andclk=1;
result:=0;
events/transactions
fori in 0to 6loop
unlikesignals
result:=resultXOR inp (i);
endloop;
p;
Assignmentofvalueis
g
outp <=result;
immediate
ENDPROCESS;

withinprocesses

unlikesignals
unlike signals

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Structural Description
StructuralDescription
InstantiationandInterconnection
h
Hierarchy

a
b

ENTITYxIS
PORT (a b: IN BIT c: OUT BIT);
PORT(a,b:INBIT,c:OUTBIT);
ENDx;

ENTITYyIS
PORT (a : IN BIT b: OUT BIT);
PORT(a:INBIT,b:OUTBIT);
ENDy;

ARCHITECTURExa OFxIS
ARCHITECTURE
OF IS
BEGIN
c<=aANDb;
ENDxa;

ARCHITECTUREya OFyIS
ARCHITECTURE
OF IS
BEGIN
b<=NOTa;
ENDxa;

X1

Y1
Z

zcontains
instances
Ofxandy
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Instantiation
and Interconnection 1
InstantiationandInterconnection
ENTITY zIS
PORT(p,q:INBIT,r:OUTBIT);
END x;
ARCHITECTUREstructuralOF zIS
COMPONENT xc
PORT (a,b:INBIT;c:OUTBIT);
ENDCOMPONENT;
COMPONENTyc
PORT (a,b:INBIT;c:OUTBIT);
ENDCOMPONENT;
FORALL:xc USEWORK.x (xa);
FORALL:yc USEWORK.y (ya);
SIGNAL t:BIT;
BEGIN
x1 xc PORTMAP(p,q,t);
x1:xc
PORT MAP (p q t)
y1:yc PORTMAP(t,r);
END structural;

X1

Y1
Z

Componentdeclaration

Configurationspecification
(whicharchitecture?)
Temporarysignal

Instantiation
27

Instantiation
and Interconnection 2
InstantiationandInterconnection
a
b

X1

Instancename
Component name
Componentname

x1:
y1:

xc PORTMAP(p,q,t);
yc PORTMAP(t,r);
Samename
impliesconnection

Y1
Z

Portassociationlist:
orderofnames
determinesconnectivity:
ap
a
b q
c t
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PortMapping
COMPONENT xc
PORT (a,b:INBIT;c:OUTBIT);
END COMPONENT;
ENDCOMPONENT;
Mappingbyposition:preferredforshortportlists
x1:xc PORTMAP(p,q,t);
Mappingbyname:preferredforlongportlists
x1:xc PORTMAP (b=>q,a=>p,c=>t);

Inbothcases,completeportmappingshouldbespecified
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Test Benches
TestBenches
Purpose
Purpose testcorrectnessofDesignUnder
test correctness of Design Under
Test(DUT)
provideinputstimulus
provide input stimulus
observeoutputs
compareagainstexpectedoutputs
compare against expected outputs

TestBenchisalsoaVHDLmodel

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TestBenchModelling
DesignUnder
Test
(DUT)

TestBench
Signals

TestbenchaseparateVHDLentity
Test bench a separate VHDL entity
PortsareconnectedtoDUTsports
i/pportcorrespondingtoDUT
i/p port corresponding to DUTsso/pport
o/p port
o/pportcorrespondingtoDUTsi/pport

Test
TestbenchinstantiatestheDUT
bench instantiates the DUT
Stimulusgenerationandoutputmonitoringina
separate VHDL process
separateVHDLprocess
SignalsareconnectedtoDUTsports

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