Beruflich Dokumente
Kultur Dokumente
FSK/ASK Transceiver IC
ADF7020
Data Sheet
FEATURES
APPLICATIONS
Low cost wireless data transfer
Remote control/security systems
Wireless metering
Keyless entry
Home automation
Process and building control
Wireless voice
RLNA
CREG[1:4]
LDO(1:4)
ADCIN
MUXOUT
TEMP
SENSOR
OFFSET
CORRECTION
ADF7020
TEST MUX
LNA
RFIN
MUX
RSSI
IF FILTER
RFINB
FSK/ASK
DEMODULATOR
7-BIT ADC
DATA
SYNCHRONIZER
GAIN
OFFSET
CORRECTION
CE
AGC
CONTROL
FSK MOD
CONTROL
RFOUT
DIVIDERS/
MUXING
-
MODULATOR
GAUSSIAN
FILTER
DIV P
DATA CLK
Tx/Rx
CONTROL
AFC
CONTROL
DATA I/O
INT/LOCK
N/N + 1
SLE
SERIAL
PORT
VCO
SREAD
SCLK
PFD
DIV R
VCOIN CPOUT
OSC
OSC1
OSC2
CLK
DIV
CLKOUT
05351-001
CP
SDATA
Figure 1.
Rev. D
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
ADF7020
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Specifications..................................................................................... 5
Readback Format........................................................................ 31
Timing Diagrams.......................................................................... 8
Registers ........................................................................................... 32
Register 0N Register............................................................... 32
Rev. D | Page 2 of 48
Data Sheet
ADF7020
REVISION HISTORY
8/12Rev. C to Rev. D
Added EPAD Notation ...................................................................11
Changed CP-48-3 Package to CP-48-5 Package ..........................47
Updated Outline Dimensions ........................................................47
Changes to Ordering Guide ...........................................................47
5/11Rev. B to Rev. C
Added Exposed Pad Notation to Outline Dimensions ..............47
Changes to Ordering Guide ...........................................................47
8/07Rev. A to Rev. B
Changes to Features .......................................................................... 1
Changes to General Description ..................................................... 4
Changes to Table 1 ............................................................................ 5
Changes to Table 2 ............................................................................ 8
Changes to Reference Input Section .............................................15
Changes to N Counter Section ......................................................16
Changes to Choosing Channels for Best Performance Section 17
Changes to Table 5 ..........................................................................20
Changes to FSK Correlator Register Settings Section ................22
Added Image Rejection Calibration Section ...............................26
Added Figure 41 ..............................................................................30
Changes to Readback Format Section ..........................................31
Changes to Register 9AGC Register Comments Section .......43
Added Register 12Test Register Comments Section ..............45
4/06Rev. 0 to Rev. A
Changes to Features .......................................................................... 1
Changes to Table 1 ............................................................................ 5
Rev. D | Page 3 of 48
ADF7020
Data Sheet
GENERAL DESCRIPTION
The ADF7020 is a low power, highly integrated FSK/ASK/OOK
transceiver designed for operation in the license-free ISM bands
at 433 MHz, 868 MHz, and 915 MHz, as well as the proposed
Japanese RFID band at 950 MHz. A Gaussian data filter option
is available to allow either GFSK or G-ASK modulation, which
provides a more spectrally efficient modulation. In addition to
these modulation options, the ADF7020 can also be used to
perform both MSK and GMSK modulation, where MSK is a
special case of FSK with a modulation index of 0.5. The modulation index is calculated as twice the deviation divided by the
data rate. MSK is spectrally equivalent to O-QPSK modulation
with half-sinusoidal Tx baseband shaping, so the ADF7020 can
also support this modulation option by setting up the device in
MSK mode.
This device is suitable for circuit applications that meet the
European ETSI-300-220, the North American FCC (Part 15),
or the Chinese Short Range Device regulatory standards. A
complete transceiver can be built using a small number of
external discrete components, making the ADF7020 very
suitable for price-sensitive and area-sensitive applications.
The transmitter block on the ADF7020 contains a VCO and
low noise fractional-N PLL with an output resolution of
<1 ppm. This frequency agile PLL allows the ADF7020 to be
used in frequency-hopping spread spectrum (FHSS) systems.
The VCO operates at twice the fundamental frequency to
reduce spurious emissions and frequency-pulling problems.
Rev. D | Page 4 of 48
Data Sheet
ADF7020
SPECIFICATIONS
VDD = 2.3 V to 3.6 V, GND = 0 V, TA = TMIN to TMAX, unless otherwise noted. Typical specifications are at VDD = 3 V, TA = 25C.
All measurements are performed using the EVAL-ADF7020DBZx using the PN9 data sequence, unless otherwise noted.
Table 1.
Parameter
RF CHARACTERISTICS
Frequency Ranges (Direct Output)
Min
Typ
Max
Unit
Test Conditions
862
902
928
431
440
RF/256
870
928
956
440
478
24
MHz
MHz
MHz
MHz
MHz
MHz
0.15
0.15
0.3
200
64 1
100
kbps
kbps
kbaud
1
4.88
100
110
620
kHz
kHz
Hz
30
dB
dBm
dBm
dB
1
1
dB
dB
0.3125
55
65
dB
dBc
dBc
50 kHz loop BW
27
21
35
30
39 + j61
48 + j54
54 + j94
dBc
dBc
dBc
kHz rms
0.5
50
20
+13
RECEIVER PARAMETERS
FSK/GFSK Input Sensitivity
Sensitivity at 1 kbps
Sensitivity at 9.6 kbps
Sensitivity at 200 kbps
OOK Input Sensitivity
Sensitivity at 1 kbps
Sensitivity at 9.6 kbps
119.2
112.8
100
dBm
dBm
dBm
116
106.5
dBm
dBm
Rev. D | Page 5 of 48
Unfiltered conductive
DR = 9.6 kbps
FRF = 915 MHz
FRF = 868 MHz
FRF = 433 MHz
At BER = 1E 3, FRF = 915 MHz,
LNA and PA matched separately 6
FDEV = 5 kHz, high sensitivity mode 7
FDEV = 10 kHz, high sensitivity mode
FDEV = 50 kHz, high sensitivity mode
At BER = 1E 3, FRF = 915 MHz
High sensitivity mode
High sensitivity mode
ADF7020
Parameter
LNA and Mixer, Input IP37
Enhanced Linearity Mode
Low Current Mode
High Sensitivity Mode
Rx Spurious Emissions 8
AFC
Pull-In Range at 868 MHz/915 MHz
Pull-In Range at 433 MHz
Response Time
Accuracy
CHANNEL FILTERING
Data Sheet
Min
Typ
Max
Unit
Test Conditions
57
47
dBm
dBm
dBm
dBm
dBm
kHz
kHz
Bits
kHz
3
5
24
50
25
48
1
27
dB
50
dB
55
dB
30
dB
50
2
70
dB
dB
dB
60
68
65
72
12
24 j60
26 j63
71 j128
dB
dB
dB
dB
dBm
110 to
24
2
3
150
dBm
dB
dB
s
65
MHz/V
130
65
89
MHz/V
MHz/V
dBc/Hz
110
128
40
dBc/Hz
Hz
s
RSSI
Range at Input
Linearity
Absolute Accuracy
Response Time
PHASE-LOCKED LOOP
VCO Gain
Rev. D | Page 6 of 48
Data Sheet
Parameter
REFERENCE INPUT
Crystal Reference
External Oscillator
Load Capacitance
Crystal Start-Up Time
ADF7020
Min
Max
Unit
Test Conditions
24
24
MHz
MHz
pF
ms
ms
CMOS levels
1
1
LSB
LSB
10
3.0
150 s +
(5 TBIT)
s
ms
CREG = 100 nF
See Table 11 for more details
Time to synchronized data out, includes AGC settling;
see the AGC Information and Timing section
3.625
3.625
33
2.1
1.0
Input Level
ADC PARAMETERS
INL
DNL
TIMING INFORMATION
Chip Enabled to Regulator Ready
Chip Enabled to RSSI Ready
Tx to Rx Turnaround Time
LOGIC INPUTS
Input High Voltage, VINH
Typ
0.7
VDD
0.2
VDD
1
10
50
DVDD
0.4
V
A
pF
MHz
V
IOH = 500 A
V
ns
pF
C
IOL = 500 A
40
0.4
5
10
+85
2.3
3.6
14.8
15.9
19.1
28.5
26.8
mA
mA
mA
mA
mA
19
21
mA
mA
0.1
Rev. D | Page 7 of 48
ADF7020
Data Sheet
TIMING CHARACTERISTICS
VDD = 3 V 10%, VGND = 0 V, TA = 25C, unless otherwise noted. Guaranteed by design, not production tested.
Table 2.
Parameter
t1
t2
t3
t4
t5
t6
t8
t9
t10
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
Test Conditions/Comments
SDATA to SCLK setup time
SDATA to SCLK hold time
SCLK high duration
SCLK low duration
SCLK to SLE setup time
SLE pulse width
SCLK to SREAD data valid, readback
SREAD hold time after SCLK, readback
SCLK to SLE disable time, readback
TIMING DIAGRAMS
t3
t4
SCLK
t1
SDATA
DB31 (MSB)
t2
DB30
DB1
(CONTROL BIT C2)
DB2
DB0 (LSB)
(CONTROL BIT C1)
t6
05351-002
SLE
t5
t1
t2
SCLK
SDATA
R7_DB0
(CONTROL BIT C1)
SLE
t3
t10
t8
RV16
RV15
RV2
RV1
05351-003
SREAD
t9
Rev. D | Page 8 of 48
Data Sheet
ADF7020
1 DATA RATE/32
1/DATA RATE
RxCLK
RxDATA
05351-004
DATA
1/DATA RATE
TxCLK
TxDATA
DATA
SAMPLE
05351-005
FETCH
NOTES
1. TxCLK ONLY AVAILABLE IN GFSK MODE.
Rev. D | Page 9 of 48
ADF7020
Data Sheet
Rating
0.3 V to +5 V
0.3 V to AVDD + 0.3 V
0.3 V to DVDD + 0.3 V
40C to +85C
65C to +125C
150C
26C/W
260C
40 sec
ESD CAUTION
Rev. D | Page 10 of 48
Data Sheet
ADF7020
48
47
46
45
44
43
42
41
40
39
38
37
CVCO
GND1
GND
VCO GND
GND
VDD
CPOUT
CREG3
VDD3
OSC1
OSC2
MUXOUT
1
2
3
4
5
6
7
8
9
10
11
12
ADF7020
TOP VIEW
(Not to Scale)
36
35
34
33
32
31
30
29
28
27
26
25
CLKOUT
DATA CLK
DATA I/O
INT/LOCK
VDD2
CREG2
ADCIN
GND2
SCLK
SREAD
SDATA
SLE
NOTES
1. EXPOSED PAD MUST BE CONNECTED TO GROUND.
05351-006
MIX_I
MIX_I
MIX_Q
MIX_Q
FILT_I
FILT_I
GND4
FILT_Q
FILT_Q
GND4
TEST_A
CE
13
14
15
16
17
18
19
20
21
22
23
24
VCOIN
CREG1
VDD1
RFOUT
RFGND
RFIN
RFINB
RLNA
VDD4
RSET
CREG4
GND4
Mnemonic
VCOIN
CREG1
VDD1
RFOUT
5
6
RFGND
RFIN
7
8
9
10
RFINB
RLNA
VDD4
RSET
11
CREG4
12
13 to 18
24
GND4
MIX_I, MIX_I,
MIX_Q, MIX_Q,
FILT_I, FILT_I
GND4
FILT_Q, FILT_Q,
TEST_A
CE
25
SLE
26
SDATA
19, 22
20, 21, 23
Description
The tuning voltage on this pin determines the output frequency of the voltage-controlled oscillator (VCO).
The higher the tuning voltage, the higher the output frequency.
Regulator Voltage for PA Block. A 100 nF in parallel with a 5.1 pF capacitor should be placed between this
pin and ground for regulator stability and noise rejection.
Voltage Supply for PA Block. Decoupling capacitors of 0.1 F and 10 pF should be placed as close as
possible to this pin. All VDD pins should be tied together.
The modulated signal is available at this pin. Output power levels are from 20 dBm to +13 dBm. The
output should be impedance matched to the desired load using suitable components. See the Transmitter
section.
Ground for Output Stage of Transmitter. All GND pins should be tied together.
LNA Input for Receiver Section. Input matching is required between the antenna and the differential LNA
input to ensure maximum power transfer. See the LNA/PA Matching section.
Complementary LNA Input. See the LNA/PA Matching section.
External bias resistor for LNA. Optimum resistor is 1.1 k with 5% tolerance.
Voltage Supply for LNA/MIXER Block. This pin should be decoupled to ground with a 10 nF capacitor.
External Resistor to Set Charge Pump Current and Some Internal Bias Currents. Use 3.6 k with 5%
tolerance.
Regulator Voltage for LNA/MIXER Block. A 100 nF capacitor should be placed between this pin and GND
for regulator stability and noise rejection.
Ground for LNA/MIXER Block.
Signal Chain Test Pins. These pins are high impedance under normal conditions and should be left
unconnected.
Ground for LNA/MIXER Block.
Signal Chain Test Pins. These pins are high impedance under normal conditions and should be left
unconnected.
Chip Enable. Bringing CE low puts the ADF7020 into complete power-down. Register values are lost when
CE is low, and the part must be reprogrammed once CE is brought high.
Load Enable, CMOS Input. When LE goes high, the data stored in the shift registers is loaded into one of
the fourteen latches. A latch is selected using the control bits.
Serial Data Input. The serial data is loaded MSB first with the two LSBs as the control bits. This pin is a high
impedance CMOS input.
Rev. D | Page 11 of 48
ADF7020
Pin No.
27
Mnemonic
SREAD
28
SCLK
29
30
GND2
ADCIN
31
CREG2
32
VDD2
33
INT/LOCK
34
35
DATA I/O
DATA CLK
36
CLKOUT
37
MUXOUT
38
OSC2
39
40
OSC1
VDD3
41
CREG3
42
CPOUT
43
44 to 47
VDD
GND, GND1,
VCO GND
CVCO
EP
48
Data Sheet
Description
Serial Data Output. This pin is used to feed readback data from the ADF7020 to the microcontroller. The
SCLK input is used to clock each readback bit (AFC, ADC readback) from the SREAD pin.
Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is latched into
the 24-bit shift register on the CLK rising edge. This pin is a digital CMOS input.
Ground for Digital Section.
Analog-to-Digital Converter Input. The internal 7-bit ADC can be accessed through this pin. Full scale is 0 V
to 1.9 V. Readback is made using the SREAD pin.
Regulator Voltage for Digital Block. A 100 nF in parallel with a 5.1 pF capacitor should be placed between
this pin and ground for regulator stability and noise rejection.
Voltage Supply for Digital Block. A decoupling capacitor of 10 nF should be placed as close as possible to
this pin.
Bidirectional Pin. In output mode (interrupt mode), the ADF7020 asserts the INT/ LOCK pin when it has
found a match for the preamble sequence. In input mode (lock mode), the microcontroller can be used to
lock the demodulator threshold when a valid preamble has been detected. Once the threshold is locked,
NRZ data can be reliably received. In this mode, a demodulation lock can be asserted with minimum delay.
Transmit Data Input/Received Data Output. This is a digital pin, and normal CMOS levels apply.
In receive mode, the pin outputs the synchronized data clock. The positive clock edge is matched to the
center of the received data. In GFSK transmit mode, the pin outputs an accurate clock to latch the data
from the microcontroller into the transmit section at the exact required data rate. See the Gaussian
Frequency Shift Keying (GFSK) section.
A Divided-Down Version of the Crystal Reference with Output Driver. The digital clock output can be
used to drive several other CMOS inputs, such as a microcontroller clock. The output has a 50:50 markspace ratio.
This pin provides the Lock_Detect signal, which is used to determine if the PLL is locked to the correct
frequency. Other signals include Regulator_Ready, which is an indicator of the status of the serial interface
regulator.
The reference crystal should be connected between this pin and OSC1. A TCXO reference can be used by
driving this pin with CMOS levels and disabling the crystal oscillator.
The reference crystal should be connected between this pin and OSC2.
Voltage Supply for the Charge Pump and PLL Dividers. This pin should be decoupled to ground with a
0.01 F capacitor.
Regulator Voltage for Charge Pump and PLL Dividers. A 100 nF in parallel with a 5.1 pF capacitor should be
placed between this pin and ground for regulator stability and noise rejection.
Charge Pump Output. This output generates current pulses that are integrated in the loop filter. The
integrated current changes the control voltage on the input to the VCO.
Voltage Supply for VCO Tank Circuit. This pin should be decoupled to ground with a 0.01 F capacitor.
Grounds for VCO Block.
A 22 nF capacitor should be placed between this pin and CREG1 to reduce VCO noise.
Exposed Pad. The exposed pad must be connected to ground.
Rev. D | Page 12 of 48
Data Sheet
ADF7020
ATTEN 0.00dB
MKR1
10.0000kHz
87.80dBc/Hz
MKR4 3.482GHz
SWEEP 16.52ms (601pts)
ATTEN 20dB
REF 10dBm
PEAK
log
10dB/DIV
FREQUENCY OFFSET
10MHz
START 100MHz
RES BW 3MHz
REF 15dBm
FSK
40
LgAv
W1 S2
S3 FC
AA
(f):
FTun
Swp
50
60
70
913.28
913.30
913.32
913.36
FREQUENCY (MHz)
913.38
05351-008
GFSK
START 800MHz
#RES BW 30kHz
VBW 30kHz
STOP 5.000GHz
SWEEP 5.627s (601pts)
05351-011
MARKER
1.834000000GHz
62.57dB
30
0
5
Mkr1 1.834GHz
62.57dB
ATTEN 30dB
NORM 1R
log
10dB/DIV
PRBS PN9
DR = 7.1kbps
FDEV = 4.88kHz
RBW = 300kHz
20
STOP 10.000GHz
SWEEP 16.52ms (601pts)
Figure 7. Phase Noise Response at 868.3 MHz, VDD = 3.0 V, ICP = 1.5 mA
10
VBW 3MHz
05351-010
1kHz
05351-007
REF LEVEL
10.00dBm
10
200kHz FILTER BW
10
20
25
30
35
40
50
55
150kHz FILTER BW
100kHz FILTER BW
10
ASK
20
OOK
30
40
60
65
70
400 300 200 100
0
100 200 300 400 500 600
350 250 150 50
50
150 250 350 450 550
IF FREQ (kHz)
50
899.60
GOOK
899.80
900.00
900.20
900.40
FREQUENCY (MHz)
900.60
900.80
05351-012
45
05351-009
15
Figure 12. Output Spectrum in ASK, OOK, and GOOK Modes, DR = 10 kbps
Rev. D | Page 13 of 48
ADF7020
Data Sheet
20
15
1
11A
10
5A
2.4V, +85C
0
7A
BER
4
3.6V, 40C
5
10
15
80
70
1
200.8k
DATA RATE
60
50
3
1.002k
DATA RATE
BER
40
30
9.760k
DATA RATE
05351-017
1100
05351-014
1050
950
1000
900
850
800
750
700
650
600
550
500
450
10
400
350
300
250
10
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
20
200
05351-016
106
107
108
109
110
111
112
113
114
115
116
117
118
119
13 17 21 25 29 33 37 41 45 49 53 57 61
PA SETTING
120
121
122
05351-013
25
123
20
124
PA OUTPUT POWER
3.0V, +25C
9A
60
20
65
0
70
SENSITIVITY (dBm)
40
RSSI READBACK LEVEL
60
80
85
CORRELATOR
AFC ON
90
95
80
CORRELATOR
AFC OFF
LINEAR AFC ON
100
100
80
60
40
RF INPUT (dB)
20
20
Rev. D | Page 14 of 48
05351-018
110
100
110
100
90
80
70
60
50
40
30
20
10
0
10
20
30
40
50
60
70
80
90
100
110
120
120
105
05351-015
75
20
Data Sheet
ADF7020
FREQUENCY SYNTHESIZER
R Counter
REFERENCE INPUT
The on-board crystal oscillator circuitry (see Figure 19) can use
an inexpensive quartz crystal as the PLL reference. The oscillator circuit is enabled by setting R1_DB12 high. It is enabled by
default on power-up and is disabled by bringing CE low. Errors
in the crystal can be corrected using the automatic frequency
control (see the AFC section) feature or by adjusting the
fractional-N value (see the N Counter section). A single-ended
reference (TCXO, CXO) can also be used. The CMOS levels
should be applied to OSC2 with R1_DB12 set low.
CP1
Regulator Ready
CL =
1
1
+
CP1 CP2
DVDD
+ CPCB
DVDD
R COUNTER OUTPUT
MUXOUT
CONTROL
CLKOUT
05351-020
DGND
CLKOUT
ENABLE BIT
DIVIDER
1 TO 15
REGULATOR READY
DIGITAL LOCK DETECT
N COUNTER OUTPUT
The CLKOUT circuit takes the reference clock signal from the
oscillator section, shown in Figure 19, and supplies a divideddown 50:50 mark-space signal to the CLKOUT pin. An even
divide from 2 to 30 is available. This divide number is set in
R1_DB[8:11]. On power-up, the CLKOUT defaults to
divide-by-8.
OSC1
05351-021
CP2
05351-019
OSC2
OSC1
Rev. D | Page 15 of 48
ADF7020
Data Sheet
Voltage Regulators
N Counter
Fractional _ N
215
REFERENCE IN
4R
PFD/
CHARGE
PUMP
VCO
Loop Filter
4N
The loop filter integrates the current pulses from the charge
pump to form a voltage that tunes the output of the VCO to the
desired frequency. It also attenuates spurious levels generated by
the PLL. A typical loop filter design is shown in Figure 22.
FRACTIONAL-N
INTEGER-N
05351-023
THIRD-ORDER
- MODULATOR
05351-022
CHARGE
PUMP OUT
Rev. D | Page 16 of 48
Data Sheet
ADF7020
LOOP FILTER
TO N
DIVIDER
VCO
MUX
TO PA
2
220F
05351-024
CVCO PIN
Rev. D | Page 17 of 48
ADF7020
Data Sheet
TRANSMITTER
RF OUTPUT STAGE
The PA of the ADF7020 is based on a single-ended, controlled
current, open-drain amplifier that has been designed to deliver
up to 13 dBm into a 50 load at a maximum frequency of
956 MHz.
PA Bias Currents
MODULATION SCHEMES
R2_DB[30:31]
2
IDAC
R2_DB[9:14]
RFOUT
R2_DB4
+
R2_DB5
RFGND
FROM VCO
4R
05351-025
DIGITAL
LOCK DETECT
PFD/
CHARGE
PUMP
PA STAGE
VCO
FSK DEVIATION
FREQUENCY
N
+fDEV
ASK/OOK MODE
R2_DB29
THIRD-ORDER
- MODULATOR
TxDATA
FRACTIONAL-N
R2_DB[30:31]
6
IDAC
6
6
R2_DB[9:14]
R2_DB[15:23]
RFOUT
R2_DB4
R2_DB5
DIGITAL
LOCK DETECT
RFGND
FROM VCO
05351-026
INTEGER-N
Rev. D | Page 18 of 48
05351-027
FSK/GFSK
The output power is set using Bits R2_DB[9:14].
ASK
The output power for the inactive state of the TxData input
is set by Bits R2_DB[15:20]. The output power for the
active state of the TxData input is set by Bits R2_DB[9:14].
OOK
The output power for the active state of the TxData input
is set by Bits R2_DB[9:14]. The PA is muted when the TxData
input is inactive.
Data Sheet
ADF7020
Gaussian frequency shift keying reduces the bandwidth occupied by the transmitted spectrum by digitally prefiltering the
TxData. A TxCLK output line is provided from the ADF7020
for synchronization of TxData from the microcontroller.
The TxCLK line can be connected to the clock input of a shift
register that clocks data to the transmitter at the exact data rate.
PFD 2m
212
PFD
DR [bps] =
DIVIDER _ FACTOR INDEX _ COUNTER
The INDEX_COUNTER variable controls the number of intermediate frequency steps between the low and high frequency.
It is usually possible to achieve a given data rate with various
combinations of DIVIDER_FACTOR and INDEX_COUNTER.
Choosing a higher INDEX_COUNTER can help in improving
the spectral performance.
Rev. D | Page 19 of 48
ADF7020
Data Sheet
RECEIVER
RF FRONT END
The ADF7020 is based on a fully integrated, low IF receiver
architecture. The low IF architecture facilitates a very low
external component count and does not suffer from power lineinduced interference problems.
Figure 28 shows the structure of the receiver front end. The
many programming options allow users to trade off sensitivity,
linearity, and current consumption against each other in the
way best suitable for their applications. To achieve a high level
of resilience against spurious reception, the LNA features a
differential input. Switch SW2 shorts the LNA input when
transmit mode is selected (R0_DB27 = 0). This feature facilitates the design of a combined LNA/PA matching network,
avoiding the need for an external Rx/Tx switch. See the
LNA/PA Matching section for details on the design of the
matching network.
I (TO FILTER)
RFIN
Tx/Rx SELECT
(R0_DB27)
SW2
LNA
LO
RFINB
Q (TO FILTER)
LNA MODE
(R6_DB15)
MIXER LINEARITY
(R6_DB18)
LNA CURRENT
(R6_DB[16:17])
05351-028
LNA GAIN
(R9_DB[20:21])
LNA/MIXER ENABLE
(R8_DB6)
The LNA has two basic operating modes: high gain/low noise
mode and low gain/low power mode. To switch between these
two modes, use the LNA_Mode bit, R6_DB15. The mixer is also
configurable between a low current and an enhanced linearity
mode using the mixer_linearity bit, R6_DB18.
Based on the specific sensitivity and linearity requirements
of the application, it is recommended to adjust control bits
LNA_Mode (R6_DB15) and Mixer_Linearity (R6_DB18), as
outlined in Table 5.
The gain of the LNA is configured by the LNA_Gain field,
R9_DB[20:21], and can be set by either the user or the
automatic gain control (AGC) logic.
IF Filter Settings/Calibration
Out-of-band interference is rejected by means of a fourth-order
Butterworth polyphase IF filter centered around a frequency of
200 kHz. The bandwidth of the IF filter can be programmed
between 100 kHz and 200 kHz by using Control Bits R1_DB[22:23]
and should be chosen as a compromise between interference rejection, attenuation of the desired signal, and the AFC pull-in range.
To compensate for manufacturing tolerances, the IF filter
should be calibrated once after power-up. The IF filter calibration logic requires that the IF filter divider in Bits R6_DB[20:28]
be set as dependent on the crystal frequency. Once initiated
by setting Bit R6_DB19, the calibration is performed
automatically without any user intervention. The calibration
time is 200 s, during which the ADF7020 should not be
accessed. It is important not to initiate the calibration cycle
before the crystal oscillator has fully settled. If the AGC loop is
disabled, the gain of IF filter can be set to three levels using the
Filter_Gain field, R9_DB[20:21]. The filter gain is adjusted
automatically, if the AGC loop is enabled.
Receiver Mode
High Sensitivity Mode (Default)
RxMode2
Low Current Mode
Enhanced Linearity Mode
RxMode5
RxMode6
LNA Mode
(R6_DB15)
0
1
1
1
1
0
Mixer
Linearity
(R6_DB18)
0
0
0
1
1
1
Rev. D | Page 20 of 48
Sensitivity
(DR = 9.6 kbps,
fDEV = 10 kHz)
110.5
104
94
88
98
107
Rx Current
Consumption
(mA)
21
20
19
19
20
21
Input IP3
(dBm)
24
13.5
5
3
10
20
Data Sheet
ADF7020
RSSI/AGC
The RSSI is implemented as a successive compression log amp
following the baseband channel filtering. The log amp achieves
3 dB log linearity. It also doubles as a limiter to convert the
signal-to-digital levels for the FSK demodulator. The RSSI itself
is used for amplitude shift keying (ASK) demodulation. In ASK
mode, extra digital filtering is performed on the RSSI value.
Offset correction is achieved using a switched capacitor integrator in feedback around the log amp. This uses the baseband
offset clock divide. The RSSI level is converted for user
readback and digitally controlled AGC by an 80-level (7-bit)
flash ADC. This level can be converted to input power in dBm.
OFFSET
CORRECTION
FWR
FWR
FWR
LATCH
FWR
FSK
DEMOD
CLK
RSSI
ASK
DEMOD
ADC
05351-029
NOTES
1. FWR = FULL WAVE RECTIFIER
RSSI Thresholds
When the RSSI is above AGC_HIGH_THRESHOLD, the gain
is reduced. When the RSSI is below AGC_LOW_THRESHOLD,
the gain is increased. A delay (AGC_DELAY) is programmed
to allow for settling of the loop. The user programs the two
threshold values (recommended defaults of 30 and 70) and the
delay (default of 10). The default AGC setup values should be
adequate for most applications. The threshold values must be
chosen to be more than 30 apart for the AGC to operate
correctly.
LNA Gain
(LG2, LG1)
H (1,1)
M (1,0)
M (1,0)
M (1,0)
L (0,1)
EL (0,0)
Filter Gain
(FG2, FG1)
H (1,0)
H (1,0)
M (0,1)
L (0,0)
L (0,0)
L (0,0)
In Register 3, the user should set the BB offset clock divide bits
R3_DB[4:5] to give an offset clock between 1 MHz and 2 MHz.
FSK correlator/demodulator
Linear demodulator
FSK CORRELATOR/DEMODULATOR
AGC is selected by default, and operates by selecting the appropriate LNA and filter gain settings for the measured RSSI level. It
is possible to disable AGC by writing to Register 9 if entering
one of the modes listed in Table 5 is desired, for example. The
time for the AGC circuit to settle and, therefore, the time to
take an accurate RSSI measurement is typically 150 s, although
this depends on how many gain settings the AGC circuit has to
cycle through. After each gain change, the AGC loop waits for
a programmed time to allow transients to settle.
The quadrature outputs of the IF filter are first limited and then
fed to a pair of digital frequency correlators that perform bandpass filtering of the binary FSK frequencies at (IF + fDEV) and
(IF fDEV). Data is recovered by comparing the output levels
from each of the two correlators. The performance of this frequency discriminator approximates that of a matched filter
detector, which is known to provide optimum detection in
the presence of additive white Gaussian noise (AWGN).
Rev. D | Page 21 of 48
ADF7020
Data Sheet
SLICER
I
LIMITERS
Q
IF fDEV
IF + fDEV
POST
DEMOD FILTER
IF
DATA
SYNCHRONIZER
FREQUENCY CORRELATOR
Discriminator _ BW
RxCLK
05351-030
0
R6_DB[4:13] R6_DB[14]
RxDATA
R3_DB[8:15]
Postdemodulator Filter
A second-order, digital low-pass filter removes excess noise from
the demodulated bit stream at the output of the discriminator.
The bandwidth of this postdemodulator filter is programmable
and must be optimized for the users data rate. If the bandwidth
is set too narrow, performance is degraded due to intersymbol
interference (ISI). If the bandwidth is set too wide, excess noise
degrades the receivers performance. Typically, the 3 dB bandwidth
of this filter is set at approximately 0.75 times the users data rate,
using Bits R4_DB[6:15].
where:
DEMOD_CLK is as defined in the Register 3Receiver Clock
Register section, second comment.
K = Round(200 103/FSK Deviation)
To optimize the coefficients of the FSK correlator, two additional bits, R6_DB14 and R6_DB29, must be assigned. The
value of these bits depends on whether K (as defined above) is
odd or even. These bits are assigned according to Table 7 and
Table 8.
Table 7. When K Is Even
K
Even
Even
K/2
Even
Odd
Bit Slicer
K
Odd
Odd
(K + 1)/2
Even
Odd
R6_DB14
0
0
R6_DB29
0
1
R6_DB14
1
1
R6_DB29
0
1
210 2 fCUTOFF
DEMOD _ CLK
where fCUTOFF is the target 3 dB bandwidth in Hz of the postdemodulator filter. This should typically be set to 0.75 times the
data rate (DR).
Some sample settings for the FSK correlator/demodulator are
DEMOD_CLK = 5 MHz
DR = 9.6 kbps
fDEV = 20 kHz
Data Synchronizer
An oversampled digital PLL is used to resynchronize the
received bit stream to a local clock. The oversampled clock rate
of the PLL (CDR_CLK) must be set at 32 times the data rate.
See the Register 3Receiver Clock Register Comments section
for a definition of how to program. The clock recovery PLL can
accommodate frequency errors of up to 2%.
DEMOD _ CLK K
800 103
Therefore,
fCUTOFF = 0.75 9.6 103 Hz
Postdemod_BW_Setting = 211 7.2 103 Hz/(5 MHz)
Postdemod_BW_Setting = Round(9.26) = 9
and
Rev. D | Page 22 of 48
Data Sheet
ADF7020
ASK/OOK Operation
Register Address
R4_DB[6:15]
R6_DB[4:13]
R6_DB14
R6_DB29
Value
0x09
0x3F
0
1
SLICER
Postdemod _ BW _ Setting
LEVEL
LIMITER
Q
FREQUENCY
LINEAR DISCRIMINATOR
FREQUENCY
READBACK
AND
AFC LOOP
R4_DB[6:15]
Postdemod _ BW _ Setting
210 2 fCUTOFF
DEMOD _ CLK
05351-031
IF
ENVELOPE
DETECTOR
RxDATA
AVERAGING
FILTER
210 2 fCUTOFF
DEMOD _ CLK
AFC
The ADF7020 supports a real-time AFC loop, which is used to
remove frequency errors that can arise due to mismatches between
the transmit and receive crystals. This uses the frequency
discriminator block, as described in the Linear FSK Demodulator
section (see Figure 31). The discriminator output is filtered and
averaged to remove the FSK frequency modulation, using a
combined averaging filter and envelope detector. In FSK mode,
the output of the envelope detector provides an estimate of the
average IF frequency.
Two methods of AFC, external and internal, are supported on
the ADF7020 (in FSK mode only).
External AFC
The user reads back the frequency information through the
ADF7020 serial port and applies a frequency correction value to
the fractional-N synthesizers N divider.
The frequency information is obtained by reading the 16-bit
signed AFC_READBACK, as described in the Readback Format
section, and applying the following formula:
FREQ_RB [Hz] = (AFC_READBACK DEMOD_CLK)/215
Rev. D | Page 23 of 48
ADF7020
Data Sheet
Internal AFC
AFC Performance
The improved sensitivity performance of the Rx when AFC is
enabled and in the presence of frequency errors is shown in
Figure 18. The maximum AFC frequency range is 50 kHz,
which corresponds to 58 ppm at 868 MHz. This is the total
error tolerance allowed in the link. For example, in a point-topoint system, AFC can compensate for two 29 ppm crystals or
one 50 ppm crystal and one 8 ppm TCXO.
AFC settling typically takes 48 bits to settle within 1 kHz. This
can be improved by increasing the postdemodulator bandwidth
in Register 4 at the expense of Rx sensitivity.
When AFC errors have been removed using either the internal
or external AFC, further improvement in the receivers sensitivity can be obtained by reducing the IF filter bandwidth using
Bits R1_DB[22:23].
Rev. D | Page 24 of 48
Data Sheet
ADF7020
APPLICATIONS INFORMATION
LNA/PA MATCHING
The ADF7020 exhibits optimum performance in terms of
sensitivity, transmit power, and current consumption only if its
RF input and output ports are properly matched to the antenna
impedance. For cost-sensitive applications, the ADF7020 is
equipped with an internal Rx/Tx switch that facilitates the use
of a simple combined passive PA/LNA matching network.
Alternatively, an external Rx/Tx switch, such as the Analog
Devices ADG919, can be used. It yields a slightly improved
receiver sensitivity and lower transmitter power consumption.
C1
L1
PA_OUT
PA
ANTENNA
ZOPT_PA
RFIN
ADG919
Rx/Tx SELECT
LNA
RFINB
ZIN_RFIN
CB
ADF7020
05351-032
LA
ZIN_RFIN
OPTIONAL CA
BPF
(SAW)
C1
L1
PA_OUT
PA
ANTENNA
ZOPT_PA
OPTIONAL
BPF OR LPF
ZIN_RFIN
CA
RFIN
LA
LNA
RFINB
ZIN_RFIN
CB
ADF7020
Rev. D | Page 25 of 48
05351-033
OPTIONAL
LPF
ADF7020
Data Sheet
Calibration Procedure and Setup
ADF7020
MATCHING
RFINB
LNA
GAIN ADJUST
EXTERNAL
SIGNAL
SOURCE
RFIN
POLYPHASE
IF FILTER
RSSI/
LOG AMP
7-BIT ADC
PHASE ADJUSTMENT
I
Q
FROM LO
SERIAL
INTERFACE
4
PHASE ADJUST
REGISTER 10
RSSI READBACK
GAIN ADJUST
REGISTER 10
Figure 34. Image Rejection Calibration Using the Internal Calibration Source and a Microcontroller
Rev. D | Page 26 of 48
05351-059
MICROCONTROLLER
Data Sheet
ADF7020
DEVICE PROGRAMMING AFTER INITIAL
POWER-UP
60
CAL AT +25C
CAL AT 40C
30
VDD = 3.0V
IF BW = 25kHz
20
10
WANTED SIGNAL:
RF FREQ = 430MHz
MODULATION = 2FSK
DATA RATE = 9.6kbps,
PRBS9
fDEV = 4kHz
LEVEL= 100dBm
0
60
40
20
INTERFERER SIGNAL:
RF FREQ = 429.8MHz
MODULATION = 2FSK
DATA RATE = 9.6kbps,
PRBS11
fDEV = 4kHz
20
40
60
100
TEMPERATURE (C)
Mode
Tx
Rx (OOK)
Rx (G/FSK)
Tx Rx
ID
FIELD
DATA FIELD
Reg. 1
Reg. 1
Reg. 1
Reg. 2
Reg. 3
Reg. 3
Reg. 4
Reg. 4
Reg. 6
Reg. 6
PREAMBLE
Register
Reg. 0
Reg. 0
Reg. 0
Reg. 0
CRC
INTERFACING TO MICROCONTROLLER/DSP
Low level device drivers are available for interfacing the
ADF7020 to the Analog Devices ADuC84x analog
microcontrollers, or the Blackfin ADSP-BF53x DSPs, using the
hardware connections shown in Figure 37 and Figure 38.
Rev. D | Page 27 of 48
ADF7020
ADuC84x
MISO
DATA I/O
MOSI
SCLOCK
DATA CLK
SS
P3.7
P3.2/INT0
GPIO
CE
INT/LOCK
P2.4
SREAD
P2.5
SLE
P2.6
SDATA
P2.7
SCLK
05351-035
CAL AT +85C
ADF7020
ADSP-BF533
SCK
MOSI
MISO
PF5
RSCLK1
DT1PRI
SCLK
SDATA
SREAD
SLE
DATA CLK
DATA I/O
DR1PRI
RFS1
PF6
INT/LOCK
CE
VDDEXT
VDD
GND
GND
05351-036
40
05351-058
50
ADF7020
Data Sheet
Using a sequenced power-on routine like that illustrated in
Figure 39 can reduce the IAVG_ON current and, hence, reduce the
overall power consumption. When used in conjunction with a
large duty-cycle or large tOFF, this can result in significantly
increased battery life. Analog Devices, Inc.s free design tool,
ADI SRD Design Studio, can assist in these calculations.
ADF7020 I DD
19mA TO
22mA
14mA
XTAL
t0
3.65mA
2.0mA
AFC
t10
t1
WR0 WR1
t2
t3
VCO
t4
AGC/
RSSI
t5
t6
t7
t8
CDR
t9
TIME
RxDATA
t11
tON
tOFF
05351-037
REG.
READY
Value
2 ms
t1
10 s
32 1/SPI_CLK
t8
150 s
t9
5 Bit_Period
t10
48 Bit_Period
t11
Packet Length
1 ms
Description
Crystal starts power-up after CE is brought high. This typically depends
on the crystal type and the load capacitance specified.
Time for regulator to power up. The serial interface can be written to after
this time.
Time to write to a single register. Maximum SPI_CLK is 25 MHz.
Signal to Monitor
CLKOUT pin
The VCO can power-up in parallel with the crystal. This depends on the
CVCO capacitance value used. A value of 22 nF is recommended as a
trade-off between phase noise performance and power-up time.
This depends on the number of gain changes the AGC loop needs to cycle
through and AGC settings programmed. This is described in more detail
in the AGC Information and Timing section.
This is the time for the clock and data recovery circuit to settle. This typically
requires 5-bit transitions to acquire sync and is usually covered by the
preamble.
This is the time for the automatic frequency control circuit to settle. This
typically requires 48-bit transitions to acquire lock and is usually covered
by an appropriate length preamble.
Number of bits in payload by the bit period.
CVCO pin
Rev. D | Page 28 of 48
MUXOUT pin
ADF7020
ADF7020 I DD
Data Sheet
15mA TO
30mA
14mA
3.65mA
2.0mA
t1
WR0 WR1
t2
t3
XTAL + VCO
t4
WR2
TIME
TxDATA
t5
t12
tON
Rev. D | Page 29 of 48
tOFF
05351-038
REG.
READY
ADF7020
Data Sheet
LOOP FILTER
XTAL
REFERENCE
VDD
ADF7020
TOP VIEW
(Not to Scale)
RSET
RESISTOR
Rev. D | Page 30 of 48
VDD
CHIP ENABLE
TO MICROCONTROLLER
RLNA
RESISTOR
DATA I/O
INT/LOCK
VDD2
CREG2
ADCIN
GND2
SCLK
SREAD
SDATA
SLE
36
35
34
33
32
31
30
29
28
27
26
25
TO
MICROCONTROLLER
CONFIGURATION
INTERFACE
VDD
3
4
5
6
7
8
9
10
11
12
CLKOUT
DATA CLK
05351-056
VDD
T-STAGE LC
FILTER
PIN 1
INDICATOR
13
14
15
16
17
18
19
20
21
22
23
24
ANTENNA
CONNECTION
VCOIN
CREG1
VDD1
RFOUT
RFGND
RFIN
RFINB
RLNA
VDD4
RSET
CREG4
GND4
TO
MICROCONTROLLER
Tx/Rx SIGNAL
INTERFACE
1
2
MATCHING
MIX_I
MIX_I
MIX_Q
MIX_Q
FILT_I
FILT_I
GND4
FILT_Q
FILT_Q
GND4
TEST_A
CE
VDD
CVCO
GND1
GND
VCO GND
GND
VDD
CPOUT
CREG3
VDD3
OSC1
OSC2
MUXOUT
48
47
46
45
44
43
42
41
40
39
38
37
CVCO
CAP
Data Sheet
ADF7020
SERIAL INTERFACE
RSSI Readback
READBACK FORMAT
These three ADC readback values are valid by just enabling the
ADC in Register 8 without writing to the other registers. The
battery voltage is measured at Pin VDD4. The readback
information is contained in Bit RV1 to Bit RV7. This also
applies for the readback of the voltage at the ADCIN pin and
the temperature sensor. From the readback information, the
battery, ADCIN voltage or temperature can be obtained using
VBATTERY = (Battery_Voltage_Readback)/21.1
VADCIN = (ADCIN_Voltage_Readback)/42.1
Temperature =
40C + (68.4 Temperature_Sensor_Readback) 9.32
AFC Readback
The AFC readback is valid only during the reception of FSK
signals with either the linear or correlator demodulator active.
The AFC readback value is formatted as a signed 16-bit integer
comprising Bit RV1 to Bit RV16 and is scaled according to the
following formula:
READBACK VALUE
DB15
DB14
DB13
DB12
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
AFC READBACK
RV16
RV15
RV14
RV13
RV12
RV11
RV10
RV9
RV8
RV7
RV6
RV5
RV4
RV3
RV2
RV1
RSSI READBACK
LG2
LG1
FG2
FG1
RV7
RV6
RV5
RV4
RV3
RV2
RV1
BATTERY VOLTAGE/ADCIN/
TEMP. SENSOR READBACK
RV7
RV6
RV5
RV4
RV3
RV2
RV1
SILICON REVISION
RV16
RV15
RV14
RV13
RV12
RV11
RV10
RV9
RV8
RV7
RV6
RV5
RV4
RV3
RV2
RV1
RV8
RV7
RV6
RV5
RV4
RV3
RV2
RV1
Rev. D | Page 31 of 48
05351-039
READBACK MODE
ADF7020
Data Sheet
REGISTERS
DB2
DB1
DB0
C2(0)
C1(0)
DB3
C4(0)
C3(0)
DB4
M15
M14
M13
M3
M2
M1
FRACTIONAL
DIVIDE RATIO
0
0
0
.
.
.
1
1
1
1
0
0
0
.
.
.
1
1
1
1
0
0
0
.
.
.
1
1
1
1
.
.
.
.
.
.
.
.
.
.
0
0
0
.
.
.
1
1
1
1
0
0
1
.
.
.
0
0
1
1
0
1
0
.
.
.
0
1
0
1
0
1
2
.
.
.
32,764
32,765
32,766
32,767
N8
N7
N6
N5
N4
N3
N2
N1
N COUNTER
DIVIDE RATIO
0
0
.
.
.
1
0
0
.
.
.
1
0
1
.
.
.
1
1
0
.
.
.
1
1
0
.
.
.
1
1
0
.
.
.
1
1
0
.
.
.
0
1
0
.
.
.
1
31
32
.
.
.
253
254
255
05351-040
DB12
M9
M1
DB13
M10
DB5
DB14
DB6
DB15
M12
M11
M2
DB16
M13
M3
DB17
MUXOUT
0
1
0
1
0
1
0
1
DB7
DB18
M15
M14
M1
0
0
1
1
0
0
1
1
M4
DB19
N1
M2
0
0
0
0
1
1
1
1
DB8
DB20
N2
M3
DB9
DB21
N3
PLL OFF
PLL ON
M5
DB22
N4
0
1
M6
DB23
N5
DB10
DB24
N6
TRANSMIT
RECEIVE
M7
DB25
0
1
DB11
DB26
N8
N7
TRANSMIT/
RECEIVE
M8
Tx/Rx
TR1
ADDRESS
BITS
15-BIT FRACTIONAL-N
DB27
DB29
M1
8-BIT INTEGER-N
TR1
DB30
M2
PLE1 DB28
DB31
M3
MUXOUT
PLL
ENABLE
REGISTER 0N REGISTER
The Tx/Rx bit (R0_DB27) configures the part in Tx or Rx mode and controls the state of the internal Tx/Rx switch.
fOUT =
XTAL
Fractional _ N
(Integer _ N +
)
R
215
If operating in 433 MHz band, with the VCO Band bit set, the desired frequency, fOUT, should be programmed to be twice the desired
operating frequency, due to removal of the divide-by-2 stage in the feedback path.
Rev. D | Page 32 of 48
Data Sheet
ADF7020
0
0
1
1
0
1
0
1
0
0
1
1
0
1
0
1
XTAL
DOUBLER
XOSC
ENABLE
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
CL1
D1
R3
R2
R1
C4(0)
C3(0)
C2(0)
C1(1)
DB13
V1
DB9
DB14
CP1
DB10
DB15
CP2
CL2
DB16
VB1
CL3
DB17
VB2
DB11
DB18
VB3
VB4
VB3
VB2
VB1
0
0
0
.
1
0
0
0
.
1
0
0
1
.
1
0
1
0
.
1
FILTER
BANDWIDTH
100kHz
150kHz
200kHz
NOT USED
CL4
DB19
VB4
VCO BAND
DB20
VA1
X1 XTAL OSC
0
OFF
1
ON
V1
VCO BIAS
CURRENT
0
1
ADDRESS
BITS
R COUNTER
DB12
DB21
FREQUENCY
OF OPERATION
850 TO 920
860 TO 930
870 TO 940
880 TO 950
CLOCKOUT
DIVIDE
X1
CP
CURRENT
VCO
ADJUST
VA1
VA2
DB22
VA2
VCO BIAS
R3
0
0
.
.
.
1
VCO Band
(MHz)
862 TO 956
431 TO 478
0.125mA
0.375mA
0.625mA
D1
0
1
R2
0
1
.
.
.
1
R1
1
0
.
.
.
1
RF R COUNTER
DIVIDE RATIO
1
2
.
.
.
7
XTAL
DOUBLER
DISABLE
ENABLED
3.875mA
CP2
CP1
ICP (mA)
0
0
1
1
0
1
0
1
0.3
0.9
1.5
2.1
CL4
0
0
0
.
.
.
1
CL3
0
0
0
.
.
.
1
CL2
0
0
1
.
.
.
1
CL1
0
1
0
.
.
.
1
CLKOUT
DIVIDE RATIO
OFF
2
4
.
.
.
30
05351-041
IR2 IR1
IR1
IR2
DB23
IF FILTER BW
The VCO Adjust Bits R1_DB[20:21] should be set to 0 for operation in the 862 MHz to 870 MHz band and set to 3 for operation in
the 902 MHz to 928 MHz band.
The VCO bias setting should be 0xA for operation in the 862 MHz to 870 MHz and 902 MHz to 928 MHz bands. All VCO gain
numbers are specified for these VCO Adjust and Bias settings.
Rev. D | Page 33 of 48
ADF7020
Data Sheet
DB12
DB11
DB10
DB9
DB8
DB7
P4
P3
P2
P1
S3
S2
DB0
DB13
P5
C1(0)
DB14
P6
DB1
DB15
D1
MUTE PA
UNTIL LOCK
PA
ENABLE
PE1
POWER AMPLIFIER
0
1
OFF
ON
MUTE PA UNTIL
MP1 LOCK DETECT HIGH
DI1
TxDATA
TxDATA
0
1
OFF
ON
PA2
PA1
PA BIAS
S3
S2
S1
MODULATION SCHEME
0
0
1
1
0
1
0
1
5A
7A
9A
11A
0
0
0
0
1
0
0
1
1
1
0
1
0
1
1
FSK
GFSK
ASK
OOK
GOOK
X
X
0
0
.
.
.
1
.
.
.
.
.
.
.
.
X
X
0
0
1
.
.
1
X
X
0
1
0
.
.
1
OOK MODE
PA OFF
16.0dBm
16 + 0.45dBm
16 + 0.90dBm
.
.
13dBm
.
.
.
.
.
.
1
.
.
.
.
.
.
.
X
0
0
1
.
.
1
X
0
1
0
.
.
1
PA OFF
16.0dBm
16 + 0.45dBm
16 + 0.90dBm
.
.
13dBm
See the Transmitter section for a description of how the PA bias affects the power amplifier level. The default level is 9 A.
If maximum power is needed, program this value to 11 A.
See Figure 13.
D7, D8, and D9 are dont care bits.
Rev. D | Page 34 of 48
05351-042
0
1
C2(1)
DB16
D2
DB2
DB17
D3
DB3
DB18
D4
C3(0)
DB19
D5
C4(0)
DB20
D6
DB4
DB21
D7
ADDRESS
BITS
PE1
DB22
D8
DB5
DB23
D9
DB6
DB24
MC1
S1
DB25
MP1
DB26
MC3
MC2
DB28
IC2
MODULATION
SCHEME
POWER AMPLIFIER
MODULATION PARAMETER
DB27
DB29
DI1
GFSK MOD
CONTROL
IC1
DB30
PA1
TxDATA
INVERT
DB31
PA2
PA BIAS
INDEX
COUNTER
Data Sheet
ADF7020
DI1
0
1
TxDATA
TxDATA
PA2
PA1
PA BIAS
0
0
1
1
0
1
0
1
5A
7A
9A
11A
DB14
DB13
DB12
DB11
DB10
DB9
DB8
DB7
DB6
DB5
P6
P5
P4
P3
P2
P1
S3
S2
S1
MP1
DB0
DB15
D1
C1(0)
DB16
D2
DB1
DB17
D3
DB2
DB18
D4
C2(1)
DB19
D5
C3(0)
DB20
D6
DB3
DB21
F DEVIATION
0
0
0
0
.
1
0
1
0
1
.
1
PLL MODE
1 fSTEP
2 fSTEP
3 fSTEP
.
511 fSTEP
0
0
1
1
.
1
DB4
DB22
D8
D7
D1
0
0
0
0
.
1
PE1
POWER AMPLIFIER
0
1
OFF
ON
MUTE PA UNTIL
MP1 LOCK DETECT HIGH
PE1
DB23
D9
ADDRESS
BITS
C4(0)
DB25
DB24
MUTE PA
UNTIL LOCK
PA
ENABLE
MODULATION
SCHEME
POWER AMPLIFIER
MC1
DB26
MC3
MODULATION PARAMETER
MC2
DB28
DB27
IC1
DB29
DI1
GFSK MOD
CONTROL
IC2
DB30
PA1
TxDATA
INVERT
DB31
PA2
PA BIAS
INDEX
COUNTER
0
1
OFF
ON
S3
S2
S1
MODULATION SCHEME
0
0
0
0
1
0
0
1
1
1
0
1
0
1
1
FSK
GFSK
ASK
OOK
GOOK
0
0
0
0
.
.
1
.
.
.
.
.
.
1
.
.
.
.
.
.
.
fSTEP = PFD/214.
When operating in the 431 MHz to 478 MHz band, fSTEP = PFD/215.
PA bias default = 9 A.
Rev. D | Page 35 of 48
X
0
0
1
.
.
1
X
0
1
0
.
.
1
PA OFF
16.0dBm
16 + 0.45dBm
16 + 0.90dBm
.
.
13dBm
05351-043
ADF7020
Data Sheet
PA1
PA BIAS
0
0
1
1
0
1
0
1
5A
7A
9A
11A
MUTE PA
UNTIL LOCK
PA
ENABLE
0
1
D9
0
0
1
1
IC2
IC1
INDEX_COUNTER
0
0
1
1
0
1
0
1
16
32
64
128
D8
0
1
0
1
GAUSSIAN OOK
MODE
NORMAL MODE
OUTPUT BUFFER ON
BLEED CURRENT ON
BLEED/BUFFER ON
0
1
.
1
DB2
DB1
DB0
C2(1)
C1(0)
S2
S1
MODULATION SCHEME
0
0
0
0
1
0
0
1
1
1
0
1
0
1
1
FSK
GFSK
ASK
OOK
GOOK
0
0
0
0
.
.
1
0
1
.
7
.
.
.
.
.
.
1
.
.
.
.
.
.
.
X
0
0
1
.
.
1
X
0
1
0
.
.
1
DB3
S3
PA OFF
16.0dBm
16 + 0.45dBm
16 + 0.90dBm
.
.
13dBm
05351-044
0
0
.
1
OFF
ON
MUTE PA UNTIL
MP1 LOCK DETECT HIGH
TxDATA
TxDATA
PA2
C3(0)
DB7
S2
OFF
ON
C4(0)
DB8
S3
POWER AMPLIFIER
0
1
DB4
DB9
P1
PE1
INVALID
1
2
3
.
127
PE1
DB10
P2
DIVIDER_FACTOR
0
1
0
1
.
1
DB5
DB11
P3
D1
0
0
1
1
.
1
DB6
DB12
P4
D2
0
0
0
0
.
1
S1
DB13
P5
D3
.
.
.
.
.
.
MP1
DB14
DB15
P6
0
0
0
0
.
1
D1
DB16
DB21
D7
D7
D2
DB22
D8
DB17
DB23
D9
DB18
DB24
MC1
D3
DB25
MC2
D4
DB26
MC3
DB19
DB27
IC1
D5
DB28
IC2
0
1
ADDRESS
BITS
DB20
DB29
DI1
DI1
MODULATION
SCHEME
POWER AMPLIFIER
D6
DB30
PA1
MODULATION PARAMETER
DB31
TxDATA
INVERT
GFSK MOD
CONTROL
PA2
PA BIAS
INDEX
COUNTER
Rev. D | Page 36 of 48
Data Sheet
ADF7020
SK7
0
0
.
1
1
0
0
.
1
1
DB0
DB5
BK2
C1(1)
DB6
OK1
DB1
DB7
OK2
C2(1)
DB8
FS1
DB2
DB9
FS2
DB3
DB10
FS3
C3(0)
DB11
FS4
ADDRESS
BITS
C4(0)
DB12
FS5
BB OFFSET
CLOCK DIVIDE
DB13
FS6
DB4
DB14
FS7
BK1
DB15
FS8
DB16
SK1
DB18
SK3
DB17
DB19
SK2
DB20
SK4
.
.
.
.
.
.
SK3
SK2
SK1
SEQ_CLK_DIVIDE
BK2
BK1
BBOS_CLK_DIVIDE
0
0
.
1
1
0
1
.
1
1
1
0
.
0
1
1
2
.
254
255
0
0
1
0
1
x
4
8
16
OK2
OK1
DEMOD_CLK_DIVIDE
0
0
1
1
0
1
0
1
4
1
2
3
FS8
FS7
FS3
FS2
FS1
CDR_CLK_DIVIDE
0
0
.
1
1
0
0
.
1
1
.
.
.
.
.
0
0
.
1
1
0
1
.
1
1
1
0
.
0
1
1
2
.
254
255
05351-045
SK8
SK5
DB21
DB22
SK7
SK6
DB23
SK8
DEMOD
CLOCK DIVIDE
Baseband offset clock frequency (BBOS_CLK) must be greater than 1 MHz and less than 2 MHz, where
BBOS _ CLK =
XTAL
BBOS _ CLK _ DIVIDE
The demodulator clock (DEMOD_CLK) must be <12 MHz for FSK and <6 MHz for ASK, where
DEMOD _ CLK =
Data/clock recovery frequency (CDR_CLK) should be within 2% of (32 data rate), where
CDR _ CLK =
XTAL
DEMOD _ CLK _ DIVIDE
DEMOD _ CLK
CDR _ CLK _ DIVIDE
Note that this can affect your choice of XTAL, depending on the desired data rate.
The sequencer clock (SEQ_CLK) supplies the clock to the digital receive block. It should be close to 100 kHz for FSK and close to
40 kHz for ASK.
SEQ _ CLK =
XTAL
SEQ _ CLK _ DIVIDE
Rev. D | Page 37 of 48
ADF7020
Data Sheet
0
0
0
0
1
1
0
0
1
1
0
1
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
DW3
DW2
DW1
DS2
DS1
C4(0)
C3(1)
C2(0)
C1(0)
DB16
DL1
OUTPUT
OUTPUT
INPUT
DB9
DB17
DL2
INT/LOCK PIN
DW4
DB18
DL3
DW5 DB10
DB19
DL4
DW6 DB11
DB20
DL5
DW7 DB12
DB21
DL6
DW8 DB13
DB22
DL7
DW9 DB14
DB23
DL8
DW10 DB15
DB24
LM1
0
1
0
1
X
DL8
ADDRESS
BITS
POSTDEMODULATOR BW
DB25
LM2
DEMOD
SELECT
DEMOD LOCK/
SYNC WORD MATCH
DS2
DS1
DEMODULATOR
TYPE
0
0
1
1
0
1
0
1
LINEAR DEMODULATOR
CORRELATOR/DEMODULATOR
ASK/OOK
INVALID
DL8
DL7
0
0
0
.
1
1
0
0
0
.
1
1
.
.
.
.
.
.
DL3
DL2
DL1
LOCK_THRESHOLD_TIMEOUT
0
0
0
.
1
1
0
0
1
.
1
1
0
1
0
.
0
1
0
1
2
.
254
255
05351-046
MODE5 ONLY
Demodulator Mode 1, Demodulator Mode 3, Demodulator Mode 4, and Demodulator Mode 5 are modes that can be activated to
allow the ADF7020 to demodulate data-encoding schemes that have run-length constraints greater than 7, when using the linear
demodulator.
211 fCUTOFF
Postdemod_BW =
DEMOD_CLK
where the cutoff frequency (fCUTOFF) of the postdemodulator filter should typically be 0.75 times the data rate.
For Mode 5, Timeout Delay to Lock Threshold = (LOCK_THRESHOLD_SETTING)/SEQ_CLK
where SEQ_CLK is defined in the Register 3Receiver Clock Register section.
Rev. D | Page 38 of 48
Data Sheet
ADF7020
DB4
DB3
DB2
DB1
DB0
C4(0)
C3(1)
C2(0)
C1(1)
DB5
CONTROL
BITS
PL1
DB6
MT1
PL2
DB7
DB8
MT2
DB9
DB10
DB11
DB12
DB13
DB14
DB15
DB16
DB17
DB19
DB18
DB20
DB21
DB22
DB23
DB24
DB25
DB26
DB27
DB28
DB29
DB30
DB31
SYNC BYTE
LENGTH
MATCHING
TOLERANCE
PL2
PL1
SYNC BYTE
LENGTH
0
0
1
1
0
1
0
1
12 BITS
16 BITS
20 BITS
24 BITS
0
0
1
1
0
1
0
1
0 ERRORS
1 ERROR
2 ERRORS
3 ERRORS
05351-047
MATCHING
MT2 MT1 TOLERANCE
Rev. D | Page 39 of 48
ADF7020
Data Sheet
LI2
LI1
LNA BIAS
800A (DEFAULT)
FC9
FC6
FC5
FC4
FC3
FC2
FC1
FILTER CLOCK
DIVIDE RATIO
0
0
.
.
.
.
1
.
.
.
.
.
.
.
0
0
.
.
.
.
1
0
0
.
.
.
.
1
0
0
.
.
.
.
1
0
0
.
.
.
.
1
0
1
.
.
.
.
1
1
0
.
.
.
.
1
1
2
.
.
.
.
511
DB2
DB1
DB0
C2(1)
C1(0)
DB5
TD2
C3(1)
DB6
TD3
0
1
DEFAULT
HIGH
DB3
DB7
TD4
0
1
DB4
DB8
TD5
TD1
DB9
CROSS PRODUCT
DOT PRODUCT
C4(0)
DB10
TD6
DB14
DP1
TD7
DB15
LG1
DOT PRODUCT
0
1
DEFAULT
REDUCED GAIN
05351-048
NORMAL OPPERATION
CDR RESET
DB11
DB16
LI1
DB24
FC5
RxRESET
0
1
TD8
DB17
LI2
DB25
FC6
NORMAL OPPERATION
DEMOD RESET
DB12
DB18
ML1
DP1
0
1
RxRESET
0
1
TD9
DOT
PRODUCT
DB19
CA1
ADDRESS
BITS
DISCRIMINATOR BW
TD10 DB13
LNA MODE
DB20
FC1
DB26
FC7
RxDATA
RxDATA
LNA
CURRENT
DB21
FC2
IF FILTER
CAL
MIXER
LINEARITY
DB22
FC3
DB27
FC8
0
1
DB23
DB28
FC9
RI1
RxDATA
INVERT
FC4
DB29
DB30
IF FILTER DIVIDER
RI1
DB31
Rx
RESET
RxDATA
INVERT
See the FSK Correlator/Demodulator section for an example of how to determine register settings.
Nonadherence to correlator programming guidelines results in poorer sensitivity.
The filter clock is used to calibrate the IF filter. The filter clock divide ratio should be adjusted so that the frequency is 50 kHz.
The formula is XTAL/FILTER_CLOCK_DIVIDE.
The filter should be calibrated only when the crystal oscillator is settled. The filter calibration is initiated every time Bit R6_DB19
is set high.
Discriminator_BW = (DEMOD_CLK K)/(800 103). See the FSK Correlator/Demodulator section. Maximum value = 600.
When LNA Mode = 1 (reduced gain mode), the Rx is prevented from selecting the highest LNA gain setting. This can be used when
linearity is a concern. See Table 5 for details of the different Rx modes.
Rev. D | Page 40 of 48
Data Sheet
ADF7020
ADC
MODE
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
RB3
RB2
RB1
AD2
AD1
C4(0)
C3(1)
C2(1)
C1(1)
RB3 READBACK
0
1
0
0
1
1
DISABLED
ENABLED
RB2 RB1 READBACK MODE
0
0
1
1
0
1
0
1
0
1
0
1
AFC WORD
ADC OUTPUT
FILTER CAL
SILICON REV
MEASURE RSSI
BATTERY VOLTAGE
TEMP SENSOR
TO EXTERNAL PIN
05351-049
READBACK
SELECT
Readback of the measured RSSI value is valid only in Rx mode. To enable readback of the battery voltage, the temperature sensor, or
the voltage at the external pin in Rx mode, AGC function in Register 9 must be disabled. To read back these parameters in Tx mode,
the ADC must first be powered up using Register 8 because this is off by default in Tx mode to save power. This is the recommended
method of using the battery readback function because most configurations typically require AGC.
Readback of the AFC word is valid in Rx mode only if either the linear demodulator or the correlator/demodulator is active.
See the Readback Format section for more information.
Rev. D | Page 41 of 48
ADF7020
Data Sheet
PA (Rx MODE)
0
1
PA OFF
PA ON
INTERNAL Tx/Rx
SWITCH ENABLE
DEMOD
ENABLE
ADC
ENABLE
FILTER
ENABLE
LNA/MIXER
ENABLE
VCO
ENABLE
SYNTH
ENABLE
DB13
DB12
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
PD7
SW1
LR2
LR1
PD6
PD5
PD4
PD3
PD2
PD1
C4(1)
C3(0)
C2(0)
C1(0)
LOG AMP/
RSSI
DEFAULT (ON)
OFF
CONTROL
BITS
PLE1
(FROM REG 0)
PD2
PD1
LOOP
CONDITION
0
0
0
0
1
0
0
1
1
X
0
1
0
1
X
VCO/PLL OFF
PLL ON
VCO ON
PLL/VCO ON
PLL/VCO ON
LR2
LR1
RSSI MODE
PD3
LNA/MIXER ENABLE
X
X
0
1
RSSI OFF
RSSI ON
0
1
LNA/MIXER OFF
LNA/MIXER ON
PD6
DEMOD ENABLE
PD4
FILTER ENABLE
0
1
DEMOD OFF
DEMOD ON
0
1
FILTER OFF
FILTER ON
PD5
ADC ENABLE
0
1
ADC OFF
ADC ON
05351-050
PD7
PA ENABLE
Rx MODE
For a combined LNA/PA matching network, Bit R8_DB12 should always be set to 0. This is the power-up default condition.
It is not necessary to write to this register under normal operating conditions.
Rev. D | Page 42 of 48
Data Sheet
ADF7020
0
1
8
24
72
INVALID
DB6
DB5
DB4
DB3
DB2
DB1
DB0
GL3
GL2
GL1
C4(1)
C3(0)
C2(0)
C1(1)
DB7
DB8
DB9
GL6
GL4
DB10
GL5
DB11
DB13
GH3
0
0
1
1
0
1
0
1
AGC LOW
GL7 GL6 GL5 GL4 GL3 GL2 GL1 THRESHOLD
AUTO AGC
HOLD SETTING
GL7
DB14
GH4
0
1
GH1
DB15
GH5
LOW
HIGH
DB12
DB16
GH6
FILTER CURRENT
0
1
GH2
DB17
DB19
GC1
FI1
ADDRESS
BITS
GH7
DB20
LG1
DB18
DB21
LG2
GS1
DB22
FG1
GAIN
CONTROL
AGC
SEARCH
DB23
FG2
LNA
GAIN
DB24
DB25
FILTER
GAIN
FI1
DB26
DIGITAL
TEST IQ
FILTER
CURRENT
0
0
0
0
.
.
.
1
1
1
AUTO
USER
0
0
0
0
.
.
.
0
0
0
0
0
0
0
.
.
.
0
0
1
0
0
0
0
.
.
.
1
1
0
0
1
1
0
.
.
.
1
1
0
0
0
0
1
.
.
.
1
1
0
1
0
1
0
.
.
.
0
1
0
1
2
3
4
.
.
.
78
79
80
0
1
0
1
<1
3
10
30
0
0
0
0
.
.
.
1
1
1
0
0
0
0
.
.
.
0
0
0
0
0
0
0
.
.
.
0
0
1
0
0
0
0
.
.
.
1
1
0
0
0
0
1
.
.
.
1
1
0
0
1
1
0
.
.
.
1
1
0
1
0
1
0
.
.
.
0
1
0
1
2
3
4
.
.
.
78
79
80
This register does not need to be programmed in normal operation. Default AGC_Low_Threshold = 30, default
AGC_High_Threshold = 70. See the RSSI/AGC section for details. Default register setting = 0xB2 31E9.
AGC high and low settings must be more than 30 apart to ensure correct operation.
Rev. D | Page 43 of 48
05351-051
AGC HIGH
GH7 GH6 GH5 GH4 GH3 GH2 GH1 THRESHOLD
ADF7020
Data Sheet
DB2
DB1
DB0
C3(0)
C2(1)
C1(0)
DB4
PR1
DB3
DB5
PR2
C4(1)
DB6
DB7
PR4
PR3
DB8
DB12
DH1
DB9
DB13
DH2
GL4
DB14
DH3
DEFAULT = 0xA
DEFAULT = 0xA
DEFAULT = 0x2
05351-052
0
1
PHASE TO I CHANNEL
PHASE TO Q CHANNEL
GL5
DB15
DH4
0
1
DB10
DB16
GC1
SIQ2 SELECT IQ
GL6
DB17
GC2
SIQ2 SELECT IQ
DB11
DB18
GC3
ADDRESS
BITS
PEAK RESPONSE
GL7
DB19
GC4
SELECT
I/Q
GAIN/ATTENUATE
DB20
DB23
R1
LEAK FACTOR
DB21
DB24
PH1
AGC DELAY
UD1
DB25
PH2
GC5
DB26
SIQ1 DB22
RESERVED
DB27
PH3
I/Q PHASE
ADJUST
PH4
SIQ2 DB28
SELECT
I/Q
GAIN TO I CHANNEL
GAIN TO Q CHANNEL
DB19
DB18
DB17
DB16
DB15
AE1
M16
M15
M14
M13
M12
DB14
DB13
DB12
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
M11
M10
M9
M8
M7
M6
M5
M4
M3
M2
M1
C4(1)
C3(0)
C2(1)
C1(1)
0
1
05351-053
INTERNAL
AE1 AFC
OFF
ON
See the Internal AFC section to program the AFC scaling coefficient bits.
The AFC scaling coefficient bits can be programmed using the following formula:
AFC_Scaling_Coefficient = Round((500 224)/XTAL)
Rev. D | Page 44 of 48
Data Sheet
ADF7020
PRESCALER
0
1
4/5 (DEFAULT)
8/9
CAL SOURCE
0
1
INTERNAL
SERIAL IF BW CAL
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
T7
T6
T5
T4
T3
T2
T1
C4(1)
C3(1)
C2(0)
C1(0)
COUNTER
RESET
T8
DB18
SF1
DB12
DB19
SF2
T9
DB20
SF3
DB17
DB21
SF4
DB13
DB22
SF5
CS1
ADDRESS
BITS
CR1
DB23
SF6
DB14
SOURCE
DB24
CS1
DB15
OSC TEST
DB25
QT1
-
TEST MODES
DEFAULT
RESET
05351-054
DIGITAL
TEST MODES
DB16
FORCE
LD HIGH
DB26
DB27
DB28
DB29
DB30
ANALOG TEST
MUX
PRE
DB31 PRESCALER
Digital test modes = 10: enables the test DAC, with offset
removal (needed for linear demodulation only, 0x02 800C).
The output of the active demodulator drives the DAC, that is, if
the FSK correlator/demodulator is selected, the correlator filter
output drives the DAC.
The evaluation boards for the ADF7020 contain land patterns
for placement of an RC filter on the CLKOUT line. This is
typically designed so that the cut-off frequency of the filter is
above the demodulated data rate.
Rev. D | Page 45 of 48
ADF7020
Data Sheet
PE2
PE1
PULSE EXTENSION
0
0
0
.
.
.
1
0
0
1
.
.
.
1
0
1
0
.
.
.
1
DB3
DB2
DB1
DB0
C4(1)
C3(1)
C2(0)
C1(1)
DB4
DB6
KP DEFAULT = 2
05351-055
PE3
0
0
0
.
.
.
1
DB7
DB8
DB12
PE1
KI DEFAULT = 3
PE4
CONTROL
BITS
KP
DB9
DB13
PE2
DB10
DB14
PE3
DB11
DB15
PE4
DB16
DB17
DB18
DB19
DB20
DB21
DB22
DB23
DB24
DB25
KI
DB5
PULSE
EXTENSION
DB26
DB27
DB28
DB29
DB30
DB31
Because the linear demodulators output is proportional to frequency, it usually consists of an offset combined with a relatively low
signal. The offset can be removed, up to a maximum of 1.0, and gained to use the full dynamic range of the DAC:
DAC_Input = (2Test_DAC_Gain) (Signal Test_DAC_Offset_Removal/4096)
Ki (default) = 3. Kp (default) = 2.
Rev. D | Page 46 of 48
Data Sheet
ADF7020
OUTLINE DIMENSIONS
0.30
0.23
0.18
PIN 1
INDICATOR
48
37
36
0.50
BSC
TOP VIEW
0.80
0.75
0.70
0.45
0.40
0.35
4.25
4.10 SQ
3.95
EXPOSED
PAD
12
25
24
13
BOTTOM VIEW
0.05 MAX
0.02 NOM
COPLANARITY
0.08
0.20 REF
SEATING
PLANE
PIN 1
INDICATOR
0.20 MIN
08-16-2010-B
7.00
BSC SQ
ORDERING GUIDE
Model1
ADF7020BCPZ
ADF7020BCPZ-RL
EVAL-ADF70xxMBZ
EVAL-ADF70xxMBZ2
EVAL-ADF7020DBZ1
EVAL-ADF7020DBZ2
EVAL-ADF7020DBZ3
1
2
Temperature Range
40C to +85C
40C to +85C
Package Description
48-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
48-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
Control Mother Board
Evaluation Platform
902 MHz to 928 MHz Daughter Board
860 MHz to 870 MHz Daughter Board
430 MHz to 445 MHz Daughter Board
Rev. D | Page 47 of 48
Package Option2
CP-48-5
CP-48-5
ADF7020
Data Sheet
NOTES
Rev. D | Page 48 of 48