Modeling of Cascade Modulated Power Amplifiers

Daniel Sira and Torben Larsen

9220 Aalborg, Denmark

Department of Electronic Systems, Aalborg University,

E-mail:

ds.tl@es.aau.dk

Voo

Abstract-Two models of the cascode modulated polar power

amplifier

(PA)

are presented. The cascode modulated

PA,

that

operates as a switch mode amplifier with class-E like output

network,

has a highly nonlinear

transfer characteristic. The

RFC

proposed empirical model is based on modeling of the peak drain

current through the cascode connected transistors.

simplified

100
Co
Lo
iout
Vd-nnnn--r

analytical model, that uses mathematical expressions to describe

the nonlinear transfer characteristic of the cascode modulated

PA,

is proposed. The behavior of the proposed baseband models

is compared with the RF domain simulations in a O.13/tm CMOS

process.

Vcasc

o-i

Vrf,in

o-f

I. INTRODUCTION
The demand for high efficiency and high linearity has driven
the power amplifier (PA) research into continuously creating

new PA topologies. Class-E PAs are capable of achieving

high efficiency but they are highly nonlinear. The switching
PAs can be linearized using a polar modulation scheme
The cascode modulation concept published in

requires further linearization to meet the stringent linearity

3G and 4G wireless standards. It is

shown in this paper that the nonlinear transfer characteristic

of the cascode modulated PA can be modeled by a baseband
Various approaches to PA modeling exist. Some models
provide a mathematical description and design equations for

[3]. Other models incorporate various non

idealities (e.g. device parasitics) and investigate their effect on

the PA performance

A.

Cascade modulated

[4]. Behavioral models represent another

large model family that includes for example polynomial,

Volterra and neural networks based models

[5].

PA

The schematic of a cascode modulated PA is shown in

Fig. l. The main feature of the cascode modulated class-E
PA is the ability to control the output power by varying the
voltage

transistor level model.

a particular PA

Cascode modulated RF power amplifier schematic.

[2] represents

one specific type of a polar PA. The cascode modulated PA

requirements of modern

F ig. 1.

[1].

Vcasc.

The cascode voltage

Vcasc

to control the average output power level

can be employed

[6] or it can be

used to apply varying envelope signal in the case of a polar

transmitter
PA in Fig.

[2]. The output network of the cascode modulated

1 is designed to operate in a class-E like mode. The

constant amplitude phase modulated signal is applied to the

switch-transistor

M1sw. The varying envelope signal is applied

M1casc.

to gate of the cascode device

In this paper two models, the empirical and analytical

The main advantage of the cascode modulation technique

model, of the cascode modulated PA are proposed. The

is the wide output power dynamic range and good reliability

proposed models track the AM-AM PA characteristic of the

[2]. The major drawback is high AM-AM nonlinearity.

cascode modulated PA. It is shown that by using a baseband

For the modeling purpose, the PA does not contain an

circuit, that is built on a replica circuit of the RF PA, it

impedance transformation network. The PA is loaded by its

3.74 n. It is assumed that the

VrE in has 50 % duty
,

is possible to reproduce the AM-AM characteristic of the

optimum load resistance RL of

RF PA. The empirical model is a baseband transistor level

phase modulated RF (sine wave) signal

model of the cascode modulated PA. The analytical model

cycle and its amplitude is

provides a mathematical description of the nonlinear transfer

characteristic of the cascode modulated PA.
II. EMPIRICAL MODEL OF A CASCODE MODULATE D PA
The concept of a cascode modulated PA was introduced in

B,

1.2 V.

Empirical model
The proposed empirical model represents a baseband model

(that tracks the AM-AM PA characteristic) of the cascode

modulated PA. The schematic of the empirical model is shown

[6]. The cascode modulation approach is an alternative tech

in Fig.

nique of amplifying polar modulated signals to a traditional

circuit, which produces a current that is proportional to the

supply modulation scheme

[1].

978-1-4577-0516-8/11/$26.00 2011

2. The goal of the modeling is to build an equivalent

PA's output RF current. In the analysis of the relation between

IEEE

Rs
I ref

01

0.3

vease

vcase

0----1

0----1

"
o

0.2
0.1 .
o L-
o
0.2

__L-__-L__-L__i-

__

(a)

(b)

Fig. 2. Empirical baseband model of the cascode modulated PA with the

DC bias current source Iref (a) and using the DC voltage source VEQ (b).
the PA output current

iout

and cascode voltage

Vcasc,

Vcasc.

Id , peak

where

lout

Ioo

lout

lout

[1

Ioo

( )]
[1
sm t.p
-

_"0

0.3

t.p

(iout

o L-
o
0.2

has to be chosen exactly as -32.48 for optimum class-E

where

Id,oc

and

...:.. Id,peak ...:.. Id,oc

Id,fund

Id,fund

are the DC and fundamental drain

(1)

0.4

0.6

0.8

Vcasc IV]

1.2

1.4

1.6

Fig. 4. Simulated peak drain currents of the cascode modulated

the empirical model circuit versus Vcasc voltage.

1.8

RF PA

and

(2)

1.537

current components respectively. Equations

__L-__-L__-L__i-

__

is the initial

performance [7]) and the RF output current can be written as

1.537

1.8

0.4 .

phase shift constant. This equation can be further simplified

1.6

0.1

is the amplitude of the RF output current

Iout

1.4

0.2

(1)

sin(t.p)]

contains only the fundamental component) and

(t.p

Vcasc IV]

1.2

0.5 .

is OFF and the output power is independent of the cascode

The peak RF current through the switch can be expressed

0.6

Mlsw

as a function of the RF output current according to [7] as

0.8

0.7 r-;========:;r-=-=::::....,
::;;
-- ld,r (Empirical model)

ON period of the RF cycle is considered. This is based on the

voltage

0.6

Fig. 3.
PA output current calculated by (2) and the actual simulated
fundamental output current versus Vcasc voltage.

only the

assumption that in the OFF period the switch transistor

0.4

and (2) are

baseband model shown in Fig. 2(a), that is based on the

replica circuit

(M2sw

M2easc)

and

of the cascode connected

derived using a simplified ideal class-E amplifier with an ideal

RF PA transistors, meets this criteria. The purpose of

RF switch. The peak drain current

smoothen the transition of the cascode transistor drain current

cascode voltage

Vcasc

on the mean value of the

From

(1)

Id,peak

depends on the DC

or, in the polar applications, it depends

Vcasc

is to

from the saturation to the linear region. The value of the

Rs

resistor is empirically obtained as

voltage.

it is evident that the relation between the output

Rs

current and peak drain current is linear. Therefore, in order to

model the nonlinear behavior of the cascode modulated PA the
relation between the peak drain current and

Rs

Vcasc

voltage is

of interest. The fundamental output current calculated from

the peak drain current using (2) is plotted in Fig.

where

the cascode modulated PA to demonstrate good match. The

Rcascode

The next step is to synthesize a circuit that exhibits the

transfer characteristic shown in Fig. 4. The proposed empirical

Rcascode

(3)

is the resistance of the cascode circuit at

0.370,

Rs

7 . 0 and

Iref

0.75A.

In order to model the conditions the cascode transistors

experience during the RF simulation, the drain voltage
has to be limited to

simulated curve represents the PA output current obtained from

a harmonic balance simulation of the PA circuit.

20 .

the saturation point of the drain. In the simulated circuit

and

compared with the simulated fundamental output current of

Rcascode

1.8 V.

The circuit behavior can be described as follows. If

Vd,r

Vcasc

is

zero there is no current flowing through the cascode circuit.

Vd,r voltage is 1.8 V; one part of

Rs and the second part returns back

Iref

The

the

to

to the supply terminal

current flows

through the diode D1. If the

Vcase

voltage is higher than the

Vee

Vee

threshold voltage of M2ease then the cascode circuit starts

to draw current. The amount of drawn current is directly
controlled by the

Vcasc

voltage. The cascode transistor M2ease

is in saturation and its drain current increases with

Vcasc.

current flows to

Rs.

The ratio of

Rs

to

Rcascode

Iref

Vcaseo-l

controls the

Rds
Id

slope and maximum drain current through transistor M2ease as

it enters the linear region.

Vg

The comparison of peak drain currents of the replica circuit

and cascode modulated PA versus
Fig.

Vcasc

voltage is shown in

The empirical model provides good match with the RF

4.

Vd

Vd

cascode circuit resistance decreases. The cascode current will

not saturate hard and suddenly because a part of the

RD

RD

The

simulated curves. There is a small discrepancy in the region

."""

where the cascode transistor operates in saturation.

Id
Vg

."""

Thevenin theorem into a form that is more suitable for

simplified calculations and intuitive analysis (see Fig. 2(b)).

(b)

(a)

The DC model from Fig. 2(a) can be re-arranged using

Fig. 5.
Cascode amplifier schematic used with the analytical model in
saturation region (a) and in linear region (b).

III. ANALYTICAL MODEL

A simplified analytical model of the cascode CirCUIt IS

proposed in this section. The main goal is to obtain an

analytical expression of the drain current

Vcasc.

Id

using an empirical relation [9]

as a function of

(7)

It is assumed that the switch transistor operates as an

ideal switch with the ON-resistance

Rsw

(Fig. 5).

RD

and

Vee

represent generic load resistance and supply voltage seen by

The cascode transistor Mease operates in two states. For low

f..lo

where the
and

Eeff

the cascode circuit respectively.

Vcasc

and bulk voltages. The effective mobility can be expressed

VT

is the cascode

transistor threshold voltage. The equivalent circuits for the

saturation and linear regions are shown in Fig. 5(a) and 5(b)

0.9 MYfcm

experienced by the carriers in the inversion layer is

Eeff (4)

Eo

approximated according to [9] as

voltages Mease is in saturation and if

it enters and remains in the linear region.

is a technological constant,

1.85 for electrons [9]. The average electrical field

where

Tox

Vgs + VT
6Tox

Vcasc + VT
6Tox

is the oxide thickness. For simplicity,

is assumed in further calculations of

By substituting of

(6)

Eeff.

(8)

Vgs

(8) into (5) and solving for

Id

Id

model of the MOSFET transistor.

Leff + ,- y'Leff(2, + Leff)

CoxR;w Wf..leff

(9)

where

A. Saturation region

The drain current of the cascode device in saturation is [8]

where

f..leff

and

-f..leffCOX- (Vgs - VT)

2
Leff

Cox

are the effective mobility of the carriers

voltage

V gs

Leff is the effective channel length.

(10)

V:ff

(5)

and the gate oxide capacity, respectively. W is the channel

width and

the

following result is obtained

respectively. The following analysis is based on a simplified

Id

Vcasc

The gate-source

Vcasc - VT.

Equation (9) represents the analytical form of the drain

current as a function of

Vcasc

voltage in the saturation region.

B. Linear region

In the linear region the cascode transistor can be substituted

of the Mease transistor can be written as

(6)
The surface mobility of the carriers in the transistor channel
depends on various process parameters and also on the gate

by the equivalent drain-source resistor

Rds

(Fig. 5(b)).

The drain current is given by the Sah equation as [8]

Id

f..leffCox

::ff [(VgS - VT)Vds - Vfs ]

(11)

0.7

30

0.6 .

20

0.5 .

-"

0.4 .

co

0.3

Q.

...
:::l
0

10
0
-10

0.2

-20

0.1 .

-30

0
0.4

0.6

0.8

1.2

Vcasc [V]

1.4

1.6

1.8

Fig. 6. Simulated (empirical model) and calculated (analytical model) drain

currents of cascode connected transistors versus Vcasc voltage.

(12)

The coefficients

and

(3

--

0.6

0.8

RF simulation

1.2

Vcasc [V]

1.4

1.6

1.8

Fig. 7.
Fundamental average output power delivered to RL load versus
Vcasc voltage. Cascode PA models and RF simulation (Harmonic balance).

V. CONCLUSION

The drain-source voltage can be found using

Substituting of (12) into (11) and solving for

-40
0.4

Id

yields (13).

are defined as

In this article two modeling approaches of the cascode

modulated PA are presented. The baseband empirical and
analytical models, that track the AM-AM characteristic of the
cascode modulated PA, have been proposed. A good fit of
both models with the RF domain based simulations has been

demonstrated. The empirical model can be easily implemented

(3

(14)

.
f..LeffCOX L
eff

RF stage e.g. process, voltage and temperature variation. It

Equation (13) represents the analytical form of the drain

current as a function of

Vcasc

voltage in the linear region .

Combining

(9)

The verification of the analytical model

is based on the comparison with the empirical model assuming

RD

Rs.

The supply voltage used in the analytical model

is given as Vee

VEQ

IrefRs

5.3 V. The values of

the technological constants are taken from the 0.13 f..Lm UMC
CMOS process.
The comparison of the calculated and simulated drain cur
rents through the cascode connected transistors is depicted in

Fig. 6. The discrepancy is largest in the transition area where

the cascode transistor operating point changes from the linear

region into saturation.

The performance of both the empirical and analytical mod
els can be evaluated from Fig. 7 where the output power of the

cascode PA is plotted as a dependence on the

Vcasc

voltage.

In the case of the empirical model the cascode transistor

drain current is simulated first and then the output power is
calculated using (2). In the case of the analytical model the
drain current is calculated using

(9)

and (13) and the output

power is calculated using (2). It can be seen that both models

shows a good fit to the RF circuit level simulation excluding
the sub-threshold region where

Vcasc

ACKN OWLEDGMEN T

Technology Foundation through the 4GMCT project.

and (13) the drain current can be calculated

Vcasc.

can be utilized to monitor the PA output power.

This work was supported by the Danish National Advanced

IV. MODEL VERIFIC ATION

as a function of

in CMOS technology. This model is potentially suitable for

analog predistortion or compensation of imperfections in the

is below 0.55 V.

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