MITS 5113

COMPUTER ARCHITECTURE AND COMPILER

DR. ASLINDA HASSAN SEM 2-2015/2016 FTMK, UTEM

ASSIGNMENT 2

INSTRUCTIONS
(i). This task is an individual work
(ii). Students are required to submit the answer (either handwritten or typed)
(iii). Students are required to submit the assignment on 1st of April 2016, before 5
pm.

Question 1
A computer system has a cache with the size of 16 blocks. Consider the following repeating sequence of addresses in hexadecimal.
40 44 48 4C 70 74 78 7C 80 84 88 8C 90 94 98 9C 0 4 8 C 10 14 18 1C 20
If Least Recently Used (LRU) algorithm is used as th replacement algorithm, nd the
number of misses for each cache organization given the above sequence of addresses:
1. direct mapped organization with block size = 1 word
2. fully associative organization with block size = 1 words
3. two-way set associative organization with block size = 2 words
4. direct mapped cache organization with block size = 2 words

Assignment 2

MITS 5113

Question 2
Consider the following parameters for a virtual memory system:

Virtual Memory Address Space

Phyical DRAM installed

Virtual Page Size

2 GB

4 KB

50

2 bytes

1. Calculate the number of bits for the physical address

2. Find the maximum number of virtual pages in the system
3. Find the number of physical pages for the system
4. Calculate the number of bits for the virtual and physical page numbers
5. Find the number of page table entries in the system page table.

Question 3
Given a 32-bit operating system, 4-KB pages and 1 GB of RAM:
1. Find the size of the virtual address and the physical address.
2. Given the initial TLB for the above virtual memory system, nd the virtual address
for the following address:
0x7A28, 0x3DAD, 0x3A98
Virtual Page

Frame Page Valid Bit

11

10

11

12

Dr. Aslinda Hassan

Assignment 2

MITS 5113

Question 4
Consider the following code fragment:
1

Loop :

ld R1 , 0( R2 )

# load R1 from address 0+ R2

daddi R1 , R1 , 1

# R1 = R1 +1

sd R1 , 0( R2 )

# store R1 at address 0+ R2

daddi R2 , R2 , 4

# R2 = R2 +4

dsub R4 , R3 , R2

# R4 = R3 - R2

bnez R4 , Loop

# branch to Loop if R4 !=0

1. Data hazards are caused by data dependences in the code. List all of the data
dependences in the code above. Record the register, source instruction, and destination instruction; for example, there is a data dependency for register R1 from
the LD to the DADDI.
2. Show the timing of this instruction sequence for the 5-stage RISC pipeline without
any forwarding or bypassing hardware. However, it is assumed that a register read
and a write in the same clock cycle "forwards" through the register le, as shown
in gure from Lecture-4 notes (Slide 17). If all memory references take 1 cycle, nd
the number of clock cycles needed for this loop to be executed
Use a pipeline timing chart as shown in Slide 7 of Lecture 4. Assume that the
branch is handled by ushing the pipeline. (Note: Remember to include any stall
that occurs during the execution of the above code fragment in the pipeline timing
chart)
3. Show the timing of this instruction sequence for the 5-stage RISC pipeline with full
forwarding and bypassing hardware. If all memory references take 1 cycle, nd
the number of clock cycles needed for this loop to be executed. Assume that the
branch is handled by ushing the pipeline.

Dr. Aslinda Hassan