Beruflich Dokumente
Kultur Dokumente
* MPU is designed with ALU, control unit and some count of processing
registers and these registers are used to store the data temporarily during
programme execution.
* Generally different MPUs available are specified like 8 bit, 16 bit, 32 bit
and so on.
* Bit capacity of MPU is defined as the no of bits it can process at a time in
parallel i.e. an 8 bit MPU can perform all 8 bit operations at a time.
* In general, the internal architecture of the microprocessor depends on
the bit capacity of the microprocessor.
* Thu system bus of MPU consist of 3 types of buses known as address
bus, data bus and control bus
* Address signals arc generated by MPU and sent to identify the address of
the memory through address bus and it is unidirectional bus.
* Data bus is used to transfer the data in between memory and MPU.
* Control signals arc generated by MPU and these signals are transferred
in between memory and MPU and used to provide timing for various
operations.
* Control signals are used to perform the required operations.
* MPU can primarily perform 4 operations Memory Read, Memory write, I/0
Read and I/O write and for each operation it generates the appropriate
control signals.
8085 Microprocessor
* It is a 40 pin IC with operating voltage 5 volts
* It is designed with 2 MB and 3.07 MHz frequencies
* Max clock frequency of 8085 is 3.07 MHz (3MHZ)
* Crystal frequency is double to its clock
* 8085 MPU is designed with on chip clock generator i.e. no external
oscillator is required
* 8085 MPU has 74 basic instructions and 246 opcodes
* 8085 supports 5 no. of hardware interrupts and 8 no of software
interrupts
* Hardware interrupts are Trap RST 7.5, RST 6.5, RST 5.5 and INTR
* Trap has the highest priority among all
*But trap has lower priority than DMAC during DMA
* Trap is also known as RST 4.5
* INTR has the lowest priority
* No. of software interrupts for 8085 are 8, and range from RST '0 to RST
7
* Opcode length varies from 1 byte to 3 byte
* Instructions, having the 16 bit address in the given instruction known as
3 byte instructions
Ex: Call 2500H
* Instructions, having the 8 bit data or port address in given instruction is
2 byte instruction
Ex: MVI A, 35H
* Instruction with neither 16 bit address nor 8 bit data is known as 1 byte
instruction
Ex: MOV A, B
* In 8085 MPU, 5 No. of flags are available and these flags are also known
as status flags, known as carry (cy) ; Auxiliary carry (Ac) ; Sign (s) ; parity
(P) and zero (z)
* 8085 MPU has 2 no of 16 bits registers known as program counter (PC)
and stack pointer (SP)
* PC always holds the address of the next instruction to be executed
* SP always holds the address of the top of the stack
* 8085 MPU has 8 bit accumulator and 8 bit flag register, and this
combination is known as
PSW (Program status word)
* 8085 MPU is designed with 6 no. Of general purpose registers along A
and F, these registers are known as B, C; DE and H, L
* These 8 bit general purpose register can be used as 3 no. of 16 bit
Register Pairs when required like BC, DE and HL pairs,
e) PCHL
f) SPHL
g) PUSH Rp
h) All Restart instructions
Note: POP and RET (unconditional) require only four T states for fetching
* During the execution of RST instructions, P.C. is modified with the
address which is available in page and allotted for separate address for
each RST type instruction.
* Different types of machine cycles of 8085 are opcode fetch, memory
Read, Memory write; I/0 Read, I/O write, Interrupt Acknowledgement, and
Bus idle cycles
* The first machine cycle of every instruction cycle is always Fetching
* ALE signal is generated during T1 state of each machine cycle
* ALE signal is generated during `T1' state of each Machine cycle
* Machine cycle format is given below
* In the above diagram M stands for machine cycle and 'T' stands for 'T'
states and M is for fetching with the maximum length of-'6' T states
Mapping: Assigning address to I / O devices or memory locations is called
mapping
Memory mapping: Assigning the address of memory locations is called
memory mapping
* Memory mapping can be changed by changing the hardware logic used
for chip selection
* To inter face a memory the 8085, necessary lower order address lines of
8085 address bus are
connected to the address lines of the memory chip and higher order
address lines are decoded to
generated CS (chip select) signal to enable the chip
* Absolute decoding: In this decoding all the address lines which are not
used for memory chip to identify a memory Register must be decoded
thus chip select can be asserted by only one address
* Linear Decoding: In this technic; one address line is used for chip select
(CS), and other are left dont cares; this technic reduces hardware but
generates multiple addresses resulting in fold back memory space.
I/O devices can be connected to microprocessor in two different
techniques:
1) Memory mapped I/O techniques
2) I/O mapped I/O technic
Memory mapped I/O technique:
* In this, the I/O devices are also treated as memory locations under that
assumption they will be given 16 bit address
* In this data bytes are transferred by using memory related data transfer
Instructions
Ex: LDA, STA, MOV A, M; MOV M,A
* In this the input device is connected (key board) instead of memory and
the input device will have the 16 bit address specified by LDA instruction
(When the device is monitor SI A instructions is used)
* In memory mapped I/O MEMR and MEMW control signals are used to
activate I/O devices
* In memory mapped I / O, the entire memory map shared by memory
locations and I/0 devices and
* One address can be used only once
* This technic is used in a system where the no. of I/O devices are more
* The max no. of I/O devices that can be connected to microprocessor in
this technic are 216 = 65536
I/O mapped I/O technique:
* In this; I/O devices are identified by the processor with separate 8 bit
port address
* This technic uses separate control signals (IOR and IOW) to activate I/O
devices and separate instructions (IN and OUT) to communicate with I/0
devices.
* In this, the data bytes are transferred using IN and OUT instructions
* Each IN and Out instructions followed by an 8 bit address of the device
(00H to FFH)
* In this only IN and Out instructions are used.
* In this, I/O mapping is independent of memory mapping and same
address can be used to identify input device and output device
* This technic is used in a system where the no. of I/O devices are less
* By using this method a maximum no. of 256 input devices and 256
output devices can be connected to the processor (total no. of devices to
be connected = 512)
INTERFACING
* It is the process of designing Hardware circuit and writing software
instructions to enable microprocessor to communicate with the peripheral
devices
* There are two basic types of interfacing devices are available
a) Non programmable interfacing devices
b) Programmable inter facing devices
Non programmable inter facing devices: Once the microprocessor system
is designed; it is not possible to program this type of devices.
Example a) 8212 Non programmable I/O port
b) 74 LS 245 bidirectional buffers
c) 74 LS 373 Trans parent Latches
Programmable interfacing devices:
These can be programmed by loading specific binary word known as
control word according to the internal logic.
Different Programmable devices
a) 8155: Programmable interfacing devices with 256 bytes RAM and 16 bit
timer / counter
* 8086 MPU can Handle the interrupt operation when there is a single I/O
device because it has only one INTR pin
* For connecting multiple I/O devices, an interfacing device is needed
whose function is to determine the priority to handle the multiple interrupt
operations
* This interfacing device is 8259
* One 8259 can handed 8 I/O devices
* For connecting more than 8 I/0 devices, more no. of 8259 s are required
and these are connected in cascading order
Description of 8259:
* IRR is an interrupt Request Register used to store the interrupt request
from the I/O devices connected to the IR input lines
* These IR input lines range from IR0 to IR7
* Priority resolver is a logic circuit used to determine the priority of the IR
input line
* ISR is an 8 bit register used to handle the IR levels having highest
priority i.e. it stores the IR level which is currently under the service
* Control unit controls the entire interrupt operation by providing INT and
INTA signals.
Data bus buffer: It's function is to transfer the data to or from the CPU
Read write logic: It controls the write or Read operation
Cascade buffer: It is used in multiple 8259 system and it's function is to
cascade multiple 8259's
* To perform the operation of 8259 words, it is needed to fill the two types
of command they are
a) initialization command words (ICWS)
b) Operation command words (OCWS)
* ICWS are used to initialize the 8259
* OCWS are used to perform the required operation
Transmitter Buffer: It's functions is to transmit the data to the I/O device
through the Tx0 pin & this includes data bus buffer Register and
Transmitter shift Register
Transmitter control: Its function is to control the data transmitter to the
I/O devices using different control signals like TXRDY TXE & TXC etc.
Receiver buffer: This unit is used to receive data from I/O devices using
different control signals like RXRDY, RYE and RXC etc.
* Data bus buffer function is to transfer the data to/from the CPU though
the data lines Do to D7
* Read/ Write control unit function is to control the Read/ Write operation
during Read/write operation during the serial communications
* MODEM control unit is to control the serial communication by means of
different hand shaking signals like DTR, DSR, RTS and CTS
DTR: Data terminal Ready
DSR: Data set Ready
RTS: Request to send
CTS: Clean to send
Different Registers in 8251:
* It had 4 no. Of registers and each capacity 8 bit
* Different registers are mode register, command register, status register
and synchronous register
* Synchronous register is used to hold the sync character and remaining 3
registers are used for programming 8251
Mode Register Format:
* B1 B0 combination is used to specify the baud rate as shown below
* L1 L0 used to specify the character length as shown below
L 1 L0
Character length
0 -
5 bit
1 -
6 bit
0 -
7 bit
1 -
8 bit
No of stop bits
0 -
invalid
1 -
1 bit
0 -
11/2 bit
1 -
2 bit
* It has 3 ports namely port A (PA), port B(PB) and port C (PC)
* These ports are used mainly for data transfer between I/O devices and
CPU
* In some cases PC is used to provide the control signals so, this port is
called as control port
* Again these 3 ports are divided in to 2 Groups namely Group A (GR-A)
and Group B (GR- B)
* Group A known as port A and PC upper (PC7 = PC4) and Group B is known
as port B and PC lower (PC3 PC0)
* These PA and PB and Pc are 8 bit ports and used for I/O operation
* Group A control unit is used to control the operation of Gr - A i.e. port A
and PCH
* Group B control unit is used to control the operation of port B and PCL
* Data bus buffer unit is used to transfer the data to / from the CPU
* Read / Write control logic unit is used to control the entire I/O operation
between the CPU and I/0 devices also Read/write operations.
Operational modes of 8255:
* It can be operated in 2 no. Of modes known as BSR(Bit set and Rest
mode) and I/O mode (input and output mode)
* However, the operation mode of 8255 is determined by control register,
which is an 8 bit register
* Control Register can be programmed as per the requirement
* When MSB in the control Register is 0' it indicates, 8255 is operating in
BSR mode ; then the data in the control Register ranges from 00H to 7FH
* When MSB in the control Register is '1 then it indicates 8255 is
operating in I/O mode
BSR mode operation
* This mode is used to program only Pc
* It is used to set/Reset the required bit port c
Control Register for mat for BSR mode
0 0 0
PCo
0 0 1
PC1
Mode 0 operation:
* In this all ports are I/O ports
* No hand shaking signals
* In this PA PB and PC can be operated independently
Mode 1 operation:
* In this only PA and PB are used as I/O ports
* PC is used for generating control signals
* In this PCH is used provides the control signals for PA and PCL is used for
providing the control signals for PB
Mode 2 operation:
* In this mode only PA is used for I/O operation hence it is bidirectional port
* PB cannot be operated in this mode
* In this PCH is used for providing control signals for port A
PROGRAMMABLE TIMER/COUNTER:
* It is used to generate accurate time delays
* 8253/8254 known as programmable timer/counter
* Each one contains 3 no of 16 bit counters
* Clock frequency range is 8 Hz to 10 MHZ for 8254
Description about 8254:
* It has an 8 bit data bus for interfacing with CPU data lines
* CS input which will be asserted by an address decoder when the device
is addressed
* It has 2 no. of address inputs known as A and Ao allow to address one of
the 3 counters or the control \vord Register in the device as follows
A1 Ao
Selects
Counter 0
Counter 1
Counter 2
C. W. R
* Each counter has 3 types of signals known as CLK GATE and OUT
* GATE input on each counter allows you to start or stop the counter with
an external Hardware signals
* The required clock signals is applied to the clock input for the specified
counter
* The output signal from each counter appears on its OUT pin
* All counters are down courtiers, i.e. the number in the counter will be
decremented by each clock pulse
* RD and WR used for perform the required Read or write operation
* 8254 has an 8 bit control Register (CWR) and it is used to program the
counter as per our requirement
* CWR accepts only writing operation and it is not possible to read the
CWR
* Each counter in 8253/54 works independently
* Each of three counters of 8253/54 can be operated in one of the
following six modes of operation
a) Mode 0 (Interrupt on terminal count) a ;
b) Mode 1 (Programmable mono shot)
c) Mode 2 (Rate Generator)
d) Mode 3 (square wave Generator)
D6: Timer Latched high when TC is reached, low when status reg is read or
reset is done
CS: Chip select that enables programming, reading the keyboard, etc.
DB7-DBO: Consists of bidirectional pins that connect to data bus on micro
IRQ: Interrupt request, becomes I when a key is pressed, data is available.
OUT A3-AO/B3-BO: Outputs that sends data to the most significant/least
significant nibble of display.
RD (WR): Connects to micro's TORD or RD signal, reads data status
registers.
RESET: Connects to system RESET.
RL7-RLO: Return lines are inputs used to sense key depression in the
keyboard matrix.
Shift: Shift connects to Shift key on keyboard.
SL3-SLO: Scan line outputs scan both the keyboard and displays.
First three bits given below select one of 8 control registers (opcode).
* 000DDMMM
Mode set: Opcode 000.
DD sets displays mode.
MMM sets keyboard mode.
DD field selects either:
(i) 8 or 16 display position.
ii) Whether new data are entered to the rightmost or leftmost display
position
Encoded: SL outputs are active-high, follow binary bit pattern 0-7 or 0-15.
Decoded: SL outputs are active-low (only one low at any time). Pattern
output: 1110, 1101, 1011, 0111.
Strobed: An active high pulse on the CN/ST input pin strobes data from
the RL pins into an internal FIFO for reading by micro later.
2-key lockout/N- key rollover: Prevents 2 keys from being recognized if
pressed simultaneously/Accepts all keys pressed from first to Last.
ADC 0808
* 8 bit ADC
* Interfaces micro-controller ports or processor DO-D7, RD WR ALE (built
in latch) for channel select through AD2- AD1-ADO inputs
* Start of conversion (SOC ) using WR
* SOC input very short duration (ns) pulse using a NOT-NAND combination
* Output enable for converted bits on DO-D7 using RD
* EOC output for end of conversion to facilitate interrupt (INTR) driven IO
* Separate analog and digital grounds to separate digital transitions noise
by direct connection of A-GND to supply GND
* Clock frequency input
DAC 0800
* To convert digital values to analog voltages
* Performs inverse operation of the Analog to Digital Converter (ADC)
The DAC0800 series are monolithic 8-bit high-speed current-output digitalto-analog converters (DAC) featuring typical settling times of 100 ns.
When used as a multiplying DAC, monotonic performance over a 40 to 1
reference current range is possible.
* In 8086 MPU, the maximum length of opcode is 6 byte so, queue register
is maintained at 6 bytes
* Fetching the next instruction while the current instruction being
executed is known as pipelining and it is used to increase the execution
speed
* In 8086, the segment Registers are used to store the higher order 16 bit
address in given 20 bit address
* 20 bit address is also known as physical address
* lower 16 bit address is known as offset address
* The Registers used for storing the offset address is known as offset
Registers
* Different offset Registers are SI, DI, IP, BP, SP and BX
* Segment Registers are also known as base Registers
* 1MB memory that can be accessed by 8086 MPU is divided into 16
logical segments with each segment capacity of 64k i.e. only 16 address
lines are sufficient to access one logical segment e
* The segments can be located anywhere of the memory
* What ever the no. of segments the 8086 MPU can operate only on 4
segments at a time ; these segment are CS, DS, SS and ES
Code segment (CS): This part of the memory is used for storing the
program (opcode)
Data segment: This Part of the memory is used for storing the operand
(data)
Extra segment: This part of the memory is used during the execution of
string instructions.
Stack segment: This part of the memory is used for storing the address
and data while a sub program is executing
Instruction pointer (IP): It used to store the address of the opcode,
when the program address is 20 bit CS, IP Register Pair is used for storing
the same
Control system: It is used to generate necessary timing and control
signals for various internal operations.