Jamil Francis B.

Cuadra

Fig 1.1 DRC Verification

DRC verification shows if there are rules not followed in a certain
technology. Mostly, DRC shows distances and areas that are not within the rules.

Fig 1.2 LVS Verification

LVS Verification shows that if the layouts and the schematics devices and nets
match with each other. We can see here that the comparison resulted to clean. It
means that the nets and devices present in the schematic are also present in the
layout

Jamil Francis B.Cuadra

Fig 1.3 Schematic CMOS inverter

When the input signal is high or 1.8v, PMOS device would turn off and the
NMOS would turn on. Thus, output voltage would result to a low signal or 0.
When the input signal is low or at 0v, the PMOS would turn on and NMOS to turn
off resulting to a flow of current from vdd to output, resulting to a high signal or
1.8v at the output.

Fig 1.4 Test Bench Schematic

Test bench schematic shows the basic connection of the circuit. With the
inverter symbol which contains our schematic CMOS inverter, it has the pulse

Jamil Francis B.Cuadra

voltage at the input and a capacitive output. The inverter has a supply voltage of
1.8v dc.

Fig 1.5 Inverter Layout

Minimal rules should be followed in making the layout of an inverter. The
multiplier indicates how many poly should be used which is in this case the

Jamil Francis B.Cuadra

multiplier is 2. Also, when you make a guard ring, you must connect them to
sources like vdd and ground. It is better to set metals in what orientation you
must use them. In this case, metal 1 is used in vertical connection while metal 2
is used in horizontal connections

Fig 1.6 Presim code

Output waveforms

T
T

S
S

Vi
n

F
F

F
F
T
T
S
S

Fig 1.7 Post simulation rise time of different corners

Jamil Francis B.Cuadra

T
T
S
S
F
F

Fig 1.8 Post simulation fall time of different corners

F
F
T
T

S
S

Fig 1.9 Pre Sim rise time of different corners

Jamil Francis B.Cuadra

T
T
S
S
F
F

Fig 1.10 Pre sim fall time of different corners

Rise Time
Corners
Fall time
Corners

TT
SS
FF

Pre sim
6.46n
6.38n
6.15n

TT
4.21n
SS
4.94n
FF
4.13n
Table 1.1 Summary of rise time and fall time

Post sim
5.91n
6.14n
6.17n
4.1n
4.86n
4.14n

Conclusion:
Inverter circuit consists of a PMOS and NMOS cascaded where the gates
and drains of each MOS are connected. Output is produced by turning the MOS
one at a time. Making a layout of the schematic has a very big factor in the
performance of the circuit. Minimal rule should be observed in order for a better
performance of the post simulation than in that of pre simulation.
As we can see from the graphs, we can see that the post simulation is
better than the pre simulation at the corners of TT and SS, however, at FF corner,
the pre simulation is slightly better because of the fact that the rise time of post
simulation is slightly greater than the pre simulation with a difference of 0.02n
and at rise time the post simulation is greater than the pre simulation by 0.01n
but this difference is negligible because of the very small difference. Moreover, In
making a layout, it must be noted that overlapping different metals needs a
contact.