Beruflich Dokumente
Kultur Dokumente
Page 15
UNIT 2
NETWORKS
2013
2.1
2.2
ONE MARK
2.6
(A) k2
(B) k
(C) 1/k
(D)
V2 ^s h
of the circuit shown below is
V1 ^s h
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(A) 0.5s 1
s1
s
2
(C)
s1
2.3
(B) 3s 6
s2
s
(D) 1
s2
2.4
(C) 800+90c
TWO MARKS
(A) 100+90c
2.5
(B) 800+0c
(D) 100+60c
2.7
2.8
2.9
GATE Electronics and Communication Topicwise Solved Paper by RK Kanodia & Ashish Murolia
Page 16
2012
2.10
(A) zero
(A) 0.8 8
(C) 2 8
ONE MARK
2.14
If VA VB 6 V then VC VD is
(A) 5 V
(C) 3 V
(B) 1.4 8
(D) 2.8 8
(B) 2 V
(D) 6 V
2.12
2.15
ONE MARK
2012
2.13
(B) 1 A
1j
2.17
(D) 0 A
TWO MARKS
Assuming both the voltage sources are in phase, the value of R for
which maximum power is transferred from circuit A to circuit B is
(A) 6.4 j 4.8
(C) 10 j 0
2.18
In the circuit shown below, the value of RL such that the power
GATE Electronics and Communication Topicwise Solved Paper by RK Kanodia & Ashish Murolia
Page 17
transferred to RL is maximum is
2010
(A) 5 8
(C) 15 8
2.19
2.23
(B) 10 8
(D) 20 8
4
(A) >
2
(A) (Vp /3) cos (t/RC )
(C) (Vp /2) cos (t/RC )
2011
2.20
TWO MARKS
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2.24
(B) 2.0+0c A
(D) 3.2+0c A
4
(D) >
2
2
S
4H
2010
2.25
2.22
0.5
S
1H
(A) 1/90
(C) 1/99
0. 5
S
1H
1
(B) >
0. 5
(A) 1.4+0c A
(C) 2.8+0c A
2
S
4H
1
(C) >
0. 5
2.21
ONE MARK
TWO MARKS
In the circuit shown, the switch S is open for a long time and is
closed at t 0 . The current i (t) for t $ 0 is
(B) 1/90
(D) 1/11
In the circuit shown below, the initial charge on the capacitor is 2.5
mC, with the voltage polarity as indicated. The switch is closed at
time t 0 . The current i (t) at a time t after the switch is closed is
(A) j1 A
(B) j1 A
GATE Electronics and Communication Topicwise Solved Paper by RK Kanodia & Ashish Murolia
(C) 0 A
2.27
Page 18
(D) 20 A
(A) 220 J
(B) 12 kJ
(C) 13.2 kJ
(D) 14.4 J
GATE 2009
(A) 0 W
(B) 5 W
(C) 10 W
(D) 100 W
GATE 2009
2.28
2.31
ONE MARK
(A) 8 VAR
(C) 28 VAR
2.32
2.33
(D) 2R
(B) 16 VAR
(D) 32 VAR
The switch in the circuit shown was on position a for a long time,
and is move to position b at time t 0 . The current i (t) for t 0
is given by
2.29
TWO MARK
GATE Electronics and Communication Topicwise Solved Paper by RK Kanodia & Ashish Murolia
2.34
(A) 2.4 8
(B) 8 8
3
(C) 4 8
(D) 6 8
2.35
Page 19
ONE MARK
In the following graph, the number of trees (P) and the number of
cut-set (Q) are
(B) P 2, Q 6
(D) P 4, Q 10
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(A) 0
(R Rs) Is
(C)
L
(B) Rs Is
L
(D) 3
GATE 2008
2.37
TWO MARKS
Assume that the capacitor has zero initial charge. Given that u (t)
is a unit step function , the voltage vc (t) across the capacitor is
given by
(A)
/ ( 1) n tu (t nT)
n1
2.38
(B) 1 s 1
s
2
(C) 2 s 1
(D) s2 s 1
s
s 2s 1
The driving point impedance of the following network is given by
Z (s) 2 0.2s
s 0.1s 2
n1
n1
GATE Electronics and Communication Topicwise Solved Paper by RK Kanodia & Ashish Murolia
2.40
1
(A) 2 ^e t e t h
(B) 2 te 2 t
3
3
1
1
(C) 2 e 2 t cos c 3 t m
(D) 2 e 2 t sin c 3 t m
2
2
3
3
For t 0 , the voltage across the resistor is
1
2
2.41
Page 20
(A) 1 _e
3
(B) e
(C)
3t
2
3
2
e 2 t i
1
3
1 sin 3 t
c 2 mG
=cos c 2 t m
3
1
2 e 2 t sin 3 t
c 2 m
3
1 t
2
GATE 2007
2.46
1
(D) 2 e 2 t cos c 3 t m
2
3
TWO MARKS
Two series resonant filters are as shown in the figure. Let the 3-dB
bandwidth of Filter 1 be B1 and that of Filter 2 be B2 . the value
B1 is
B2
(A) 4
(C) 1/2
2.47
(B) 1
(D) 1/4
For the circuit shown in the figure, the Thevenin voltage and
resistance looking into X Y are
(A)
(C)
Under following conditions, the readings obtained are:
(1) S1 -open, S2 - closed A1 0,V1 4.5 V,V2 1.5 V, A2 1 A
(2) S1 -open, S2 - closed A1 4 A,V1 6 V,V2 6 V, A2 0
2.42
1.5
1.5G
4. 5
1. 5 G
1. 5
(B) =
1. 5
4.5
(D) =
1.5
(B) 4 V, 23 8
(D) 4 V, 2 8
3 1
(B) =
3 0.67 G
3
1
(D) =
3 0.67 G
GATE 2007
2.45
4. 5
4. 5 G
1.5
4.5G
2.44
V, 2 8
V, 23 8
2.43
2.48
4
3
4
3
2.49
In the ac network shown in the figure, the phasor voltage VAB (in
Volts) is
(B) 5+30c
(D) 17+30c
GATE Electronics and Communication Topicwise Solved Paper by RK Kanodia & Ashish Murolia
GATE 2006
2.50
Page 21
TWO MARKS
2.51
In the two port network shown in the figure below, Z12 and Z21 and
respectively
2.53
GATE 2005
2.56
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(A) 0.5 A
(C) 1.0 A
(B) 2.0 A
(D) 0.0 A
2.57
In the figure shown below, assume that all the capacitors are initially
uncharged. If vi (t) 10u (t) Volts, vo (t) is given by
-t/0.004
(A) 8e
Volts
(C) 8u (t) Volts
2.55
ONE MARK
The condition on R, L and C such that the step response y (t) in the
figure has no oscillations, is
L
C
(C) R $ 2
(D) R 1
LC
The ABCD parameters of an ideal n: 1 transformer shown in the
figure are
n 0
>0 x H
(A) R $ 1
2
2.54
(B) 8 (1 e
(D) 8 Volts
-t/0.004
) Volts
L
C
L
C
(C) n2
2.58
(B) 1
n
(D) 12
n
2.59
(B) R $
(D) 2Q # 10 4 Hz
GATE Electronics and Communication Topicwise Solved Paper by RK Kanodia & Ashish Murolia
Page 22
the figure, then the reading in the ideal voltmeter connected between
a and b is
2.60
(A) 1 W
(B) 10 W
(C) 0.25 W
(D) 0.5 W
GATE 2005
2.61
(A) 0.238 V
(C) 0.238 V
2.65
For the circuit shown in the figure, the instantaneous current i1 (t) is
0.1 0.1
(A) =
0.1 0.3G
30 20
(C) =
20 20G
2.66
(A) 10 3 90c A
2
(B) 10 3 90c A
2
(C) 5 60c A
(D) 5 60c A
(A) j29 8
(C) j19 8
For the circuit shown in the figure, Thevenins voltage and Thevenins
equivalent resistance at terminals a b is
(A) 5 V and 2 8
(C) 4 V and 2 8
2.64
(B) j9 8
(D) j39 8
GATE 2004
2.67
10 1
(B) =
1 0.05G
10 1
(D) =
1 0.05G
(A) 3 V
(C) 4 V
2.63
(D) 1 V
TWO MARKS
2.62
(B) 0.138 V
(B) 3 V
(D) 4 V
ONE MARK
Consider the network graph shown in the figure. Which one of the
following is NOT a tree of this graph ?
GATE Electronics and Communication Topicwise Solved Paper by RK Kanodia & Ashish Murolia
(A) a
(C) c
2.68
Page 23
(B) b
(D) d
GATE 2004
2.72
(A) L1 L2 M
(C) L1 L2 2M
2.69
(B) L1 L2 M
(D)L1 L2 2M
TWO MARKS
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(A)
(B)
(C)
(D)
2.70
For the circuit shown in the figure, the time constant RC 1 ms.
The input voltage is vi (t) 2 sin 103 t . The output voltage vo (t) is
equal to
1j
(A) =
1j
1j
(C) =
1j
2.73
1j
1 jG
1j
1 jG
1j 1j
(B) =
1 j 1 j G
1 j 1 j
(D) =
1 j 1 j G
s2
s2 s 1
(D) 2 1
s s1
Vo (s)
The transfer function H (s)
of an RLC circuit is given by
Vi (s)
s
s2 s 1
(C) 2 s 2
s s1
(A)
2.74
(B)
106
s 20s 106
The Quality factor (Q-factor) of this circuit is
(A) 25
(B) 50
H (s)
GATE Electronics and Communication Topicwise Solved Paper by RK Kanodia & Ashish Murolia
(C) 100
2.75
1
s 106 s 106
103
(C) 2
s 103 s 106
2.76
(D) 5000
(C) 100
For the circuit shown in the figure, the initial conditions are zero. Its
V (s)
is
transfer function H (s) c
Vi (s)
(A)
Page 24
2.80
The differential equation for the current i (t) in the circuit of the
figure is
2
(A) 2 d 2i 2 di i (t) sin t
dt
dt
2
d
i
di
(C) 2 2 2 i (t) cos t
dt
dt
106
s 103 s 106
106
(D) 2
s 106 s 106
(B)
(D) 200
2
(B) d 2i 2 di 2i (t) cos t
dt
dt
2
d
i
(D) 2 2 di 2i (t) sin t
dt
dt
GATE 2003
2.81
2.82
TWO MARKS
(A) 3
(C) 6
2.78
2.79
ONE MARK
(B) 4
(D) 7
2.83
2.84
At t 0+ , the current i1 is
(B) V
(A) V
R
2R
V
(C)
(D) zero
4R
I1 (s) and I2 (s) are the Laplace transforms of i1 (t) and i2 (t) respectively.
The equations for the loop currents I1 (s) and I2 (s) for the circuit
shown in the figure, after the switch is brought from position 1 to
position 2 at t 0 , are
V
R Ls Cs1 Ls I1 (s)
s
(A) >
= G
G
1 H=
Ls
R Cs I2 (s)
0
R Ls Cs1 Ls I1 (s)
Vs
(B) >
Ls
R Cs1 H=I2 (s)G = 0 G
GATE Electronics and Communication Topicwise Solved Paper by RK Kanodia & Ashish Murolia
Page 25
R Ls Cs1
Ls
I1 (s)
Vs
(C) >
Ls
R Ls Cs1 H=I2 (s)G = 0 G
V
R Ls Cs1
Cs
I1 (s)
s
(D) >
Ls
R Ls Cs1 H=I2 (s)G = 0 G
2.85
3 (s 3)
2 (s 3)
(B) 2
s2 2s 3
s 2s 2
3 (s 3)
2 (s 3)
(C) 2
(D) 2
s 2s 2
s 2s 3
An input voltage v (t) 10 2 cos (t 10c) 10 5 cos (2t 10c)
V is applied to a series combination of resistance R 1 8 and
an inductance L 1 H. The resulting steady-state current i (t) in
ampere is
(A) 10 cos (t 55c) 10 cos (2t 10c tan1 2)
(B) 10 cos (t 55c) 10 23 cos (2t 55c)
(C) 10 cos (t 35c) 10 cos (2t 10c tan1 2)
(D) 10 cos (t 35c)
2.87
3
2
2.91
(D) 0 V
TWO MARKS
(A) 16 8
(B) 40 8
3
(C) 60 8
(D) 20 8
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(A)
(B)
(C)
(D)
(B) 50 V
(C) 50 V
GATE 2002
2.90
(A)
2.86
(A) 25 V
(A) 90+32.44c
(C) 80+ 32.44c
(B) 80+32.44c
(D) 90+ 32.44c
GATE 2001
GATE 2002
2.88
2.92
ONE MARK
(A) delivers 80 W
(C) delivers 40 W
2.89
ONE MARK
(A) 2 V
(C) 4 V
(B) absorbs 80 W
(D) absorbs 40 W
In the figure, the switch was closed for a long time before opening
at t 0 . The voltage vx at t 0+ is
2.93
2.94
(B) 4/3 V
(D) 8 V
GATE Electronics and Communication Topicwise Solved Paper by RK Kanodia & Ashish Murolia
Page 26
2.98
GATE 2001
2.95
The z parameters z11 and z21 for the 2-port network in the figure are
TWO MARKS
(A) 48 V
(C) 36 V
(B) 24 V
(D) 28 V
ONE MARK
(A) 16 V
(B) 4 V
2.97
In the figure, the value of the load resistor RL which maximizes the
power delivered to it is
(A) 14.14 8
(C) 200 8
(B) 10 8
(D) 28.28 8
GATE 2000
2.102
(D) 16 V
TWO MARKS
Use the data of the figure (a). The current i in the circuit of the
figure (b)
GATE Electronics and Communication Topicwise Solved Paper by RK Kanodia & Ashish Murolia
Page 27
2.107
(A) 2 A
(C) 4 A
(B) 2 A
(D) 4 A
GATE 1998
GATE 1999
2.103
ONE MARK
2.108
ONE MARK
2.109
(A) begh
(C) abfg
2.104
(D) 10
(B) defg
(D) aegh
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A 2-port network is shown in the given figure. The parameter h21 for
this network can be given by
(A) 1/2
(C) 3/2
(B) 1/2
(D) 3/2
GATE 1999
2.105
2.111
(A) IR 1 mA
(C) IR IC 1 mA
2.112
2.106
TWO MARK
2.113
(B) IR IL 1 mA
(D) IR IC 1 mA
0 1/2
The short-circuit admittance matrix a two-port network is >
1/2 0 H
The two-port network is
(A) non-reciprocal and passive
(B) non-reciprocal and active
(C) reciprocal and passive
(D) reciprocal and active
The voltage across the terminals a and b in the figure is
(A) 2
(C) 8
(B) 4
(D) 16
(A) 0.5 V
(C) 3.5 V
2.114
(B) 3.0 V
(D) 4.0 V
GATE Electronics and Communication Topicwise Solved Paper by RK Kanodia & Ashish Murolia
Page 28
2.119
(B) 15 V
(C) 5 V
ONE MARK
2.120
(A) 12 A
(C) 4 A
2.116
(A) 10 V
(A) 36 Joules
(B) 16 Joules
(B) 12 A
(D) None or these
(A) b 16 l 8
3
(B) b 8 l 8
3
(C) b 8 12j l 8
3
GATE 1996
2.121
(A) 3 V
(C) 5 V
2.117
ONE MARK
(B) 3 V
(D) None of these
(A) 1 A
(B) 5 A
(B) 5 V
(D) None of the above
2.122
2.123
TWO MARKS
The voltages VC1, VC2, and VC3 across the capacitors in the circuit in
GATE Electronics and Communication Topicwise Solved Paper by RK Kanodia & Ashish Murolia
Page 29
(A) 80 V, 32 V, 48 V
(B) 80 V, 48 V, 32 V
(C) 20 V, 8 V, 12 V
(D) 20 V, 12 V, 8 V
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GATE Electronics and Communication Topicwise Solved Paper by RK Kanodia & Ashish Murolia
Page 30
SOLUTIONS
2.1
j40
100 53.13c
j4 3
40 90c
100 53.13c
5 53.13c
800 90c
VTh 10 VL1
2.5
2
Rb Rc
k
k Ra Rb Rc
Since,
So,
or,
at
k RA
hence, it is also scaled by a factor k
2.2
2.3
2.4
at
VWZ
V
100 V ; WX 100
100
VYZ
2
2.6
GATE Electronics and Communication Topicwise Solved Paper by RK Kanodia & Ashish Murolia
Page 31
2.8
C2 5 NF ; ^V2hmax 5 V
C 3 2 NF ; ^V3hmax 2V
So, from Eq (1) we have
V2 2
5
V3
for
^V3hmax 2
We obtain,
V2 2 # 2 0.8 volt 5
5
i.e.,
V2 ^V2hmax
Hence, this is the voltage at C2 . Therefore,
V3 2 volt
V2 0.8 volt
and
V1 V2 V3 2.8 volt
Now, equivalent capacitance across the terminal is
Ceq C 2 C 3 C1 5 # 2 10 80 NF
52
7
C2 C3
Equivalent voltage is (max. value)
Vmax V1 2.8
So, charge stored in the effective capacitance is
Q Ceq Vmax b 80 l # ^2.8h 32 NC
7
Option (D) is correct.
I (s)
vc (0) /s
v (0)
c
1 1
1 1
C1 C 2
C1 s C 2 s
vC (0) 12 V
I (s) b C1 C2 l (12 V) 12Ceq
C1 C 2
Taking inverse Laplace transform for the current in time domain,
i (t) 12Ceq E (t)
2.11
In phasor form,
Alternate method:
Z (4 j3) 8 ,
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2
Pavg 1 Re $ I Z . 1 # Re "(5) 2 # (4 j3),
2
2
1 # 100 50 W
2
2.12
2.10
(Impulse)
2.13
V1 (j 1 1) j 1 1 0c j1
V1 1
1 j1
1
V1 1 0c 1 j 1
Current
I1
j1
j1
j
1
A
(1 j) j 1 j
Option (A) is correct.
We obtain Thevenin equivalent of circuit B .
GATE Electronics and Communication Topicwise Solved Paper by RK Kanodia & Ashish Murolia
Page 32
ZTh R
Thevenin Voltage :
For a one port network current entering one terminal, equals the
current leaving the second terminal. Thus the outgoing current from
A to B will be equal to the incoming current from D to C as shown
VTh 3 0c V
Now, circuit becomes as
i.e.
I1 10 3
2R
Power transfer from circuit A to B
P (I 12) 2 R 3I1
2
P :10 3D R 3 :10 3D
2R
2R
49
21
R
P
(2 R) 2 (2 R)
49R 21 (2 R)
P
(2 R) 2
42
70R
P
(2 R) 2
2
dP (2 R) 70 (42 70R) 2 (2 R) 0
dR
(2 R) 4
(2 R) [(2 R) 70 (42 70R) 2] 0
IDC IAB 3 A
IL
VTh,10 V
RTh RL
For RL 1 8 , IL 3 A
V
3 Th,10 V
RTh 1
For RL 2.5 8 , IL 2 A
V
Th,10 V
RTh 2.5
...(i)
...(ii)
GATE Electronics and Communication Topicwise Solved Paper by RK Kanodia & Ashish Murolia
Page 33
ISC
2.18
3RTh 3 2RTh 5
RTh 2 8
Substituting RTh into equation (i)
VTh,10 V 3 (2 1) 9 V
Note that it is a non reciprocal two port network. Thevenin voltage
seen at port B depends on the voltage connected at port A. Therefore
we took subscript VTh,10 V . This is Thevenin voltage only when 10 V
source is connected at input port A. If the voltage connected to port
A is different, then Thevenin voltage will be different. However,
Thevenins resistance remains same.
Now, the circuit is as shown below :
RTH 10 # 10 10 15 8
10 10
2.19
For RL 7 8 ,
2.16
IL
VTh,10 V
9 1A
2 RL 2 7
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VTh, 6 V RTh # 7 1 # 7 2 # 7 7 7 V
3
3
3 3
This is a linear network, so VTh at port B can be written as
VTh V1 B C
where V1 is the input applied at port A.
We have V1 10 V , VTh,10 V 9 V
...(i)
`
9 10B C
When V1 6 V , VTh, 6 V 9 V
...(ii)
`
7 6B C
Solving (i) and (ii)
B 0.5 , C 4
Thus, with any voltage V1 applied at port A, Thevenin voltage or
open circuit voltage at port B will be
So,
VTh, V 0.5V1 4
For
V1 8 V
VTh,8 V 0.5 # 8 4 8 Voc (open circuit voltage)
jXRC
jXRC (1 jXRC) 2
j
Here X 1
RC
j (1 j) 2
j
1
3
(1 j) 2 j
Vp
b l cos (t/RC)
3
Vout
Vin
2.17
25
(16 0 ) (6.4 j4.8) A
25 15 j30
Thus
2.20
v out
GATE Electronics and Communication Topicwise Solved Paper by RK Kanodia & Ashish Murolia
Thus
R1
Page 34
Ra Rb
6.6
28
Ra Rb Rc 6 6 6
Here
R1 R 2 R 3 2 8
Replacing in circuit we have the circuit shown below :
2.24
...(2)
...(1)
...(2)
I2 0.01V1 0.1V2
Now, applying KVL in outer loop;
V2 100I2
or
I2 0.01V2
From eq (2) and eq (3) we have
Now,
Z in
At resonance
1 XC
XL
Z in 1 R
1/R
(maximum at resonance)
1
1 1 jXC
R jXL
Input impedance
So,
...(3)
...(1)
V (3) 100 V
VC (t) VC (3) (VC (0) VC (3)) et/RC
t
100 ( 50 100) e 10 # 50 # 10
6
100 150e (2 # 10 t)
ic (t) C dV
dt
3
Now
15e2 # 10 t
3
GATE Electronics and Communication Topicwise Solved Paper by RK Kanodia & Ashish Murolia
Page 35
2VA 10 2 0 V4 4 V
I1 10 4 3 A
2
i (3) 15 0.5 A
3
3
103 sec
U L 15 # 10
Req
10 (10 || 10)
t
Now
and
So,
Hence
2.26
3
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Where,
Voltage across Z2
VZ Z2 : 20 0
Z1 Z 2
2
c
20j
c 1 20j m
20j
c 20j 1 20j m
( 20j)
: 20 j
20j 400 20j m
I 12 I1
I is always less then 12 A So, only option (A) satisfies this conditions.
: 20
2.29
Current in resistor R is
j
V
I Z j A
1
R
2
2.27
RL
1
R RRL sC RL
1 R RsC
RL
2.30
GATE Electronics and Communication Topicwise Solved Paper by RK Kanodia & Ashish Murolia
Page 36
E
Vx 4 # 12.5 50 V
I2 100 Vx 100 50 12.5 A
4
4
Pr VL IL* IL ZL # IL* ZL IL 2
2
(7 # 4j) 20+0c (7 4j) 28 16j
8 6j
Isc I1 I2 25 A
Rth Voc 100 4 8
Isc
25
Voc 100 V
I1 100 12.5 A
8
2.34
2.35
There can be four possible tree of this graph which are as follows:
V (0) 100 V
Thus
V (0) 100 V
At t 0+ , the circuit is as shown below
There can be 6 different possible cut-set.
I (0+) 100 20 mA
5k
At steady state i.e. at t 3 is I (3) 0
Now
i (t) I (0) e
t
RCeq
u (t)
2.33
2.36
GATE Electronics and Communication Topicwise Solved Paper by RK Kanodia & Ashish Murolia
Thus
but
Thus
2.37
Page 37
vL (0+) Is Rs
di (0)
vL (0+) L
dt
di (0+)
v (0) Is Rs
L
L
L
dt
At t 5T, Vc T Volts
Thus the output waveform is
Vc
dt t 4T
4T
or
Zth (1 s) ( s1 1)
(1 s)( s1 1)
[ 1 1 1 s]
s 1
(1 s) ( s1 1)
s s 11
Zth 1
Alternative :
Here at DC source capacitor act as open circuit and inductor act
as short circuit. Thus we can directly calculate thevenin Impedance as 1 8
2.38
s
C
s
RC
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1
LC
Vc (s)
2
Vc (s) 2 =
G
3 (s 12 ) 2 43
Taking inverse Laplace transform we have
Vt 2 e sin c 3 t m
2
3
t
2
2.41
Vc
dt
dt t
or
At t T, Vc T Volts
For T t 2T , capacitor will be discharged from T volts as
T
dt t 2T
2T
At t 3T, Vc T Volts
For 3T t 4T , capacitor will be discharged from T Volts
Vc T
At t 4T, Vc 0 Volts
dt 4T t
3T
vR (t) e cos
1
2
dt 2T t
At t 2T, Vc 0 volts
For 2T t 3T , capacitor will be charged from 0 V
(s 12 )
(s 12 ) 2
e 2 =cos
Vc T
1
(s2 s 1)
or
Vc
Vs (s) 1 and
Z (s) R 1 sL 2
sC
s
We have been given
Z (s) 2 0.2s
s 0.1s 2
Comparing with given we get
1 0.2 or C 5 F
C
1 0.1 or R 2 8
RC
1 2 or L 0.1 H
LC
2.39
2.42
3
4
1
2
(s 12 ) 2
3 t1
2 e sin 3 t
2
2# 3
2
1
2
3 t 1 sin 3 t
2
2 G
3
3
4
GATE Electronics and Communication Topicwise Solved Paper by RK Kanodia & Ashish Murolia
z11 z12
1.5 4.5
=z z G =1.5 1.5 G
21 22
2.43
Page 38
2.46
have
4.5 3
1.5
1 0.67
1. 5
2.47
or
i2 i1
Putting in equation for v1, we get
v1
i1
v1 (z11 z12) i1
h11 z11 z12 1.5 4.5 3
v2 = 0
Therefore
Vth Vth Vth 2Vth 2
2
1
1
or
Vth 4 volt
From the figure shown below it may be easily seen that the short
circuit current at terminal XY is isc 2 A because i 0 due to
short circuit of 1 8 resistor and all current will pass through short
circuit.
2.45
Therefore
2.48
Here we get V0 0
Vi
At X 0 , capacitor acts as open circuited and circuit look like as
shown in fig below
Rth Vth 4 2 8
isc
2
or
GATE Electronics and Communication Topicwise Solved Paper by RK Kanodia & Ashish Murolia
Now
IC (t) C
Page 39
dVC (t)
dt
(5 3j) (5 3j)
(5 3j) # (5 3j)
5 3j 5 3j
(5) 2 (3j) 2
25 9 3.4
10
10
2.54
v0 (0+) 0
At steady state capacitor act as open circuit.
Thus
Now
and
also
From (1) and (2)
Thus
V1 AV2 BI2
I1 CV2 DI2
V2 I2 RL
we get
V1 AV2 BI2
CV2 DI2
I1
...(1)
...(2)
...(3)
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Thus,
At input port
V1 re I1
At output port
V2 r0 (I2 CI1) r0 CI1 r0 I2
Comparing standard equation
1 4 0.8 k8
4 1 5 NF
Req Ceq 0.8k8 # 5NF 4 ms
v 0 (3) [v 0 (3) v 0 (0)] et/U
8 (8 0) et/0.004
v0 (t) 8 (1 et/0.004) Volts
Req
Ceq
U
v0 (t)
V1 z11 I1 z12 I2
V2 z21 I1 z22 I2
z12 0 and z21 r0 C
2.52
2.55
v Ldi
dt
2.53
v0 (3) 4 # vi 4 # 10 8
5
5
or
2.56
Re Z1 (s) $ Rneg
Rneg # Re Z1 (jX)
For all X.
GATE Electronics and Communication Topicwise Solved Paper by RK Kanodia & Ashish Murolia
1
Y (s)
1
sC
2
1
U (s)
LC
scR 1
s
R sL
sC
1
LC
s2 R s 1
L
LC
Page 40
R $2
L
C
2.58
2.63
V1 AV2 BI2
I1 CV2 DI2
n 0
A B
=C D G = 0 1 G
n
1
x
n
or
Vab 7.5 Vth
Short circuit at terminal ab is shown below
Resonant frequency
f0
1
2Q LC
2Q
3
1
1 # 1 # 10 - 6
400
10 # 20 10 Hz
Q
2Q
Option (C) is correct.
Maximum power will be transferred when RL Rs 1008
In this case voltage across RL is 5 V, therefore
Thus
2
Pmax V 5 # 5 0.25 W
R
100
2.60
2.59
I2 V1 n
1
V2
I1
I
2
or
and V1 nV2
I1
n
Comparing with standard equation
Thus
2.64
2.65
GATE Electronics and Communication Topicwise Solved Paper by RK Kanodia & Ashish Murolia
Page 41
V1 h11 I1 h12 V2
I2 h21 I1 h22 V2 Applying KVL at input port
V1 10I1 V2
Applying KCL at output port
V2 I I
1
2
20
or
I2 I1 V2
20
or
i (t) 0
i (t) 0.31
i (t) 0.5
Graph (C) satisfies all these conditions.
Z (s) s 2
V (s)
1
I (s) i
s 2 s (s 2)
I (s) 1 ; 1 1 E
2 s s2
Impedance
2.72
V1 z11 I1 z12 I2
V2 z11 I1 z22 I2
z11 V1
I1 I 0
2
Vc 3 V
V2 Vc 3 V
2.67
2.68
2.69
2.70
2 sin 103 t
2 +0c
1
jXC
1
V
V0
.Vt
1 jXCR i
R 1
jXC
1
1 j # 103 # 10 - 3
1 45c
v0 (t) sin (103 t 45c)
2.71
2 + 0c
vi (t) u (t)
Vi (s) 1
s
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z21 V2
I1
I1 0
Consider the given lattice network, when I2 0 . There is two similar path in the circuit for the current I1. So I 1 I1
2
Here Za 2j and Zb 28
1j j1
z11 z12
Thus
=z z G = j 1 1 j G
21 22
GATE Electronics and Communication Topicwise Solved Paper by RK Kanodia & Ashish Murolia
2.73
Page 42
Ldi (t) 1
dt
C
3
0
i (t) dt
Hence
or
2.74
I (s) vc (0+)
sC
sC
851 4
2.78
2.80
Now
2.75
L Q
C
2
2YX 20
2Y 203 0.02
10
Q 1 1 50
2Y
0.02
Thus
L
C
s2 20s 106 0
Xn
ZL ZS* Rs jXs
ZL 1 1j
Thus
2.79
V0 (s)
Vi (s)
1
1
sC
2
s LC sCR 1
R sL 1
sC
1
2 2
s (10 # 104) s (104 # 10 4) 1
106
6 2 1
2
10 s s 1 s 106 s 106
2.76
2.77
so, we get
Vab b i # 1l b i # 1l b 1 # 1l 0
3
6
3
2.83
Option ( ) is correct.
Data are missing in question as L1 &L2 are not given.
Option (A) is correct.
At t 0 - circuit is in steady state. So inductor act as short circuit
and capacitor act as open circuit.
GATE Electronics and Communication Topicwise Solved Paper by RK Kanodia & Ashish Murolia
Page 43
Now
i1 (0 ) i2 (0 ) 0
At t 0 ,
-
vc (0 -) V
+
At t 0 the circuit is as shown in fig. The voltage across capacitor and current in inductor cant be changed instantaneously. Thus
i1 i2 V
2R
2.84
2.87
At t 0+ ,
Z1 R jX1 L 1 j1
Z2 R jX2 L 1 j2
v (t) v (t)
i (t) 1 2
Z1
Z2
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z11 I1 z12 I2 V1
or
2.86
0
2 # 1 2 0.5
211
4
1
1
1
#
0.25
R2
211
4
2
1
#
R3
0.5
211
R1
V1
= G
V2
2.85
V2
V
> s H
0
Now
z11 V1
I1
v1
z12 R3 0.25
2.88
I2 = 0
v2
V2 V2 V1 V1
5
5
5
GATE Electronics and Communication Topicwise Solved Paper by RK Kanodia & Ashish Murolia
or
V2 V1 20 V
Voltage across dependent current source is 20 thus power delivered by it is
PV2 # V1 20 # 20 80 W
5
5
Page 44
2.91
1500 3 c VL mc VL m cos R
3
3 ZL
ZL
(400) 2 (.844)
90 8
1500
2.93
e0 4 V
Vx 2.5 # 20 50 V
2.90
Here
Applying KCL at Node, we get
0.5I1 Vth I1
20
or
but
Thus
and
Vth 10I1 0
I1 Vth 50
40
V
th 50
Vth
0
4
or
Vth 10 V
For Isc the circuit is shown in figure below.
Now
2.94
but
ZA ZB ZC
3Z 3Z
Z
3Z 3Z 3Z
3
2.95
GATE Electronics and Communication Topicwise Solved Paper by RK Kanodia & Ashish Murolia
Page 45
or
2.96
V0 RL
Vs
RL Rs
At resonant frequency X
V0 0 .
(finite value)
2.97
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Xs XL 10 8
For maximum power transfer
RL
2.98
Rs2 Xs2
2.100
2.101
Thus z11 6
11
iL eat ebt
V (t) vL L diL L d [eat ebt] aeat bebt
dt
dt
or
2.102
V0 RL
Vs
RL Rs
(finite value)
2.103
10 5 E 1 0
E 16 V
GATE Electronics and Communication Topicwise Solved Paper by RK Kanodia & Ashish Murolia
Page 46
Req 58 208 48
Req 5.20 4 4 4 8 8
5 20
2.107
2.104
2.108
2.109
Now
and
Thus
Va V1 Va 0 Va 0 0
R
R
R
& Va V1
3Va V1
3
V1 V1
3 2V1
I1 V1 Va
R
R
3R
V
0 1 V
3
1
I2 0 Va
R
R
3R
V1 /3R 1
I2
h21
2
I1 V 0
2V1 /3R
2.110
2.111
2.112
2.113
2.114
2.115
Vab 1 Vab 6
Vab 6 1 3.5 V
2
2.105
4j100
3 4j
3 4j # 3 4j
GATE Electronics and Communication Topicwise Solved Paper by RK Kanodia & Ashish Murolia
Page 47
I i 4
i 4 12 amp
so
2.117
2.118
2.119
V 3 0 3 volt
Now
t
t
VC (t) 10 (6 10) e RC 10 4e RC 10 4e 8
VR (t) 10 VC (t)
10 10 4e
Energy absorbed by resistor
t
RC
4e
#0 3V RR(t) #0 3 164e 4
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t
RC
t
E
2.120
t
RC
t
#0 3 4e 4
16 J
2.122
2.123