19 views

Uploaded by tchoudacy

lesson on multivibrator

lesson on multivibrator

© All Rights Reserved

- Pa0klt Manual
- Chapter 7
- 19968014 JK Flip Flop Experiment 9
- Static Timing Analysis Facts PDF
- ESTIMATING PAPER IN VARIABLE GAIN RELAYING ON IMPERFECT CSI
- 2_BSCIT_COA
- Design and Analysis of Low Power Johnson Counter with Improved Performance using MT-CMOS and Clock Gating
- Digital Integrated Circuits - A Design Perspective (2nd Ed) toc
- 141302-QB
- lab3
- Hardware interview
- Universal ICSP Adapter for PIC in DIL Housing
- DPSD 2 Marks
- 10 Handout
- 01_Solon
- Counters
- An Efficient D-Flip Flop Using Current Mode Signalling Scheme
- Sample Paper..
- Electronics Interview
- Optrex Im50240 Modificacion 2

You are on page 1of 14

MULTIVIBRATORS

INTRODUCTION

A multivibrator is an electronic circuit used to implement a variety of simple two-state

systems such as oscillators, timers and flip-flops. It is most often used in circuit that required a

square or rectangular waves signal or timed intervals for their operation. There are three principle

type of multivibrator circuit.

The astable M.V

The bistable M.V

SPECIFIC OBJECTIVES

By the end of this lesson, each student should be able to:

Define: a multivibrator, a monostable M.V, and an astable M.V

Describe the functioning of an astable multivibrator with BJT and logic gate

Describe the functioning of a monostable multivibrator with BJT and logic gate

Voof different multivibrator circuit

Calculate the period

I. THE MONOSTABE M.V

Vi

This is a circuit having two functional states; one being stable and the other unstable. Initially the

Supply

t

circuitt is at its stable state, once a control pulse is applied

at its input, the circuit toggle to an

unstable state for a certain time call period (T) and return to a stable stable.

MONOSTABLE

Page 1 sur 14

I.1-)

a) Circuit diagram

Vc

Vi

b) Functioning

When triggered by an external pulse, it changes over to an unstable state for a time T and then

toggle back to its stable state and wait for another trigger pulse.

At switch on, Q2 is quickly forward biased by R2. This turn Q2 ON giving it a low collector

voltage. This low collector voltage is cross connected to the base of Q 1, turning Q1 OFF. Since

VB1 < 0.7v. The capacitor then charges through R1 towards V ccV B 2 . This is the stable state.

If a negative pulse is applied to the base of Q 2, this turn Q2 OFF therefore VC2 goes high and

forward biased Q1 giving it a low voltage (V C1 = 0) and V c =V B 2 . This is the unstable state.

The current flow now from the supply to the ground (i.e. V C1 = 0) through R2 and C1 then the

capacitor discharges towards zero while VB2 is rising up to VB2 > 0.7v then Q2 turn ON and Q1

OFF then the capacitor start charging again. This is the stable state one more.

c) Characteristic curves

Page 2 sur 14

Vcc

T =0.7 R2 C

Application exercise:

Let consider the circuit diagram of a monostable multivibrator with BJTs. We calculate the

discharge time of the capacitor if R1 = R4 = 10Kohm and R2 = 330ohm

I.2-)

a) Circuit diagram

C1

A

3

2

Vc

V1 V2

R1

Vo

Vi

b) Functioning

Initially, the circuit is at its stable state with V O = 1 and VI also tied at logic state 1. The

capacitor is completely discharged. This implies V1 = 0, V2 = 0. No current flows in the circuit this

is the stable state.

t(ms)

If we now apply a low logic level at the input i.e. Vi = 0, V1 =1. The capacitor

brutally transmits this

t(ms)

t(ms)

T

Page 3 sur 14

signal to the inputs of the second gate. This implies V2 = 1 and Vo = 0.t(ms)

The capacitor C charges through R. as Vc increases, V2 decreases since V1 = VC + V2. When V2

reaches ViLmax of the second gate, its toggles and VO = 1. Thus the stable state again. At this level, V1

= 0 therefore C discharges through R towards 0.

VS(v)

VDD

c) Chronogrammes

t(ms)

I

VDD/2

-VDD/2

t(ms)

The period can be determine by applying the formular below for Cmos integrated circuit

T =1.1 R 1 C

Application exercise: consider the figure above, determine the normalize value of R1 if we wish to

obtained a charging time of 10s. given that C = 1uF

UBE

a) Circuit diagram

Vdd

R

C

VI

V1

V2

VO

VBE

Page 4 sur 14

t(ms)

3/2VDD

b) Functioning

VDD/2

t(ms)

this signal to the input of the second gate therefore V2 = 1, no current flows in the circuit. This is the

the stable state.

If a positive pulse is applied at the input i.e VI = 1, V1 = 0, C transmits the signal to the

input of the second gate, then V2 = 0 and VO = 1 the capacitor charges through R. V2 increase

0

exponentially, at V2 = VIHmin of the second gate, its toggle and VO = 0. This is once more the

stable state.

c) Chronogrammes

The period can be determine by applying the formular below for Cmos integrated circuit

T =1.1 RC

An astable multivibrator is a circuit that presents two unstable states; one high and the other low.

It continuously oscillates from one unstable state to another. That is why it is usually refered to a

free Running m.v. Thus it required no input signal, but may sometimes need a synchronizing input

to control its action.

suppl

ASTABLE

Vo

Vo

Page 5 sur 14

t

II.2-) Realisation with BJTs

a) Circuit diagram

b) functioning

V'O

VO

VC1

VC2

So how does the circuit work? To begin, when power is applied, theoretically both T1 and

T2 should turn on, since their base pins are connected through resistors (R2 and R3) to Vcc.

However, due to small differences in the electric properties, one of them will turn on slightly earlier

than the other. Lets assume Q2 turns on first. Therefore, Q2s collector begins to conduct and can be

thought of as shorted to ground (V'O=0). Note that C2s right lead is connected to T2s collector,

and since C2 is not charged yet, its left lead also has a voltage close to ground. This immediately

shuts off Q1, i.e. T1 becomes an open circuit (VO = VCC). Therefore C1s left lead is in floating

status, and its right lead is connected to Q 2s base, which is about 0.7V due to the forward voltage

drop of transistors. This forward voltage drop is the same as a diode.

Stage1: During this period, Q2s collector (output V'O) remains low, and C2 begins to charge through

R3. Thus the voltage on C2s left lead will rise, and the rising time depends on R3 x C2. At the

same time, C1 also charges, through R1, which is typically a small resistor (e.g. 100-1000 ohm). So

C1s left lead (output VO) will quickly rise up to Vcc and remains high. As C2 continues to charge,

a critical moment will happen when its left lead rise up to 0.7V, at which moment transistor Q 1 will

turn on, and its collector will conduct to ground. Note that since C1s left lead is connected to T1s

collector, it will also drop to ground voltage. As C1 is fully charged, its right lead will suddenly

Page 6 sur 14

drop to a negative voltage (-Vcc). This will shuts off Q 2 firmly. During this period, VO will remain

low, and V'O will quickly rise to Vcc (due to the charging of C2 through a small resistor R4). At the

same time, C1 charges through R2 and the voltage on its right lead will rise over time determined

by R2 x C1. As C1 continues to charge, the next critical moment happens when C1s right lead rises

above 0.7V. At that point, T2 will conduct again while T1 shuts off.

c) Chronogrammes

VBE2(v)

Vcc 0,7

RC1

RB2

RB2

C1

VS1

RC2

-(Vcc-0,7)

Vs2(v)

Vcc

C2

T1

T2

VS2

VBE1

t(ms)

VBE2

t(ms)

0

VBE1(v)

0,7

0

t(ms)

-(Vcc-0,7)

Vs1(v)

Vcc

t(ms)

0

T =T 1 +T 2

Where

T 1 =0.693 R 2C1

and

T 1 =0.693 R 3C 2

Therefore

T =0.693( R2C1 + R3C2 )

Application exercise:

Let consider the circuit diagram of an astable multivibrator with BJTs. Determine the off time of

transistors Q1 and Q2 that is T1 and T2 and deduce the period T if C1 = C2 = 0,01F ;

R3 = R2 = 10Kohm.

Page 7 sur 14

a) Circuit diagram

S'

R2

R

Vs

A

C

b) Functioning

Initially, suppose the output of the second gate is at logic 1. This implies S' = 0 and E = 1

the capacitor C charges through R. As C charges up, the voltage at point A decreases until the lower

threshold voltage of the firs gate is reached (V ILMAX). At this point, the first gate changes state and

S'= 1, while E = 0 and VS = 0. The capacitor is now reversed biased and discharges itself through R2

During the discharge, VA increase till the upper threshold voltage of the second gate (VIHMIN) then it

toggles again and the capacitor charges once more. Thus the cycle repeat.

Chronogramme

VA

c)

Chronogram

Page 8 sur 14

T =2.2 RC

It is a circuit having two stable state. the circuit can be flipped from one stable state to another by an

external trigger. Such a circuit is important in the fundamental building block of register or memory

device. The bistable is still called a lacth or a flip-flop.

a) Circuit diagram

Page 9 sur 14

b) Functioning

This circuit is similar to an astable multivibrator, except that there is no charge or discharge

time, due to the absence of capacitors. Hence, when the circuit is switched on, if Q1 is on, its

collector is at 0 V. As a result, Q2 gets switched off. This results in more than half +V volts being

applied to R4 causing current into the base of Q1, thus keeping it on. Thus, the circuit remains

stable in a single state continuously. Similarly, Q2 remains on continuously, if it happens to get

switched on first. Switching of state can be done via Set and Reset terminals connected to the bases.

For example, if Q2 is on and Set is grounded momentarily, this switches Q2 off, and makes Q1 on.

Thus, Set is used to "set" Q1 on, and Reset is used to "reset" it to off state.

c) Chronnogram

SET

RESET

As well as producing a bistable multivibrator from individual discrete components such as

transistors, we can also construct bistable circuits using commonly available integrated circuits. The

following circuit shows how a basic bistable multivibrator circuit can be constructed using just two

Page 10 sur 14

a) Circuit diagram

b) Functionning

When the input pulse goes LOW the bistable latches into its SET state, with its output at logic

level 1, that is V0 = 1, V1 = 1, V2 = 0. The circuit will remain at this state till the input goes

HIGH causing the bistable to latch into its RESET state, with its output at logic level 0. The

output of a bistable multivibrator will stay in this RESET state until another input pulse is applied

and the whole sequence will start again.

IV.

CONCLUSION

Page 11 sur 14

TUTORIAL SHEET

Exercice1: the owner of a building with two floors in Bamenda town realized that his electricity bill

was very high due to the fact that the bulbs used to illuminate the stairs linking the upper floor to

the lower floor were constantly on. He wishes that, once the switch is activated, the bulbs should be

on for 30 seconds. Suppose that you are the electonician that have been call to solve his problem.

a) Which type of multivibrator is suitable to solve this problem?

b) Draw the circuit of that multivibrator using BJTs

Page 12 sur 14

c) Calculate the value of the resistor (R) and the capacitor (C) to be choose in order to obtained

and approximated period of 30s.

Exercise2:

An Astable Multivibrator circuit is constructed using two timing capacitors of equal value of

3.3uF and two base resistors of value 10k. Calculate the minimum and maximum frequencies of

oscillation if a 100k dual-gang potentiometer is connected in series with the two resistors.

Exercise3:

Soulution

Page 13 sur 14

Exercice2:

with the potentiometer at 0%, the value of the base resistance is equal to 10k.

with the potentiometer at 100%, the value of the base resistance is equal to 10k + 100k = 110k.

Then the output frequency of oscillation for the astable multivibrator can be varied from between 2.0 and 22

Hertz.

Page 14 sur 14

- Pa0klt ManualUploaded byIan McNair
- Chapter 7Uploaded byredberryyes
- 19968014 JK Flip Flop Experiment 9Uploaded byNev Callejo
- Static Timing Analysis Facts PDFUploaded byLalit Gohate
- ESTIMATING PAPER IN VARIABLE GAIN RELAYING ON IMPERFECT CSIUploaded byIJSRMS Journal
- 2_BSCIT_COAUploaded bywishpond
- Design and Analysis of Low Power Johnson Counter with Improved Performance using MT-CMOS and Clock GatingUploaded byIJSTE
- Digital Integrated Circuits - A Design Perspective (2nd Ed) tocUploaded byemilko
- 141302-QBUploaded byDhilip Prabakaran
- lab3Uploaded byVõ Bá Quang Duy
- Hardware interviewUploaded bySaurabhSharma
- Universal ICSP Adapter for PIC in DIL HousingUploaded byDai Daiduong
- DPSD 2 MarksUploaded byDhilip Prabakaran
- 10 HandoutUploaded byAsher Wayne
- 01_SolonUploaded byMourad Mkhakh
- CountersUploaded byAshutoshdash1111
- An Efficient D-Flip Flop Using Current Mode Signalling SchemeUploaded byIJSTE
- Sample Paper..Uploaded byankit
- Electronics InterviewUploaded byShivam Pitaria
- Optrex Im50240 Modificacion 2Uploaded byPedro Perez
- CODING Stle for SynthUploaded byAishwarya a nair
- DatasheetUploaded byLeonardo Sarmiento
- P34x_EN_SG_B76.pdfUploaded byOmar Chayña Velásquez
- Low Power On-Chip Delay MeasurementUploaded byRahul Krishnamurthy
- 5 Analysis Combinational CircuitUploaded byVan-Huynh Nguyen
- Fsm Router1Uploaded bybhanu prakash
- 0816-ELEC-121-0816-ELEC-121Uploaded bylilama45-1
- Electrical & Electronics Engineering (EEE)Uploaded bysrmuniversity
- EEE CurriculumUploaded byYan Yantono
- 91929ii,III & IV Year i Sem.r09Uploaded bystudedicts

- 1015Uploaded byBigBud123
- Bobcat 773 Service Repair ManualUploaded bybretweller
- Configuration Description - LG34Uploaded byBreni Sukarno
- Adre Plot DescriptionUploaded byCreativeManMan
- Risk Log ExampleUploaded byWaqas Ahmed
- V Belt FailureUploaded bymuki10
- Investigating Process SchedulingUploaded bypdparthasarathy03
- TT8750+AN005 - SkyPatrol Counter Report Decoding Rev 1_0Uploaded byrezortez
- 4092.PDFUploaded by995aarvee
- FYBSc Computer Science 2015-16 SyllabusUploaded bymukeshnt
- Ship ManagementUploaded byDeepak Shori
- Conduction and Breakdown of Pure LiquidsUploaded byPrakash Parajuli
- Sika Intraplast ZUploaded byreborn_willy
- Layer 7 Solutions for CloudUploaded byLayer7Tech
- Fundamentals of Structural Dynamics QF2014Uploaded byAfham Ahmad
- Cross Compile Python for Embedded LinuxUploaded byKuma Akira
- Pump CharacteristicsUploaded bygeocaustas
- Analysis of Business EnvironmentUploaded byLapi Boy Mics
- Google Drive TrashUploaded byFernanda Torres
- File HandlingUploaded byranjan_prashant52
- Software_Notes2018.docxUploaded byAshley
- Graphics - AssemblyUploaded byannesoria
- 33-002-USB (4)Uploaded byChoco Loco
- TENDRA AP CPNTROLADOR AC500.pdfUploaded byiraudy
- Oliva CurriculumUploaded bychonac
- Tension TestUploaded byArjun Radhakrishnan
- Example_ Software Architecture DocumentUploaded bySubbu6502
- nadp_sap2Uploaded byShijo Antony
- Hydrodynamic Loadings of Buildings in FloodsUploaded bypn1313
- CABOS UTPUploaded byRoberto Rmo