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Understanding and
Predicting Power MOSFET
Switching Behavior
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APPLICATION NOTE
The best way to predict a MOSFETs switching speed is
not by using an RC time constant or the concept of the Miller
capacitance. RC time constants and Miller capacitance have
their uses, but they are usually not appropriate for the
selection of a power MOSFETs gate drive resistor. Before
we discuss the preferred method of gate drive design, lets
look at the problems of using RC time constants and Miller
capacitance. Since using an RC time constant is the easier
prey, lets take a look at it first.
Authors of books and papers commonly suggest using the
formula tr or tf = 2.2 Rg Ciss as a first pass estimate of gate
voltage rise and fall time. Of course, the idea is to estimate
the 0% to 90% transition time by using the time constant
established by the gate drive impedance and the MOSFETs
input capacitance Ciss (the parallel combination of the
gatetosource capacitance and the gatetodrain
capacitance). The formula is inappropriate for use with
power MOSFETs because the MOSFETs input
characteristics are poorly modeled by a single
gatetosource capacitor.
One problem is that the magnitude of Ciss changes during
switching. But more importantly, using a simple RC model
ignores the large amount of charge required by the
draintogate capacitance when the draintosource
voltage changes. Using 400 pF as the Ciss of an MTP2N50
(a 2 A, 500 V MOSFET) and setting Rg equal to 200 W, the
gate voltage rise or fall time is estimated to be 176 ns, far
from the 850 ns seen in Figure 1. Even if the gate voltage
transition time is known, it gives little information about the
more important draintosource voltage switching time.
Amazingly, by coincidence, the draintosource voltage
rise time in Figure 1 is very close to 176 ns. This is probably
why the method has enjoyed popularity even though it has
little basis in fact.
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VDS (V/DIV)
VDS
ID
50
ID (A/DIV)
0
VGS (V/DIV)
VGS
50
0
VGS (V/DIV)
VDS (V/DIV)
0
t1
t2
ta
t3
t4
200 ns/DIV
tb
tc
td
Qg, GATE CHARGE (5 nC/DIV)
9V
7V
ID (mA/DIV)
ID (mA/DIV)
6V
500
500
t1
t2
t3
5.2 V
t4
5V
VGS = 4 V
0
0
0
VGS (1 V/DIV)
VDS (2 V/DIV)
t5
400 V
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= 160 ns. Again the estimated time is very close to actual
performance.
A similar analysis can be used for turnon behavior. The
major differences are: 1) during the turn on delay time Ciss
is equal to the reciprocal of the first slope of the gate charge
curve and 2) the gate current during the plateau region is
equal to the gate supply voltage minus the plateau voltage
divided by the series gate resistance. The above method
works well for the most common applications. Conditions
that alter the actual switching time are: inductance in the
source circuit, onvoltage of the transistors in the drive IC,
draintosource snubbing networks, etc.
An additional benefit of this method is that the designer
gains a greater understanding of how the MOSFET
switches. For instance, it becomes clear that adding
gatetosource capacitance may not slow the
draintosource voltage rise time. Adding 100 pF to the gate
drive circuit above increased turnoff delay time, but did not
alter switching speed. Placing the same 100 pF from
draintogate more than doubles Vds rise time.
Brushless motor control circuits which PWM the
transistors for speed control are another example of a
situation where the concepts are useful. Assume that in a 3
phase system the upper transistors are switching at 20 kHz.
The tendency is to build a high speed gate drive for only the
lower transistors. However, as VDS changes on a lower
device, an upper device experiences a VDS change of equal
magnitude and opposite polarity. The dv/dt also appears
across the upper MOSFETs draintogate capacitance. If
the upper transistor does not have a gate drive impedance
equivalent to that of the lower, the upper device may
partially turnon, briefly pass shoot through currents, and
increase switching losses.
5 nC/4 V = 1250 pF. During the turnoff delay (t1 to t2), the
fall of Vgs can be predicted by:
tdelay(off) + Rg Ciss in 1 *
plateau voltage
supply voltage
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