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DEL LITORAL
FACULTAD DE INGENIERIA ELECTRICA Y COMPUTACION
LABORATORIO DE SISTEMAS DIGITALES
PROYECTO #1
INTEGRANTES:
PROFESOR:
ING. GABRIELA SANCHEZ
PARALELO:
11
Contenido
Pgina
1 ESPECIFICACION DEL PROYECTO
2 DIAGRAMAS DE BLOQUES
3 DIAGRAMA ASM
4 DIAGRAMA DE TIEMPO
10
13
6 DESCRIPCION VHDL
18
7 REPORTE DE APROVECHAMIENTO
36
8 COMPONENTES UTILIZADOS
37
38
10 RECOMENDACIONES Y CONCLUSIONES
40
Pgina 2
Al salir el sensor detectar que hay un carro, se prende un led, que indica
que tiene que pagar, paga el dueo del carro, se apaga el led, se levanta la
palanca pasa el carro y se baja la palanca.
Restricciones: Se necesitar de un display el cual indicar cuantos carros hay en el interior
del estacionamiento el cual tendr un lmite y cuando llegue a este, ya no permitir la
entrada a ningn otro carro.
Pgina 3
2.
DIAGRAMAS DE BLOQUES
Diagrama principal
Pgina 4
Diagramas de displays
Diagrama de botoneras
Pgina 5
Bloque comparador
Comparador 500
Pgina 6
Comparador clave
Mux 2 a 1
Este bloque es un decodificador bcd a 7 seg anidado, osea que decodifica las unidades y decenas
para mostrar el numero de parqueos disponibles
Contador up
Pgina 7
Delay
Antirrebote
Teclado
Pgina 8
3. DIAGRAMA ASM
Pgina 9
4. DIAGRAMA DE TIEMPO
Se realizara varias simulaciones debido a que no alcanza el diagrama de tiempo en el quartus para
hacerlo todo en una sola simulacin
Primero tenemos la simulacin, cuando ingresa un visitante:
Pgina 10
Ahora cuando est lleno parqueadero visitante, que ser igual cuando est lleno parqueadero
propietario
Pgina 11
Finalmente cuando se va a simular cuando se va a sacar un carro del parqueadero, en este caso
visitante
Pgina 12
VCC
R? R? R? R? R? R? R? R? R? R? R? R? R? R? R? R? R? R? R? R? R? R?
Res1 Res1 Res1 Res1 Res1 Res1 Res1 Res1 Res1 Res1 Res1 Res1 Res1 Res1 Res1 Res1 Res1 Res1 Res1 Res1 Res1 Res1
12K 12K 12K 12K 12K 12K 12K 12K 12K 12K 12K 12K 12K 12K 12K 12K 12K 12K 12K 12K 12K 12K
b3
U?H
BANK 8
b6
SW-PB
C8
D8
E8
F8
A7
B7
C6
A6
B6
E7
E6
A5
B5
D6
A4
B4
A2
A3
D5
B3
C3
D3
b7
SW-PB
b8
SW-PB
b1
SW-PB
bpr
SW-PB
b2
SW-PB
bvi
SW-PB
Smux
SW-PB
b5
SW-PB
b4
SW-PB
bp
SW-PB
bt
SW-PB
EP4CE22F17C6
bo
SW-PB
b2p
SW-PB
b2v
SW-PB
bo
SW-PB
bs1
SW-PB
bo
SW-PB
bo
SW-PB
bo
SW-PB
Resetn
SW-PB
SW-PB
U?D
GND
U?D
D?
R?
BANK 4
EP4CE22F17C6
N9
R10
T10
R11
T11
R12
T12
P9
P11
R13
T13
M10
N11
T14
T15
N12
P14
R14
D?
LED0
D?
LED0
D?
LED0
D?
LED0
D?
LED0
D?
LED0
D?
LED0
LED0
Res2
330
R?
Res2
330
R?
Res2
330
R?
Res2
330
R?
Res2
330
R?
Res2
330
R?
Res2
330
R?
Res2
330
Pgina 13
GND
Pgina 14
R?
U?C
BANK 3
IO, DIFFIO_B1p
IO, DIFFIO_B1n, (DM3B/BWS#3B)/(DM5B/BWS#5B)
IO, DIFFIO_B2p, (DQ3B)/(DQ5B)
IO, DIFFIO_B2n
IO, (DQS1B/CQ1B#,CDPCLK2)/(DQS1B/CQ1B#,CDPCLK2)
IO, PLL1_CLKOUTp
IO, PLL1_CLKOUTn
IO, DIFFIO_B4p, (DQ3B)/(DQ5B)
IO, DIFFIO_B4n, (DQ3B)/(DQ5B)
IO, (DQ3B)/(DQ5B)
IO, VREFB3N0
IO, DIFFIO_B5p, (DQS3B/CQ3B#,DPCLK2)/(DQS3B/CQ3B#,DPCLK2)
IO, DIFFIO_B6p, (DQ3B)/(DQ5B)
IO, DIFFIO_B6n
IO, DIFFIO_B7p, (DQ3B)/(DQ5B)
IO, DIFFIO_B7n
IO, (DQ3B)/(DQ5B)
IO, DIFFIO_B8p, (DQ3B)/(DQ5B)
IO, DIFFIO_B8n, (DQS5B/CQ5B#,DPCLK3)/(DQS5B/CQ5B#,DPCLK3)
IO, DIFFIO_B9n, (DQ3B)/(DQ5B)
IO, DIFFIO_B10n, (DM5B/BWS#5B)/(DM5B/BWS#5B)
IO, DIFFIO_B11p, (DQ5B)/(DQ5B)
IO, DIFFIO_B12n, (DQ5B)/(DQ5B)
EP4CE22F17C6
N3
P3
R3
T3
T2
R4
T4
N5
N6
M6
P6
M7
R5
T5
R6
T6
L7
R7
T7
L8
M8
N8
P8
DS?
1
2
3
4
5
6
7
8
16 10
15 9
14 8
13 5
12 4
11 2
10 3
9
7
Res Pack4
1K
a
b
c
d
e
f
g
DP
K
K
1
6
GND
Dpy Red-CC
DS?
R?
1
2
3
4
5
6
7
8
16 10
15 9
14 8
13 5
12 4
11 2
10 3
9
7
Res Pack4
1K
Pgina 15
a
K
b
K
c
d
e
f
g
DP
Dpy Red-CC
1
6
GND
Pgina 16
Pgina 17
6. DESCRIPCION VHDL
Cdigo principal
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity maquinaparqueadero is
port(Resetn, Clock: in std_logic;
Smux, bp, bt, bvi, bpr, bs1, b2v, b2p : in std_logic;
b0,b1,b2,b3,b4,b5,b6,b7,b8,b9: in std_logic;
lep, let, lev, lepr, leplv, leplpr, ling, linc: out std_logic;
Q: out std_logic_vector (13 downto 0));
end maquinaparqueadero;
architecture estructural of maquinaparqueadero is
component b14seg
port (A: in std_logic_vector (3 downto 0);
B: out std_logic_vector (13 downto 0));
END component;
component Comparador
port(A: in std_logic_vector(3 downto 0);
AiguB: out std_logic);
END component;
component Comparador500
port(A: in std_logic_vector(8 downto 0);
AiguB: out std_logic);
end component;
component Comparador4
port(A: in std_logic_vector(2 downto 0);
AiguB: out std_logic);
end component;
component delay
port (clock,en: in std_logic;
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Pgina 18
reset: in std_logic;
Q: out std_logic_vector(8 downto 0));
end component;
component Mu2a1
port( A, B: in std_logic_vector(3 downto 0);
s: in std_logic;
y: out std_logic_vector(3 downto 0));
end component;
component teclado
port (a,b,c,d,e,f,g,h,j,k: in std_logic;
reset,clock: in std_logic;
load,en: in std_logic;
cont: out std_logic_vector(2 downto 0);
Q: out std_logic_vector(13 downto 0));
end component;
component contu
port (clock, eni, eno: in std_logic;
reset: in std_logic;
Q: out std_logic_vector(3 downto 0));
end component;
component CLOCK_DIV is
PORT
( CLOCK_8MHz :IN STD_LOGIC;
CLOCK_1MHz :OUT STD_LOGIC;
CLOCK_100KHz :OUT STD_LOGIC;
CLOCK_10KHz :OUT STD_LOGIC;
CLOCK_1KHz :OUT STD_LOGIC;
CLOCK_100Hz :OUT STD_LOGIC;
CLOCK_10Hz :OUT STD_LOGIC;
CLOCK_1Hz :OUT STD_LOGIC);
end component;
component pantirebote
port ( clck,resetn, sr: in std_logic;
r: out std_logic);
end component;
component controlador
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Pgina 19
-- clock
relojdiv: CLOCK_DIV port map (Clock, f1m, f100k, f10k, f1k, f100, f10, f1);
--tecladoantirebote
rebote0: pantirebote port map (f100,Resetn,b0, pbr0);
rebote1: pantirebote port map (f100,Resetn,b1, pbr1);
rebote2: pantirebote port map (f100,Resetn,b2, pbr2);
rebote3: pantirebote port map (f100,Resetn,b3, pbr3);
rebote4: pantirebote port map (f100,Resetn,b4, pbr4);
rebote5: pantirebote port map (f100,Resetn,b5, pbr5);
rebote6: pantirebote port map (f100,Resetn,b6, pbr6);
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Pgina 20
--teclado
teclado1: teclado port map
(pbr0,pbr1,pbr2,pbr3,pbr4,pbr5,pbr6,pbr7,pbr8,pbr9,Resetn,f100,loadt,ennc,contt,c);
--comparadorclave
comclave: comparadorclave port map (c,iguc);
--mss
mss: controlador port map (Resetn, f100, igu0v, igu0p, igu15v, igu0p, pbt, pbp, iguc, pbs1, pbs2v,
pbs2p, pbv, pbpro,c4,c500, ennvi, ennpi, ennvo, ennpo, lep, let, leplv, leplpr, lev, lepr,loadt,
endd,ennc,ling, linc);
--contadores
contv: contu port map (f100, ennvi, ennvo, Resetn, vo);
contp: contu port map (f100, ennpi, ennpo, Resetn, po);
--comparadorcero
comcerov: comparador port map (vo,igu0v);
comcerop: comparador port map (po,igu0p);
--comparadorquince
comquincev: comparador15 port map (vo,igu15v);
comquincep: comparador15 port map (po,igu15p);
Pgina 21
--mux
mux1: mu2a1 port map (vo, po, Smux, qmux);
--binarioa14seg
seg: b14seg port map (qmux, Q);
--delay
temporizador: delay port map (f100,endd, Resetn, qq);
-compara4: comparador4 port map (contt,c4);
compara500: comparador500 port map (qq,c500);
end estructural;
library ieee;
use ieee.std_logic_1164.all;
entity controlador is
port ( resetn, clock, vio, pro, viq, prq: in std_logic;
ticket, pagar, clave, s1, s2v, s2p, v, p, cont4, cont500: in std_logic;
envi, enpi, envs, enps, lpagar, lticket, plumav, plumap, lv, lp, load,
delay,enc,lingrese,lincorrecto: out std_logic);
end controlador;
architecture solucion of controlador is
type estado is (ta, tb, tc, td, te, tf, tg, th, ti, tj, tk, tl, tm, tn,tp ,tq ,tr ,ts , tt, tu ,tv ,tw ,tx ,ty
,tz ,taa ,tab ,tac ,tad, tae, taf, tag, tah, tai, taj, tal, tam, tan, tap, taq, tar, tas, tat, tma, tmb, tva,
tvb);
signal y: estado;
begin
process (resetn, clock)
begin
if resetn='1' then y<=ta;
elsif clock'event and clock='1' then
case y is
when ta => if vio='0' then if pro='0' then y<=tb; else y<=td; end if; else if pro='0' then
y<=te; else y<=tc; end if; end if;
Control de estacionamiento por cupo
Pgina 22
when tb => if prq='0' then if viq='0' then y<=tas; else y<=tar; end if; else if viq='0' then
y<=tah; else y<=tai; end if; end if;
when tc => if s1='0' then y<=tc; else y<=tag; end if;
when td => if viq='0' then y<=tf; else y<=th; end if;
when te => if prq='0' then y<=tq; else y<=ty; end if;
when tf => if s1='0' then if s2v='0' then y<=tf; else y<=ti; end if; else y<=tg; end if;
when tg => if v='0' then if p='0' then y<=tg; else y<=tv; end if; else y<=ts; end if;
when th => if s1='0' then if s2v='0' then y<=th; else y<=ti; end if; else y<=tl; end if;
when ti => if pagar='0' then y<=ti; else y<=tj; end if;
when tj => if s1='0' then y<=tj; else y<=tk; end if;
when tk => y<=ta;
when tl => if p='0' then y<=tl; else y<=tm; end if;
when tm => if cont4='0' then y<=tm; else y<=tma; end if;
when tma => if clave='0' then y<=tmb; else y<=tn; end if;
when tmb => if cont500='0' then y<=tmb; else y<=tm; end if;
when tn => if s2p='0' then y<=tn; else y<=tp; end if;
when tp => y<=ta;
when tq => if s1='0' then if s2p='0' then y<=tq; else y<=tad; end if; else y<=tr; end if;
when tr => if v='0' then if p='0' then y<=tr; else y<=tv; end if; else y<=ts; end if;
when ts => if ticket='0' then y<=ts; else y<=tt; end if;
when tt => if s2v='0' then y<=tt; else y<=tu; end if;
when tu => y<=ta;
when tv => if cont4='0' then y<=tv; else y<=tva; end if;
when tva => if clave='0' then y<=tvb; else y<=tw; end if;
when tvb => if cont500='0' then y<=tvb; else y<=tv; end if;
when tw => if s2p='0' then y<=tw; else y<=tx; end if;
when tx => y<=ta;
when ty => if s1='0' then if s2p='0' then y<=ty; else y<=tad; end if; else y<=tz; end if;
when tz => if v='0' then y<=tz; else y<=taa; end if;
when taa => if ticket='0' then y<=taa; else y<=tab; end if;
when tab => if s2v='0' then y<=tab; else y<=tac; end if;
when tac => y<=ta;
when tad => if pagar='0' then y<=tad; else y<=tae; end if;
when tae => if s1='0' then y<=tae; else y<=taf; end if;
when taf => y<=ta;
when tag => if v='0' then if p='0' then y<=tag; else y<=tv; end if; else y<=ts; end if;
when tah => if s1='0' then if s2p='0' then if s2v='0' then y<=tah; else y<=tan; end if; else
y<=tad; end if; else y<=tz; end if;
when tai => if s2p='0' then if s2v='0' then y<=tai; else y<=tan; end if; else y<=taj; end if;
when taj => if pagar='0' then y<=taj; else y<=tal; end if;
when tal => if s1='0' then y<=tal; else y<=tam; end if;
when tam => y<=ta;
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Pgina 23
when tan => if pagar='0' then y<=tan; else y<=tap; end if;
when tap => if s1='0' then y<=tap; else y<=taq; end if;
when taq => y<=ta;
when tar => if s1='0' then if s2p='0' then if s2v='0' then y<=tar; else y<=ti; end if; else
y<=taj; end if; else y<=tl; end if;
when tas => if s1='0' then if s2p='0' then if s2v='0' then y<=tas; else y<=ti; end if; else
y<=tad; end if; else y<=tat; end if;
when tat => if p='0' then if v='0' then y<=tat; else y<=ts; end if; else y<=tv; end if;
end case;
end if;
end process;
process(y)
begin
envi<='0'; enpi<='0'; envs<='0'; enps<='0'; lpagar<='0'; lticket<='0'; plumav<='0';
plumap<='0'; lv<='0'; lp<='0'; load<='0'; delay<='0'; enc<='0'; lingrese<='0';lincorrecto<='0';
case y is
when ta =>
when tb =>
when tc =>
when td =>
when te =>
when tf =>
when tg =>
when th => lv<='1';
when ti => lpagar<='1';
when tj => plumav<='1';
when tk => envs<='1';
when tl => lv<='1';
when tm => lv<='1'; lingrese<='1';
when tma => lv<='1'; load<='1';
when tmb => lv<='1'; delay<='1'; lincorrecto<='1'; enc<='1';
when tn => lv<='1'; plumap<='1'; enc<='1';
when tp => enpi<='1'; lv<='1';
when tq =>
when tr =>
when ts => lticket<='1';
when tt => plumav<='1';
when tu => envi<='1';
Control de estacionamiento por cupo
Pgina 24
Codigo antirrebote
library ieee;
use ieee.std_logic_1164.all;
entity pantirebote is
port ( clck,resetn, sr: in std_logic;
r: out std_logic);
end pantirebote;
architecture solucion of pantirebote is
type estado is (ta, tb, tc);
Control de estacionamiento por cupo
Pgina 25
signal y: estado;
begin
process (resetn, clck)
begin
if resetn='1' then y<=ta;
elsif clck'event and clck='0' then
case y is
when ta => if sr='1' then y<=tb; else y<=ta; end if;
when tb => if sr='1' then y<=tb; else y<=tc; end if;
when tc => y<=ta;
end case;
end if;
end process;
process(y)
begin
r<='0';
case y is
when ta=>
when tb=>
when tc=> r<='1';
end case;
end process;
end solucion;
Codigo delay
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
entity delay is
port (clock,en: in std_logic;
reset: in std_logic;
Q: out std_logic_vector(8 downto 0));
Control de estacionamiento por cupo
Pgina 26
end delay;
architecture solucion of delay is
signal a,b: std_logic_vector(8 downto 0);
begin
process(clock,reset) is
begin
b<="000000001";
if reset ='1' then
a<="000000000";
elsif clock'event and clock='1' then
if a="111110100" then
a<="000000000";
else
if en='1' then
a<=a+b;
end if;
end if;
end if;
end process;
Q<=a;
end solucion;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.STD_LOGIC_ARITH.all;
USE IEEE.STD_LOGIC_UNSIGNED.all;
ENTITY CLOCK_DIV IS
PORT
( CLOCK_8MHz :IN STD_LOGIC;
CLOCK_1MHz :OUT STD_LOGIC;
CLOCK_100KHz :OUT STD_LOGIC;
CLOCK_10KHz :OUT STD_LOGIC;
CLOCK_1KHz :OUT STD_LOGIC;
CLOCK_100Hz :OUT STD_LOGIC;
Control de estacionamiento por cupo
Pgina 27
Pgina 28
ELSE
count_100Khz <= "000";
clock_100Khz_int <= NOT clock_100Khz_int;
END IF;
END PROCESS;
-- Divide by 10
PROCESS
BEGIN
WAIT UNTIL clock_100Khz_int'EVENT and clock_100Khz_int = '1';
IF count_10Khz /= 4 THEN
count_10Khz <= count_10Khz + 1;
ELSE
count_10Khz <= "000";
clock_10Khz_int <= NOT clock_10Khz_int;
END IF;
END PROCESS;
-- Divide by 10
PROCESS
BEGIN
WAIT UNTIL clock_10Khz_int'EVENT and clock_10Khz_int = '1';
IF count_1Khz /= 4 THEN
count_1Khz <= count_1Khz + 1;
ELSE
count_1Khz <= "000";
clock_1Khz_int <= NOT clock_1Khz_int;
END IF;
END PROCESS;
-- Divide by 10
PROCESS
BEGIN
WAIT UNTIL clock_1Khz_int'EVENT and clock_1Khz_int = '1';
IF count_100hz /= 4 THEN
count_100hz <= count_100hz + 1;
ELSE
count_100hz <= "000";
clock_100hz_int <= NOT clock_100hz_int;
END IF;
END PROCESS;
-- Divide by 10
PROCESS
BEGIN
WAIT UNTIL clock_100hz_int'EVENT and clock_100hz_int = '1';
Control de estacionamiento por cupo
Pgina 29
IF count_10hz /= 4 THEN
count_10hz <= count_10hz + 1;
ELSE
count_10hz <= "000";
clock_10hz_int <= NOT clock_10hz_int;
END IF;
END PROCESS;
-- Divide by 10
PROCESS
BEGIN
WAIT UNTIL clock_10hz_int'EVENT and clock_10hz_int = '1';
IF count_1hz /= 4 THEN
count_1hz <= count_1hz + 1;
ELSE
count_1hz <= "000";
clock_1hz_int <= NOT clock_1hz_int;
END IF;
END PROCESS;
END a;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity b14seg is
port (A: in std_logic_vector (3 downto 0);
B: out std_logic_vector (13 downto 0));
end b14seg;
architecture solution of b14seg is
begin
with A select
--decenas,unidades
B<="11111101111110" when "0000",
"11111100110000" when "0001",
"11111101101101" when "0010",
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Pgina 30
Codigo teclado
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
entity teclado is
port (a,b,c,d,e,f,g,h,j,k: in std_logic;
reset,clock: in std_logic;
load,en: in std_logic;
cont: out std_logic_vector(2 downto 0);
Q: out std_logic_vector(13 downto 0));
end teclado;
architecture solucion of teclado is
signal i: std_logic_vector(2 downto 0);
signal l,m,n,o: std_logic_vector(13 downto 0);
begin
process(reset,clock) is
begin
Pgina 31
Pgina 32
l<="01101101011000";
i<=i+'1';
elsif j='1' then
l<="01111101000000";
i<=i+'1';
elsif k='1' then
l<="10001100101000";
i<=i+'1';
end if;
elsif i="001" then
if a='1' then
m<="00000000000000";
i<=i+'1';
elsif b='1' then
m<="00000001100100";
i<=i+'1';
elsif c='1' then
m<="00000011001000";
i<=i+'1';
elsif d='1' then
m<="00000100101100";
i<=i+'1';
elsif e='1' then
m<="00000110010000";
i<=i+'1';
elsif f='1' then
m<="00000111110100";
i<=i+'1';
elsif g='1' then
m<="00001001011000";
i<=i+'1';
elsif h='1' then
m<="00001010111100";
i<=i+'1';
elsif j='1' then
m<="00001100100000";
i<=i+'1';
elsif k='1' then
m<="00001110000100";
i<=i+'1';
end if;
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Pgina 33
Pgina 34
o<="00000000000010";
i<=i+'1';
elsif d='1' then
o<="00000000000011";
i<=i+'1';
elsif e='1' then
o<="00000000000100";
i<=i+'1';
elsif f='1' then
o<="00000000000101";
i<=i+'1';
elsif g='1' then
o<="00000000000110";
i<=i+'1';
elsif h='1' then
o<="00000000000111";
i<=i+'1';
elsif j='1' then
o<="00000000001000";
i<=i+'1';
elsif k='1' then
o<="00000000001001";
i<=i+'1';
end if;
end if;
end if;
end if;
end if;
end process;
cont<=i;
Q<=l+m+n+o;
end solucion;
Pgina 35
7. REPORTE DE APROVECHAMIENTO
Pgina 36
8. COMPONENTES UTILIZADOS
Componentes
Cantidad
FPGA
Bus de datos de 40 entradas
Botoneras
displays 7 segmentos , CC
resistencias de 390 ohmios
resistencias de 82K ohmios
leds
Cables macho
Switch
1
2
18
2
24
19
8
50
1
Pgina 37
Pgina 38
Pgina 39
RECOMENDACIONES
Arme su circuito con cables jumpers ya que si lo hace con los tradicionales utp es muy
probable que tenga muchos errores de rebote o de contacto y en este tipo de proyectos
se debe cuidar mucho eso.
Verifique continuidad en los buses de datos que entregan en el laboratorio ya que muchos
son muy viejos y han tenido muchos usos y eso hizo que nos demoremos en la entrega de
este primer proyecto debido a que nos dimos cuenta que era un bus de datos que nos
ocasionaba rebotes en los pulsadores y se nos salte estados el programa y no funciones
correctamente.
CONCLUSIONES
Las tarjetas FPGA de Altera son muy tiles en este tipo de proyectos, para sistemas
digitales, debido a su funcionalidad y versatilidad.
Los sistemas digitales ms complejos necesitaran otro tipo de controlador, mas avanzado,
ya que en este proyecto usamos los dos puertos JP1 y JP2 ya que tuvimos que hacer un
teclado para ingresar la contrasea y nos ocupo mas pines de E/S de la FPGA.
Pgina 40