Beruflich Dokumente
Kultur Dokumente
SN7414, SN74LS14
HEX SCHMITT-TRIGGER INVERTERS
SDLS049B DECEMBER 1983 REVISED FEBRUARY 2002
D
D
D
1A
1Y
2A
2Y
3A
3Y
GND
description
Each circuit functions as an inverter, but because
of the Schmitt action, it has different input
threshold levels for positive-going (VT+) and
negative-going (VT) signals.
These circuits are temperature compensated and
can be triggered from the slowest of input ramps
and still give clean, jitter-free output signals.
14
13
12
11
10
VCC
6A
6Y
5A
5Y
4A
4Y
1Y
1A
NC
VCC
6A
SN54LS14 . . . FK PACKAGE
(TOP VIEW)
3 2 1 20 19
18
17
16
15
14
9 10 11 12 13
6Y
NC
5A
NC
5Y
3Y
GND
NC
4Y
4A
2A
NC
2Y
NC
3A
NC No internal connection
ORDERING INFORMATION
PACKAGE
TA
TOP-SIDE
MARKING
Tube
SN7414N
SN7414N
Tube
SN74LS14N
SN74LS14N
Tube
SN7414D
SN7414DR
Tube
SN74LS14D
SN74LS14DR
SOP NS
SN7414NSR
SN7414
SSOP DB
SN74LS14DBR
LS14
Tube
SN5414J
SN5414J
Tube
SNJ5414J
SNJ5414J
Tube
SN54LS14J
SN54LS14J
Tube
SNJ54LS14J
SNJ54LS14J
Tube
SNJ5414W
SNJ5414W
Tube
SNJ54LS14W
SNJ54LS14W
Tube
SNJ54LS14FK
PDIP N
0C to 70C
ORDERABLE
PART NUMBER
SOIC D
CDIP J
55C to 125C
CFP W
LCCC FK
7414
LS14
SNJ54LS14FK
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2002, Texas Instruments Incorporated
SN5414, SN54LS14,
SN7414, SN74LS14
HEX SCHMITT-TRIGGER INVERTERS
SDLS049B DECEMBER 1983 REVISED FEBRUARY 2002
1Y
2A
2Y
3A
3Y
4A
4Y
5A
11
10
5Y
6A
13
12
6Y
Y=A
Pin numbers shown are for the D, DB, J, N, NS, and W packages.
SN5414, SN54LS14,
SN7414, SN74LS14
HEX SCHMITT-TRIGGER INVERTERS
SDLS049B DECEMBER 1983 REVISED FEBRUARY 2002
schematic
14
VCC
100
6 k
Output Y
Input A
GND
LS14
VCC
20 k
Output Y
Input A
GND
Resistor values shown are nominal.
SN5414, SN54LS14,
SN7414, SN74LS14
HEX SCHMITT-TRIGGER INVERTERS
SDLS049B DECEMBER 1983 REVISED FEBRUARY 2002
absolute maximum ratings over operating free-air temperature (unless otherwise noted)
Supply voltage, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Input voltage: 14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
LS14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Package thermal impedance, JA (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86C/W
DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96C/W
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80C/W
NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76C/W
Storage temperaturerange, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65C to 150C
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. Voltage values are with respect to network ground terminal.
2. The package termal impedance is calculated in accordance with JESD 51-7
Supply voltage
IOL
TA
MIN
NOM
4.5
SN7414
MIN
NOM
MAX
5.5
4.75
5.25
0.8
mA
16
mA
70
0.8
16
55
UNIT
MAX
125
TEST CONDITIONS
PARAMETER
MIN
TYP
UNIT
MAX
VT+
VT
VCC = 5 V
VCC = 5 V
1.5
1.7
0.6
0.9
1.1
Hysteresis
(VT+ VT)
VCC = 5 V
0.4
0.8
VIK
VOH
VCC = MIN,
VCC = MIN,
II = 12 mA
VI = 0.6 V,
VOL
IT+
VCC = MIN,
VCC = 5 V,
VI = 2 V,
VI = VT+
IT
II
VCC = 5 V,
VCC = MAX,
VI = VT
VI = 5.5 V
IIH
IIL
VCC = MAX,
VCC = MAX,
VIH = 2.4 V
VIL = 0.4 V
IOS
ICCH
VCC = MAX
V
1.5
IOH = 0.8 mA
IOL = 16 mA
2.4
3.4
0.2
V
0.4
0.43
mA
1
mA
40
1.2
mA
55
mA
22
36
mA
ICCL
39
For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
All typical values are at VCC = 5 V, TA = 25C.
Not more than one output should be shorted at a time.
60
mA
18
V
mA
0.56
0.8
VCC = MAX
VCC = MAX
SN5414, SN54LS14,
SN7414, SN74LS14
HEX SCHMITT-TRIGGER INVERTERS
SDLS049B DECEMBER 1983 REVISED FEBRUARY 2002
FROM
(INPUT)
TO
(OUTPUT)
tPLH
SN5414
SN7414
TEST CONDITIONS
MIN
RL = 400
,
tPHL
UNIT
TYP
MAX
15
22
15
22
CL = 15 pF
F
ns
SN74LS14
UNIT
MIN
NOM
MAX
MIN
NOM
MAX
4.5
5.5
4.75
5.25
VCC
IOH
Supply voltage
High-level output current
0.4
0.4
mA
IOL
TA
mA
70
55
125
TEST CONDITIONS
PARAMETER
SN74LS14
MIN TYP
MAX
UNIT
VT+
VT
VCC = 5 V
VCC = 5 V
1.4
1.6
1.9
1.4
1.6
1.9
0.5
0.8
0.5
0.8
Hysteresis
(VT+ VT)
VCC = 5 V
0.4
0.8
0.4
0.8
VIK
VOH
VCC = MIN,
VCC = MIN,
II = 18 mA
VI = 0.5 V,
2.5
3.4
2.7
3.4
VOL
VCC = MIN
MIN,
VI = 1.9
19V
IT+
IT
VCC = 5 V,
VCC = 5 V,
VI = VT+
VI = VT
II
IIH
VCC = MAX,
VCC = MAX,
VI = 7 V
VIH = 2.7 V
0.1
20
20
IIL
IOS
VCC = MAX,
VCC = MAX
VIL = 0.4 V
0.4
0.4
mA
100
mA
ICCH
ICCL
VCC = MAX
VCC = MAX
1.5
IOH = 0.4 mA
IOL= 4 mA
0.25
1.5
0.4
IOL = 8 mA
0.14
0.25
0.4
0.35
0.5
mA
0.1
20
V
mA
0.18
100
V
V
0.14
0.18
20
mA
8.6
16
8.6
16
mA
12
21
12
21
mA
TYP
MAX
15
22
15
22
For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
All typical values are at VCC = 5 V, TA = 25C.
Not more than one output should be shorted at a time, and duration of the short-circuit should not exceed one second.
FROM
(INPUT)
TO
(OUTPUT)
tPHL
TEST CONDITIONS
RL = 2 k
k,
CL = 15 pF
F
MIN
UNIT
ns
SN5414, SN54LS14,
SN7414, SN74LS14
HEX SCHMITT-TRIGGER INVERTERS
SDLS049B DECEMBER 1983 REVISED FEBRUARY 2002
VCC
RL
From Output
Under Test
CL
(see Note A)
CL
(see Note A)
High-Level
Pulse
1.5 V
S2
LOAD CIRCUIT
FOR 3-STATE OUTPUTS
3V
Timing
Input
1.5 V
1 k
Test
Point
LOAD CIRCUIT
FOR OPEN-COLLECTOR OUTPUTS
LOAD CIRCUIT
FOR 2-STATE TOTEM-POLE OUTPUTS
S1
(see Note B)
CL
(see Note A)
RL
(see Note B)
RL
From Output
Under Test
VCC
From Output
Under Test
Test
Point
1.5 V
0V
tw
Low-Level
Pulse
1.5 V
tsu
Data
Input
1.5 V
VOLTAGE WAVEFORMS
PULSE DURATIONS
1.5 V
1.5 V
In-Phase
Output
(see Note D)
tPHL
VOH
1.5 V
Out-of-Phase
Output
(see Note D)
0V
1.5 V
1.5 V
Waveform 1
(see Notes C
and D)
tPLZ
VOH
1.5 V
1.5 V
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
1.5 V
1.5 V
VOL
tPZH
tPLH
1.5 V
0V
tPZL
VOL
tPHL
1.5 V
3V
Output
Control
(low-level
enabling)
0V
tPLH
3V
1.5 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
3V
Input
th
Waveform 2
(see Notes C
and D)
VOL + 0.5 V
tPHZ
VOH
1.5 V
VOH 0.5 V
1.5 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS
SN5414, SN54LS14,
SN7414, SN74LS14
HEX SCHMITT-TRIGGER INVERTERS
SDLS049B DECEMBER 1983 REVISED FEBRUARY 2002
VCC
RL
(see Note B)
From Output
Under Test
CL
(see Note A)
High-Level
Pulse
1.3 V
S2
LOAD CIRCUIT
FOR 3-STATE OUTPUTS
3V
Timing
Input
1.3 V
5 k
Test
Point
LOAD CIRCUIT
FOR OPEN-COLLECTOR OUTPUTS
LOAD CIRCUIT
FOR 2-STATE TOTEM-POLE OUTPUTS
S1
(see Note B)
CL
(see Note A)
RL
CL
(see Note A)
RL
From Output
Under Test
VCC
From Output
Under Test
Test
Point
1.3 V
0V
tw
Low-Level
Pulse
1.3 V
tsu
0V
In-Phase
Output
(see Note D)
3V
1.3 V
1.3 V
0V
tPZL
tPLZ
tPHL
VOH
1.3 V
1.3 V
Waveform 1
(see Notes C
and D)
VOL
tPZH
tPLH
VOH
1.3 V
1.3 V
VOL
Waveform 2
(see Notes C
and D)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
1.5 V
1.3 V
VOL
tPHL
Out-of-Phase
Output
(see Note D)
1.3 V
0V
Output
Control
(low-level
enabling)
1.3 V
tPLH
1.3 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
3V
1.3 V
3V
Data
Input
1.3 V
VOLTAGE WAVEFORMS
PULSE DURATIONS
Input
th
VOL + 0.5 V
tPHZ
VOH
1.3 V
VOH 0.5 V
1.5 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS
SN5414, SN54LS14,
SN7414, SN74LS14
HEX SCHMITT-TRIGGER INVERTERS
SDLS049B DECEMBER 1983 REVISED FEBRUARY 2002
VCC = 5 V
1.70
1.69
1.68
1.67
1.66
1.65
1.64
1.63
1.62
1.61
1.60
VCC = 5 V
0.89
0.88
0.87
0.86
0.85
0.84
0.83
0.82
0.81
0.80
75 50
25
25
50
75
100
125
75 50
25
25
50
75
100
TA Free-Air Temperature C
TA Free-Air Temperature C
Figure 3
Figure 4
HYSTERESIS
vs
FREE-AIR TEMPERATURE
850
VCC = 5 V
840
V T+ V T Hysteresis mV
830
820
810
800
790
780
770
760
750
75 50
25
25
50
75
100
125
TA Free-Air Temperature C
Figure 5
Data for temperatures below 0C and above 70C and supply voltage below 4.75 V and above 5.25 V are applicable for SN5414 only.
125
SN5414, SN54LS14,
SN7414, SN74LS14
HEX SCHMITT-TRIGGER INVERTERS
SDLS049B DECEMBER 1983 REVISED FEBRUARY 2002
DISTRIBUTION OF UNITS
FOR HYSTERESIS
2.0
VCC = 5 V
TA = 25C
TA = 25C
1.8
Threshold Voltage - V
1.6
Positive-Going Threshold Voltage, VT+
1.4
1.2
1.0
0.8
740
760
780
800
820
840
860
880
900
5.25
5
4.75
VT+ VT Hysteresis mV
4.5
VT+ VT Hysteresis mV
Figure 6
Figure 7
OUTPUT VOLTAGE
vs
INPUT VOLTAGE
HYSTERESIS
vs
SUPPLY VOLTAGE
4
2.0
VCC = 5 V
TA = 25C
TA = 25C
1.8
VT
VT+
1.6
VO Output Voltage V
V T+ VT Hysteresis V
5.5
1.4
1.2
1.0
0.8
0.6
1
0.4
0.2
0
0
4.5
5
5.25
4.75
VCC Supply Voltage V
5.5
0.4
0.8
1.2
1.6
Figure 8
Figure 9
Data for temperatures below 0C and above 70C and supply voltage below 4.75 V and above 5.25 V are applicable for SN5414 only.
SN5414, SN54LS14,
SN7414, SN74LS14
HEX SCHMITT-TRIGGER INVERTERS
SDLS049B DECEMBER 1983 REVISED FEBRUARY 2002
VCC = 5 V
1.69
1.70
1.68
1.67
1.66
1.65
1.64
1.63
1.62
1.61
0.88
0.87
0.86
0.85
0.84
0.83
0.82
0.81
1.60
75 50
25
25
50
75
100
VCC = 5 V
0.89
0.80
125
0
25
50
75 100
25
TA Free-Air Temperature C
75 50
TA Free-Air Temperature C
125
Figure 11
Figure 10
HYSTERESIS
vs
FREE-AIR TEMPERATURE
DISTRIBUTION OF UNITS
FOR HYSTERESIS
850
V T+ VT Hysteresis V
VCC = 5 V
TA = 25C
VCC = 5 V
840
830
820
810
800
790
780
770
99% ARE
ABOVE
735 mV
760
750
75 50
25
25
50
75
100
125
TA Free-Air Temperature C
720
740
760
780
800
820
840
860
880
VT+ VT Hysteresis mV
Figure 12
Figure 13
Data for temperatures below 0C and above 70C and supply voltage below 4.75 V and above 5.25 V are applicable for SN5414 only.
10
SN5414, SN54LS14,
SN7414, SN74LS14
HEX SCHMITT-TRIGGER INVERTERS
SDLS049B DECEMBER 1983 REVISED FEBRUARY 2002
OUTPUT VOLTAGE
vs
INPUT VOLTAGE
2.0
4
VCC = 5 V
TA = 25C
TA = 25C
1.8
VT
VT+
1.4
VO Output Voltage V
Threshold Voltage V
1.6
1.2
Negative-Going Threshold Voltage, VT
1.0
0.8
Hysteresis, VT+ VT
0.6
1
0.4
0.2
0
0
4.5
4.75
5.25
5.5
0.4
0.8
1.2
1.6
VI Input Voltage V
Figure 15
Figure 14
Data for temperatures below 0C and above 70C and supply voltage below 4.75 V and above 5.25 V are applicable for SN5414 only.
11
SN5414, SN54LS14,
SN7414, SN74LS14
HEX SCHMITT-TRIGGER INVERTERS
SDLS049B DECEMBER 1983 REVISED FEBRUARY 2002
TTL System
VT+
VT
Input
CMOS
Sine-Wave
Oscillator
Output
Pulse Shaper
0.1 Hz to 10 MHz
VT+
330
VT
Input
Input
Output
Threshold Detector
Multivibrator
Open-Collector
Output
Input
Input
A
Output
Point A
Output
Pulse Stretcher
12
VT+
www.ti.com
3-Dec-2015
PACKAGING INFORMATION
Orderable Device
Status
(1)
Eco Plan
Lead/Ball Finish
(2)
(6)
(3)
Op Temp (C)
Device Marking
(4/5)
5962-9665801Q2A
ACTIVE
LCCC
FK
20
TBD
POST-PLATE
-55 to 125
59629665801Q2A
SNJ54LS
14FK
5962-9665801QCA
ACTIVE
CDIP
14
TBD
A42
-55 to 125
5962-9665801QC
A
SNJ54LS14J
5962-9665801QDA
ACTIVE
CFP
14
TBD
A42
-55 to 125
5962-9665801QD
A
SNJ54LS14W
5962-9665801VCA
OBSOLETE
CDIP
14
TBD
Call TI
Call TI
-55 to 125
5962-9665801VC
A
SNV54LS14J
5962-9665801VDA
ACTIVE
CFP
14
TBD
A42
-55 to 125
5962-9665801VD
A
SNV54LS14W
JM38510/31302BCA
ACTIVE
CDIP
14
TBD
A42
-55 to 125
JM38510/
31302BCA
M38510/31302BCA
ACTIVE
CDIP
14
TBD
A42
-55 to 125
JM38510/
31302BCA
SN5414J
ACTIVE
CDIP
14
TBD
A42
-55 to 125
SN5414J
SN54LS14J
ACTIVE
CDIP
14
TBD
A42
-55 to 125
SN54LS14J
SN7414D
ACTIVE
SOIC
14
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
7414
SN7414DG4
ACTIVE
SOIC
14
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
7414
SN7414DR
ACTIVE
SOIC
14
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
7414
SN7414N
ACTIVE
PDIP
14
25
Pb-Free
(RoHS)
CU NIPDAU
0 to 70
SN7414N
SN7414N3
OBSOLETE
PDIP
14
TBD
Call TI
Call TI
0 to 70
SN7414NE4
ACTIVE
PDIP
14
25
Pb-Free
(RoHS)
CU NIPDAU
0 to 70
Addendum-Page 1
SN7414N
Samples
www.ti.com
3-Dec-2015
Orderable Device
Status
(1)
Eco Plan
Lead/Ball Finish
(2)
(6)
(3)
Op Temp (C)
Device Marking
(4/5)
SN7414NSR
ACTIVE
SO
NS
14
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
SN7414
SN74LS14D
ACTIVE
SOIC
14
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
LS14
SN74LS14DBR
ACTIVE
SSOP
DB
14
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
LS14
SN74LS14DBRG4
ACTIVE
SSOP
DB
14
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
LS14
SN74LS14DE4
ACTIVE
SOIC
14
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
LS14
SN74LS14DG4
ACTIVE
SOIC
14
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
LS14
SN74LS14DR
ACTIVE
SOIC
14
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
LS14
SN74LS14DRE4
ACTIVE
SOIC
14
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
LS14
SN74LS14DRG4
ACTIVE
SOIC
14
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
LS14
SN74LS14N
ACTIVE
PDIP
14
25
Pb-Free
(RoHS)
CU NIPDAU
0 to 70
SN74LS14N
SN74LS14N3
OBSOLETE
PDIP
14
TBD
Call TI
Call TI
0 to 70
SN74LS14NE4
ACTIVE
PDIP
14
25
Pb-Free
(RoHS)
CU NIPDAU
0 to 70
SN74LS14N
SN74LS14NSR
ACTIVE
SO
NS
14
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
74LS14
SNJ5414J
ACTIVE
CDIP
14
TBD
A42
-55 to 125
SNJ5414J
SNJ5414W
ACTIVE
CFP
14
TBD
A42
-55 to 125
SNJ5414W
SNJ54LS14FK
ACTIVE
LCCC
FK
20
TBD
POST-PLATE
-55 to 125
59629665801Q2A
SNJ54LS
14FK
SNJ54LS14J
ACTIVE
CDIP
14
TBD
A42
-55 to 125
5962-9665801QC
A
SNJ54LS14J
Addendum-Page 2
Samples
www.ti.com
3-Dec-2015
Orderable Device
Status
(1)
SNJ54LS14W
ACTIVE
14
Eco Plan
Lead/Ball Finish
(2)
(6)
(3)
TBD
A42
Op Temp (C)
Device Marking
(4/5)
-55 to 125
5962-9665801QD
A
SNJ54LS14W
(1)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 3
Samples
www.ti.com
3-Dec-2015
Addendum-Page 4
14-Jul-2012
Device
SN7414DR
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
SOIC
14
2500
330.0
16.4
6.5
9.0
2.1
8.0
16.0
Q1
SN7414NSR
SO
NS
14
2000
330.0
16.4
8.2
10.5
2.5
12.0
16.0
Q1
SN74LS14DBR
SSOP
DB
14
2000
330.0
16.4
8.2
6.6
2.5
12.0
16.0
Q1
SN74LS14DR
SOIC
14
2500
330.0
16.4
6.5
9.0
2.1
8.0
16.0
Q1
SN74LS14NSR
SO
NS
14
2000
330.0
16.4
8.2
10.5
2.5
12.0
16.0
Q1
Pack Materials-Page 1
14-Jul-2012
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
SN7414DR
SOIC
14
2500
367.0
367.0
38.0
SN7414NSR
SO
NS
14
2000
367.0
367.0
38.0
SN74LS14DBR
SSOP
DB
14
2000
367.0
367.0
38.0
SN74LS14DR
SOIC
14
2500
367.0
367.0
38.0
SN74LS14NSR
SO
NS
14
2000
367.0
367.0
38.0
Pack Materials-Page 2
MECHANICAL DATA
MSSO002E JANUARY 1995 REVISED DECEMBER 2001
DB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
28 PINS SHOWN
0,38
0,22
0,65
28
0,15 M
15
0,25
0,09
8,20
7,40
5,60
5,00
Gage Plane
1
14
0,25
08
0,95
0,55
Seating Plane
2,00 MAX
0,10
0,05 MIN
PINS **
14
16
20
24
28
30
38
A MAX
6,50
6,50
7,50
8,50
10,50
10,50
12,90
A MIN
5,90
5,90
6,90
7,90
9,90
9,90
12,30
DIM
4040065 /E 12/01
NOTES: A.
B.
C.
D.
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