06rr410506 Fault Tolerant Systems

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Code No: RR410506 Set No. 1

IV B.Tech I Semester Regular Examinations, November 2006
FAULT TOLERANT SYSTEMS
( Common to Computer Science & Engineering and Electronics &
Computer Engineering)
Time: 3 hours Max Marks: 80
Answer any FIVE Questions
All Questions carry equal marks
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1. Define and derive the following terms in a system.
(a) MTTR [2+6]

(b) Hazard rate functions. [2+6]
2. (a) A circuit realizes the function.

Z=X1 X4 +X2 X3 +X1 X4
Using Boolean Difference method find the test vectors for SA0, SA1 faults on
all input lines of the circuit.
(b) What are the different properties of Boolean differences? Explain [5+5+6]
3. (a) Explain the 5MR Reconfiguration scheme. Explain in detail the function of
each block. [4+4]
(b) Discuss the 3 cases for which the 5MR system automatically reconfigure to
tolerate single and multiple faults. Explain each with an example. [3+3+2]
4. (a) What is the mechanism adopted in COPRA a fault Tolerant system. Explain
in detail.
(b) What is meant by Time redundancy? Explain. [4+4+4+4]

5
5. (a) Construct a self-checking code checker.
3
(b)
With neat block diagram explain in detail about self-checking realization of
n
. [8+8]
k
6. (a) Explain the design consideration of self checking PLA considering stray faults
with suitable example.
(b) How do you implement strong fault service for the functional PLA. [8+8]
7. (a) What are the draw backs of Reed-Muller expansion Technique.

(b) What is an unate function?
(c) Give the design procedure for a completely fault locatable networks for unate
function. [6+4+6]
8. (a) What is meant by built in test of VLSI? Explain.

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(b) Discuss the crosscheck approach to incorporate test circuitry into the basic
cells used in implement VLSI design. [8+8]
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1. (a) A computer system contains 10,000 components each with failure rate 0.5%
per 1000 hours. What is the period of 0.99 reliability of this system.
(b) What is meant by active repair time and passive repair time referred in main-
tainability of a system. Derive the expression for the MTTR. [6+3+3+4]
2. (a) A circuit realizes the function.

Z=X1 X4 +X2 X3 +X1 X4
Using Boolean Difference method find the test vectors for SA0, SA1 faults on
all input lines of the circuit.
(b) What are the different properties of Boolean differences? Explain [5+5+6]
3. Derive the Reliability factor of TMR and Triplicathd TMR systems. Show that
R(t) of Triplicated TMR is better than R(t) of TMR system. [5+5+6]
4. (a) What is the mechanism adopted in COPRA a fault Tolerant system. Explain
in detail.
(b) What is meant by Time redundancy? Explain. [4+4+4+4]
5. (a) What is the need for self checking circuits
(b) Design a totally self checking checker by using reddy’s partition method for
2out of 5 code. [6+10]
7. Explain the technique for designing minimally testable network which produces a
circuit which can be tested by three tests only.Modify the function f = A BC +A
B C into a circuit which has only three tests. [10+6]
8. (a) What is meant by circular BIST technique?

(b) Give a simplified configuration of circular BIST and explain. [8+8]
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1. (a) A computer system contains 10,000 components each with failure rate 0.5%
per 1000 hours. What is the period of 0.99 reliability of this system.
(b) What is meant by active repair time and passive repair time referred in main-
tainability of a system. Derive the expression for the MTTR. [6+3+3+4]
2. (a) Distinguish between fault detection and fault location [2+2]

(b) Illustrate the principles involved in fault table method of test generation using
the figure2b given below.Verify the above test vector, generated, with the help
of D-algorithm for C SAO fault. [12]
Figure 2b
3. (a) Explain fail soft-operation. [4]
(b) Explain the 5 MR reconfiguration mechanism and also explain how it care
tolerate single, double and Trible faults in a given system. [3x4=12]
4. (a) Explain in detail the practicle fault Tolerant space shuttle computer complex
system.
(b) What are the different ways to have software redundancy. [8+8]

7. (a) Explain three level OR-AND-OR design technique.

(b) Write a short note on adding control logic in to a combinational logic to have
only 5 test pattern. [8+8]
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8. (a) Explain pseudo-exhaustive pattern generation with example.
(b) Write the concept of autonomous design verification technique. [8+8]
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1. Define and derive the following terms in a system.
(a) MTBF [2+6]

(b) Failure rate. [2+6]
2. For the circuit shown as in figure 2 , derive
Figure 2
(a) minimal complete fixed scheduled fault detection experiment.
(b) minimal complete fixed scheduled fault location experiment. [8+8]
3. (a) Explain fail soft-operation. [4]

(b) Explain the 5 MR reconfiguration mechanism and also explain how it care
tolerate single, double and Trible faults in a given system. [3x4=12]
4. (a) What is the goal of “pluibus” system used in ARPA network. Explain its
working.
(b) What is ment by fail soft operation? What should a system have to achieve
the capability of fail soft operation. [4+4+4+4]

6. (a) Explain the advantages of PLA and how it is used as totally self-checking
circuit.
(b) For the given 4 input, 4 output function design a totally self checking checker
circuit using PLAs.
P [6+10]
f1 (A,B,C,D) = (0,2,3,7,8,10,12,13,15)
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P
f2 (A,B,C,D) = P (0,2,3,4,9,12,13,15)
f3 (A,B,C,D) = P (0,1,2,4,8,9,10,14)
f4 (A,B,C,D) = (0,1,2,4,5,6,8,11,14).
7. (a) What are the draw backs of Reed-Muller expansion Technique.

(b) What is an unate function?
(c) Give the design procedure for a completely fault locatable networks for unate
function. [6+4+6]
8. (a) Draw the structure of Built in Self Test for ult under test.
(b) Explain Exhaustive testing approach for BIST schemes. [8+8]
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06rr410506 Fault Tolerant Systems

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www.andhracolleges.

com The Complete Information About Colleges in Andhra Pradesh

Code No: RR410506 Set No. 1

1. Define and derive the following terms in a system.

(a) MTTR [2+6]

2. (a) A circuit realizes the function.

7. (a) What are the draw backs of Reed-Muller expansion Technique.

8. (a) What is meant by built in test of VLSI? Explain.

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Code No: RR410506 Set No. 1

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Code No: RR410506 Set No. 2

2. (a) A circuit realizes the function.

8. (a) What is meant by circular BIST technique?

Seminar Topics - Scholarships - Admission/Entrance Exam Notifications

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Code No: RR410506 Set No. 3

2. (a) Distinguish between fault detection and fault location [2+2]

5. (a) What is the need for self checking circuits

7. (a) Explain three level OR-AND-OR design technique.

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Code No: RR410506 Set No. 3

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Code No: RR410506 Set No. 4

1. Define and derive the following terms in a system.

(a) MTBF [2+6]

2. For the circuit shown as in figure 2 , derive

3. (a) Explain fail soft-operation. [4]

5. (a) What is the need for self checking circuits

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Code No: RR410506 Set No. 4

7. (a) What are the draw backs of Reed-Muller expansion Technique.

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