New materials are being integrated into High Volume Manufacturing (HVM) of semiconductor

ICs, while old materials are being extended with more stringent specifications. Defects
within materials cause yield losses in HVM fabs, and engineers must identify the specific
source of an observed defect before corrective steps can be taken. Honeywell Electronic
Materials has been using molecular modeling software provided by Scienomics to both
develop new materials and to modify old materials. Modeling allowed Honeywell to uncover
the origin of subtle solvation-based film defects within Bottom Anti-Reflective Coatings
(BARC) which were degrading yield in a customers lithographic process module.
Scienomics sponsored a Materials Modeling and Simulations online seminar on February
26th of this year, featuring Dr. Nancy Iwamoto of Honeywell discussing how Scienomics
software was used to accelerate response to a customers manufacturing yield loss. This
was a product running at a customer line, explained Iwamoto, and we needed to find the
solution. The product was a Bottom Anti-Reflective Coating (BARC) organo-silicate polymer
delivered in solution form and then spun on wafers to a precise thickness.
Originally observed during optical inspection by fab engineers as 1-2 micron sized vague
spots in the BARC, the new defect type was difficult to see yet could be correlated to
lithographic yield loss. The defects appeared to be discrete within the film instead of on the
top surface, so the source was likely some manner of particle, yet filters did not capture
these particles.
The filter captured some particles rich in silicon, as well as other particles rich in carbon.
Sequential filtration showed that particles were passing through impossibly small pores,
which suggested that the particles were built of deformable gel-like phases. The challenge
was to find the material handling or processing situation, which resulted in
thermodynamically possible and kinetically probable conditions that could form such gels.

Fig: Materials Processes and Simulations (MAPS) gives researchers access to visualization
and analysis tools in a single user interface together with access to multiple simulation
engines. (Source: Scienomics)

Molecular modeling and simulation is a powerful technique that can be used for materials
design, functional upgrades, process optimization, and manufacturing. The Figure shows a
dashboard for Scienomics modeling platform. Best practices in molecular modeling to find
out-of-control parameters in HVM include a sequential workflow:
Build correct models based on experimental observables,
Simulate potential molecular structures based on known chemicals and hierarchical
models,
Analyze manufacturing variabilities to identify excursion sources, and
Propose remedy for failure elimination.
Honeywell Electronic Materials researchers had very few experimental observables from
which to start: phenomenon is rare (yet effects yield), not filterable, yet from
thermodynamic hydrolysis parameters it must be quasi-stable. Re-testing of product and reexamination of Outgoing Quality Control (OQC) data at the Honeywell production site

showed that the molecular weight of the product was consistent with the desired
distribution. There was also an observed BARC thickness increase of ~1nm on the wafer
associated with the presence of these defects.
Using the modeling platform, Honeywell looked at the solubility parameters for different
small molecular chains off of known-branched back-bone centers. Gel-like agglomerations
could certainly be formed under the wrong conditions. Once the agglomerations form, they
are not very stable so they can probably dis-aggregate when being forced through a filter
and then re-aggregate on the other side.
What conditions could induce gel formation? After a few weeks of modeling, it was
determined that temperature variations had the greatest influence on the agglomeration,
and that variability was strongest at the ~250K recommended for storage. Storage at
230K resulted in measurably worse agglomeration, and any extreme in heating/cooling
ramp rate tended to reduce solubility.
Molecular modeling was used in a forensic manner to find that the root cause of gel-like
defects was related to thermal history:
* Thermodynamics determined the most likely oligomers that could agglomerate,
* Temperature-dependent solubility models determined which particles would reach wafers.
Because of the on-wafer BARC thickness increase of ~1nm, fab engineers could use all of
the molecular modeling information to trace the temperature variation to bottles installed in
the lithographic track tool. The fab was able to change specifications for the storage and
handling of the BARC bottles to bring the process back into control.
Tags: ARC, BARC, defect, fab, Honeywell, HVM, IC, inspection, lithography, materials, modeli
ng,molecular, Scienomics, Semiconductor, SST News, yield
Posted in Design, Top Stories | No Comments

EUV Resists and Stochastic Processes

Friday, March 4th, 2016

By Ed Korczynski, Sr. Technical Editor

In an exclusive interview with Solid State Technology during SPIE-AL this year, imec
Advanced Patterning Department Director Greg McIntyre said, The big encouraging thing at
the conference is the progress on EUV. The event included a plenary presentation by TSMC
Nanopatterning Technology Infrastructure Division Director and SPIE Fellow Anthony Yen on
EUV Lithography: From the Very Beginning to the Eve of Manufacturing. TSMC is currently
learning about EUVL using 10nm- and 7nm-node device test structures, with plans to deploy
it for high volume manufacturing (HVM) of contact holes at the 5nm node. Intel researchers
confirm that they plan to use EUVL in HVM for the 7nm node.

Recent improvements in EUV source technology 80W source power had been shown by the
end of 2014, 185W by the end of 2015, and 200W has now been shown by ASMLhave
been enabled by multiple laser pulses tuned to the best produce plasma from tin droplets.
TSMC reports that 518 wafers per day were processed by their ASML EUV stepper, and the
tool was available ~70% of the time. TSMC shows that a single EUVL process can create
46nm pitch lines/spaces using a complex 2D mask, as is needed for patterning the metal2
layer within multilevel on-chip interconnects.
To improve throughput in HVM, the resist sensitivity to the 13.54nm wavelength radiation of
EUV needs to be improved, while the line-width roughness (LWR) specification must be held
to low single-digit nm. With a 250W source and 25 mJ/cm2 resist sensitivity an EUV stepper
should be able to process ~100 wafer-per-hour (wph), which should allow for affordable use
when matched with other lithography technologies.
Researchers from Inpriathe company working on metal-oxide-based EUVL resistslooked
at the absorption efficiencies of different resists, and found that the absorption of the metal
oxide based resists was 4 to 5 times higher than that of the Chemically-Amplified Resist
(CAR). The Figure shows that higher absorption allows for the use of proportionally thinner
resist, which mitigates the issue of line collapse. Resist as thin as 18nm has been patterned
over a 70nm thin Spin-On Carbon (SOC) layer without the need for another Bottom AntiReflective Coating (BARC). Inpria today can supply 26 mJ/cm2 resist that creates 4.6nm LWR
over 140nm Depth of Focus (DoF).

To prevent pattern collapse, the thickness of resist is reduced proportionally to the minimum
half-pitch (HP) of lines/spaces. (Source: JSR Micro)
JEIDEC researchers presented their summary of the trade-off between sensitivity and LWR
for metal-oxide-based EUV resists: ultra high sensitivity of 7 mJ/cm2 to pattern 17nm lines
with 5.6nm LWR, or low sensitivity of 33 mJ/cm2 to pattern 23nm lines with 3.8nm LWR.
In a keynote presentation, Seong-Sue Kim of Samsung Electronics stated that, Resist
pattern defectivity remains the biggest issue. Metal-oxide resist development needs to be
expedited. The challenge is that defectivity at the nanometer-scale derives from
stochastics, which means random processes that are not fully predictable.
Stochastics of Nanopatterning
Anna Lio, from Intels Portland Technology Development group, stated that the challenges of
controlling resist stochastics, could be the deal breaker. Intel ran a 7-month test of vias
made using EUVL, and found that via critical dimensions (CD), edge-placement-error (EPE),
and chain resistances all showed good results compared to 193i. However, there are
inherent control issues due to the random nature of phenomena involved in resist
patterning: incident photons, absorption, freed electrons, acid generation, acid
quenching, protection groups, development processes, etc.
Stochastics for novel chemistries can only be controlled by understanding in detail the
sources of variability. From first-principles, EUV resist reactions are not photon-chemistry,
but are really radiation-chemistry with many different radiation paths and electrons which
can be generated. If every via in an advanced logic IC must work then the failure rate must
be on the order of 1 part-per-trillion (ppt), and stochastic variability from non-homogeneous
chemistries must be eliminated.
Consider that for a CAR designed for 15mJ/cm2 sensitivity, there will be just:
145 photons/nm2 for 193, and
10 photons/nm2 for EUV.
To improve sensitivity and suppress failures from photon shot-noise, we need to increase
resist absorption, and also re-consider chemical amplification mechanisms. The

requirements will be the same for any resist and any chemistry, reminded Lio. We need to
evaluate all resists at the same exposure levels and at the same rules, and look at different
features to show stochastics like in the tails of distributions. Resolution is important but
stochastics will rule our world at the dimensions were dealing with.
E.K.
Tags: 10nm, 14nm, 22nm, 5nm, 7nm, advanced, control, EUV, EUVL, HVM, IC, Imec, Intel, lit
ho,lithography, mask, node, patterning, random, resist, resolution, Samsung, sensitivity, SPI
E-AL, SST Top Story Right, stochastic, TSMC
Posted in Design, Top Stories | No Comments

Many Mixes to Match Litho Apps

Thursday, March 3rd, 2016

By Ed Korczynski, Sr. Technical Editor

Mix and Match has long been a mantra for lithographers in the deep-sub-wavelength era
of IC device manufacturing. In general, forming patterns with resolution at minimum pitch as
small as 1/4 the wavelength of light can be done using off-axis illumination (OAI) through
reticle enhancement techniques (RET) on masks, using optical proximity correction (OPC)
perhaps derived from inverse lithography technology (ILT). Lithographers can form 40-45nm
wide lines and spaces at the same half-pitch using 193nm light (from ArF lasers) in a single
exposure.
Figure 1 shows that application-specific tri-layer photoresists are used to reach the
minimum resolution of 193nm-immersion (193i) steppers in a single exposure. Tighter halfpitch features can be created using all manner of multi-patterning processes, including
Litho-Etch-Litho-Etch (LELE or LE2) using two masks for a single layer or Self-Aligned Double
Patterning (SADP) using sidewall spacers to accomplish pitch-splitting. SADP has been used
in high volume manufacturing (HVM) of logic and memory ICs for many years now, and SelfAligned Quadruple Patterning (SAQP) has been used in HVM by at least one leading memory
fab.

Fig.1: Basic tri-layer resist (TLR) technology uses thin Photoresist over silicon-containing
Hard-Mask over Spin-On Carbon (SOC), for patterning critical layers of advanced ICs.
(Source: Brewer Science)

Next-Generation Lithography (NGL) generally refers to any post-optical technology with at

least some unique niche patterning capability of interest to IC fabs: Extreme Ultra-Violet
(EUV), Directed Self-Assembly (DSA), and Nano-Imprint Lithography (NIL). Though
proponents of each NGL have dutifully shown capabilities for targeted mask layers for logic
or memory, the capabilities of ArF dry and immersion (ArFi) scanners to process >250
wafers/hour with high uptime dominates the economics of HVM lithography.
The worlds leading lithographers gather each year in San Jose, California at SPIEs Advanced
Lithography conference to discuss how to extend optical lithography. So of all the NGL
technologies, which will win out in the end?
It is looking most likely that the answer is all of the above. EUV and NIL could be used for
single layers. For other unique patterning application, ArF/ArFi steppers will be used to
create a basic grid/template which will be cut/trimmed using one of the available NGL. Each
mask layer in an advanced fab will need application-specific patterning integration, and one
of the rare commonalities between all integrated litho modules is the overwhelming need to
improve pattern overlay performance.
Naga Chandrasekaran, Micron Corp. vice president of Process R&D, provided a fantastic
overview of the patterning requirements for advanced memory chips in a presentation
during Nikons LithoVision technical symposium held February 21st in San Jose, California
prior to the start of SPIE-AL. While resolution improvements are always desired, in the mixand-match era the greatest challenges involve pattern overlay issues. In high volume
manufacturing, every nanometer variation translates into yield loss, so what is the best
overlay that we can deliver as a holistic solution not just considering stepper resolution?
asks Chandrasekaran. We should talk about cost per nanometer overlay improvement.
Extreme Ultra-Violet (EUV)
As touted by ASML at SPIE-AL, the brightness and stability and availability of tin-plasma EUV
sources continues to improve to 200W in the lab for one hour, with full dose control,
according to Michael Lercel, ASMLs director of strategic marketing. ASMLs new TWINSCAN
NXE:3350B EUVL scanners are now being shipped with 125W power sources, and Intel and
Samsung Electronics reported run their EUV power sources at 80W over extended periods.
During Nikons LithoVision event, Mark Phillips, Intel Fellow and Director of Lithography
Technology Development for Logic, summarized recent progress of EUVL technology: ~500
wafers-per-day is now standard, and ~1000 wafer-per-day can sometimes happen. However,
since grids can be made with ArFi for 1/3 the cost of EUVL even assuming best productivity
for the latter, ArFi multi-patterning will continue to be used for most layers. Resolution is
not the only challenge, reminded Phillips. Total edge-placement-error in patterning is the
biggest challenge to device scaling, and this limit comes before the device physics limit.
Directed Self-Assembly (DSA)
DSA seems most suited for patterning the periodic 2D arrays used in memory chips such as
DRAMs. Virtual fabrication using directed self-assembly for process optimization in a 14nm
DRAM node was the title of a presentation at SPIE-AL by researchers from Coventor, in
which DSA compared favorably to SAQP.
Imec presented electrical results of DSA-formed vias, providing insight on DSA processing
variations altering device results. In an exclusive interview with Solid State
Technology and SemiMD, imecs Advanced Patterning Department Director Greg McIntyre
reminds us that DSA could save one mask in the patterning of vias which can all be
combined into doublets/triplets, since two masks would otherwise be needed to use 193i to
do LELE for such a via array. There have been a lot of patterning tricks developed over the
last few years to be able to reduce variability another few nanometers. So all sorts of selfalignments.

While DSA can be used for shrinking vias that are not doubled/tripled, there are
commercially proven spin-on shrink materials that cost much less to use as shown by Kaveri
Jain and Scott Light from Micron in their SPIE-AL presentation, Fundamental characterization
of shrink techniques on negative-tone development based dense contact holes. Chemical
shrink processes primarily require control over times, temperatures, and ambients inside a
litho track tool to be able repeatably shrink contact hole diameters by 15-25 nm.
Nano-Imprint Litho (NIL)
For advanced IC fab applications, the many different options for NIL technology have been
narrowed to just one for IC HVM. The step-and-pattern technology that had been developed
and trademarked as Jet and Flash Imprint Lithography or J-FIL by, has been
commercialized for HVM by Canon NanoTechnologies, formerly known as Molecular Imprints.
Canon shows improvements in the NIL mask-replication process, since each production mask
will need to be replicated from a written master. To use NIL in HVM, mask image placement
errors from replication will have to be reduced to ~1nm., while the currently available
replication tool is reportedly capable of 2-3nm (3 sigma).
Figure 2 shows normalized costs modeled to produce 15nm half-pitch lines/spaces for
different lithography technologies, assuming 125 wph for a single EUV stepper and 60 wph
for a cluster of 4 NIL tools. Key to throughput is fast filling of the 26mmx33mm mold nanocavities by the liquid resist, and proper jetting of resist drops over a thin adhesion layer
enables filling times less than 1 second.

Fig.2: Relative estimated costs to pattern 15nm half-pitch lines/spaces for different
lithography technologies, assuming 125 wph for a single EUV stepper and 60 wph for a
cluster of 4 NIL tools. (Source: Canon)
Researchers from Toshiba and SK Hynix described evaluation results of a long-run defect test
of NIL using the Canon FPA-1100 NZ2 pilot production tool, capable of 10 wafers per hour
and 8nm overlay, in a presentation at SPIE-AL titled, NIL defect performance toward high-

volume mass production. The team categorized defects that must be minimized into
fundamentally different categoriestemplate, non-filling, separation-related, and pattern
collapseand determined parallel paths to defect reduction to allow for using NIL in HVM of
memory chips with <20nm half-pitch features.
E.K.
Tags: 193, 193i, advanced, application-specific, ArF, ArFi, ASML, DSA, EUV, EUVL, HVM, IC, IL
T, Imec,integration, Intel, LELE, litho, lithography, Micron, module, multi-pattern, NGL, OPC,
optical, pattern,process, R&D, resist, RET, SADP, SAQP, SPIE-AL, SST News, tri-layer
Posted in Design, Top Stories | No Comments

Measuring 5nm Particles In-Line

Monday, November 30th, 2015
By Ed Korczynski, Sr. Technical Editor
Industrial Technology Research Institute (ITRI) (https://www.itri.org.tw/) worked with TSMC
(http://www.tsmc.com) in Taiwan on a clever in-line monitor technology that transforms
liquids and automatically-diluted-slurries into aerosols for subsequent airborn
measurements. They call this SuperSizer technology, and claim that tests have shown
resolution over the astounding range of 5nm to 1 micron, and with ability to accurately
represent size distributions over that range. Any dissolved gas bubbles in the liquid are lost
in the aerosol process, which allows the tool to unambiguously count solid impurities. The
Figure shows the compact components within the tool that produce the aerosol.

Aerosol sub-system inside SuperSizer in-line particle sizing tool co-developed by

ITRI/TSMC. (Source: ITRI)
Semiconductor fabrication (fab) lines require in-line measurement and control of particles in
critical liquids and slurries. With the exception of those carefully added to chemicalmechanical planarization (CMP) slurries, most particles in fabs are accidental yield-killers

that must be kept to an absolute minimum to ensure proper yield in IC fabs, and ever
decreasing IC device feature sizes result in ever smaller particles that can kill a chip.
Standard in-line tools to monitor particles rely on laser scattering through the liquid, and
such technology allows for resolution of particle sizes as small as 40nm. Since we cannot
control what we cannot measure, the IC fab industry needs this new ability to measure
particles as small as 5nm for next-generation manufacturing.
There are two actual measurement technologies used downstream of the SuperSizer aerosol
module: a differential mobility analyzer (DMA), and a condensation particle counter (CPC).
The aerosol first moves through the DMA column, where particle sizes are measured based
on the force balance between air flow speed in the axial direction and an electric field in the
radial direction. The subsequent CPC then provides particle concentration data.
Combining both data streams properly allows for automated output of information on
particle sizes down to 5nm, size distributions, and impurity concentrations in liquids. Since
the tool is intended for monitoring semiconductor high-volume manufacturing (HVM), the
measurement data is automatically categorized, analyzed, and reported according to the
needs of the fabs automated yield management system. Users can edit the measurement
sequences or recipes to monitor different chemicals or slurries under different conditions
and schedules.
When used to control a CMP process, the SuperSizer can be configured to measure not just
impurities but also the essential slurry particles themselves. During dilution and
homogeneous mixing of the slurry prior to aerosolization, mechanical agitation needs to be
avoided so as to prevent particle agglomeration which causes scratch defects. This new tool
uses pressured gas as the driving force for solution transporting and mixing, so that any
measured agglomeration in the slurry can be assigned to a source somewhere else in the
fab.
TSMC has been using this tool since 2014 to measure particles in solutions including slurries,
chemicals, and ultra-pure water. ITRI, which owns the technology and related patents, can
now take orders to manufacture the product, but the research organization plans to license
the technology to a company in Taiwan for volume manufacturing. EETimes reports
(http://www.eetimes.com/document.asp?doc_id=1328283) that the current list price for a
tool capable of monitoring ultra-pure water is ~US$450k, while a fully-configured tool for
CMP monitoring would cost over US$700k.
E.K.
Tags: 5nm, aerosol, CMP, control, fab, HVM, IC, in-line, ITRI, liquid, manufacturing, measurin
g,monitoring, node, particles, R&D, slurry, SST News, technology, TSMC
Posted in Design, News Stories | No Comments

Managing Dis-Aggregated Data for SiP Yield Ramp

Monday, August 24th, 2015

By Ed Korczynski, Sr. Technical Editor

In general, there is an accelerating trend toward System-in-Package (SiP) chip designs
including Package-On-Package (POP) and 3D/2.5D-stacks where complex mechanical forces

primarily driven by the many Coefficient of Thermal Expansion (CTE) mismatches within
and between chips and packagesinfluence the electrical properties of ICs. In this era, the
industry needs to be able to model and control the mechanical and thermal properties of the
combined chip-package, and so we need ways to feed data back and forth between
designers, chip fabs, and Out-Sourced Assembly and Test (OSAT) companies. With
accelerated yield ramps needed for High Volume Manufacturing (HVM) of consumer mobile
products, to minimize risk of expensive Work In Progress (WIP) moving through the supply
chain a lot of data needs to feed-forward and feedback.
Calvin Cheung, ASE Group Vice President of Business Development & Engineering, discussed
these trends in the Scaling the Walls of Sub-14nm Manufacturing keynote panel
discussion during the recent SEMICON West 2015. In the old days it used to take 12-18
months to ramp yield, but the product lifetime for mobile chips today can be only 9 months,
reminded Cheung. In the old days we used to talk about ramping a few thousand chips,
while today working with Qualcomm they want to ramp millions of chips quickly. From an
OSAT point of view, we pride ourselves on being a virtual arm of the manufacturers and
designers, said Cheung, but as technology gets more complex and knowledge-basecentric we see less release of information from foundries. We used to have larger teams in
foundries. Dick James of ChipWorks details the complexity of the SiP used in the Apple
Watch in his recent blog post at SemiMD, and documents the details behind the assumption
that ASE is the OSAT.
With single-chip System-on-Chip (SoC) designs the final test can be at the wafer-level, but
with SiP based on chips from multiple vendors the final test now must happen at the
package-level, and this changes the Design For Test (DFT) work flows. DRAM in a 3D stack
(Figure 1) will have an interconnect test and memory Built-In Self-Test (BIST) applied from
BIST resident on the logic die connected to the memory stack using Through-Silicon Vias
(TSV).

Fig.1: Schematic cross-sections of different 3D System-in-Package (SiP) design types.

(Source: Mentor Graphics)

The test of dice in a package can mostly be just re-used die-level tests based on
hierarchical pattern re-targeting which is used in many very large designs today, said Ron
Press, technical marketing director of Silicon Test Solutions, Mentor Graphics, in discussion
with SemiMD. Additional interconnect tests between die would be added using boundary
scans at die inputs and outputs, or an equivalent method. We put together 2.5D and 3D
methodologies that are in some of the foundry reference flows. It still isnt certain if
specialized tests will be required to monitor for TSV partial failures.
Many fabless semiconductor companies today use solutions like scan test diagnosis to
identify product-specific yield problems, and these solutions require a combination of test
fail data and design data, explained Geir Edie, Mentor Graphics product marketing
manager of Silicon Test Solutions. Getting data from one part of the fabless organization to
another can often be more challenging than what one should expect. So, whats often
needed is a set of best practices that covers the entire yield learning flow across
organizations.
We do need a standard for structuring and transmitting test and operations meta-data in a
timely fashion between companies in this relatively new dis-aggregated semiconductor
world across Fabless, Foundry, OSAT, and OEM, asserted John Carulli, GLOBALFOUNDRIES
deputy director of Test Development & Diagnosis, in an exclusive discussion with SemiMD.
Presently the databases are still proprietary either internal to the company or as part of
third-party vendors applications. Most of the test-related vendors and users are supporting
development of the new Rich Interactive Test Database (RITdb) data format to replace
the Standard Test Data Format (STDF) originally developed by Teradyne.
The collaboration across the semiconductor ecosystem placed features in RITdb that
understand the end-to-end data needs including security/provenance, explained
Carulli. Figure 2 shows that since RITdb is a structured data construct, any data from
anywhere in the supply chain could be easily communicated, supported, and scaled
regardless of OSAT or Fabless customer test program infrastructure. If RITdb is truly
adopted and some certification system can be placed around it to keep it from diverging,
then it provides a standard core to transmit data with known meaning across our disaggregated semiconductor world. Another key part is the Test Cell Communication Standard
Working Group; when integrated with RITdb, the improved automation and control path
would greatly reduce manually communicated understanding of operational practices/issues
across companies that impact yield and quality.

Fig.2: Structure of the Rich Interactive Test Database (RITdb) industry standard, showing how
data can move through the supply chain. (Source: Texas Instruments)
Phil Nigh, GLOBALFOUNDRIES Senior Technical Staff, explained to SemiMD that for
heterogeneous integration of different chip types the industry has on-chip temperature
measurement circuits which can monitor temperature at a given time, but not necessarily
identify issues cause by thermal/mechanical stresses. During production testing, we should
detect mechanical/thermal stress failures using product testing methods such as IO
leakage, chip leakage, and other chip performance measurements such as FMAX, reminded
Nigh.
Model but verify
Metrology tool supplier Nanometrics has unique perspective on the data needs of 3D
packages since the company has delivered dozens of tools for TSV metrology to the world.
The companys UniFire 7900 Wafer-Scale Packaging (WSP) Metrology System uses white-light
interferometry to measure critical dimensions (CD), overlay, and film thicknesses of TSV,
micro-bumps, Re-Distribution Layer (RDL) structures, as well as the co-planarity of Cu
bumps/pillars. Robert Fiordalice, Nanometrics Vice President of UniFire business group,
mentioned to SemiMD in an exclusive interview that new TSV structures certainly bring
about new yield loss mechanisms, even if electrical tests show standard results such as
partial open. Fiordalice said that, weve had a lot of pull to take our TSV metrology tool,
and develop a TSV inspection tool to check every via on every wafer. TSV inspection tools
are now in beta-tests at customers.
As reported at 3Dincites, Mentor Graphics showed results at DAC2015 of the use of Calibre
3DSTACK by an OSAT to create a rule file for their Fan-Out Wafer-Level Package (FOWLP)
process. This rule file can be used by any designer targeting this package technology at this
assembly house, and checks the manufacturing constraints of the package RDL and the
connectivity through the package from die-to-die and die-to-BGA. Based on package
information including die order, x/y position, rotation and orientation, Calibre 3DSTACK
performs checks on the interface geometries between chips connected using bumps, pillars,
and TSVs. An assembly design kit provides a standardized process both chip design
companies and assembly houses can use to ensure the manufacturability and performance
of 3D SiP.
E.K.
Tags: 3D, advanced, Assembly, BiST, chip, CTE, design, DFM, DFT, die, EDA, fab, foundry,Glo
balFoundries, heterogeneous, HVM, IC, inspection, integration, manufacturing, Mentor
Graphics,metrology, Nanometrics, OSAT, package, ramp, RDL, RITdb, SEMI, SEMICON, Silicon
, SiP, SST News,test, TSV, wafer, yield
Posted in Design, Top Stories | No Comments

Technologies for Advanced Systems Shown at IMEC Tech Forum USA

Tuesday, July 14th, 2015

By Ed Korczynski, Sr. Technical Editor

Luc Van den hove, president and CEO, imec opened the Imec Technology Forum USA in San
Francisco on July 13 by reminding us of the grand vision and motivation behind the work of
our industry to empower individuals with micro- and nano-technologies in his talk, From the
happy few to the happy many. While the imec consortium continues to lead the world in
pure materials engineering and device exploration, they now work on systems-integration

complexities with over 100 applications partners from agriculture, energy, healthcare, and
transportation industries.
We are now living in an era where new chip technologies require trade-offs between power,
performance, and bandwidth, and such trade-offs must be carefully explored for different
applications spaces such as cloud clusters or sensor nodes. An Steegen, senior vice
president process technology, imec, discussed the details of new CMOS chip extensions as
well as post-CMOS device possibilities for different applications spaces in her presentation
on Technology innovation: an IoT era. EUV lithography technology continues to be
developed, targeting a single-exposure using 0.33 Numerical Aperture (NA) reflective lenses
to pattern features as small as 18nm half-pitch, which would meet the Metal1 density
specifications for the industrys so-called 7nm node. Patterning below 12nm half-pitch
would seem to need higher-NA which is not an automatic extension of current EUV
technology.
So while there is now some clarity regarding the pre-competitive process-technologies that
will be needed to fabricate next-generation device, there is less clarity regarding which new
device structures will best serve the needs of different electronics applications. CMOS finFETs
using strained silicon-doped-with-Germanium Si(Ge) will eventually be replaced by gate-allaround (GAA) nano-wires (NW) using alternate-channel materials (ACM) with higher
mobilities such as Ge and indium-gallium-arsenide (InGaAs). While many measures of CMOS
performance improve with scaling to smaller dimensions, eventually leakage current and
parasitic capacitances will impede further progress.
Figure 1 shows a summary of energy-vs.-delay analyses by imec for all manner of devices
which could be used as switches in logic arrays. Spin-wave devices such as spin-transfertorque RAM (STT-RAM) can run at low power consumption but are inherently slower than
CMOS devices. Tunnel-FET (TFET) devices can be as fast or faster than CMOS while running
at lower operating power due to reduced electrostatics, leading to promising R&D work.

Fig.1: Energy vs. delay for various logic switches. (Source: imec)
In an exclusive interview, Steegen explained how the consortium balances the needs of all
partners in R&D, When you try to predict future roadmaps you prefer to start from the
mainstream. Trying to find the mainstream, so that customers can build derivatives from
that, is what imec does. Were getting closer to systems, and systems are reaching down to

technology, said Steegen. We reach out to each other, while we continue to be experts in
our own domains. If Im inserting future memory into servers, the system architecture needs
to change so we need to talk to the systems people. Its a natural trend that has evolved.
Network effects from the cloud and from future smart IoT nets require high-bandwidth and
so improved electrical and optical connections at multiple levels are being explored at imec.
Joris Van Campenhout, program director optical I/O, imec, discussed Scaling the cloud using
silicon photonics. The challenge is how to build a 100Gb/s bandwidth in the near term, and
then scale to 400G and then 1.6T though parallelism of wavelength division multiplexing;
the best results to date for a transmitter and receiver reach 50Gb/s. By leveraging the
existing CMOS manufacturing and 3-D assembly infrastructure, the hybrid CMOS silicon
photonics platform enables high integration density and reduced power consumption, as
well as high yield and low manufacturing cost. Supported by EDA tools including those from
Mentor Graphics, there have been 7 tape-outs of devices in the last year using a Process
Design Kit (PDK). When combined with laser sources and a 40nm node foundry CMOS chip, a
complete integrated solution exists. Arrays of 50Gb/s structures can allow for 400Gb/s
solutions by next year, and optical backplanes for server farms in another few years.
However, to bring photonics closer to the chip in an optical interposer will require radical
new new approaches to reduce costs, including integration of more efficient laser arrays.
Alexander Mityashin, project manager thin film electronics, imec, explained why we need,
thin film electronics for smart applications. There are billions of items in our world that
could be made smarter with electronics, provided we can use additive thin-film processes to
make ultra-low-cost thin-film transistors (TFT) that fit different market demands. Using
amorphous indium-gallium-zinc-oxide (a-IGZO) deposited at low-temperature as the active
layer on a plastic substrate, imec has been able to produce >10k TFTs/cm2 using just 4-5
lithography masks. Figure 2 shows these TFT integrated into a near-field communications
(NFC) chip as first disclosed at ISSCC earlier this year in the paper, IGZO thin-film transistor
based flexible NFC tags powered by commercial USB reader device at 13.56MHz. Working
with Panasonic in 2013, imec showed a flexible organic light-emitting diode (OLED) display
of just 0.15mm thickness that can be processed at 180C. In collaboration with the Holst
Center, they have worked on disposable flexible sensors that can adhere to human skin.

Fig.2: Thin-Film Transistors (TFT) fabricated on plastic using Flat Panel Display (FPD)
manufacturing tools. (Source: imec/Holst Center)

Jim ONeill, Chief Technology Officer of Entegris, expanded on the systems-level theme of the
forum in his presentation on Putting the pieces together Materials innovation in a
disruptive environment. With so many additional materials being integrated into new
device structures, there are inherently new yield-limiting defect mechanisms that will have
to be controlled. With demand for chips now being driven primarily by high-volume
consumer applications, the time between first commercial sample and HVM has compressed
such that greater coordination is needed between device, equipment, and materials
companies. For example, instead of developing a wet chemical formulation on a tool and
then optimizing it with the right filter or dispense technology, the Process Engineer can start
envisioning a bottle-to-nozzle wetted surface solution. By considering not just the intended
reactions on the wafer but the unintended reactions that can occur up-steam and downstream of the process chamber, full solutions to the semiconductor industrys most
challenging yield problems can be more quickly found.
E.K.
Tags: 3D, ACM, CMOS, EUV, finFET, GAA, Ge, Germanium, HVM, IGZO, Imec, IoT, lithography,
materials, nW, photonics, Si, Silicon, SST News, TFET, TFT
Posted in Design, Top Stories | 1 Comment

Applied Materials Olympia ALD Spins Powerful New Capabilities

Monday, July 13th, 2015

By Ed Korczynski, Sr. Technical Editor

Applied Materials today unveiled the Applied Olympia ALD system, using thermal sequentialALD technology for the high-volume manufacturing (HVM) of leading-edge 3D memory and
logic chips. Strictly speaking this is a mini-batch tool, since four 300mm wafers are loaded
onto a turn-table in the chamber that continuously rotates through four gas-isolated modular
processing zones. Each zone can be configured to flow any arbitrary ALD precursor or to
exposure the surface to Rapid-Thermal-Processing (RTP) illumination, so an extraordinary
combination of ALD processes can be run in the tool. What are the applications that will
result from this? We dont know yet because the world has never before had a tool which
could provide these capabilities, said David Chu, Strategic Marketing, Applieds Dielectric
Systems and Modules group.

Fig.1: The four zones within the Olympia sequential-ALD chamber can be configured to use
any combination of precursors or treatments. (Source: Applied Materials)
Figure 1 shows that in addition to a high-throughput simple ALD process such that wafers
would rotate through A-B-A-B precursors in sequence, or zones configured in an A-B-C-B
sequence to produce a nano-laminate such as Zirconia-Alumina-Zirconia (ZAZ), almost any
combination of pre- and post-treatments can be used. The gas-panel and chemical source
sub-systems in the tool allow for the use up to 4 precursors. Consequently, Olympia opens
the way to depositing the widest spectrum of next-generation atomic-scale conformal films
including advanced patterning films, higher- and lower-k dielectrics, low-temperature films,
and nano-laminates.
The Olympia system overcomes fundamental limitations chipmakers are experiencing with
conventional ALD technologies, such as reduced chemistry control of single-wafer solutions
and long cycle times of furnaces, Dr. Mukund Srinivasan, vice president and general
manager of Applieds Dielectric Systems and Modules group. Because of this, were seeing
strong market response, with Olympia systems installed at multiple customers to support
their move to 10nm and beyond. Future device structures will need more and more
conformal ALD, as new materials will have to coat new 3D features.
When engineering even-smaller structures using ALD, thermal budgets inherently decrease
to prevent atomic inter-diffusion. Compared to thermal ALD, Plasma-Enhanced ALD (PEALD)
functions at reduced temperatures but tend to induce impurities in the film because of
excess energy in the chamber. The ability of Olympia to do RTP for each sequentially
deposited atomic-layer leads to final film properties that are inherently superior in
defectivity levels to PEALD films at the same thermal budget: alumina, silica, silicon-nitride,
titania, and titanium-nitride depositions into high aspect-ratio structures have been shown.
Purging (from the tool) pump-purge

Fab engineers who have to deal with ALD technologyfrom process to facilitiesshould be
very happy working with Olympia because the precursors flow through the chamber
continuously instead of having to use the pump-purge sequences typical of single-wafer and
mini-batch ALD tools used for IC fabrication. Pump-purge sequences in ALD tools result in
the following wastes:
* Wasted chemistry since tools generally shunt precursor-A past the chamber directly to the
pump-line when precursor-B is flowing and vice-versa,
* More wasted chemistry because the entire chamber gets coated along with the wafer,
* Wasted cleaning chemistry during routine chamber and pump preventative-maintenance,
* Wasted downtime to clean the chamber and pump, and
* Wasted device yield because precursors flowing in the same space at different times can
accidentally overlap and create defects.
Today there are chemistries that are more or less compatible with tools, reminded Chu.
When you try to use less-compatible chemistries, the purge times in single-wafer tools
really begin to reduce the productivity of the process. There are chemistries out there today
that would be desirable to use that are not pursued due to the limitations of pump-purge
chambers.
E.K.
Tags: 300mm, ALD, AMAT, Applied Materials, atomic layer
deposition, control, HVM, IC, materials, mini-batch, nano-laminate, PEALD, productivity, RTP,
Semiconductor, sequential-ALD, SST Top Story Left,temperature
Posted in Top Stories | No Comments

EMC2015 New Devices, Old Tricks

Tuesday, June 30th, 2015
By Ed Korczynski, Sr. Technical Editor
The 57th annual Electronic Materials Conference (http://www.mrs.org/57th-emc/), held June
24-26 in Columbus, Ohio, showcased research and development (R&D) of new device
structures, as well as new insights into the process-structure-properties relationships of
electronic devices now running in high-volume manufacturing (HVM) lines globally. A
plethora of papers on compound-semiconductor quantum-dots and nanorods, LEDs and
quantum-dot detectors, power electronics, and flexible and bio-compatible devices all show
that innovation will not slow down despite the limitations of Dennard Scaling and Moores
Law. With 3D stacking of existing devices on novel substrates an ongoing integration
challenge for HVM, the conference also explored substrate engineering and 3D stacking
technologies.
CEA-Letis Smart-cut technology has been used for over 20 years to cleave crystalline
layers for transfer and bonding to stack substrate functionalities, such as Silicon-OnInsulator (SOI) wafers. Researchers from Leti looked at the discrete steps involved in the
hydrogen implantation, annealing to create the buried plane of micro-bubbles within the
crystal, and then the acoustic wave that travels through the plane to complete the cleave. A
periodic wave pattern is dynamically generation during cleaving, with the evolving
wavefront dependent upon the contribution of all the past fracture fronts to any particular
point. The cleaved roughness is related to the speed of the fracture wave moving through
the wafer plane, and that depends on the micro-cracks the are originally present due to the
micro-bubbles.

Leti researchers also reported on Copper grain-size effects on direct metallic bonding
mechanisms such as will be used in 3D chip-stacking. The main limitation on the density of
3D copper (Cu) connections between chips is the micro-bump pitch, with Cu-Cu bonds
providing both electrical and mechanical connections. Since the grain-size of annealed Cu
thin-films depends on film thickness, they used electro-chemical deposition (ECD) to grow
two different thicknesses, annealed each at 400C for 10 hours to allow for maximum grain
growth, and then used CMP to get all samples to the same final thickness. The result was
fine-grain Cu bumps with 0.6 micron diameter grains, and large-grain bumps with ~2.1
micron diameter grains. With no post-bond-anneal there was significant improvement in
bonding strength with fine-grain-structure Cu compared to large-grains, but with post-bondanneals up to 300C the grain-size effect was reduced such that all samples approaching the
same high levels of bond strength. However, 400C annealing resulted in a newly observed
voiding phenomenon between the Cu and TiN barrier layers, with more voids associated with
finer-grains.
Artificial Neural Networks
Researchers from Sandia Labs showed data on multi-level data storage using memristors.
Lacking repeatable processes to manufacture memristors, people have used SRAM arrays to
build the first Artificial Neural Networks (ANN) such as those commercialized by NeuroMem
Inc. However, models indicate that changing from SRAM- to memristor-arrays would reduce
power by 16x and chip area by 6x (assuming 25,600 elements). Sandia has been working
with TaOx (where 3 < x < 5) as the memristor switching layer, and has been able to show up
to 5 discrete High Resistance States (HRS) to be able to do multi-bit storage in a single cell.
For multilevel switching, the standard deviation of a target resistance increases with
increasing resistance (not with the magnitude of the resistance change). However, each cell
was only cycled 25-50 times, so reliability/wear-out has not yet been explored.
IBM Almaden Labs began work on Phase-Change Memory (PCM) with Macronix and Qimonda
in 2004, and recently have explored PCM to build ANN. They sacrifice density and double up
the artificial synapses to separately encode excitory and inhibitory functions. In PCM it is
easy to slowly step up the High-Resistance State (HRS) levels since a crystalline plug is the
Low Resistance State (LRS) and gradual crystallization of the edges of the plug gradually
increases resistance, while reset back to LRS either happens on doesnt across the entire
plug so there is an inherently asymmetrical response. For Resistance RAM (ReRAM)
structures there is opposite asymmetry in that the conductive filament either forms or
doesnt, while reset to LRS can happen gradually. These asymmetries in the inherent
dynamic responses of artificial synapses result in problems for learning/programming of ANN
since ideal learning calls for slight increases and decreases in resistances.
E.K.
Tags: 3D, ANN, compound semiconductor, Dennard
Scaling, device, electronic, EMC, HVM, materials,memristor, micro-bump, Moores
Law, neural network, R&D, Silicon, Smart Cut, SST News
Posted in Design | No Comments

Monolithic 3D processing using non-equilibrium RTP

Friday, April 17th, 2015

By Ed Korczynski, Senior Technical Editor, Solid State Technology

Slightly more than one year after Qualcomm Technologies announced that it was assessing
CEA-Letis monolithic 3D (M3D) transistor stacking technology, Qualcomm has now
announced that M3D will be used instead of through-silicon vias (TSV) in the companys next
generation of cellphone handset chips. Since Qualcomm had also been a leading industrial
proponent of TSV over the last few years while participating in the imec R&D consortium,
this endorsement of M3D is particularly relevant.
Letis approach to 3D stacking of transistors starts with a conventionally built and locallyinterconnected bottom layer of transistors, which are then covered with a top layer of
transistors built using relatively low-temperature processes branded as CoolCube. Figure 1
shows a simplified cross-sectional schematic of a CoolCube stack of transistors and
interconnects. CoolCube M3D does not transfer a layer of built devices as in the approach
using TSV, but instead transfers just a nm-thin layer of homogenous semiconducting
material for subsequent device processing.

Fig. 1: Simplified cross-sectional rendering of Monolithic 3D (M3D) transistor stacks, with

critical process integration challenges indicated. (Source: CEA-Leti)

The reason that completed transistors are not transferred in the first place is because of
intrinsic alignment issues, which are eliminated when transistors are instead fabricated on
the same wafer. We have lots of data to prove that alignment precision is as good as can be
seen in 2D lithography, typically 3nm, explained Maud Vinet, Letis advanced CMOS
laboratory manager in an exclusive interview withSST.
As discussed in a blog post online at Semiconductor Manufacturing and
Design(http://semimd.com/hars/2014/04/09/going-up-monolithic-3d-as-an-alternative-tocmos-scaling/) last year by Leti researchers, the M3D approach consists of sequentially
processing:
processing a bottom MOS transistor layer with local interconnects,
bonding a wafer substrate to the bottom transistor layer,
chemical-mechanical planarization (CMP) and SPE of the top layer,
processing the top device layer,
forming metal vias between the two device layers as interconnects, and
standard copper/low-k multi-level interconnect formation.
To transfer a layer of silicon for the top layer of transistors, a cleave-layer is needed within
the bulk silicon or else time and money would be wasted in grinding away >95% of the

silicon bulk from the backside. For CMOS:CMOS M3D thin silicon-on-insulator (SOI) is the
transferred top layer, a logical extension of work done by Leti for decades. The heavy dose
ion-implantation that creates the cleave-layer leaves defects in crystalline silicon which
require excessively high temperatures to anneal away. Letis trick to overcome this thermalbudget issue is to use pre-amorphizing implants (PAI) to completely dis-order the silicon
before transfer and then solid-phase epitaxy (SPE) post-transfer to grow device-grade singlecrystal silicon at ~500C.
Since neither aluminum nor copper interconnects can withstand this temperature range, the
interconnects for the bottom layer of transistors need to be tungsten wires with the highest
melting point of any metal but somewhat worse electrical resistance (R). Protection for the
lower wires cannot use low-k dielectrics, but must use relatively higher capacitance (C)
oxides. However, the increased RC delay in the lower interconnects is more than offset by
the orders-of-magnitude reduction in interconnect lengths due to vertical stacking.
M3D Roadmaps
Leti shows data that M3D transistor stacking can provide immediate benefit to industry by
combining two 28nm-node CMOS layers instead of trying to design and manufacture a single
14nm-node CMOS layer: area gain 55%, performance gain 23%, and power gain 12%. With
cost/transistor now expected to increase with sequential nodes, M3D thus provides a way to
reduce cost and risk when developing new ICs.
For the industry to use M3D, there are some unique new unit-processes that will need to
ramp into high-volume manufacturing (HVM) to ensure profitable line yield. As presented by
C. Fenouillet-Beranger et al. from Leti and ST (paper 27.5) at IEDM2014 in San Francisco,
New Insights on Bottom Layer Thermal Stability and Laser Annealing Promises for High
Performance 3D Monolithic Integration, due to stability improvement in bottom transistors
found through the use of doping nickel-silicide with a noble metal such as platinum, the top
MOSFET processing temperature could be relaxed up to 500C. Laser RTP annealing then
allows for the activation of top MOSFETs junctions, which have been characterized
morphologically and electrically as promising for high performance ICs.
Figure 2 shows the new unit-processes at <=500C that need to be developed for top
transistor formation:
* Gate-oxide formation,
* Dopant activation,
* Epitaxy, and
* Spacer deposition.

Fig. 2: Thermal processing ranges for process modules need to be below ~500C for the top
devices in M3D stacks to prevent degradation of the bottom layer. (Source: CEA-Leti)
After the above unit-processes have been integrated into high-yielding process modules for
CMOS:CMOS stacking, heterogeneous integration of different types of devices are on the
roadmap for M3D. Leti has already shown proof-of-concept for processes that integrate new
IC functionalities into future M3D stacks:
1)

CMOS:CMOS,

2)

PMOS:NMOS,

3)

III-V:Ge, and

4)

MEMS/NEMS:CMOS.

Thomas Ernst, senior scientist, Electron Nanodevice Architectures, Leti, commented to SST,
Any application that will need a pixelated device architecture would likely use M3D. In
addition, this approach will work well for integrating new channel materials such as III-Vs
and germanium, and any materials that can be deposited at relatively low temperatures
such as the active layers in gas-sensors or resistive-memory cells.
Non-Equilibrium Thermal Processing
Though the use of an oxide barrier between the active device layers provides significant
thermal protection to the bottom layer of devices during top-layer fabrication, the thermal
processes of the latter cannot be run at equilibrium. One way of controlling the thermal
budget is to use what we sometimes call the crme brle approach to only heat the very
top surface while keeping the inside cool, explained Vinet. Everyone knows that you want
a nice crispy top surface with cool custard beneath. Using a laser with a short wavelength
prevents penetration into lower layers such that essentially all of the energy is absorbed in
the surface layer in a manner that can be considered as adiabatic.
Applied Materials has been a supplier-partner with Leti in developing M3D, and the company
provided responses from executive technologists to queries from SST about the general
industry trend to controlling short pulses of light for thermal processing. Laser nonequilibrium heating is enabling technology for 3D devices, affirmed Steve Moffatt, chief
technology officer, Front End Products, Applied Materials. The idea is to heat the top layer
and not the layers below. To achieve very shallow adiabatic heating the toolset needs to
ramp up in less than 100 nsec. In order to get strong absorption in the top surface, shorter
wavelengths are useful, less than 800 nm. Laser non-equilibrium heating in this regime can
be a critical process for building monolithic 3D structures for SOC and logic devices.
Of course, with ultra-shallow junctions (USJ) and atomic-scale gate-stacks already in use for
CMOS transistors at the 22nm-node, non-equilibrium thermal processing has already been
used in leading fabs. Gate dielectric, gate metal, and contact treatments are areas where

we have seen non-equilibrium anneals slowly taking the place of conventional RTP, clarified
Abhilash Mayur, senior director, Front End Products, Applied Materials. For approximate
percentages, I would say about 25 percent of thermal processing for logic at the 22nm-node
is non-equilibrium, and seen to be heading toward 50 percent at the 10nm-node or lower.
Mayur further explained some of the trade-offs in working on the leading-edge of thermal
processing for demanding HVM customers. Pulse-times are in the tens of nsec, with longer
pulses tending to allow the heat to diffuse deeper and adversely alter the lower layers, and
with shorter pulses tending to induce surface damage or ablation. Our roadmap is to ensure
flexibility in the pulse shape to tailor the heat flow to the specific application, said Mayur.
Now that Qualcomm has endorsed CoolCube M3D as a preferred approach to CMOS:CMOS
transistor stacking in the near-term, we may assume that R&D in novel unit-processes has
mostly concluded. Presumably there are pilot lots of wafers now being run through
commercial foundries to fine-tune M3D integration. With a roadmap for long-term
heterogeneous integration that seems both low-cost and low-risk, M3D using non-equilibrium
RTP will likely be an important way to integrate new functionalities into future ICs.
Tags: 3D, adiabatic, CEA-Leti, CoolCube, Ge, HVM, III-V, integration, materials, node, nonequilibrium,PAI, process, Qualcomm, RTP, Si, Silicon, SOI, SPE, SST News, stack, TSV
Posted in News Stories, Top Stories | 1 Comment

The Week in Review: October 24, 2014

Friday, October 24th, 2014
IBM and GLOBALFOUNDRIES this week announced that GLOBALFOUNDRIES will acquire IBMs
global commercial semiconductor technology business, including IBMs intellectual property,
technologists and technologies. IBM will pay GLOBALFOUNDRIES $1.5 billion in cash over the
next three years to take the chip operations off its hands. The cash consideration will be
adjusted by the amount of working capital which is estimated to be $200 million.
Capped by last weeks announcement that Qualcomm Inc. would buy CSR PLC, the
automotive semiconductor industry recently has been undergoing a wave of merger and
acquisition activity that has shaken up the competitive order of the market, according
to IHS Technology.
Adlyte Inc., a developer of high-brightness extreme light sources for advanced
semiconductor inspection and metrology applications, announced it has reached a key
performance benchmark for its extreme ultraviolet (EUV) light source for high-volume
manufacturing (HVM)-readiness.
Gigaphoton Inc., a lithography light source manufacturer, announced that it has succeeded
in achieving 3-hour continuous operation of its prototype LPP EUV light source at 50 percent
duty cycle and 42-W output, equivalent to usage in a high-volume-manufacturing (HVM)
environment.
North America-based manufacturers of semiconductor equipment posted $1.17 billion in
orders worldwide in September 2014 (three-month average basis) and a book-to-bill ratio of
0.94, according to the September EMDS Book-to-Bill Report published today
by SEMI. A book-to-bill of 0.94 means that $94 worth of orders were received for every
$100 of product billed for the month.
Tags: Adlyte; IBM, automotive, book-to-bill, EUV, Gigaphoton, GlobalFoundries, HVM, SEMI
Posted in News Stories | No Comments
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