A register is often referred to as memory.

The functional behavioral displays an ideal run of the system.

The timing behavioral displays real life scenario of a system. This is where time delays
take effect. Suppose a system is currently running a program and on the same system
another program runs simultaneously with it, as the latter program is about to start, it
takes a few second to respond as it is suppose to do thus having a time delay. Though this
time delay is short, it still must be taken into consideration because in terms of modeling
a system it is important to no its initial conditions ( in this case a time delay).
Implementations of a 4-bit hold register
A 4-bit hold register stores a 4-bit value (0-15 in binary) . If the reset is low this means
that the output will be the same as the input which leads to the system not reset; as it
stores the 4-bit. If the reset is high that means whatever was stored is now erased from the
memory (register).

Figure 1: Schematic for 4-bit hold register

Figure 2: Timing behavioral for 4-bit hold register

As you can see, the 4-bit entered was (0101) , the reset was 0, thus the system did not
reset. This made the output the same value ( 0101) and thus led to the system storing the
value. This shows evidence that the system functions properly.

Implementation of a 4-bit hold register using buses and bus taps.

With the implementation of busses and bus taps there is no need to feed an input to each
flip flop. We use the configuration (3:0) meaning 3 down to 1, in other words a 4-bit
input.
D3, D2, D1, D0 4-bit; by assigning a name to the bus line, it indicates which input bit
goes to its designated bus line. Example (1001) means a high input assigned to D3, a low
input assigned to D2 etc. This does the same thing as before; takes the 4-bit, stores it if
the reset is low or erases it if the rest is high and displays the output, but instead of
feeding a single bit to each of the four output , the bus tap allow us to input all 4 bits as a
single input.

A bus is a network topology or circuit arrangement in which all devices are attached to a
line directly and all signals pass through each of the devices. Each device has a unique
identity and can recognize those signals intended for it. This reduces the number of single
inputs for a system, thus making it one input signal and using a bus to identify the signal.

Implementations of an 8-bit hold register using 2 4-bit hold register

By using 2 4-bit hold registers, we can combine them to make one 8-bit bit hold register.
One register will hold the first 4 least significant bits ( 3:0) and the other will hold the 4
most significant bits (7:4).( the input will be (7:0)). Just as before, using bus taps and
busses to create a 4-bit hold register using 4 1-bit hold register; the design of the 8-bit
register can be implemented.

Figure 3: Schematic for an 8-bit hold register

Figure 4: Timing behavioral of an 8-bit hold register

By observation one can see an 8-bit at the input. Since the reset is low, the system stores
the 8-bit thus the output displays the 8-bit in its memory, which concludes that the system
is functioning properly.

Implementations of a 1-bit 4 to 1 multiplexer.

The way a multiplexer (mux) is that it has selects which controls the integrated circuit of
the mux. Each of the 4 inputs (Ax, Bx, Cx, Dx) takes a specific configuration of the select
bits ( S0, S1) so that it can be outputted. Looking at the Schematic below you can see that
the mux consists of NOT gates (inverters), AND3 gates ( the 3 denotes the number of
inputs it can take) and an OR4 gate. For a high output for an AND gate A.B.C = 1 (all
inputs are high) and for an OR gate it is A + B + C +D = 1 ( at least 1 input high) When
the select is (S0 = 0 , S1 = 0), the system will search for which input that will give a high
output at its corresponding AND gate. NOTE: the inputs (Ax, Bx, Cx, Dx) are all high.
When the selects (S0 = 0 , S1 = 0) are chosen, by observation one can see that only AND
gate gives a high output thus it will be at the output. As explained before the select
controls what input should be displayed at the output.

Figure 5: Schematic for the 1-bit 4 to 1 multiplexer

Figure 6: Timing behavioral for the 1-bit 4 to 1 mux

First we must know how the integrating circuit works inside the multiplexer so that we
use the correct selects (S0 , S1 ) to output our desired signal. Looking at the timing
behavioral we chose our selects as (S0 = 0 , S1 = 0). Since we know that this select
configuration outputs Ax, we can clearly see from above that it outputs the signal of Ax,
thus it functions properly.

Problems faced:
1) System did not run. (Schematics)
2) Modelsim did not run. (Libraries crashed)
3) Built my project on many computers since the timing behavioral only works in the
electronics lab.
Corrective measures taken:
1)
2)
3)
4)

Make sure no breaks in the circuit.

Make sure all the ports a named correctly.
Make sure when creating the testbench choose the correct schematic.
Make sure you run Modelsim as an administrator or else the testbench will not
run. Please correct this issue as I spent a lot of time wondering why I could not
run Modelsim in the Electronics Lab.
5) Make sure not to name the schematics or any file with illegal characters as - , as
this caused problems.
6) Troubleshoot the libraries, make sure the destination file is in c drive > modelsim
> win32 file.
7) Ensure that when starting a project make sure it is schematic and not the default
VHDL.

POST LAB:

Figure 7: 16-bit hold register

Design:
The way this was built is that we use two 4-bit hold register ( the schematic for the 4-bit
hold register is shown in Figure 1) with bus taps to acquire an 8-bit hold register. Then
two 8-bit hold register with bus tap was used to produce a 16-bit hold register as seen
above.
Verification:
From the functional behavior figure, a 16-bit was fed into the input and since the reset is
low that means the output should be the same as the input.

Figure 8: Functional behavioral for a 16-bit hold register

Figure 9: Timing behavioral for a 16-bit hold register

Question 2

Figure 10: 1-bit 4 to 1 line multiplexer

Figure 11: Macro for the 1-bit 4 to 1 line multiplexer

Figure 12: 4-bit 4 to 1 line multiplexer

Design:
4 macros of the 1-bit 4 to 1 line multiplexer were used with the addition of busses to
create the 4-bit 4 to 1 line multiplexer as shown above.
Verification:
As you can see from the functional diagram above, the selects S0 = 1 , S1 = 0 gives the
input of gate C, hence the output X should be the same input signal as C.

Figure 13: Functional behavioral for the 4-bit 4 to 1 line multiplexer

Figure 14: Timing behavioral for the 4-bit 4 to 1 line multiplexer

(file named badly but it is the 4bit 4 to 1 mux)

Question 3

Figure 15: 1-bit 3 to 1 line multiplexer

Figure 16: Macro of the 1-bit 3 to 1 line multiplexer

Figure 17: 2-bit 3 to 1 line multiplexer

Figure 18: Macro for the 2-bit 3 to 1 line multiplexer

Figure 19: 4-bit 3 to 1 line multiplexer

Figure 20: Macro for a 4-bit 3 to 1 line multiplexer

Figure 21: 8-bit 3 to 1 line multiplexer

Figure 22: Macro for the 8-bit 3 to 1 line multiplexer

Figure 23: 16-bit 3 to 1 line multiplexer

Figure 24: Functional behavioral for the 16-bit 3 to 1 line multiplexer

Figure 25: Timing behavioral for the 16-bit 3 to 1 line multiplexer

( I built over the project as a different name because the current computer had the same
name files stored)
Design:
First a 1 bit 3 to 1 mux was built, then a macro was obtained.( There is an internal Vcc to
compensate for the select configuration of S0 = 1 , S1 = 1, this simply implies that for that
particular select of S0 = 1 , S1 = 1 ,I will obtain my Vcc signal. Now this macro was bus
tap with another macro just like it to create a 2-bit 3 to 1 mux. A macro was created and
then 2 of these macros was used to make a 4-bit 3 to 1 mux. A 4-bit 3 to 1 mux macro
was created and two of these were bus tap to make an 8-bit 3 to 1 mux. This macro was
created and two of these were bus tap to make a 16-bit 3 to 1 mux.
Verification:
As you can see from the functional diagram above, the selects S0 = 1 , S1 = 0 gives the
input of gate C, hence the output X should be the same input signal as C.