THE UNIVERSITY OF THE WEST INDIES

ST. AUGUSTINE, TRINIDAD & TOBAGO, WEST INDIES

FACULTY OF ENGINEERING
Department of Electrical & Computer Engineering

ECNG 2004
LABORATORY & PROJECT DESIGN II
http://myelearning.sta.uwi.edu/course/view.php?id=1678
Semester I, 2009/2010

1. GENERAL INFORMATION
DIGLAB1

Lab #:
Name of the Lab:

Introduction to the Xilinx Schematic Editor

3

Lab Weighting:

Delivery mode:

Lecture
Online
; Lab
Other

Venue for the Lab:

Electronics Laboratory

Lab Dependencies2

The theoretical background to this lab is provided in ECNG 1014

Theoretical content link: http://myelearning.sta.uwi.edu/course/view.php?id=684
Pre-Requisites None

Recommended
prior knowledge
and skills3:

None

Course Staff

Position/Role

Marcus L George Instructor

Estimated total
study hours1:

E-mail
Phone
Office


Marcus.George@uwi.sta.edu ext3164 Electronics
Lab Office

Office
Hours
Fridays
10am - 1pm

THE UNIVERSITY OF THE WEST INDIES

ST. AUGUSTINE, TRINIDAD & TOBAGO, WEST INDIES
FACULTY OF ENGINEERING
Department of Electrical & Computer Engineering

2. LAB LEARNING OUTCOMES

Upon successful completion of this lab assignment, students will be able to:
1. Demonstrate competence with the simulation and implementation of digital
systems utilizing Xilinx and the Spartan III FPGA development board.
2. Understand the basics of Xilinx Schematic Editor
- Select macros for the creation of schematics
- Search for macros using the symbol name filter feature
- Create a schematic using macros selected
- Add wires to the schematic to interface macros
- Add I/O markers to the design
- Observe the internal structure of macros available from the Xilinx
symbol library.
- Obtain the datasheets for macros used in the editor using the
symbol info feature.
3. Create a 1-bit adder macro and use it to create a 4-bit adder macro.

Cognitive
Level
C
C

4. View the RTL Schematic of the system implemented.

5. Perform both functional simulation(Simulate Behavioural Model) and

timing simulation(Simulate Post-Place and Route VHDL Model) for a
digital system using Modelsim 6.0SE/XE.
6. Create an implementation Constraints file for the design and assign
package pins and downloading the implementation onto the FPGA
development board.

THE UNIVERSITY OF THE WEST INDIES

ST. AUGUSTINE, TRINIDAD & TOBAGO, WEST INDIES
FACULTY OF ENGINEERING
Department of Electrical & Computer Engineering

3. PRE-LAB
Due Date:
Submission
Procedure:
Estimated time to
completion:

Students must have completed the pre-lab exercise in advance of the inlab exercise.
N/A
30 minutes

3.1. Required Reading Resources

Using suitable reading resources (ECNG1014 notes, recommended books, internet, etc), research
and understand the following topics.
a) Half Adder
b) Full Adder
Make sure to fully understand the implementation of these digital circuits using logic gates. Also
read through the laboratory manual for DIGLAB1 to understand how these circuits may have
been utilized.

DIGLAB1: Introduction to the Xilinx Schematic Editor

4. IN-LAB
Allotted Completion 3 hours
Time:
1 printed copy of the DIGLAB1 manual (students must bring this copy to
Required lab
the lab)
Equipment:
1 Computer
Spartan 3 Development board (including J-Tag cable & adaptor)

4.1. Introduction
You can build moderately complex logic circuits of up to several hundred gates wiring the SSI and
MSI ICs. Logic synthesis programs are often used in digital system design. The logic circuit can
input a truth table, a circuit schematic (best for smaller circuits), or use a hardware description
language (HDL). Operation of the circuit is then simulated to make sure the logic design is correct.
The next step is typically to either design a custom VLSI IC (usually only justified for high volume
applications or applications with specialized requirements), or programmed into either a field
programmable gate array (FPGA) or a complex programmable logic device (CPLD). In this lab,we
will learn how to use the Xilinx ISE Tools to implement and simulate logic circuit designs from a
schematic.

DIGLAB1: Introduction to the Xilinx Schematic Editor

4.2. Creating a New Project

A project in ISE is a collection of all files necessary to create and download a design to the selected
device. To create a new project:
4.2.1.

Select File > New Project.

4.2.2.

In the New Project Wizard dialog box, enter the project name My_4bit_Adder_ in the
diagram below. You can browse to the desired directory using the browse button next to
the Project Location field.

4.2.3.

Now Click Next.

DIGLAB1: Introduction to the Xilinx Schematic Editor

4.2.4.

In the New Project Wizard Device and Design Flow dialog box, use the pull-down arrow
to select the Value for each Property Name. Click in the field to access the pull down list.

Change the values as follows:

Device Family: Spartan3

Device: xc3s400/xc3s1000

Package: ft256

Speed Grade: -5

Synthesis Tool: XST (VHDL/Verilog)

Simulator: Modelsim

Generated Simulation Language: VHDL

DIGLAB1: Introduction to the Xilinx Schematic Editor

4.2.5.

Click Next

This will open a New Project dialog box.

Click Next! Then click Next again! Then click Finish.

4.2.6.

In the New Source dialog box select Schematic from the list. Name the file as
MyFullAdder in the File Name field. Verify that the Add to project check box is
selected.

DIGLAB1: Introduction to the Xilinx Schematic Editor

4.2.7.

Click Next. Then click Finish!

This will launch Engineering Capture System (ECS). You may have to choose the tab
labeled MyFullAdder and close other windows in the left side (dont close the Sources
8

DIGLAB1: Introduction to the Xilinx Schematic Editor

window). A blank sheet opens in an ECS schematic window. In ECS, you can create a
schematic diagram from scratch.

DIGLAB1: Introduction to the Xilinx Schematic Editor

4.3. Creating a Schematic

On the left side of the screen you will see two small windows Categories and Filter. This is
where we will find all the components we will need to assemble our full adder.
4.3.1.

Select Logic in the Categories window. Only logic gates in the Symbols window will be
displayed. From the Filter window add an OR2 gate along with two AND2 gates onto your
workspace. Also grab two XOR2 gates.

10

DIGLAB1: Introduction to the Xilinx Schematic Editor

4.3.2.

Click on the Add Wire icon

. This will allow you to connect the components together.

Click on the lead of one gate then on the lead of the next and a wire will be drawn that
connects the two together. Note that

S=ABC
Cout = (A B) C + AB
Note the use of the following symbols:

used to denote XOR, eg. A B means A XOR B

+ used to denote OR, eg. A + B means A OR B

used to denote AND,

eg. AB means A AND B

After the wires have been connected your circuit should look as follows. Make sure to add
wires to outputs S and Cout.

Now we need to add I/O Markers. These markers will help Xilinx determine where the
inputs/outputs are when it converts this schematic into a macro.

11

DIGLAB1: Introduction to the Xilinx Schematic Editor

4.3.3.

Click the I/O Marker icon

. Place markers on each input and output by clicking on the

terminal that you wish to place the marker.

Your schematic should look like this with the markers in place. Xilinx automatically assigns names
to the markers, but remembering the names can get confusing really fast. For clarity, change the
names. Right click on the marker and rename. Alternatively, you can select the pointer tool

and

double click on the marker you wish to rename. In the Object properties dialog box change the
name of the marker by changing the name in the Value field. Click Ok. Similarly rename all
your markers. When you are done the schematic will appear as follow.

12

DIGLAB1: Introduction to the Xilinx Schematic Editor

13

DIGLAB1: Introduction to the Xilinx Schematic Editor

4.4. Creating a Macro

Now that our schematic is complete we would like to create a macro. A macro is a user-created
symbol that can be used just like a component. The advantage of creating a macro is that once you
have a macro for your full adder you can use the same macro over and over again. First, save your
schematic. Then from the tool bar select Tools, then Symbol Wizard. Finally select Specify
Manually.

Click Next!

14

DIGLAB1: Introduction to the Xilinx Schematic Editor

A dialog box with the input and output ports of the schematic open up. Click Add Pin in order to
add pin to macro. Check whether the input and output ports are defined as you intended.

Click Next!

In this dialog box you can change some appearance properties of the symbol being created.

Click Next!

You can see your symbol in a symbol wizard dialog box. Click Finish!
15

DIGLAB1: Introduction to the Xilinx Schematic Editor

16

DIGLAB1: Introduction to the Xilinx Schematic Editor

Now there is a shortcut for creating macros!!!

4.4.1.

Click/highlight any of the VHDL or schematic files in the source window so that you see
the corresponding process window.

4.4.2.

In the process window double click on Create Schematic Symbol (refer to screen-shot
below). This creates the schematic symbol corresponding to the VHDL code created and
adds it to the library so you can use it in your designs. Create Schematic Symbol
creates macros using default settings. You can use it instead of using the symbol editor.

4.4.3.

Now close the Symbol editor. Close the schematic we had just been working on, and return
to the project navigator.

17

DIGLAB1: Introduction to the Xilinx Schematic Editor

4.4.4.

Now we will create a new Schematic. Right click on the Device (xc3s400-5 ft 256), then
select New Source

4.4.5.

Select Schematic from the list and name it My_4bit_Adder_Chip. Next click Finish

This will reopen the schematic editor.

18

DIGLAB1: Introduction to the Xilinx Schematic Editor

4.4.6.

Now select the symbols tab and look in the Categories Window. You will realize that a
new category named <E:/./My_4bit_Adder> has been added. In this category the full
adder created previously can be found.

You have just completed creating your first macro!

19

DIGLAB1: Introduction to the Xilinx Schematic Editor

4.5. Mini-Exercise
Use the new schematic previously created named My_4bit_Adder_Chip and the fulladder macro created previously to create a 4-bit adder. You can select copies of this adder from
the new category created and connect them together as shown in the diagram below. The
resulting macro must look like the 4-bit adder macro shown in the next diagram.

DIGLAB1: Introduction to the Xilinx Schematic Editor

4.6. Obtaining the RTL Schematic for the system

Obtain the RTL Schematic for My_4bit_Adder_Chip by double clicking on the View RTL
Schematic section of the Process View window as shown in the diagram below. The RTL
Schematic allows the user to view he internal architecture of the macro created. You will notice
the RTL Schematic resembles the schematic you implemented.

21

DIGLAB1: Introduction to the Xilinx Schematic Editor

4.7. Simulation of the design using Modelsim 6.0SE/XE

If Modelsim 6.0SE/XE is not already linked to the Xilinx 7.1ISE softare then you need to do so
before progressing in this lab, using the reading resource named Linking Modelsim 6.0SE/XE
to Xilinx 6.3i/7.1i. This document can be downloaded from the course Website on
MyElearning.
In the New Source dialog box select Test Bench Waveform from the list. Name the file as
My_4bit_Adder_tbin the File Name field. Verify that the Add to project check box is
selected.

Click Next!

22

DIGLAB1: Introduction to the Xilinx Schematic Editor

Attach the test bench waveform file to the top level schematic module My_4bit_Adder_Chip
and click Next! Then click Finish!

Set the test bench waveform with the following test cases as shown in the table below.
A3
0
0
0
1

A2
0
1
0
0

A1
1
0
0
0

A0
1
0
1
0

B3
0
0
0
1

B2
0
0
0
0

B1
0
1
0
0

B0
1
0
0
0

Cin
0
0
1
0

Table 1: Test cases for simulation

Now save the design.

N.B.: In this lab you will be introduced to two kinds of simulation, functional and timing
simulation. This will be introduced in section 4.8 of the lab.

23

DIGLAB1: Introduction to the Xilinx Schematic Editor

4.8. Simulation Theory

Functional Simulation
A functional simulation is done to verify the operation of the circuit. We use it to ensure that the
circuits functional behavior correct. If we want to perform a functional simulation we just
double click on Simulate Behavioral Model in the Xilinx 6.3i/7.1i process window.

Timing Simulation
The timing simulation will give you detailed information about the time it takes for a signal to
pass from one gate to the other (gate delay) and gives information on the circuit worst-case
conditions. The total delay of a complete circuit will depend on the number of gates the signal
sees and on the way the gates have been placed in the FPGA or CPLD. Thus timing information
can only be obtained after the design has been implemented. If we want to perform a timing
simulation we just double click on Simulate Post-Place & Route VHDL Model in the Xilinx
6.3i/7.1i process window.

24

DIGLAB1: Introduction to the Xilinx Schematic Editor

4.9. Practical: Simulation using Modelsim

Highlight the test bench waveform in the Module View window, then double click Simulate
Behavioral Model from the process window. The Modelsim 6.0SE/XE GUI loads
automatically.

Verify that the system is functional by thoroughly analyzing the timing diagram generated.

Repeat the simulation using Simulate Post-Place and Route VHDL Model.
25

DIGLAB1: Introduction to the Xilinx Schematic Editor

4.10. Programming the FPGA development board

The first step to programming the FPGA development board is to create the implementation
constraints file. This is done by selecting Implementation Constraints File from the New
Source dialog window. The file must then be given the name My_4bit_Adder_ucf. We then
click Next.

Ensure that the implementation constraint file created is connected to the top level schematic
My_4bit_Adder_Chip as shown in diagram below. Then click Next. Then click Finish.

26

DIGLAB1: Introduction to the Xilinx Schematic Editor

We then double click the Implementation Constraints File from the Module View and then
assign package pins using the table below.
Before you create the Implementation constraints file students are advised to utilize the
datasheet of the Spartan 3 Toolkit (SBOARD.pdf) to locate the switches, pushbuttons and
LEDs to be used in this laboratory exercise. If you are having problems doing this please call
the attention of a TA.

27

DIGLAB1: Introduction to the Xilinx Schematic Editor

Table 2: Pin assignments for the Implementation

Design Port
A3
A2
A1
A0
B3
B2
B1
B0
Cin
S3
S2
S1
S0
Cout

FPGA Pin Assigned

K13
K14
J13
J14
H13
H14
G12
F12
M13
N14
L12
P14
K12
P11

(FPGA switch)
(FPGA switch)
(FPGA switch)
(FPGA switch)
(FPGA switch)
(FPGA switch)
(FPGA switch)
(FPGA switch)
(FPGA Pushbutton)
(FPGA LED)
(FPGA LED)
(FPGA LED)
(FPGA LED)
(FPGA LED)

After assigning package pins, save the changes made and double click Configure Device
iMPACT under the Generate Programming File tab from the Process Window as shown in the
diagram below.

28

DIGLAB1: Introduction to the Xilinx Schematic Editor

Click Next!

Click Finish!

29

DIGLAB1: Introduction to the Xilinx Schematic Editor

Click OK!

Click Open!

You are now prompted for a PROM programming file as shown in the figure below. We are not
programming the PROM at this time, therefore select Bypass.
30

DIGLAB1: Introduction to the Xilinx Schematic Editor

Finally, you will reach the point shown in Figure 1.31. iMPACT is ready to program the FPGA.
Select the FPGA icon in the window and then use the right mouse button to activate the menu as
shown and select the Program option.

31

DIGLAB1: Introduction to the Xilinx Schematic Editor

After programming the Spartan 3 FPGA development boards please perform on-board testing
using the test cases of Table 1 above in addition to the switches, pushbuttons and LEDs of the
Spartan 3 development board. Show your TA your functional system.

Proceed to post-lab exercise.

32

DIGLAB1: Introduction to the Xilinx Schematic Editor

5. POST-LAB
A signed plagiarism declaration form must be submitted with your assignment.
Due Date:
Submission
Procedure:
Deliverables:

N/A
N/A
N/A

End of DIGLAB1: Introduction to the Xilinx Schematic Editor

33