PLL Simulation on NI AWR to Understand the Impact of Various Parameters

Schematic: Basic Type I PLL Topology

Input Reference:
Output:
Filter:

Freq_in = 1MHz
Freq_out = 1MHz
Cut Off Freq = 0.5MHz

Ph_in = 0
VCO Gain = 0.5MHz/V

After around 8u sec output frequency is getting blocked and steady state error is approx. 0.
Note: Output is 90deg out of phase with respect to input due the kind of phase detector used i.e.
a multiplier which leads to quadrature shift.
Lets now look at the effect of changing a few parameters:
a) Filter Cut Off Frequency
i) Increasing fc = 0.7MHz
It reaches steady state faster i.e. system responds faster but the price we pay for faster lock
time is oscillations in error which translate to phase noise. Phase noise means that the output
tune isnt pure.

ii) Reducing fc = 0.3MHz

Transients took longer to settle but there will be no oscillations i.e. lower phase noise.

b) Reference Frequency Phase

i) Increasing Ph_in = 0.5
It locks fine means PLL is working fine!

ii) Decreasing Ph_in = -1

Again it locks fine means PLL is working fine!

c) VCO Gain
i) Increasing KVCO = 0.8MHz/V
Transients may take a little bit longer and there will be more oscillations i.e. more phase noise. It
starts to get more unstable.

Really large KVCO = 2MHz/V

Output doesnt even settle and is not even sinusoid.

ii) Decreasing KVCO = 0.2MHz/V

Output settles smoothly.

d) Input Reference Frequency

i) Increasing Freq_in = 1.05MHz
Output is being locked but is no longer leading the input by 90deg. We also have a non-zero
error signal (DC value > 0) which is being fed to input of VCO. So, it locks in frequency but not in
phase i.e. there is phase error.

Increasing Freq_in too much might lead to neither frequency locking nor phase locking. This is
because its outside PLL capture range. Freq_in = 1.3MHz

ii) Decreasing Freq_in = 0.95MHz

Output is being locked but is no longer leading the input by 90deg. We also have a non-zero
error signal (DC value < 0) which is being fed to input of VCO. So, it locks in frequency but not in
phase i.e. there is phase error.

Decreasing Freq_in too much might lead to neither frequency locking nor phase locking. This is
because its outside PLL capture range. Freq_in = 0.8MHz

iii) Increasing Freq_in = 1.1MHz & Increasing K VCO = 1MHz/V

Output is being locked but is no longer leading the input by 90deg. We also have a non-zero
error signal (DC value > 0). Note that the error is more if VCO gain is not increased while error
reduces on increasing VCO gain, though, output takes longer time to settle.

Note that if we keep on increasing VCO gain, the system will finally get unstable due to poor
phase margin and output wont lock.
iv) Increasing Freq_in = 1.1MHz & Decreasing K VCO = 0.1MHz/V
Output wont settle i.e. it wont lock as there is not sufficient gain from VCO leading to
insufficient DC voltage to drive VCO towards lock.

Thus, there is a sweet spot for KVCO.

v) Increasing Freq_in = 1.1MHz & Decreasing K VCO = 1MHz/V
Issue here is that frequency is locked but out of phase due to phase error (DC error > 0).

So, to lock both phase and frequency: We make Type1 PLL to Type2 PLL by adding a PI-Controller.

TYPE 2 PLL WITH PI CONTROLLER

Schematic: Type II PLL Topology

Input Reference:
Output:
Filter:
PI Controller:

Freq_in = 1.1MHz
Freq_out = 1MHz
Cut Off Freq = 0.5MHz
Kprop = -7dB

Ph_in = 0
VCO Gain = 1MHz/V
Kint = 105dB

Note: Its tracking both frequency and phase.

Frequency Tracking: out and ref oscillating with same frequency
Phase Tracking: same rise and fall
Now, lets increasing the input reference frequency to 1.2MHz