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Fig. 2. Block diagram of the sixth-order CTF consisting of three biquads and
the implementation of a differential biquad.
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V. BW TUNING
Both and are applied in the CTF for the tuning of
Fig. 7. Test chip output buffer. the cutoff frequency / . A 3-bit plus “sign” binary
coded digital-to-analog converter (DAC) is programming
(see Fig. 10). The current for the OTAs is derived as
a combination of the three resistors, is reduced by the negative , where is the
feedback through and the diff-pair on . reference voltage proportional to absolute temperature (PTAT),
and the tail current define the diff-pair’s gain. Values of and and are external and internal resistors, respec-
resistors are selected to define the depth of the feedback tively.
of the amplifier so that the output impedance would be reduced The PTAT reference compensates temperature depen-
two times to achieve 50 . dency, while makes insensitive to the on-chip
resistance. The remaining secondary effect of the on-chip resis-
IV. OPERATIONAL TRANSCONDUCTANCE AMPLIFIER tance on the cutoff frequency is compensated by subtracting the
The requirement of achieving high frequency at reasonable part of the current set by . The resulting current in OTAs
power limits the OTA’s architecture to the simplest diff-pair is slightly increasing when the internal resistance increases.
and rules out the possibility of the application of the CMOS The current variation by the DAC is limited to a relatively
transistors. The SNR requirements dictate the CTF’s ability to small 25% range since tuning also results in the change of
work with as large signals as possible. The increase in signal linearity, biasing points and dynamics of OTAs. For this reason,
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Fig. 10. 3-bit plus “sign” binary coded DAC used for g programming.
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Fig. 15. Simplified (only single-ended signal path shown) schematic diagram
of the attenuator.
Fig. 18. Schematic diagram of the current reference block producing the
Fig. 16. Simplified offset control circuit. bandgap current proportional to 1=R .
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its layout design. Due to the fact that there are 12 signal transis- Fig. 21. CTF test chip photograph showing the main blocks.
tors and four current sources, the layout of the cell is relatively
large. Consequently, it is evident that the regular symmetrical
layout would space the components apart, thus compromising
the symmetry in case of the process parameters and temperature
gradients. To avoid this effect, the transistors in the diff-pairs
are interdigitated and placed in two rows (see Fig. 20). The
current source transistors and resistors are placed at the edges
of the layout, namely, are located on one side and
are placed on the other.
A 0.18- m SiGe process from Jazz Semiconductor is used for
the CTF’s implementation. The die size is 3.2 3.7 mm (see Fig. 22. SDD11 measured from 300 MHz to 5.5 GHz. Worst case reflections
Fig. 21) with the CTF occupying the space of only 0.17 mm . 0
are below 13 dB.
The test chip is wire bonded in a custom solder bumped package.
Before being delivered to the CTF, the signal on the test chip
is normalized and has its offset corrected by the VGA. The
CTF output signal is buffered and delivered over 1 mm distance
to a 50- terminated linear output buffer driving output pads
through 50- coplanar transmission lines. The SPI is used for
the test chip configuration and tuning of the CTF’s BW. The rest
of the chip area is used for other functions (beyond the scope of
this paper) as well as for biasing blocks and power-supply by-
passing capacitors.
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Fig. 27. CTF output response for 10-Gb/s NRZ input data: ideal filter (left),
simulated schematics (middle), measured (right).
TABLE I
PERFORMANCE SUMMARY
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TABLE II [6] D. Baranauskas et al., “A 6th order 1.6 to 3.2 GHz tunable low-pass
COMPARISON WITH SIMILAR PUBLISHED DESIGNS linear phase gm-C filter for fiber optic adaptive EDC receivers,” in
Proc. IEEE RFIC Symp. Tech. Dig., Jun. 2009, pp. 495–498.
[7] C. Holdenried et al., “Analysis and design of HBT Cherry–Hooper am-
plifiers with emitter–follower feedback for optical communications,”
IEEE J. Solid-State Circuits, vol. 39, no. 11, pp. 1959–1967, Nov. 2004.
[8] Y. Lu et al., “A 70 MHz–4.1 GHz 5th-order elliptic gm-C low-pass
filter in complementary SiGe technology,” in Proc. BCTM Tech. Dig.,
Oct. 2006, pp. 80–83.
[9] T. Deliyannis, Y. Sun, and J. K. Fidler, Continuous-Time Active Filter
Design. Boca Raton, FL: CRC, 1999, ch. 9.
REFERENCES
[1] S. Elahmadi et al., “A monolithic one-sample/bit partial response max-
imum likelihood SiGe receiver for electronic dispersion compensation Salam Elahmadi received the B.S.E.E and M.S.E.E degrees from the Univer-
of 10.7 GB/s fiber channels,” presented at the Opt. Fiber Commun. sity of Oklahoma , Norman , in 1991 and 1994, respectively, and the Ph.D. de-
Conf. Exhibition/Nat. Fiber Opt. Eng. Conf., Mar 2009. gree in electrical engineering from Southern Methodist University, Dallas, TX,
[2] F. Dülger et al., “A 1.3-V 5-mW fully integrated tunable bandpass filter in 2009.
at 2.1 GHz in 0.35-m CMOS,” IEEE J. Solid-State Circuits, vol. 38, From 1995 to 2003, he was a Research and Development Manager with Nortel
no. 6, pp. 918–928, Jun. 2003. Networks, Richardson, TX, where he led various wireless system integration
[3] V. Dhanasekaran et al., “A 1.1 GHz fifth order active-LC Butterworth projects. From 1999 to 2002, he was a Project Leader with Qtera (later ac-
type equalizing filter,” IEEE J. Solid-State Circuits, vol. 42, no. 11, pp. quired by Nortel), Richardson, TX, where he contributed to the development
2411–2420, Nov. 2007. of ultra-long haul WDM systems. In 2004, he co-founded Menara Networks,
[4] V. Saari et al., “A 1.2 V 240 MHz CMOS continuous-time low-pass Dallas , TX , where he leads ASIC and transceiver development teams as the
filter for a UWB radio receiver,” in Proc. ISSCC Tech. Dig., Feb. 2007, companys Chief-Technology Officer. He possesses over 16 years of experi-
pp. 122–123. ence in design, test, and deployment of various wireline and wireless commu-
[5] S. D’Amico et al., “A 6th-order 100 A 280 MHz source-follower- nications systems. His background includes in-depth knowledge of signal-pro-
based single-loop continuous-time filter,” in Proc. ISSCC Tech. Dig., cessing techniques, digital communication theory, nonlinear fiber optics, and
Feb. 2008, pp. 72–73. high-speed electronics.
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Jomo K. Edwards received the B.S.E.E. degree from Rutgers University, New Christopher A. Gill received the B.S.E.E. degree from the California Poly-
Brunswick, NJ, in 1997, and the M.S.E.E. degree from Stanford University, Palo technic State University, San Luis Obispo, in 1999.
Alto, CA, in 2000. In 1999, he was with VTC, where he was engaged in research on bipolar-com-
From 1997 to 2000, he was with Agilent Technologies, where he was engaged plimentary metal–oxide–semiconductor preamplifier IC for hard disk drives. He
in research on high-speed transceivers for serial communications links. From then joined QLogic, where he designed low-phase noise voltage-controlled os-
2000 to 2004, he was with the Multilink Technology Corporation, where he cillators (VCOs) and other phase-locked loop (PLL) related circuits. In 2006,
designed SONET, XAUI, and SFI-5 compliant transceivers. From 2004 to 2005, he was with Menara Networks, Irvine, CA, where he was involved in design
N
he was with Globespan, where he designed fractional- frequency synthesizers. type-2 PLLs and dual-edge phase detector blocks. He is currently with Teridian
From 2005 to 2009, he was with Menara Networks, where he was engaged in Semiconductor, Irvine, CA, where he is engaged in research on mixed signal
research on analog timing recovery and equalization techniques for dispersive circuits for modem ICs.
optical links. He is currently with Holt Integrated Circuits, Mission Viejo, CA.
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