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Analog Integrated Circuit Design

Nagendra Krishnapura
Address: Dept. of Electrical Engg., IIT Madras, Chennai, 600036, India.
Phone/Fax: +91-44-2257-4444/+91-44-2257-4402
e-mail: nagendra@iitm.ac.in

A video course under the NPTEL


Assignment problem set

Nagendra Krishnapura, Dept. of EE


Indian Institute of Technology, Madras

Analog Integrated Circuit Design

A video course under the NPTEL

Contents
1 Negative feedback systems

Opamps using controlled sources

Opamp circuits

Components and their models

10

Noise and mismatch

12

Miscellaneous

15

Opamp design at the transistor level

17

Oscillators

19

Bandgap reference

20

10 Low dropout regulator

21

11 Continuous-time filters

22

12 Switched-capacitor filters

24

13 Appreciating approximations

26

2
Nagendra Krishnapura, Dept. of EE
Indian Institute of Technology, Madras

Analog Integrated Circuit Design

A video course under the NPTEL

Topic 1

Negative feedback systems


vi

vo

u
s

+
-

Vi

Ve

f(Ve)

+
-

f()

e-sTd

Vo

(a)
Vi

Figure 1.1: Problem 1

f()

1+f(0)

1.

(a) Setup the differential equation for the system


above.

Vnl
Vi

(b) Vi is 1 V for a long time and changes to 0 V at

+
+

t = 0. What is the equation for t > 0?

Vo

(b)

Vo

(c)

(c) Assume that the solution is of the form


Vp exp(t). Obtain the equation from which

Figure 1.2: Problem 2

you will determine (You are not required to


solve it).

(a) In each case, denote the transfer characteristic


of the overall system by g, i.e. Vo = g(Vi ) and
calculate the first three terms of the Taylor se-

(d) Express the above equation as f () = 0.


Sketch f (). Determine the extremum of f ()
in terms of Td . For what value of Td does the

ries of g about the operating point of the circuit


in terms of f and its derivatives. Assume that

extremum become equal to zero?

f (0) = 0.

(e) Assume that the solution is of the form


Vp exp(( + j)t). Obtain the equations from

(b) Fig. 1.2(c) shows the linear small signal equivalent circuit from Vi to Vo with an additional

which you will determine and (You are not


required to solve them).

input Vnl . For the systems in Fig. 1.2(a) and


(c) Fig. 1.2(b), compute the small signal equivalent
gain A and the additional input Vnl . What do

(f) Reduce the above to a single equation in .


2. Fig. 1.2(a) shows a nonlinearity f enclosed in a
negative feedback loop with a feedback fraction .
VFig. 1.2(b) shows a nonlinearity f preceded by an

you infer from the results?


3. Fig. 1.3(a) shows the amplifier studied in class.
Fig. 1.3(b) shows the same system with the input

attenuation factor.

applied at a different place. Calculate the dc gain,


3
Nagendra Krishnapura, Dept. of EE
Indian Institute of Technology, Madras

Analog Integrated Circuit Design

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Nagendra Krishnapura (nagendra@iitm.ac.in)

Vi

+
-

Ve

Vo

u dt

(k-1)R

Vf

R
(a)
+
-

Ve

Vo

u dt

(k-1)R

Vf

R
(b)

Vi

Figure 1.3: Problem 3


the -3dB bandwidth, and the gain bandwidth product of the system and compare them to the corresponding quantities in Fig. 1.3(b). Also compare
the loop gains. Remark on conventional wisdom
such as constant gain bandwidth product, closed
loop bandwidth = unity gain frequency/closed loop
dc gain. What is the reason for the discrepancy?
Draw an equivalent block diagram of Fig. 1.3(b) such
that the classical form of feedback (sensed error integrated to drive the output) is clearly obvious (Hint:
compute the error voltage Ve ).
4. The loop gain L(s) of a system with N extra poles is
given by
L(s) =

u,loop
1
PN
m
s
m=0 am s

a0 = 1. What does the loop gain step response (inverse laplace transform of L(s)/s) look
like after an initial transient period? Give your answer in terms of the poles of the additional factor (Hint: Split L(s) into a sum of two parts, one of
which is u,loop /s)

Nagendra Krishnapura, Dept. of EE


Indian Institute of Technology, Madras

Analog Integrated Circuit Design

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Topic 2

Opamps using controlled sources


Gf
Vi

Gi

case). Comment on the results.


voltage buffer

Vo

+
GL

Gm2vo1 Go2
1

+
vo1
-

vd

CL

Cc

Gm1vd Go1 Co1

out

(a)
current controlled current source

Ci1

Gm1 Go1 Co1 Cc

Rc

Gm2 Go2

ic

out
+

Gm1vd Go1 Co1

Gm2vo1 Go2

+
vo1
-

vd

Cc

ic

out

(b)
+

Figure 2.1: Problem 1

Gm2vo1 Go2

+
vo1
-

vd
-

1. Gm1 = 20S, Go1 = 0.25S, Gm2 = 80S, Go2 =

Cc

Gm1vd Go1 Co1

out

(c)

2S, GL = Gf = Gi = 4S, Ci1 = 10 fF, Co1 =


40 fF, Cc = 250 fF, CL = 1 pF, Rc = 12.5 k.

Figure 2.2: Problem 2

Determine the poles and zeros of the loop gain

2. The circuits in Fig. 2.2(a, b) are modified


versions of the two stage miller compensated

Calculate them based on approximations discussed


in the class, and by calculating the Loop gain func-

opamp (Fig. 2.2(c)). Calculate their transfer functions and compare them to that of the conventional

tion symbolically and extracting the roots numerically. Comment on the accuracy of approximations.

structure. What is the difference? Explain the results.

Determine the closed loop transfer function and calculate its poles and zeros. How do these relate to
poles and zeros of the loop gain function.

3. Design a three stage opamp (Fig. 2.3(a)) using the


opamp in Fig. 2.1 as the inner opamp (Fig. 2.3(b)).

Plot the unit step response and the loop gain magnitude and phase response.
Change each (one at a time) of Cc , Rc , GL = Gf =

Exclude Rc , Ci1 , Gi , Gf , and GL from Fig. 2.1. Use


C3 = 1 pF. For the first stage of Fig. 2.3, use the
same values as in the first stage of Fig. 2.1. Deter-

Gi to 0.5 and 2 their nominal values. Plot the


unit step response and the loop gain magnitude and

mine the value of Cm1 to obtain a phase margin of


60 . What is the unity gain frequency of the three

phase response (overlaid on the same plot for each

stage opamp?
5

Nagendra Krishnapura, Dept. of EE


Indian Institute of Technology, Madras

Analog Integrated Circuit Design

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Nagendra Krishnapura (nagendra@iitm.ac.in)

6
Cm1

components have their nominal values). Comment


on the results.

Cm2
Gm1

Vi

Ro1

C1

Gm2

Ro2

C2

Gm3

Ro3

Vf

5. Calculate the poles and zeros for each case in the

C3

+
Ve
-

+
Vo
-

above problem. How do they compare to the approximate expressions?

(a)
Cm1
Gm1

Vi
Vf

Ro1

C1

A(s)
+

+
Ve
-

Vo

(b)

Figure 2.3: Problem 3


Where are the poles and zeros? (Derive the expression assuming G1 = G2 = G3 = 0 and find the
roots exactly. Calculate the dc gain and unity gain
frequency separately). Comment on the location of
the zeros.
Connect a zero cancelling resistor in series with Cm2
such that the corresponding zero moves to infinity.
What is the phase margin?
With the zero cancelling resistor in place, adjust Cm1
such that the phase margin is 60 . What is the new
unity gain frequency?

Gs

Cgs Cgd g g
ds
m

CL

GL
+
Vo
-

+
Vs
-

Figure 2.4: Problem 4


4. Fig. 2.4 shows the small signal equivalent circuit of a
common source amplifier. gm = 100S, gds = 1S,
GL = 2S, Gs = 1S, Cgs = 0.1 pF, Cgd =
0.05 pF, CL = 0.5 pF. Plot the magnitude and phase
response of the circuit (overlaid) for the following
cases: a) Cgd = {0, 0.05, 0.1, 0.2, 0.4, 0.8, 1.6} pF,
b) CL = {0, 0.05, 0.1, 0.2, 0.4, 0.8, 1.6} pF, c)
GL = {0, 1, 2, 4, 8, 16} S. (In each case all other

Nagendra Krishnapura, Dept. of EE


Indian Institute of Technology, Madras

Analog Integrated Circuit Design

A video course under the NPTEL

Topic 3

Opamp circuits
(k-1)R

Vi

kR

Rin

Rin

Rout

Rout

Vo

Vo

(k-1)R

Vo

+
Vi

Vi
(a)

R
Ii

Vo
R

(a)
Vi

(b)

Rin

(b)

vopa

Figure 3.1: Problem 1

Rout

1. Fig. 3.1(a) and Fig. 3.1(b) shows amplifiers which

Rin

vopa

+
vopa
R

(c)

Io

Io

+
vopa

Ii
load

Rout

(k-1)R

load

(d)

realize gains of k and k respectively with ideal


opamps. Compare the following parameters of the Figure 3.2: Problem 2. (a) VCVS, (b) CCVS, (c) VCCS,
two circuits. Model the opamp as an integrator u /s. (d) CCCS
(a) Input impedance

3. Due to some parasitic effects, an opamp has a trans-

(b) Bandwidth

fer function with an extra pole p2 (u /s(1 + s/p2 )


instead of u /s). This is used to realize an amplifier with a closed loop dc gain k. Instead of

(c) Differential (V+ (s) V (s)) and common

mode ((V+ (s) + V (s))/2) input voltages of


the opamps

the step response, the criterion here is the bandwidth. Find the conditions to maximize the band-

Assuming that the sign of the gain is unimportant

width without the closed loop gain increasing above


k for any frequency (This condition is known as max-

in your application, what would make you choose


one over the other? Is there any reason to choose
Fig. 3.1(b) at all?

imal flatness, and the mathematical condition is to


have dn /d n |H(j)|2 = 0, n = 1, 2, . . . for as large

2. Fig. 3.2 shows the four types of controlled sources

an n as possible). To avoid mess, assume a general


form of the second order transfer function, evaluate
the damping factor for maximal flatness, and substi-

using an opamp. Model the opamp as an integrator u /s. For each of these, calculate the transfer ratio (output/input), input impedance, and output
impedance at (a) dc, and (b) an arbitrary frequency
. For (b), set Rout = 0 when calculating the input

tute the values from the transfer function of the amplifier. How does it compare to a critically damped
system?

impedance and Rin = while calculating the output impedance. What happens to these three quanti-

4. Fig. 3.3 shows a transimpedance amplifier driven by


a photodiode. The photodiode can be modelled as

ties at high frequencies in each case?


7
Nagendra Krishnapura, Dept. of EE
Indian Institute of Technology, Madras

Analog Integrated Circuit Design

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Nagendra Krishnapura (nagendra@iitm.ac.in)

Llarge

Cf
Clarge

Rf

Vi(j)

Vi(j)

Vo

Vo(j)

Vo1(j)

(a)

(b)

Ao=10

fu=100MHz

Figure 3.4: Problem 5: Measuring an opamps frequency

p2=400MHz

response

1pF

in Fig. 3.4(a), the opamp may not be biased cor-

Is

rectly. As you know, the opamp is biased correctly


only when there is dc negative feedback around the

Figure 3.3: Problem 4


a current source in parallel with a capacitor. The

opamp. A trick to maintain dc negative feedback,


but break the feedback loop for higher frequencies is
shown in Fig. 3.4(b). For frequencies where the volt-

opamp has Ao = 103 , u /2 = 100 MHz and


p2 /2 = 400 MHz (Make a model of the opamp us-

age drop across the capacitor and the current through


the inductor are negligible, the input voltage appears

ing controlled sources and passive elements. A parameterized macromodel of the opamp is very useful

directly across the opamp and there is no feedback.


Since this is a simulator, use comfortably large val-

for future circuit designs).

ues like Clarge = 1 F and Llarge = 1 kH.

(Dont include Cf for this part) What is the largest


transimpedance Rf you can have without peaking in

What are the dc gain, unity gain frequency, and

the frequency response Vo /Is ? Show the ac magnitude response and the transient response to a current

nondominant pole(s)? Estimate these from magnitude/phase plots.


R2

step of 1/Rf Amperes with a 100 ps risetime?


Increase Rf by 20 and show the ac magnitude response step response (current step of 1/Rf Amperes.

Vi

R1

(a)

Vi=0 R1

R2

for maximal flatness. Calculate Cf for the increased


value of Rf and show the magnitude response and

Vtest(j)

-L(j)Vtest(j)

the step response. What does the loop gain look like
for this circuit?
Calculate the expression for the gain-bandwidth

Vo

Compare this to the earlier case and comment on the


results.
Calculate |Vo /Is | including Cf . Find the condition

(b)
R2
Vi=0 R1

product with Cf (gain = Rf ).

(For analytical calculations of maximally flat magnitude response, itll be simpler to use an ideal integra-

-L(j)Vtest(j)

Llarge
Clarge
Vtest(j)

(c)

tor model for the opamp, and then adjust the values
to account for the second pole).

Figure 3.5: Problem 6: Inverting amplifier


5. Simulate the open loop frequency response of the
opamp OPA656. If you try to measure it as given

Nagendra Krishnapura, Dept. of EE


Indian Institute of Technology, Madras

6. Simulate the frequency response and the loop gain of

Analog Integrated Circuit Design

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Analog Integrated Circuit Design; Assignment problem set

an inverting amplifier (Fig. 3.5(a)) of gain 100. Loop


gain L(j) can be determined by breaking the loop
as shown in Fig. 3.5(b). DC negative feedback has
to be maintained and the same trick as in the previous problem can be used (Fig. 3.5(c)). Do these
simulations for R1 = 100 and R1 = 10k . Do
the closed loop bandwidths match the unity loop gain
frequencies? Are the latter in turn consistent with the
opamps unity gain frequency evaluated in the previous experiment? Explain the results clearly.
7. Design inverting and non-inverting amplifers with
gains 5 and +5 respectively using the opamp

OPA656 and 5 V supplies. Simulate these amplifiers with 10 MHz sinusoidal inputs of 400 mV peak.
Compute the distortion components upto the fifth
harmonic and compare the distortion performance of
the two amplifiers.
Plot the differential and common mode inputs of the
opamp in the two cases and explain the results using
the results from the previous problem.
When taking the DFT for distortion analysis, ensure that steady state is reached (wait
for a sufficiently long time before taking the
first point) and that you use an integer number of cycles to avoid spectral leakage (Refer to
http://www.ee.iitm.ac.in/nagendra/E6316/current/handouts.html
or the relevant lecture from EE658 at
http://www.ee.iitm.ac.in/nagendra/videolectures/)
OPA656
model
is
available
at
http://www.ee.iitm.ac.in/nagendra/cadinfo.html

Nagendra Krishnapura, Dept. of EE


Indian Institute of Technology, Madras

Analog Integrated Circuit Design

A video course under the NPTEL

Topic 4

Components and their models


Vbias
V0+vx/2

plate parasitic capacitance.


3. (Repeat this for nMOS and pMOS and compare the
results) Bias a transistor with VGS = VDS = 1.0 V

V0-vx/2

V0+vx/2

and determine W (with L = 0.18 m) to get a current of 200 A. Simulate SID the noise spectral density of drain current from 100 Hz to 100 MHz.

V0-vx/2
200k

Double the length and resize W to get 200 A, and


simulate SID . Repeat until L = 5.76 m. Over-

Figure 4.1: Problem 1


1. (For this problem, The minimum usable dimension
is 0.3 m.) A MOSFET is used as a 200 k re-

lay the spectral density plots (log y axis) and identify the 1/f noise corners. Plot the 1/f noise corners vs. L. Briefly explain the results. Plot ID vs.

sistor (Fig. 4.1) V0 = 0.5 V and vx is restricted to


0.25 V. The nonlinear part of the current (Difference

VDS (0 to 1.8 V) for VGS from 0 to 1.5 V in steps of


0.25 V and VBS = 0 V. Overlay the plots for W/L =

between the exact expression and its linear approximation) in the resistor should be at most 5%. Cal-

3.6 m/0.36 m and W/L = 36 m/3.6 m. Comment on the results.

culate the gate bias Vbias and the dimensions of the


transistor. If a linear resistive material with a sheet
resistance of 10 /sq. is available, what would be

4. Plot ID vs. VDS (0 to 1.8 V) for VBS from -1 V to

its dimensions? What is the motivation for using a


transistor instead of a resistive material?
2. Design a 2 pF capacitor using A square nMOS de-

0 V in steps of 0.25 V and VGS = 1.5 V. Overlay


the plots for W/L = 3.6 m/0.36 m and W/L =
36 m/3.6 m. Comment on the results.
5. Plot (log-log) ID vs.

VGS (18 mV to 1.8 V) for

vice (drain/source shorted). Plot its capacitance as


a function of voltage (0 to 1.8 V). What is the usable

VDS = 1 V and VBS = 0 V. Overlay the


plots for W/L = 3.6 m/0.36 m and W/L =

voltage range of this capacitor? (For this problem use


the process information given in the cadinfo page).

36 m/3.6 m and temperatures of {0, 27, 100} C.


Comment on the results. Calculate the subthreshold

Repeat the above for a square pMOS device.

slope . The current in a MOS transistor in the subthreshold region is proportional to exp(VGS /Vt )

A square Metal1-Metal2 structure.

where Vt is the thermal voltage.

A square sandwiched structure with poly, M2, M4


tied together and M1, M3, M5 tied together.
For the last two structures, determine the bottom

6. Plot (log-log) ID vs. VBS (-1.5 V to -15 mV) for


VDS = 1 V and VGS = 1 V. Overlay the
plots for W/L = 3.6 m/0.36 m and W/L =

10
Nagendra Krishnapura, Dept. of EE
Indian Institute of Technology, Madras

Analog Integrated Circuit Design

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Analog Integrated Circuit Design; Assignment problem set

11

36 m/3.6 m and temperatures of {0, 27, 100} C.


Comment on the results.

Nagendra Krishnapura, Dept. of EE


Indian Institute of Technology, Madras

Analog Integrated Circuit Design

A video course under the NPTEL

Topic 5

Noise and mismatch


Rf
Iin

referred and output noise spectral densities. How

does the simulated noise compare to analytical calculations? What fraction of noise is contributed by
Rf ? (The relative contribution of different compo-

Vo

nents can be printed out in the simulator)

Sv,opa

R
Rf/k

Vpcos(t)
-

Iin

R/k

Vo

Sv,opa

Figure 5.2: Problem 3

Sv,opa

3. The filter in Fig. 5.2 is driven by a sinusoid at =

Rf
Iin

Rx

C vo
-

1/RC. Calculate the output noise voltage, output


signal to noise ratio (ratio of mean squared signal to

Vo

mean squared noise voltages), and the power dissipated in the circuit. If the impedances of all com-

ponents are scaled up by a factor , what happens


to the transfer function of the circuit, output noise
voltage, output signal to noise ratio, and the power

Sv,opa

dissipation?

Figure 5.1: Problem 1

Derive a relationship between the signal to noise ra1. Determine the output noise spectral density and input
referred (current) noise spectral density of the transimpedance amplifiers in Fig. 5.1. The opamp has
an input referred voltage noise spectral density of

tio, power dissipation, and the bandwidth of the circuit (in Hz). What tradeoffs does this relationship
represent?
4. Determine the rms signal, rms noise, signal to noise

Sv,opa V2 /Hz and is otherwise ideal.


2. Design a transimpedance amplifier with a gain of
10 k and the highest possible bandwidth without
peaking using an OPA656 opamp. The photodiode
has a 5 pF capacitance. Simulate the frequency response, step response (100 A step input), and input

ratio (as a ratio of mean squared quantities) at the


output of Fig. 5.3. Assume an low frequency input.
What is the amplifiers transfer function? The opamp
can be either (i) class A (Fig. 5.3(b)): In this case
a constant current Ibias , equal to the highest possible output current) is drawn from the amplifier; or

12
Nagendra Krishnapura, Dept. of EE
Indian Institute of Technology, Madras

Analog Integrated Circuit Design

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Analog Integrated Circuit Design; Assignment problem set

13

Vdd

Ibias=max(iout)

R
R/k

+
Vi=(Vpp/2k)cos(t)

+Vs/2

Vo

+
-Vs/2

+Vs/2
Ibias

I0/n

I0/n
Iout

iout

-Vs/2

W/4n
M
L 2

W
M4
W/n

(a)

(b)
+Vs/2

W
M1

M3

gm4, gds4

gm3, gds3

+Vs/2

Figure 5.5: Problem 6

-Vs/2

-Vs/2
(c)

and 24 , VT 24 between M2 and M4 ). Which of


the mismatches is more critical?

Figure 5.3: Problem 4

Vdd=1.8V

(ii) class B (Fig. 5.3(c)): In this case, currents out of

M1

M2 100A

the opamp are drawn from the positive supply and


currents into the opamp are pushed into the negative

max. voltage=1.1V

supply. In each case, calculate the power dissipation.


Relate the power dissipation to amplifier specifications: gain, bandwidth, and signal to noise ratio.
I0/n

1A

(a)

Vdd=1.8V

M1

M2 100A

Iout
W/n

Vout

M3

M4
Vbiasp2
max. voltage=1.1V
1A

Figure 5.4: Problem 5


5. You are required to design a current mirror that can
operate with an output voltage Vout (Fig. 5.4). The
total current drawn from the supply must be Itot . Determine W/L and n which will maximize the ratio of
signal (load current) to noise (rms current in a bandwidth fB )? Consider only the thermal noise spectral
density. Think about why this value of n is optimal
for signal to noise ratio.
6. Determine the output current in Fig. 5.5. Determine
the output noise current in terms of small signal parameters of M3 and M4 . Which of the devices primarily contribute to the noise? Determine the output current error due to current factor and threshold mismatches (13 , VT 13 between M1 and M3 ,

Nagendra Krishnapura, Dept. of EE


Indian Institute of Technology, Madras

(b)

Figure 5.6: Problem 7


7. Fig. 5.6 shows a simple current mirror and a cascode
current mirror delivering 100 A from a 10 A reference. The maximum voltage at the output can be
1.1 V.
(a) Design the simple mirror with L = 2 m.
(b) Design the cascode current mirror for the same
output voltage constraint with L = 2 m for M1,2 .
Choose M3,4 as you wish subject to the constraints
that the output impedance should be as high as possible at all frequencies and that the output thermal

Analog Integrated Circuit Design

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14

noise spectral density should not increase by more


than 3 dB when compared to the simple current mirror. Provide an arrangement to generate Vbiasp2 .
Plot the output impedance and output current noise
spectral density in for the two mirrors (Terminate the
output with a 1.1 V dc source). What is the relative
noise contribution from different devices? Plot the
dc output current as the output voltage is varied from
0 to 1.8 V.
ID-ID/2

ID+ID/2
+ Vout

+ Vout

+
VGS
-

Figure 5.7: Problem 8


8. Two transistors carrying a current ID are required to
have a current mismatch ID and operate in saturation with an output voltage Vout (Fig. 5.7). Compute the transistor dimensions and its fT in terms of

the mismatch constants AV T and A , ID , ID and


Vout . Comment on the tradeoffs implied by this relationship.

Nagendra Krishnapura, Dept. of EE


Indian Institute of Technology, Madras

Analog Integrated Circuit Design

A video course under the NPTEL

Topic 6

Miscellaneous
1. The circuit in Fig. 6.1(b) is the miller equivalent
of Fig. 6.1(a). Determine the transfer functions of
Fig. 6.1(a) and Fig. 6.1(b)? Are they the same?
Determine the transfer function of Fig. 6.1(c). Replace Fig. 6.1(c) by its miller equivalent Fig. 6.1(d)
and determine its transfer function. Are the results
the same? If not, what are the differences and why?
Carry out this exercise by first omitting Cgs and CL ,
and then including them in the analysis.
Vdd
RL
Vdd
RL

Vo

Vdd
Vi
I0

Vo

Vo

Vi

VG

Rs

Vi
I0
(a)

I0
(b)

I0
(c)

Figure 6.2: Problem 2


2. Determine the spectral density of output noise voltage and input referred noise voltage of the stages in
Fig. 6.2.

15
Nagendra Krishnapura, Dept. of EE
Indian Institute of Technology, Madras

Analog Integrated Circuit Design

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16

C
Rs

Rs C(1+A)
-A

+
Vi
-

+
Vo
-

C(1+1/A)
-A

+
Vi
-

Co

C
Rs
+
Vi
-

+
Vo
-

CL
Cgs

+
Vo
-

Rs

+
Vo
-

Ci

+
Vi
-

gm, gds

gm, gds

Figure 6.1: Problem 1

Nagendra Krishnapura, Dept. of EE


Indian Institute of Technology, Madras

Analog Integrated Circuit Design

A video course under the NPTEL

Topic 7

Opamp design at the transistor level


Vdd
M3

Vdd

M4

M3
vo

Vcm+vcm

Vdd

M4

R1

vo
Vcm+vcm

M1

M2

M1

R2

Vcm+vi/2

M2

Vcm-vi/2
vx

I0

I0/2

I0

gds0

gds0

(a)

(b)

Figure 7.3: Problem 3

Figure 7.1: Problem 1

3. Calculate the small signal tail node voltage vx in


Fig. 7.3. vi is a small signal increment. The tran-

1. The common mode gain of a differential amplifier is


measured by applying a small signal common mode
input vcm as shown in Fig. 7.1. Fig. 7.1(a) has a cur-

sistors can be modeled using gm and gds .

rent mirror load and Fig. 7.1(b) has a current source


load which is independently biased. What is the
common mode gain of these two configurations? Ex-

4.
2

press the answer in terms of the small signal parameters of: M0 (gm0 , gds0 ), M1,2 (gm0 , gds1 = ),

M3,4 (gm3 , gds3 )


I0/2

Vcm+vi/2

1
Vcm vi /2

I0/2

- vo +

Vcm+vi/2

8 pF

+v
o
-

vi = Vip cos(2fin t)

I0

1
2

(b)

(a)

Vcm

Vcm-vi/2

I0

8 pF
+
vout

8 pF

I0/2

Vcm-vi/2

8 pF

1/fs

Figure 7.2: Problem 2


Figure 7.4: Problem 5: Sample and hold circuit
2. Determine the small signal dc gains of the two amplifiers in Fig. 7.2. The transistors can be modeled
using gm and gds . Explain the results.

5. Sample and hold: Design the sample and hold circuit in Fig. 7.4 using the fully differential folded cas-

17
Nagendra Krishnapura, Dept. of EE
Indian Institute of Technology, Madras

Analog Integrated Circuit Design

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Nagendra Krishnapura (nagendra@iitm.ac.in)

18

code opamp designed above. Use ideal switches with


1 k on resistance. Use fs = 4 MHz and fin =
{1/4, 9/4} MHz (sinusoidal input with 1.6 Vppd1
amplitude) and plot the output waveforms. Provide a
plot that shows the settling behavior of the opamp.
10 k
8 pF
10 k
vip

10 k
Vcm

vin

10 k
10 k
8 pF

Vcm = 0.9 V
10 k

vip
Vcm

Vcm
vin

differential step

vip , vin

common mode step

Figure 7.5: Problem 6: Inverting amplifier


6. Inverting amplifier: Design the inverting amplifier
in Fig. 7.5 using the fully differential two stage amplifier designed above. Show the output waveforms
for a 1 V differential step and a 0.5 V common mode
step.

1 Vppd:

volts, peak-peak differential

Nagendra Krishnapura, Dept. of EE


Indian Institute of Technology, Madras

Analog Integrated Circuit Design

A video course under the NPTEL

Topic 8

Oscillators
Vdd
Rs
L

Vdd

Rs
Rdiff

Rs

vom

C
vop

there anything special about it? Model the transistor


using only its gm .

Rs
ix

vom

Vdd

vx

vop

L
ix

I0

Rs

I0

(a)

C1
C2

I0

(b)

Figure 8.3: Problem 3


Figure 8.1: Problem 1
3. Calculate the small signal impedance vx /ix . What is
1. Calculate the current flowing in each transistor in
Fig. 8.1(a) in the quiescent condition. Calculate the
small signal differential resistance Rout looking into

the condition for this to be infinity? What is the frequency at which this happens? Model the transistor
using only its gm .

the drains of the two transistors.


N inverters(N: odd)

In Fig. 8.1(b), calculate (vop vom )/ix . What is

the condition for this to be infinity? What is the frequency at which this happens?

Vdd
Figure 8.4: Problem 4

Zin

C1
C2

4. In Fig. 8.4, assume that all nodes are at the self bias
voltage of the inverter. Model the small signal gain
of each inverter as A0 /(1 + s/p1 ) and calculate the

I0

condition for instability (i.e. when the loop gain becomes 1). Hint: Among the roots of 1, pick the
one which satisfies the above for the lowest value of

Figure 8.2: Problem 2


2. Calculate the input impedance Zin in Fig. 8.2. Is

A0 .

19
Nagendra Krishnapura, Dept. of EE
Indian Institute of Technology, Madras

Analog Integrated Circuit Design

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Topic 9

Bandgap reference
Bias a 1x sized diode connected PNP1 at 5 A as shown
in Fig. 9.1(a) and sweep the temperature from 0 to 100 C.

Vdd

Determine dVBE /dT at 27 C.


Design the bandgap shown in Fig. 9.1(c). Choose R1 for
a quiescent current of 5 A and R2 to get zero tempera-

C1

5A
+
Vbe

ture coefficient at Vbg . Choose R3 = R2 . What is the role


of R3 ? Simulate the bandgap reference with the model

adjust R1,C1,2 and gm1 to model the pole-zero doublet

(a)

and the transconductance of the single stage opamp

(b)

Vdd
W/L

W/L
Vbg
R2

Vx
Vy

+
Cc

R1

and Vbg change? What is the purpose of this modification? Resimulate with the opamp model as before and

output.

model of the
single stage opamp

R3

of R1 , R2 , R3 (= R2 ) if necessary to get zero TC at 27 C.


Modify the circuit as in Fig. 9.1(d). How should Vx , Vy ,

vious assignment and simulate the temperature sensitivity


of Vbg and the transient response to a current step at the

C2

1.0

model of the single stage opamp

and plot Vbg . Test the transient response by applying a


1 uA pulse to the output of the opamp. Adjust the values

test the temperature sensitivity, transient response and the


loop gain.
Substitute the differential pair opamp designed in the pre-

R1

of a single stage opamp assuming that the single stage


opamp is made like the first stage of the previous problem. (Fig. 9.1(b)-model the gm, and the pole zero doublet). Choose Cc for ringing 10%. Test the bandgap
reference by sweeping the temperature from 0 to 100 C

gm1

1G

1x

1A pulse for
transient test

8x

(c)
Vdd
W/L

W/L

single stage opamp

Vz or Vx

Vbg
Vz

Vw or Vy

Vw

+
R2

R3

Vx

Cc

1A pulse for
transient test

Vy
R1
connect the opamp inputs to

1x

8x

Vx and Vy OR Vz and Vw depending on the


input common mode range

(d)

Figure 9.1: Bandgap reference


1 Use

the model ideal pnp in ideal diode.lib

20
Nagendra Krishnapura, Dept. of EE
Indian Institute of Technology, Madras

Analog Integrated Circuit Design

A video course under the NPTEL

Topic 10

Low dropout regulator


Vdd
Bandgap
reference

1.2V

output voltage is constant over time. These are departures from conventional amplifiers.

Isup
IL

Vout

Fig. 10.1(b) shows a pass transistor M1 enclosed in a

Load

feedback loop. For simplicity, a unity gain case is shown.


M1 should have a high enough W/L to remain in saturation with the desired dropout and the highest output

R2
R1
(a)
Bandgap
reference

1.2V

current. Miller compensation around M1 is usually not


used because it severely compromises power supply re-

Vdd

jection (Incremental voltage gain from Vdd to the output


voltage).

M1
+
Vout
20A

IL
Load

CL

(b)

Use the model in Fig. 9.1(b) for the single stage opamp.
Use a 50 A quiescent current in M1 . Adjust the
width (with minimum length) of M1 for a dropout of
300 mV with a 50 mA current. You can use a 1.2V voltage
source in place of the bandgap reference. Compensate the

Zout

loop using a load capacitor CL for a phase margin of 45


at IL = 0 and IL = 50 mA and choose the higher one. Do

Figure 10.1: Low dropout regulator

A voltage regulator is nothing but a noninverting amplifier the following (except the last one) for two cases (IL = 0
whose input is the bandgap voltage from a reference. In and IL = 50 mAyou can use a current source for the
Fig. 10.1(a), the output voltage is (R2 /R1 )Vbg . By mak- load):
ing R2 variable, one can get a variable voltage output.

1. Vary Vdd from 1.4 V to 1.8 V and plot Vout

The output impedance should be very low: This is


accomplished by realizing a very high loop gain over
as wide a bandwidth as possible.
The efficiency ((Vout IL )/(Vdd Isup )) should be very

2. Plot Zout from 1 kHz to 10 MHz


3. Plot the transfer function from Vdd to Vout from
1 kHz to 10 MHz

high: For this, the current Isup IL consumed by the


circuit should be minimized (This makes it hard to

4. Plot the small signal step response for a 10 A step


in the output current

satisfy the previous condition). The dropout Vdd


Vout should be minimized.

5. Plot the large signal step response (IL switching


from zero to 50 mA and 50 mA to zero)

Usually only a positive IL needs to be driven. The


21
Nagendra Krishnapura, Dept. of EE
Indian Institute of Technology, Madras

Analog Integrated Circuit Design

A video course under the NPTEL

Topic 11

Continuous-time filters
(a) Compute the transfer functions Vo /Vi in terms

(b) Using the parameterized subcircuits for the bi-

of the parameters (Q, p , b0 , b1 , b2 ) for the circuits in Fig. 11.1(a, b).


(b) Turn these circuits into parameterized subcir-

linear and the biquadratic filters, simulate the


four filters (using the cascade structure) in a circuit simulator. Use the rules of cascading dis-

cuits bilinear and biquad in a circuit simulator1 with the required parameters. You can

cussed in the lectures. Clearly state the order of


cascade and the pole zero pairing.

then use these subcircuits to realize ideal cascade realizations of any transfer function.

For the Bessel filter, simulate the frequency

1.

0dB

0dB

-1dB

-1dB

-40dB

-40dB

response of the prototype (last column of Table 11.1). If this filter were scaled such that it
had an attenuation As = 40 dB at 2 MHz (the
stopband edge), what would be its attenuation
at the passband edge (1 MHz)?2 Does it meet
the specs in Fig. 11.2(a)?

(a)

2 rad/s

1 rad/s

2MHz

1MHz

Now simulate the scaled Bessel filter.


Plot their magnitude and phase responses3 , and
the group delay.

(b)

(c) For each filter, determine the maximum transfer function magnitude from the input to each
of the stage (first or second order) outputs. If
each output were limited to 1 V, what is the

Figure 11.2: Problem 2


2. You are required to realize a filter that meets
the specifications shown in Fig. 11.2(a). You

maximum input voltage that could be applied


to each without having distortion?

are given (Table 11.1) the poles and zeros of 4


types (Excluding Bessel) of filters which satisfy the

(d) For each of the 5 filters list the maximum


quality factor of the biquad stages used, the
maximum resonant frequency, and the maxi-

prototype specifications in Fig. 11.2(b).


(a) Tabulate the order, the resonance frequencies,
the quality factors of the poles, and the location of transmission zeros (if present) of the different types of filters that satisfy the specs. in
Fig. 11.2(a).
1 In

circuit simulators, to realize a current controlled voltage source,


you also usually need to have a 0 V voltage source through which the
desired current is flowing.

2 You dont need to rescale the filter and simulate. You should be able
to answer this by looking at the prototype response.
3 Plot the magnitude responses of the 5 filters in the same plot; same
for the phase response and the group delay. Plot the magnitude response (in dB) twiceonce showing the whole picture and once zoomed
in on the passband. Use sensible scales so that the details of the response
can be seen. e.g. with notches, the response goes down to dB and
the default scale may be totally unsuitable.

22
Nagendra Krishnapura, Dept. of EE
Indian Institute of Technology, Madras

Analog Integrated Circuit Design

A video course under the NPTEL

+
Vi
-

+
C=1/p R=1

+
-

b1IC

+
-

b0IR

Vo

Vi
IC

23
transconductance=1S

transconductance=1S

Analog Integrated Circuit Design; Assignment problem set

+
Vi
-

C=1/p R=Q

L=1/p

Vi

IR

IC

(a)

IR

+
-

b2IC

+
-

b1IR Vo

+
-

b0IL

IL
(b)

"bilinear"

"biquad"

Figure 11.1: Problem 1


mum group delay variation in the passband (<
1 MHz). This gives you a comparison of different types of filters that are designed to meet a
given specification (Fig. 11.2).

Table 11.1: Prototype zeros and poles

Butterworth

Chebyshev

Inverse Chebyshev

Elliptic

Bessel

poles

poles

zeros

poles

zeros

poles

poles

1.1031 j0.2194

0.0895 j0.9901

j3.0671

0.2811 j1.1013

j3.5251

0.3643 j0.4786

0.3868 j1.0991

0.9351 j0.6248

0.2342 j0.6119

j1.8956

0.9461 j0.8751

j1.6095

0.1053 j0.9937

0.6127 j0.8548

0.6248 j0.9351

0.2895

1.4202

0.2194 j1.1031

0.7547 j0.6319
0.8453 j0.4179
0.8964 j0.2080
0.9129

Nagendra Krishnapura, Dept. of EE


Indian Institute of Technology, Madras

Analog Integrated Circuit Design

A video course under the NPTEL

Topic 12

Switched-capacitor filters
1. A continous time first order filter has a transfer function
Hc (s) =

3. Simulate each of the filters designed in problem 3


in a circuit simulator. Plot the magnitude and phase
responses.

2
1 + s/p

4. A second order filter has a transfer function has the


form

p = 2 20 krad/s. Transform Hc (s) into discrete

time transfer functions Hd (z) using bilinear transformation. The sampling frequency fs = 1 MHz.

Plot the magnitude and phase responses of Hc and

H(s) =

N (s)
1 + (s/Qp p ) + (s/p )2

Hd with the real frequency (Hz) from 0 to 1 MHz


along the x axis. Are the magnitude and phase responses the same for all the cases? Comment on the

(a) What is N(s) for lowpass, bandpass, highpass,

results.

(b) Transform each of these into a discrete time fil-

and band stop filters? (In each case, assume that


the gain in the center of the passband is unity)
ter using bilinear transformation. Assume that
Qp = 4 and p = fs /10, where fs is the sam-

Repeat for p = 2 200 krad/s.


2. Design the above filter (Hc (s) or Hd (z)) as

pling frequency.

(a) a continuous time opamp-RC filter


(b) bilinear transformed switched capacitor filter (for this, assume that both the input Vi and
its inverted form Vi are available)
(c) switched capacitor version of a) with the resistor replaced by a switched capacitor

(c) Sketch the pole zero plots of the continumous


time filters and their discrete time counterparts.
5. Compute the transfer function V1 /Vi in the Fleischer
Laker biquad. Fig. 12.1. The output is defined at the
end of 1 and the input Vi changes on the rising edge
of 2 .

(d) Noninverting delayed switched capacitor integrator whose magnitude response is equal to

6. Transform a second order CT (continuous time)

that of the bilinear transformed filter at dc and


the 3 dB frequency (i.e., the pole of the SC in-

bandpass filter into a DT(discrete time) bandpass filter using bilinear transformation. The gain at center

tegrator should be adjusted such that its -3dB


frequency is the same as that of the LDI trans-

frequency and the quality factor of the CT prototype


are both 10. The resonant frequency fp (in Hz) is
20% of the sampling frequency fs (in Hz).

formed filter).
Do it for both p = 2 20 krad/sand p = 2
200 krad/s. In each case, give the schematic and the
component values.

7. Compute the values of the capacitors in the


Fleischer-Laker biquad to realize the above filter.
Assume B = D = 1 and A = C. Also, usually,

24
Nagendra Krishnapura, Dept. of EE
Indian Institute of Technology, Madras

Analog Integrated Circuit Design

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Analog Integrated Circuit Design; Assignment problem set

25

E
2

1
2

Vi

n+2

n+1

1
H

V1

n-1

2
1

1
2
2

1
J

V2

Vi[n-1]

Vi[n]

Vi[n+1]

Vi[n+2]

V1[n-1]

V1[n]

V1[n+1]

V1[n+2]

V2[n-1]

V2[n]

V2[n+1]

V2[n+2]

(input)

Figure 12.1: Problem 5


you can set one of G, H, I, J to zero. Try each of the
following cases
(a) V1 as output; F circuit (E = 0)
(b) V1 as output; E circuit (F = 0)
(c) V2 as output; F circuit (E = 0)
(d) V2 as output; E circuit (F = 0)
What is the spread in capacitor values (The ratio of
the largest to the smallest capacitor) in each case?
8. Simulate the magnitude and phase responses of
the first case above in a circuit simulator. See
the handout below on guidelines to simulating switched capacitor filters in a circuit simulator:
http://www.ee.iitm.ac.in/nagendra/E4215/2004/handouts/scfsim.pdf

Nagendra Krishnapura, Dept. of EE


Indian Institute of Technology, Madras

Analog Integrated Circuit Design

A video course under the NPTEL

Topic 13

Appreciating approximations
Approximations are key to understanding anything complicated. Exact expressions, even when possible, may be
too complicated to give any insight to the problem. Approximating is not the same as being sloppy. On the contrary, a greater understanding of the problem is required
to judiciously use approximations than plug in the whole
formula (e.g. see the quadratic eq. example below).
Evaluate the conditions for 1% and 10% accuracy for the
quantities mentioned using the approximations below.

1. You are required to calculate 1 + x and you approximate it by 1 + x/2.


2. You are required to solve the quadratic equation
ax2 +bx+c and you approximate the roots by b/a,
c/b. This works for widely separated real roots.
How widely do they have to be separated (ratio)?

3. You have a two stage amplifier in feedback loop with


loop gain L(s) = A0,loop /(1 + s/p1 )(1 + s/p2 ),
p2 > p1 , p1 = u,loop /A0,loop and you approximate
it by moving the lower frequency pole to the origin
i.e. use the transfer function L(s) (u,loop /s)(1 +
s/p2 ) instead. You have to calculate (a) natural frequency n , (b) damping factor . Compare the expressions for the two quantities. Calculate A0,loop to
get the above errors (Assume p2 = 2u,loop ).
The above are rather simple examples to show how much
you can get away with, if you use judicious approximations. See the book below for an extensive treatment of
approximation techniques.
Sanjoy Mahajan, Street-Fighting Mathematics: The Art of
Educated Guessing and Opportunistic Problem Solving,
The MIT Press, 2010.
26
Nagendra Krishnapura, Dept. of EE
Indian Institute of Technology, Madras

Analog Integrated Circuit Design

A video course under the NPTEL