Seminar Report

TRI-GATE TRANSISTOR
iv
Babu Banarasi Das Northern India Institute of Technology
, Lucknow
INTRODUCTION
Since their inception in the late 1950s, planar transistors have acted as the basic
building block of microprocessors. The scaling of planar transistors requires the
scaling of gate oxides andsource/drain junctions. However, as these transistor
elements become harder to scale, so does thetransistor gate length. The scaling of
planar transistors is getting more difficult due to theworsening electrostatics and
short-channel performance with reducing gate-length dimension. Ina multigate
device, the channel is surrounded by several gates on multiple surfaces,
allowingmore effective suppression of "off-state" leakage current. Multiple gates
also allow enhancedcurrent in the "on" state, also known as drive current. These
advantages translate to lower power consumption and enhanced device
performance. Non-planar devices are also more compact thanconventional planar
transistors, enabling higher transistor density which translates to smaller overall
microelectronics.A new transistor architecture that can significantly improve the
electrostatics and short-channel performance is the tri-gate transistor, as shown in
Figure 1
.This transistor, which can befabricated either on the SOI substrate or standard
bulk-silicon substrate, has a gate electrode onthe top and two gate electrodes on the
sides of the silicon body.
Figure 1.
Tri-Gate Transistor.

HISTORY OF TRANSISTORS
A transistor is a semiconductor device used to amplify and switch electronic
signals and power.It is composed of a semiconductor material with at least three
terminals for connection to anexternal circuit. A voltage or current applied to one
pair of the transistor's terminals changes thecurrent flowing through another pair of
terminals. Because the controlled (output) power can behigher than the controlling
(input) power, a transistor can amplify a signal. Today, sometransistors are
packaged individually, but many more are found embedded in integrated
circuits.The transistor is the fundamental building block of modern electronic
devices, and is ubiquitousin modern electronic systems. Following its development
in the early 1950s the transistor revolutionized the field of electronics, and paved
the way for smaller and cheaper radios,calculators, and computers, among other
things.The thermionic triode, a vacuum tube invented in 1907, propelled the
electronics age forward,enabling amplified radio technology and long-distance
telephony. The triode, however, was afragile device that consumed a lot of power.
Physicist Julius Edgar Lilienfeld filed a patent for afield-effect transistor (FET) in
Canada in 1925, which was intended to be a solid-statereplacement for the triode.
Lilienfeld also filed identical patents in the United States in 1926 and1928.
However, Lilienfeld did not publish any research articles about his devices nor did
his patents cite any specific examples of a working
prototype. Since the production of high-qualitysemiconductor materials was still
decades away, Lilienfeld's solid-state amplifier ideas wouldnot have found
practical use in the 1920s and 1930s, even if such a device were built. In
1934,German inventor Oskar Heil patented a similar device.From November 17,
1947 to December 23, 1947, John Bardeen and Walter Brattain at AT&T'sBell Labs
in the United States, performed experiments and observed that when two gold
pointcontacts were applied to a crystal of germanium, a signal was produced with
the output power greater than the input. Solid State Physics Group leader William
Shockley saw the potential inthis, and over the next few months worked to greatly
expand the knowledge of semiconductors.The term transistor was coined by John
R. Pierce as a
portmanteau of the term "transfer resistor".According to Lillian Hoddeson and
Vicki Daitch, authors of a recent biography of John Bardeen,Shockley had
proposed that Bell Labs' first patent for a transistor should be based on the field-e
ffect and that he be named as the inventor. Having unearthed Lilienfelds patents
that went into

obscurity years earlier, lawyers at Bell Labs advised against Shockley's proposal
since the idea of a field-effect transistor which used an electric field as a
grid was not new. Instead, what
Bardeen, Brattain, and Shockley invented in 1947 was the first bipolar pointcontact transistor. Inacknowledgement of this accomplishment, Shockley, Bardeen,
and Brattain were jointlyawarded the 1956 Nobel Prize in Physics "for their
researches on semiconductors and their discovery of the transistor effect."
In 1948, the point-contact transistor was independently invented
by German physicists Herbert Matar and Heinrich Welker while
working at the Compagnie des Freins et Signaux, aWestinghouse
subsidiary located in Paris. Matar had previous experience in
developing crystalrectifiers from silicon and germanium in the
German radar effort during World War II. Usingthis knowledge, he
began researching the phenomenon of "interference" in 1947. By
witnessingcurrents flowing through point-contacts, similar to what
Bardeen and Brattain had accomplishedearlier in December 1947,
Matar by June 1948, was able to produce consistent results by
usingsamples of germanium produced by Welker. Realizing that
Bell Labs' scientists had alreadyinvented the transistor before
them, the company rushed to get its "transistron" into
productionfor amplified use in France's telephone network.The
first silicon transistor was produced by Texas Instruments in 1954.
This was the work of Gordon Teal, an expert in growing crystals of
high purity, who had previously worked at BellLabs. The first MOS
transistor actually built was by Kahng and Atalla at Bell Labs in
1960

MOSFET
Scaling and Moores Law
In 1965, Gordon Moore published his famous paper describing the evolution of the
transistor density in integrated circuits. He predicted that the number of transistors
per chip wouldquadruple every three years. This prediction became known as
Moores law
and has beenremarkably followed by the semiconductor industry for the last forty
years (Figure1.1).Since the
early 1990s semiconductor companies and academia have
teamed up to predict more preciselythe future of the industry. This initiative gave
birth to the International Technology Roadmap for Semiconductors (ITRS)
organization. Every year, the ITRS issues are port that serves as a benchmark for
the semiconductor industry. These reports describe the type of technology,
designtools, equipment and metrology tools that have to be developed in order to
keep pace with the
exponential progress of semiconductor devices predicted by Moores law.
Figure 1.1 shows theevolution of the number of transistors per chip predicted by
the ITRS 2005 for DRAMs andhigh-performance microprocessors.
The semiconductor industrys workhorse technology is
silicon CMOS, and the building block of CMOS is the MOS transistor, or
MOSFET(MOS field-effect transistor). In order to keep up with the frantic pace
imposed by Moores law, the linear
dimensions of transistors have reduced by half every three years. The sub-micron
dimension barrier was overcome
in the early 1980s, and in 2010 semiconductor manufacturers will produce
transistors with a 20nm gate length on a regular basis. Since the first integrated
circuit transistors
were fabricated on bulk silicon wafers. At
the end of the 1990s, however, it became apparent
that significant performance improvement could be gained by switching to a new
type of substrate, called SOI (Silicon-On-Insulator) in which transistors are made
in a thin silicon layer sitting on top of a silicon dioxide layer. SOI technology
brings about improvements in both
circuit speed and power consumption. In the early 2000s major semicon

ductor companies,including IBM, AMD and Free scale, began manufacturing

microprocessors using SOI substrateson an industrial scale. SOI devices offer the
advantage of reduced parasitic capacitances andenhanced current drive

Seminar Report
TRI-GATE TRANSISTOR
viii
Babu Banarasi Das Northern India Institute of Technology
, Lucknow
Gate Geometry and Electrostatic Integrity
Short-channel effects arise when control of the channel region by the gate is
affected by electricfield lines from source and drain. These field lines is illustrated
graphically in Figure 1.2. In
a bulk device (Fig. 1.2.A), the electric field lines propagate through the depletion r
egionsassociated with the junctions. Their influence on the channel can be reduced
by increasing thedoping concentration in the channel region. In very small devices,
unfortunately, the dopingconcentration becomes too high (10
19
cm
-3
) for proper device operation. In a fully depleted
SOI
(FDSOI) device, most of the field lines propagate trough the buried oxide (BOX)
before reachingthe channel region (Fig. 1.2.B). Short channel effects in
FDSOI
devices may be better or worsethan in bulk MOSFETs, depending on the silicon
film thickness, buried oxide thickness, anddoping concentrations. Short-channel
effects can be reduced in FDSOI MOSFETs by using athin buried oxide and an
underlying ground plane. In that case, most of the electric field linesfrom the
source and drain terminate on the buried ground plane instead of the channel
region(Figure 1.2.C). This approach, however, has the inconvenience of increased
junction capacitanceand body effect. A much more efficient device configuration is
obtained by using the double-gate transistor structure. This device structure was
first proposed by Sekigawa and Hayashi in1984 and was shown to reduce
threshold voltage roll-off in short-cannel devices. In a double-gate device, both
gates are connected together. The electric field lines from source and
drainunderneath the device terminate on the bottom gate electrode and cannot,

therefore, reach thechannel region (Fig. 1.2.D). Only the field lines that propagate
through the silicon film itself canencroach on the channel region and degrade
short-channel characteristics. This encroachmentcan be reduced by reducing the
silicon film thickness.
MULTIGATE DEVICES
A
multigate device
or
multiple gate field-effect transistor
(
MuGFET
) refers to a MOSFETwhich incorporates more than one gate into a single device.
The multiple gates may be controlled by a single gate electrode, wherein the
multiple gate surfaces act electrically as a single gate,
or by independent gate electrodes. A multigate device employing independent gate
electrodes issometimes called a
Multiple Independent Gate Field Effect Transistor
or
MIGFET
.Multigate transistors are one of several strategies being developed by CMOS
semiconductor manufacturers to create ever-smaller microprocessors and memory
cells, colloquially referred toas extending
Moore's Law
which states that the number of transistors on a chip will doubleabout every two
years. Intel has kept that pace for over 40 years, providing more functions on achip
at significantly lower cost per function. Other complementary strategies for device
scalinginclude channel strain engineering, silicon-on-insulator-based technologies,
and high-k/metalgate materials.In a multigate device, the channel is surrounded by
several gates on multiple surfaces, allowingmore effective suppression of
"off-state"
leakage current. Multiple gates also allow enhancedcurrent in the "on" state, also
known as drive current. These advantages translate to lower power consumption
and enhanced device performance. Non-planar devices are also more compact
thanconventional planar transistors, enabling higher transistor density which
translates to smaller overall microelectronics.
MULTIGATE SOI MOSFETs :
The first SOI transistor dates back to 1964. These were partially depleted devices
fabricated onsilicon-sapphire (SOS) substrates. SOS technology was successfully
used for numerous militaryand civilian applications and is still being used to
realize commercial HF circuits in fullydepleted CMOS. Once the first SOI

substrates (the insulator is now silicon dioxide) wereavailable for experimental

MOS device fabrication, partially depleted technology the naturalchoice derived
from SOS experience. Partially depleted CMOS continues to be used nowadaysand
several commercial IC manufacturers have SOI products and product lines such
asmicroprocessors and memory chips. Variations on the partially depleted SOI
MOSFET themeinclude devices where the gate is connected to the floating body.
These devices, which have beencalled
voltage
-controlled bipolar-MOS device
, hybrid bipolar
MOS device
,
gate
controlled lateral BJT, multiple
-threshold C
MOS, dynamic threshold MOS
, or
var
iable-thresh
old MOS have
ideal subthreshold characteristics, reduced body effect,improved current drive, and
superior HF characteristics. They are mostly used for very low-voltage (0.5 V)
applications.
Figure 1.6 shows the Family Tree of SOI MOSFETs and shows the
evolution from partiallydepleted, single-gate devices to multi-gate, fully depleted
structures. Partially depleted silicon
MOSFETs are the successors of earlier SOS (Silicon-On-Sapphire) devices.
PDSOI MOSFETswere first used for niche applications such as radiation-hardened
or high-temperature electronics.At the turn of the century PDSOI technology
became main stream as major semiconductor manufacturers started to use it to
fabricate high-performance microprocessors. The low-voltage performance of
PDSOI devices can be enhanced by creating a contact between the gate
electrodeand the floating body of the device. Such a contact improves the sub
threshold slope, body factor and current drive, but limits the device operation to
sub-1V supply voltages. Fully depleted SOIdevices have a better electrostatic

coupling between the gate and the channel. This results in a better linearity, sub
threshold slope, body coefficient and current drive
.
FDSOI technology isused in a number of applications ranging from low-voltage,
low-power to RF integrated circuits.
DELTA/FinFET structureGate-all-around (GAA) MOSFET

he triple-gate MOSFET is a thin-film, narrow silicon island with a

gate on three of its sides.
mplementations include the quantum-wire SOI MOSFET and the
tri-gate MOSFET. Improvedversions feature either a field-induced,
pseudo-fourth gate such as the P-gate device and the X-gate
device. The structure that theoretically offers the best possible
control of the channel region by the gate is the surroundinggate MOSFET. Such a device is usually fabricated using a pillar-like
silicon island with a vertical-channel. Such devices include the
CYNTHIA device (circular-section device, Fig. 5) and the pillar
surrounding-gate MOSFET (square-section device)
Current drive of multiple-gate SOI MOSFETs
The current drive of multiple-gate SOI MOSFETs is essentially proportional to the
total gatewidth. For instance, the current drive of a double-gate device is double
that of a single-gatetransistor with same gate length and width. In triple-gate and
vertical double-gate structures allindividual devices need to have the same
thickness and width. As a result the current drive isfixed to a single, discrete value,
for a given gate length. To drive larger currents multi-fingereddevices need to be
used. The current drive of a multi-fingered MOSFET is then equal to thecurrent of
an individual device multiplied by the number of fingers (also sometimes referred
to
as fins or legs). Considering a pitch P for the fingers, the current per unit
device width is
given by:I
D
=I
D0
(W + 2t
si
)/Pwhere I
D0
is the current of a unit-width, planar, single gate device, and where W is the width
of each individual finger, t
si
is the silicon film thickness, and P is the finger pitch (Fig. 6). TheFinFET device
achieves high current drive through the use of a relatively thick silicon thickness.In
that device there is no current flow at the top of the silicon island, such that I

D
=I
D0
(2t
si
/P). Intriple gate devices (where t
si
= W) the finger pitch needs to be smaller than 3W to obtain a larger current drive
than in a single-gate, planar device occupying the same silicon real estate.
Cross-section of a multi-fingered triple-gate MOSFET (left) and SEM picture of
the fingers (right
SHORT CHANNEL EFFECT:
It is possible to predict how small the silicon film thickness should
be in multiple-gate devices toavoid short-channel effects (or, at
least, to maintain a decent sub threshold swing). Sub
thresholdswing degradation and other short-channel effects are
caused by the encroachment of electricfield line from the drain on
the channel region, thereby competing for the
available depletioncharge, and reducing the threshold voltage.
Definition of coordinate system in a multiple-gate device. Gateinduced fields are in the x- and z-directions. Drain penetration
field is in the y-direction.
Fig. 7 shows how the gates and the drain compete for the
depletion charge. Gate control isexerted in the yand z-directions
and competes with the variation of electric field in the x-direction
due to the drain voltage. The one-dimensional analysis of a fully
depleted device yieldsa parabolic potential distribution in the
silicon film in the y (vertical) direction
Triple- gate structures
It is quite clear from the above considerations, than the
surrounding-gate structure offers the
best possible characteristics in terms of current drive and short ch
annel effects control. Allsurrounding-gate devices reported in the

literature have a vertical-channel and have a non-planar nature,

and the source and drain are situated at different depths in the
silicon film (Fig. 5). It is,however, possible to design and fabricate
quasi-surrounding- gate MOSFETs using a processsimilar to that
used to fabricate triple-gate SOI MOSFETs. Such devices are called
either P-gate[39,40] or X-gate [41] MOSFETs (Fig. 9). These
devices are basically triple gate devices with anextension of the
gate electrode below the active silicon island, which increases
current drive andimproves short-channel effects. The gate
extension can readily be formed by slightly over etching the
buried oxide (BOX) during the silicon island patterning step. The
gate extensionforms a virtual, field induced gate electrode
underneath the device that can block drain electricfield lines from
encroaching on the channel region at the bottom of the active
silicon. Instead thelines terminate on the gate extensions. This
gate structure is very effective at reducing short-channel effects.
Such devices can be called 3 (triple-plus)-gate devices because
their characteristics lie between those of triple- and quadruplegate devices. Fig. 10 presents theequipotential line distribution in
(A) a triple-gate, (B) a quadruple-gate, and (C) Pi-gate device.The
gate length silicon film thickness and width are 30, 50, and 50 nm
respectively. The gatevoltage and substrate (back gate) voltages
are 0V, while the drain voltage is 1 V. Encroachmentof electric
field from drain on the channel region can be seen in the triplegate device, but not inthe Pi-gate and quadruple-gate devices.
These contour plots illustrate the effectiveness of thefieldinduced, pseudo back gate created by the gate extension. Fig. 11
compares the subthreshold swing of transistors with 2

4 gates with that of a P-gate device. Increasing the number of

gates improves the sub threshold swing because the control of
the channel region by thegate(s) becomes more effective and
because multiple gates offer more shielding plates protectingthe

channel region from the electric field lines from the drain. It
should be noted that the performances of the P-gate structure are
very close to those of a 4-gate device.
P-gate (Pi-gate) and X-gate (Omega-gate) MOSFET cross-sections

TRI-GATE TRANSISTORS

Tri-gate
or
3-D
are the terms used by Intel Corporation to describe their nonplanar transistor architecture planned for use in future
microprocessors. These transistors employ a single gatestacked
on top of two vertical gates allowing for essentially three times
the surface area for electrons to travel. Intel reports that their trigate transistors reduce leakage and consume far less power than
current transistors. This allows up to 37% higher speed, and a
power consumption atunder 50% of the previous type
of transistors used by Intel.Intel explains, "The additional control
enables as much transistor current flowing as possiblewhen the
transistor is in the 'on' state (for performance), and as close to
zero as possible when itis in the 'off' state (to minimize power),
and enables the transistor to switch very quickly betweenthe two
states (again, for performance)."
The worlds first demonstration of a 22nm microprocessor
--code-named Ivy Bridge --that will be the first highvolume chip to use 3-D Tri-Gate transistors. Further to increase th
e drivestrength for increased performance, multiple fins are used.
Figure 2.a
shows such a design with just a single fin while that of
figure 2.b
and

figure 2.c
show designs with two and three finsrespectively.
Figure 2.a
Design with a single Fin
Figure 2.b
Design with a two Fins

PERFORMANCE TEST RESULTS

The performance tests were done by Intel with other planar
devices of different technologies andthe test results are obtained
for Gate voltage versus Channel current shown in figure 3
(fig 3.aand fig 3.b)
and Operating Voltage versus Transistor Gate Delay shown in
figure4 (fig4.a-fig4.d).
Figure 3.a
Comparison of Planar and Tri-Gate

CONCLUSION

As transistors get smaller, parasitic leakage currents and power

dissipation become significantissues. By integrating the novel
three-dimensional design of the tri-gate transistor with

advancedsemiconductor technology such as strain engineering

and high-k/metal gate stack, Intel hasdeveloped an innovative
approach toward addressing the current leakage problem
whilecontinuing to improve device performance.Because tri-gate
transistors greatly improve performance and energy efficiency,
they enable toextend the scaling of silicon transistors. Intel
expects that the tri-gate transistors could becomethe basic
building block for microprocessors in future technology nodes.
The technology can beintegrated into an economical, high-volume
manufacturing

process, leading to high-performanceand low-power products.