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Throughout the labs we will use a generic, foundry independent 90nm CMOS mixed-signal process
kit developed by Cadence. We will call it generic PDK 90 nm briefly as gpdk90. As seen from the
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figure above a PDK contains all the necessary design and technology data to successfully design
and simulate a VLSI chip on a particular foundry. The foundry provides the necessary
technological data, design rules, and the device models. Also PDK contains schematic symbols
with all necessary views, as well as device extraction rules for Layout versus Schematic (LVS)
check. It also provides parasitic extraction rules.
3. In the library path editor execute File Save as. Make sure that both cds.lib and lib.defs are
selected.
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Click OK the new paths will be saved and you will be able to use the above library.
4. Following the above procedure add the analogLib library from the following location
/usr/local/cadence/ic612/tools.lnx86/dfII/etc/cdslib/artist
5. Similarly add the library basic from the following location
/usr/local/cadence/ic612/tools.lnx86/dfII/etc/cdslib
Creating a library
Now we will create a working library to store our design and attach it to desired technology library.
1. In the CIW, execute File New Library
2. The new Library form appears. In the name field of the New Library type gpdktraining.
3. In the field under the Directory Section, verify that the path to the library is set to
/var/home/EEE458GRPx/
4. Select Attach to an existing tech file and click ok.
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7. Repeat this for PMOS to set Total Width and Finger Width to 480nm. To deselect the
object press keyboard command contrl-d.
8. Next, instantiate DC voltage source (cell vdc from analogLib library) to bias the transistors.
Place VDC in a suitable place in the schematic window to simulate Drain-Source Voltge
VDS. Similarly place VDC to simulate Gate Source Voltage VGS. Since we are going to
sweep values of gate and drain voltages, specify parametric values VGS and VDS as DC
voltage under object properties.
Now save the parametric settings shown below:
9. Use Add Wire menu or simply press w key to enter wiring mode / Esc to exit. It is a
good practice to periodically save your work by clicking on Check and Save button (the
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checkmark button just below of the Tools menu). You can also save your work from the
drop-down menu Design Save.
10. The last step is to add zero valued voltage sources in series with the transistors in order to
be able to probe the currents. The final schematic looks like this:
Click Close and point your mouse cursor over the Virtuoso editing window.
Make sure that the view name field in the form is set to symbol. You will update the Library
Name, Cell Name, and the property values given in the table below as you place each
component.
1-7. Netlist Creation and Simulation using Spectre and observation of MOS I-V
Characteristics
Opening the Analog Design Environment
1. In the Schematic window execute Launch ADE L
Analog Design Environment (ADE) window will open.
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5. In this model libraries there are models to simulate various corners like fast-fast (FF), fastslow (FS), typical-typical(TT) etc. We will choose the section typical from the section scroll
bar and select the section 'TT_s1v'. These will enable us to use the TT models of the 1.2 V
MOS transistors.
6. Now we will edit the variables. Execute Variables Edit to specify initial values for VDS
and VGS parameters. Enter VDS in the Name field and 0.5 in the Value (Expr) field and
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click Add to save the variable settings. Repeat this for VGS, you should get the window as
shown on the left and click OK.
7. Now choose the analysis to be done. Select DC analysis. In the DC analysis window select
Design Variable and put Variabel Name VDS. Select Sweep range as start 0 stop 1, Step
type Linear, Step Size 0.05. Repeat the same for the variable VGS.
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8. Your Analog Design Environment window should now look like this:
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The Analog Design Environment window should now look like this:
10. Before closing the Virtuoso Analog Environment window, it is a good idea to save design
settings in a state file, so we can load it up next time. To do this, click on Session Save
State and save state name in the Save As field as state_MOS_IV. Next time you run
Cadence, you can simply load the simulation settings from this file.
Note: when you are loading up the file, dont forget to specify the correct path (in our case,
it is: Var/home/GRPxxx/.state_MOS_IV).
11. The settings so far would generate I-V curve for a single value of VGS variable (0.5V). In
order to sweep VGS, go to Tools Parametric Analysis and set the parameters as shown
below:
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Here select sweep 1 variable VGS, From 0.2 to 1 Step control Linear, Total Steps 5.
12. It is a good idea to save design settings again in a state file, so we can load it up next time.
To do this, click on Session Save State and set State Save Directory to
~/.artist_states
and save state name in the Save As field as state_MOS_IV. Next time you run Cadence,
you can simply load the simulation settings from this file.
Note: when you are loading up the file, dont forget to specify the correct path (in our case,
it is: ~.artist_states).
13. Now in Parametirc analysis window perform Analysis Start-selected. to create netlist
and run parametric simulation. After the simulation finishes, you will get a plot of
overlapped I-V curves for NMOS and PMOS that look like this:
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Finally, we are going to separate the plots into two sub-graphs. Click on the New Subwindow
button as shown in the figure above. Left click on the V4 curves, one by one, and drag over to the
right plot. We can format the axis to display currents on the same scale. Double-click on the Yaxis labels for the NMOS (left plot) and enter the Y-axis setting from 0 to 175 A. Do the same for
PMOS (right plot) to plot both currents on a 0-175A scale. You can also color the lines and add
labels (Graph > Label > Add).
The final plot should look like as shown below.
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Exercise:
[Note: Details about different types of devices available in the gpdk and their rules are available in
the following location :[ /usr/local/cadence/local/gpdk090_v4.6/docs/gpdk090_DRM.pdf
(/usr/local/cadence/local/gpdk090_v4.6/docs/gpdk090_pdk_referenceManual.pdf ]
Repeat the above simulation with Slow and Fast NMOS by selecting the SS and FF model corners.
Explain the difference in I-V curve.
(1) Repeat the above procedure and examine the I-V curve of the High threshold voltage (high
vt) NMOS and PMOS and also the High voltage (2.5 volts) NMOS and PMOS in the
technology library. Explain the difference in I-V curves.
(2) The practical way of measuring the threshold voltage of a MOS transistor is to plot the
(IDS) vs. VGS curve by keeping the transistor in saturation region (VGS=VDS). The slop of
the curve is linear. The interception of the slope of the curve with VGS axis is taken as the
threshold voltage of the device. Find the threshold voltage of the TT, FF, SS MOS model
corners. Also find the threshold voltage of the high threshold voltage (high vt) and high
voltage (2.5 volts) NMOS transistors.
Report :
All the Reports relating to EEE458 have to be submitted in the form of the standard lab report
template for EEE458. In addition to the requirements in the template answer the following
questions:
(1) Observe the BSIM3v3 MOS models of the different MOS transistors available in the
gpdk090 technology library and try to understand the meaning of different parameters. In a
Table summarize the values of the critical parameters for different types of MOS transistors
and make comment about the difference. (see ../gpdk090_v4.6/models/spectre/gpdk090_mos.scs)
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