Beruflich Dokumente
Kultur Dokumente
Nagendra Krishnapura
Department of Electrical Engineering
Indian Institute of Technology, Madras
Chennai, 600036, India
04 Nov 2006
Nagendra Krishnapura
Flash converters:
Area and power consumption increase exponentially with
number of bits N
Impractical beyond 7-8 bits.
Nagendra Krishnapura
Vin
+
-
S/H
2M-1 comparators
A/D1
Vq
2M
2MVq
M+K
A/D1
D/A
Vref
m
Vref
K bits
M bits
Vref
k
concatenation
Nagendra Krishnapura
Resolution N = M + K , output n = 2K m + k
Concatenate the bits from the two A/D converters to form
the final output
Nagendra Krishnapura
Vq
Vref
3VLSB2
input range
of A/D2
transition points
of A/D2
Vref
2VLSB2
VLSB2
VLSB1
2M-1VLSB1
Vref
VLSB1
2VLSB1
2M-1VLSB
VLSB
2VLSB
Vref
Vin
Vin
transition points
of the overall A/D
Quantization error Vq
Vq
Vref
slope=1
size of discontinuity
= D/A step size
VLSB1
Vref
Vin
location of discontinuities
=A/D1 transition points
Nagendra Krishnapura
Vq
Vref
Vref
input range
of A/D2
3Vref/4
Vref/2
Vref/4
VLSB1
2M-1VLSB1
Vref
VLSB1
2VLSB1
2M-1VLSB
Vref
VLSB
2VLSB
Vin
Vin
Nagendra Krishnapura
A/D2 overload
2MVq
Vq
Vref
Vref
ideal transitions
input range
of A/D2
actual transitions
VLSB1
Vref
Vin
A/D2 overload
V[2M-1]
V[2]
V[1]
V[2M-1]
V[2]
V[1]
Vref
Vin
+
-
S/H
2M-1 comparators
A/D1
Vq
2M-1
2MVq
M+K-1
A/D1
D/A
Vref
m
Vref
K-1
Digital output n = 2
K-2
m+k-2
K bits
M bits
Vref
addition with
1 bit overlap
k
2K-2
0 1 0 0 0
subtract
Vq
Vref
Vref
input range
of A/D2
3Vref/4
Vref/2
Vref/4
2VLSB1
VLSB1
Vin
Vin
2M-1VLSB
Vref
VLSB
2VLSB
2M-1VLSB
Vref
VLSB
2VLSB
Nagendra Krishnapura
Vq
Vref
ideal transitions
actual transitions
2VLSB1
input range
of A/D2
Vref
VLSB1
V[2M-1]
V[2]
V[1]
V[2M-1]
Vref
V[2]
V[1]
Vref
Vin
Vin
Nagendra Krishnapura
Nagendra Krishnapura
+
-
2M-1 comparators
0.5LSB offset
A/D1
Vq
2M
2MVq
M+K-1
A/D1
D/A
Vref
m
Vref
Digital output n = 2
K-1
m+k
K bits
M bits
Vref
k
addition with 1 bit overlap
Nagendra Krishnapura
Vq
Vref
Vref
input range
of A/D2
3Vref/4
Vref/2
Vref/4
2VLSB1
VLSB1
Vref
2M-0.5VLSB
2.5VLSB
1.5VLSB
2.5VLSB
1.5VLSB
Vref
2M-0.5VLSB
Vin
Vin
Vq
Vref
Vref
ideal transitions
actual transitions
input range
of A/D2
3Vref/4
Vref/2
2VLSB1
Vref/4
VLSB1
V[2M-1]
V[2]
V[1]
Vref
V[2M-1]
V[2]
V[1]
Vref
Vin
Vin
Nagendra Krishnapura
Nagendra Krishnapura
+
-
2M-2 comparators
0.5LSB offset
A/D1
Vq
2M
2MVq
M+K-1
A/D1
D/A
Vref
m
Vref
Digital output n = 2
K-1
m+k
K bits
M bits
Vref
k
addition with 1 bit overlap
Vq
Vref
input range
of A/D2
Vref
2VLSB1
VLSB1
Vin
Vref
2M-1.5VLSB
2.5VLSB
last
comparator
removed
1.5VLSB
2M-1.5VLSB
2.5VLSB
1.5VLSB
Vref
Vin
last
comparator
removed
Vq
Vref
Vref
ideal transitions
2VLSB1
3VLSB2
input range
of A/D2
transition points
of A/D2
actual transitions
2VLSB2
VLSB2
VLSB1
Vin
Vin
V[2M-2]
V[2]
V[1]
Vref
V[2M-2]
V[2]
V[1]
Nagendra Krishnapura
Nagendra Krishnapura
C1
0V
Vout
-C1Vin
C2
C1
0V
Vout
C1
Vin
0V
+
total charge on
this surface = 0
Vout
+
total charge on
this surface = 0
1
C1
0V
Vout
C2
Vin
C1
0V
C1
Vout
+
total charge on
this surface = -C1Vin
Vout
+
total charge on
this surface = -C1Vin
Nagendra Krishnapura
C/4
b11
b11
2
2M-1C
C/4
0V
b21
Vout
b21
2
1
C/2
Ts
clock phases
2 1 2 1 2 1
sampling instant
Vin
S/H
+
-
2 -2 comparators
0.5LSB offset
2MVq
2M
D/A
A/D1
m available
A/D1
Vref
K bits
Vref
DAC+Amplifier
S R S R S
amplify
amplify
reset
1/2 cycle
delay
reset
clk(1,2)
Vref
clk(1,2)
M bits
clk(1,2)
A/D1
Vq
k available
k
A/D2
S R S R
to adder
Nagendra Krishnapura
1
S/H tracks the input
A/D1 regenerates the digital value m
Amplifier samples Vref of S/H on m/2M C
Opamp output settles to the amplified residue
A/D2 samples the amplified residue
2
A/D2 regenerates the digital value k . m, delayed by 1/2
clock cycle, can be added to this to obtain the final output
S/H, A/D1, Amplifier function as before, but on the next
sample Vi [n + 1]
C1
Voff
+
Voff
Vout
C1(Voff-Vin)
C2
C1
Voff
+
Voff
total charge on
this surface = CVoff
2
Vout
Vin
C1
Voff
+
Voff
total charge on
this surface = CVoff
Vout=Voff-C1/C2Vin
Correction of offset on C2
2
C2
Vin
C1
Voff
+
Voff
Vout
Nagendra Krishnapura
Nonidealities
Nagendra Krishnapura
Rsw3
C2
Vin
Rsw1
C1
0V
Rsw2
Vnsw3
Vout
1
Voff
Rsw3
C2
C2
Vin
Rsw1
Vnsw1
C1
C1
0V
0V
Vout
Rsw2
Voff
Vout
Vnsw2
Voff
Nagendra Krishnapura
1 :
Rsw1 : Its contribution in 2 (kT /C1 ) will be amplified to
kT /C1 (C1 /C2 )2
Rsw2 : Its contribution in 2 (kT /C1 ) will be held
Rsw3 : Results in a noise kT /C1 on C1 and kT /C1 (C1 /C2 )2
at the output
Total output noise: kT /C2 (2C1 /C2 + 1) 2kT /C1 (C1 /C2 )2
Input referred noise: kT /C1 (2 + C2 /C1 ) 2kT /C1
Nagendra Krishnapura
|Vout/Vd| (dB)
Op amp models
finite dc gain model: A0
first order model: A0/(1+s/d)
integrator model: u/s
full model: A0/(1+s/d)(1+s/p2)(1+s/p3) ...
A0
p2 p3
|Vout/Vd| (dB)
C1
Vx
Vout
A0
Adc
p2 p3
2 : Vout = Vx = 0
1 : Vout = C1 /C2 1/1 + (1 + C1 /C2 )/A0 Vin ;
Reduced dc gain in the amplifier
Nagendra Krishnapura
C2
Vin
C1
Vx(t)
u/s
+
Vout(t)
A0
p2 p3
Nagendra Krishnapura
C2
Vin
C1
Vx(t)
u/s
+
Vout(t)
A0
p2 p3
1 : Vout (t)=
2
2
t)
+ Vout (0) exp(u C1C+C
t)
C1 /C2 Vin 1 exp(u C1C+C
2
2
Incomplete settling of amplified residue Vq
Worst case: C1 /C2 Vin = Vref ; Error smaller than Vref /2K +1
at the t = Ts /2; Vout (0) = 0 after reset.
u /(1 + 2M1 ) 2 ln(2)(K + 1)fs (u in rad/s, fs in Hz)
u /(1 + 2M1 ) is the unity loop gain frequency assuming
no parasitics
p2,3,... > u /(1 + 2M1 )
Nagendra Krishnapura
Nagendra Krishnapura
gmvin
Vin
C1
0V
Vout
Model of a
single stage opamp
SC amplifier
C2
C2
C1
C1
Vout
Vout
1 : Capacitive load = C1
2 : Capacitive load = C1 C2 /(C1 + C2 )
Nagendra Krishnapura
C1
Vf
C2
C1
Vt
Vout
Vf
Vt
Vout
2
Vout (s)/Vt (s) = gm /s(C1 C2 /C1 + C2 )
Opamp unity gain frequency u = gm /(C1 C2 /C1 + C2 )
Vf (s)/Vt (s) = gm /sC1
Unity loop gain frequency u,loop = gm /C1
Nagendra Krishnapura
Nagendra Krishnapura
Vin
9 bit A/D
V4
4b A/D
+
residue gen.
6 bit A/D
V3
4b A/D
+
residue gen.
C5 4 bits
/12
D4
DN
V2
4b A/D
+
residue gen.
C4 4 bits
CN
Dout
3 bit A/D
/9
D3
DN
3b A/D
C3 4 bits
CN
DN-1
V1
3 bits
CN
DN-1
/6
D2
DN
/3
DN-1
D1
(14 comparators)
Analog path
Quantizer and
4b A/D
+
residue gen.
Vin
S/H
A/D
D/A
Vq
8Vq
8
residue generator
Vref
Vref
4 bits
Digital path
CN
Digital correction
DN-1
DN
DN = 2K-1CN+DN-1
K: cumulative number of bits after Nth stage
Nagendra Krishnapura
Nagendra Krishnapura