Wireless Pers Commun

DOI 10.1007/s11277-015-2814-3

Co-design Approach for Wide-Band Asymmetric Cross

Shaped Slotted Patch Antenna with LNA
Sandeep Kumar1,2 Binod Kumar Kanaujia2
Santanu Dwari1 Ganga Prasad Pandey3
Dinesh Kumar Singh1

 Springer Science+Business Media New York 2015

Abstract The proposed work presents a co-design approach for a new asymmetric
rectangular cross shaped slotted patch antenna with low noise amplifier that occupies
17.225.8 GHz wide-band for SDR applications. This co-design approach minimizes the
chip area and noise and also improves integration system over the bandwidth of 8.6 GHz.
Three different architectures have been designed in this work. Firstly, a two stage CMOS
CGCS LNA is designed using a technique of seriesparallel resonant network as an input
matching network and as inter-stage matching network between CG and CS LNA. In
second architecture stage, a rectangular shaped microstrip antenna is designed and a slot of
asymmetric cross shape is cut on the patch antenna. In third architecture the slotted antenna
is integrated with low noise amplifier in order to form a co-design approach in which
seriesparallel resonant network is used as a band pass filter between slotted patch antenna
and LNA. A two-stage CMOS LNA design is simulated and layout is made using foundry
design kit for the TSMC 65 nm CMOS process in ADS.v.12. A simulation result of LNA
achieves S11 of -21.4 dB with gain ranging from 7.4 to 21.3 dB over the wide-band of
19.128.8 GHz. The slotted antenna achieves S11 of -19 dB at 26 GHz and covers
& Binod Kumar Kanaujia
bkkanaujia@yahoo.co.in; bkkanaujia@ieee.org
Sandeep Kumar
fedrer.engg@gmail.com
Santanu Dwari
santanu_dwari@rediffmail.com
Ganga Prasad Pandey
ganga.mait@gmail.com
Dinesh Kumar Singh
dinesh12dk@gmail.com
1

Department of Electronics Engineering, Indian School of Mines, Dhanbad 826004, India

Department of Electronics and Communication Engineering, Ambedkar Institute of Advanced

Communication Technologies and Research, Delhi 110031, India

Department of Electronics and Communication Engineering, MAIT, Delhi 110085, India

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S. Kumar et al.

frequency range of 20.127.8 GHz with good radiation and receiving patterns. This codesign approach is analysed considering the 50 X impedance matching throughout the
design and simulated on the platform of ADS.v.12. The best achievement of proposed codesign approach is reduced noise figure which is most suitable for SDR applications.
Keywords Software defined radio (SDR)  Low noise amplifier (LNA)  Complementary
metal oxide semiconductor (CMOS)  Microstrip antenna

1 Introduction
In Last few years, a fastest growth for the wide range of wireless networks is continuously
finding a new solution, which often comes either with new frequency bands or with new
modulation schemes. Recently, the hardware and software system design have been done
individually for every standard which overcomes the drawback of redesigning of hardware
modules for every new standard. This suggests the integration of many communication
devices into a single chip [1]. Moreover, there have been researchers for the already
available spectrum for their efficient use e.g., cognitive radio. It is desirable to have a
universal programmable hardware which gives the flexibility in designing the system by
using software-defined radio (SDR) technique [2]. The first proposed idea of an SDR,
developed by Mitola [3], is to perform all RF and baseband signal processing designs in
both analog and digital domains. It brings the flexibility, cost efficiency and enhanced
power in order to carry forward communication, resulting in benefits to the service providers [4]. The extensive progress of CMOS technology has enabled its application in SDR
wireless networks. At present, the CMOS technology is one of the most attractive choices
in implementing receiver due to its low cost and high level of integration [5]. In spite of
having several advantages, the design of CMOS receiver in SDR applications exhibit
various challenges and difficulties to which the designers should take care off. Although by
using the integrated patch antenna with LNA, most of the performances parameters have
been improved but SDR applications are not yet considered.
The most difficult task for the wide band co-design of low noise amplifier (LNA) with
microstrip antenna are: (1) To take care of the performance parameters like impedance
matching and noise over a wider range (2) To take care of size an effect of miniaturization
and (3) Low power consumption for long lasting battery. Several authors have devoted
their research about the many LNAs and different shaped slotted antennas which offered
wider bandwidth [6, 7]. But the wide band co-design approach of slotted antenna with
LNA concept is still needs exploration.
In [8], the return loss of filter degrades the noise figure (NF) when LC ladder filter has
been placed at the input of a common source (CS) amplifier. Another inter-stage LC
network is added to CGCS stage that increase the power gain, but the NF is 6 dB at
around 10 GHz [9]. In [10], coupled resonators have been used to design a wideband interstage matching network for a V-band cascaded CS amplifier. A wideband LNA operating
in 2332 GHz has been proposed in which coupled resonators are used as a load for the
common-emitter stage [11]. In [12], design of wideband LNAs using parallel-series resonant matching network between CG and CS stages at 310 and 1429 GHz achieved
9.612.7 and 8.251.65 dB gain but sacrificed NF. In [13], analysis of LNA-antenna co-

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Co-design Approach for Wide-Band Asymmetric Cross Shaped

design for UWB system achieved 13 dB gains on the 3.255 GHz bandwidth but noise
performances has not been discussed.
In this paper, a new approach of co-design of wide band asymmetric cross shaped
microstrip antenna with LNA is proposed. Three architectures operating in the frequency
ranges of 20.1327.8, 19.128.8 and 17.225.8 GHz respectively are executed to verify
this co-design approach. The designing of asymmetric cross shaped antenna is discussed in
section II. Section III, presents the analysis of Wide band CMOS CGCS topology using
seriesparallel resonant network. A co-design approach over wide band range is addressed
in **Sect. 4. Finally, simulated results are discussed in Sect. 5 and are followed by
conclusion in Sect. 6.

2 Design and Implementation of Asymmetric Cross Shaped Microstrip

Antenna
The microstrip antenna is a small electrically thin patch having numerous advantages i.e.
light weight, inexpensive, and easily integrable with active devices for improving system
reliability. The schematic of the proposed antenna is shown in Fig. 1. The feedline of
dimension W1 9 L1 is attached with a slot loaded rectangular patch of dimension L 9 W in
the same plane. An asymmetric cross slot is cut in the rectangular patch. All the detailed
dimensions are listed in Table 1. The proposed structure is designed on RT Duriod-5870
substrate. The height, dielectric constant and loss tangent of the substrate are 0.762 mm,

Fig. 1 Geometry of proposed antenna with asymmetric cross shaped slot

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S. Kumar et al.
Table 1 Dimensions of patch
antenna with cross shaped cutslot

Dimensions

Values (mm)

9.2

4.6

W1

2.2

W2

0.9

W3

0.7

W4

0.7

W5

0.7

Ws

0.7

9.4

3.1

L1

1.6

L2

0.4

L3

1.2

L4

0.5

L5

1.1

Ls

1.1

d1

1.9

d2

1.9

d3

0.4

d4

2.2

d5

1.8

Fig. 2 3D view of asymmetric cross shaped slotted patch antenna

2.33, and 0.0012 respectively. The width of the smaller rectangular patch section (W1) is
adjusted to provide a 50 X microstrip line. By cutting a cross slot on the patch, additional
resonances are created and much wider impedance bandwidth is produced. The 3D

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Co-design Approach for Wide-Band Asymmetric Cross Shaped

isometric view of asymmetric shape slotted antenna is shown in Fig. 2. The simulated
return loss and radiation at 26 GHz of the antenna is shown in Figs. 3 and 4 respectively.
The return loss plot clearly shows two resonances eparated appropriately to create a
wideband response. The bandwidth of the antenna ranges from 20.1 to 27.8 GHz providing
a fractional bandwidth of 32.15 %. Figure 4 illustrates the simulated radiation pattern at
resonant frequency of 26 GHz when phi rotates 90. This plot shows electric field components of co and cross polarization.

3 Wide-Band CMOS LNA Analysis

In order to achieve the best impedance matching, gain and NF over a wide band range,
many topologies are available [14]. Out of these topologies, CS and common gate (CG) are
the most popular choices for LNA design. The CS with the source inductor degeneration
technique achieves a good input impedance matching with ideal noiseless components
providing a minimal NF and a higher gain whereas CG offers wideband operating performance with good linearity and inputoutput isolation property [15]. But at higher frequencies, cascaded CGCS topology suffers with noise. Therefore, a seriesparallel
resonant network is used for CGCS amplifier as an input and inter-stage matching network which improves the noise performance and other parameters. The details of the
proposed structure of two stage CGCS LNA using series to parallel resonant network are
addressed below.

3.1 SeriesParallel Resonant Network

In [12], a parallel to series resonant network is used as a band pass filter is shown in Fig. 5.
This resonant network achieved a band pass response and dual band response by selecting
proper values of inductors and capacitors. For the parallel and series resonance networks,
the impedances Zp and Zs are shown in Eq. (1) and (2) respectively [12].

Fig. 3 Variation of return loss with operating frequency

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S. Kumar et al.

Fig. 4 Simulated radiation pattern of the proposed antenna at 26 GHz

Fig. 5 Schematic of parallel-series resonant network


Zp

1
1
jwC1
R1
jwL1

Zs R2 jwL2  j

1

1
wC2

1
2

Here, the concept implies that different values of source and load impedances
R1 = 250 X and R2 = 40 X in parallel to series resonant network offered dual band
response with a dip in the middle. A wide band response is achieved when parallel-series
network is used as inter-stage matching network between CG and CS LNA. The same
concept is used in this work. However parallel-series resonant network is inverted as
seriesparallel resonance network which is used as matching network between CG and CS
LNA for improving performance parameters like impedance matching, NF and gain over
wider range of operating frequencies. A proposed two stage CMOS CGCS LNA using
inverted parallel-series resonant network is discussed in subsection B.

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Co-design Approach for Wide-Band Asymmetric Cross Shaped

3.2 CGCS LNA Using SeriesParallel Resonant Network

The proposed schematic of two stages CGCS LNA using seriesparallel resonant network
is shown in Fig. 6. This is implemented using commercial TSMC design kit of 65 nm RF
CMOS technology in Agilent Advanced Design System (ADS). The input matching and
inter-stage matching networks of CGCS LNA are composed of inductors and capacitors
as L1, L2, L3, L4, C1, C2, C4, C5 having values of 0.48, 0.27, 0.83, 0.6 nH, 14.75, 30, 0.06
and 0.0835 pF respectively.
Selection of on-chip inductors is the key for the designing of a matching network, as it
determines the performance quality of matching network. The input and inter-stage
matching network is accomplished with the combination of a seriesparallel LC impedance
transformation network. In order to maintain the 50 X impedance matching, firstly a single
stage of CG LNA using series to parallel resonant network as an input is designed that
provides good reverse isolation parameter over a wide band range of operation. It is well
known that the NF and high gain are the essential requirements of the LNA design. For
improving these parameters further, the next stage i.e. CS with source degeneration via
seriesparallel resonant network is combined. For the two-stage of CGCS LNA, the width
of M1 (WM1) is calculated to be 492 lm using Eq. (3) as given in [14]. The second stage of
CS device is designed to meet the desired performance criterion while width of M2 (WM2)
is calculated as 532 lm using Eq. (4) as given in [14].

WM1

3 cgs
2 Lmin cox

g2m Lmin
2Kn ID

WM2

where, L is channel length, Kn is transconductance parameters, Cox is gate oxide capacitance, ID is the drain current, gm is transconductance of device and Cgs is the gate to source
capacitance. In this design, a more difficult task is to maintain an output impedance of

Fig. 6 Proposed schematic of CMOS CGCS LNA using series to parallel network

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250 X of CG stage and input impedance of 40 X of CS stage for obtaining wide band
operation. The designed circuit of CGCS LNA is simulated and reflection coefficient of
-21.4 and -21 dB at operating frequency of 20.5 and 26.2 GHz is obtained respectively.
This return loss shows a frequency band from 19.1 to 28.8 GHz with a fractional bandwidth of 40.5 % as shown in Fig. 7. It also shows transmission gain S21 of the circuit. The
CMOS LNA provides a gain in the range of 7.421.3 dB for the entire band of operation
with relatively constant NF of around 2.8 dB as shown in Figs. 7 and 8 respectively. The
forward gain (S21) shows a high gain over the bandwidth of 9.7 GHz ranging from 19.1 to
28.8 GHz as shown in Fig. 7. Using seriesparallel networks a wideband impedance
matching is obtained as shown in Fig. 9. It clearly indicates that the imaginary part of input
impedance remains near zero value while real part is matched around 50 X within the band
of operation. The total power consumption for two stage CGCS LNA is 11.2 mW from
1.6-V power supply. Figure 10 shows layout of CGCS LNA with final area of 0.74 mm2.
Table 2. Show the comparison of previous works with present one on various parameters.

4 Strategy of Combined Structure

In this section, the technique of proposed combined structure of slotted patch antenna with
LNA is addressed. The schematic of this co-design is shown in Fig. 11. From the schematic, it can be observed that slotted patch antenna is integrated with the CMOS LNA
which forms a co-design structure. In this structure, the input of CGCS LNA i.e. series
parallel resonant network has been used as an inter-stage matching network between the
asymmetric slotted patch antenna and the CGCS LNA. As discussed above, the series
parallel resonant network which acts as a band pass filter is connected between slotted
patch antenna and LNA to form a complete receiver system. The RF signal is applied to
patch antenna with the help of two ports and the output from the antenna is connected to
the microstrip line with help of another port while applying the approach of co-design, four
major goals need to be fulfilled: (1) To sustain 50 X impedance matching throughout the
design for achieving performance parameters (2) To achieve higher gain and lower NF that

Fig. 7 Variation of return loss and forward gain of CGCS LNA

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Co-design Approach for Wide-Band Asymmetric Cross Shaped

Fig. 8 Variation of NF with frequency

Fig. 9 Variation of Input impedance of CGCS LNA with frequency

is essential for amplification (3) To minimize the chip area and (4) To achieve less power
dissipation [1618]. To predict the received signal, one port of RF signal with 50 X is
attached on the slotted patch and the received signal is passed via series to parallel resonant
network to the LNA for the amplification. Keeping above goals in mind, a strategy is
adopted to combine the structure of slotted patch antenna and LNA that provides good
results as per design specifications and that would be discussed in next section.

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S. Kumar et al.

Fig. 10 Layout snapshot of CMOS CGCS LNA

Table 2 Comparisons of LNAs with other reported papers
Design parameters

[19]

[20]

[12]

[12]

Present work

Technology

0.18 lm

0.18 lm

0.18 lm

0.18 lm

.065 lm

Peak Gain (dB)

12.4

12.9

12.7

8.95

21.3

NF (dB)

4.46.5

3.74.7

2.53.9

4.35.8

2.92.7

B.W (GHz)

0.410

1.511.7

3.110.3

1429 GHz

19.228.8

Power (mW)

12

10.34

13.4

13.9

11.2

Area (mm2)

0.42

0.536

0.68

0.54

0.74

Fig. 11 Schematic of co-design of slotted patch antenna with LNA

5 Results Discussion of Co-design

From previously discussed results of slotted antenna and LNA in section II and III, it can
be seen that the proposed asymmetric cross shaped antenna works on the wide band range
of 20.127.8 GHz with fractional bandwidth of 32.15 % whereas LNA achieves a wide

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Co-design Approach for Wide-Band Asymmetric Cross Shaped

Fig. 12 Return loss and forward gain behavior for co-design strategy

Fig. 13 NF variation with frequency for co-design system

range of 19.128.8 GHz with fractional bandwidth of 40.15 %. The obtained bandwidths
of both the devices are approximately same and give the wide band when co-design
approach is applied. Using above discussed strategy the two structures are combined,
analyzed and simulated on ADS platform. The simulated result of co-design structure
obtains the S11 of -18 dB at three different frequencies 19.8, 21 and 23.4 GHz with a wide
band ranging from 17.2 to 25.8 GHz with fractional bandwidth of 40 % as shown in
Fig. 12. The band of operation of the complete design shifts downward while the impedance matching of antenna and LNA remains within the acceptable limit. The best
achievement of this co-design is to improve the performance parameters like gain and NF
that is required for receiver system. The new band of operation is 17.225.8 GHz with gain
ranging from 3.413 dB. The NF varies between 2.91.9 dB which is shown in Fig. 13.

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Fig. 14 Impedance variation with frequency for co-design system

Moreover, an impedance matching (real and imaginary) of co-design structure is also

obtained and shown in Fig. 14. The calculated area of the slotted patch antenna is
9.2 9 9.4 mm2 whereas the area of two stage CGCS LNA is 0.92 9 0.81 mm2. The total
area of co-design layout is 9.2 9 10.2 mm2.

6 Conclusions
The proposed method of co-design of asymmetric cross shaped patch antenna with LNA is
discussed in the paper with achieving a wider bandwidth of 17.225.8 GHz. It is also found
that the proposed antenna design exhibits an extremely wideband impedance by new type
of slot cut in the cross shaped and also LNA design revealed an wideband by using series to
parallel resonant network as a input and inter-stage matching network. The state of the art
of this co-design work achieves S11 of -18 dB by proper impedance matching with wider
gain variation from 3.1 to 13 dB and NF from 2.9 to 1.9 dB. Moreover, the proposed
method of co-design system for SDR applications, increase the level of system integration,
reducing chip area size thus, escalating the overall system performance.

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Sandeep Kumar received his B.E. degree in Electronics and Communication Engineering in 2008 and M.Tech. degree in VLSI Design
in 2012 from Gautam budh University, Uttar Pradesh, India. Currently,
he is doing Ph.D. Degree in Electronics Engineering from Indian
School of Mines, Dhanbad, India. His current research interests are
focus on transceiver systems, Millimeter wave applications and
microstrip antennas.

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Binod Kumar Kanaujia (M 04) joined Ambedkar Institute of
Technology (AIT), Govt. of N.C.T. Delhi, Geeta colony Delhi -31 as
Assistant Professor in Jan. 2008 in the Department of Electronics and
Communication Engineering after getting selected by Union Public
Service Commission, New Delhi. Before joining AIT, Dr. Kanaujia
has served in the M.J.P Rohilkhand University in the capacity of
Reader in Electronics and Communication Engineering Department
from 26/02/2005 to 30/01/2008 and lecturer in ECE Department from
25/06/1996 to 25/02/2005. While working with MJP Rohilkhand
University Dr. Kanaujia has been a active Member of Academic
council and Executive council of the university and played a vital role
in the academic reforms. He has also served as Head of Department of
E&C Department of the university for the period from 25th July 2006
to 30th Jan 2008. Prior to his career in the academics, Dr. Kanaujia has
been working as Executive Engineer in the R&D division of M/s
UPTRON India Ltd. Dr. Kanaujia, presently working as Associate
Professor in ECE Department of AIT has served various key portfolios i.e. he has been Head of Department
of E&C Department of the Ambedkar Institute of Technology from 21 February 2008 to 05 Aug 2010, and
17 Aug. 2012 to till now, As Library In-charge of Central Library of AIT from March 2008 to 05 Aug 2010
and responsible for upgrading the Library with the introduction of Fully Automatic Book issue and
receiving, on-line journal, on-line retrieval of catalogue of the Library, Establishment of E-Library. Apart
from it, he has been holding the Charge of Head of office of Ambedkar Institute of Technology since 09
Aug. 20083rd May 2013 and responsible for day to day administration of the institute. Dr. Kanaujia has
done his B.Sc. from Agra University Agra U.P. in 1989 and B.Tech. in Electronics Engineering from KNIT
Sultanpur U.P. in 1994. He did his M.Tech. and Ph.D. from Electronics Engineering Department of IIT
Banaras Hindu University,Varanasi in 1998 and 2004 respectively. He has been awarded Junior Research
fellow by UGC Delhi in 20012002 for his outstanding work in his field. His keen research interest in design
and Modeling of Microstrip Antenna, Dielectric Resonator Antenna, Left handed Metamaterial Microstrip
Antenna, Shorted Microstrip Antenna Wireless Communication, Wireless Communication and Microwave
Engineering etc. Till date he has been credited to publish more than 80 research papers in peer-reviewed
journals and International/national conferences. Dr. Kanaujia is a Member of IEEE and Life members of the
Institution of Engineers (India), Indian Society for Technical Education and The Institute of Electronics and
Telecommunication Engineers of India.
Santanu Dwari was born in Howrah, West Bengal, India. He received
his B.Tech. and M.Tech. degree in Radio Physics and Electronics from
University of Calcutta, Kolkata, West Bengal, India in the year of 2000
and 2002 respectively and PhD degree from Indian Institute of Technology, Kharagpur, West Bengal, India in the year of 2009. He joined
Indian School of Mines, Dhanbad, Jharkhand, India in 2008 where he
is currently an Assistant Professor in the Department of Electronics
Engineering. He has published seven research papers in referred
International Journals. He is carrying out two sponsored research
project as Principal Investigator. His research interest includes
Antennas, RF planar circuits, Computational Electromagnetic.

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Co-design Approach for Wide-Band Asymmetric Cross Shaped

Ganga Prasad Pandey received B. Tech. in Electronics Engineering
from K.N.I.T. Sultanpur, India in 2000. He completed M.E. in Computer Technology and Application from Delhi College of Engineering
Delhi (India) in 2004. Presently, he is Assistant Professor in Electronics and Communication Engineering department of Maharaja
Agrasen Institute of Technology, Delhi, India. He is currently working
towards his Ph.D. degree from Uttrakhand Technical University. His
research interests include active, Reconfigurable, frequency agile
microstrip antennas and microwave/millimeter wave integrated circuits
and devices.

Dinesh Kumar Singh received B.E. in Electronics and Communication Engineering from Kumaon University, Nainital, in 2003. He is
done M. Tech. in Digital Communication from RGPV University,
Bhopal, India. Currently, he is pursuing PhD from ISM, Dhanbad. His
area of interest is microwave Engineering.

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