Beruflich Dokumente
Kultur Dokumente
com
What happens when all the gates in a two level AND-OR gate network is replaced by NOR
Implement Y=A+(B+C)1+(AB)1
If A and B are Boolean variable and if A=1 and (A+B)1=0 find B
Express the switching function fAB =A in terms of minterms
Apply demorgans theorems to simplify (A+BC1)1
www.vidyarthiplus.com
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
16.
17.
18.
19.
20.
21.
22.
23.
24.
25.
26.
27.
28.
29.
30.
31.
32.
www.vidyarthiplus.com
Express x+yz as the sum of minterms
What is prime implicannt
What are min-terms and max-terms
Why binary number system is used in digital systems?
Define the laws of Boolean algebra
For a switching is a function of n variables how many distinct minterms and max are possible
State two adsorption properties of Boolean algebra
Find the octal equivalent of the decimal number 64
Find the hexadecimal equivalent of the octal number 153.4
Define canonical form. Express F=BC1+AC in a cannonical SOP form
Determine the decimal equivalent of binary .1101
Find the octal equivalent of hexadecimal number AB.CD
What is the advantage of biquinary code?
Find the hexadecimal equivalent of decimal number 256
What is mean by weighted and non-weighted coding
Convert A3BH and 2F3H into binary and octal respectively
Find the decimal equivalent of 1239
Find the complement of x+yz
State and prove consensus theorem
Implement AND and OR gate using NAND gates
Find the binary representation of decimal 125
Complement the express X(Y1+Z1)
Convert y=A+BC1+AB+BCA1
What is meant by essential prime implicant
Obtain the complent of f=wx1+xy1+wxy using demorgan theorm
Show that A+A1B=A+B using the theorms of Boolean algebra
What is the advantage of grey codes over theb inary number sequence
UNIT-2
COMBINATION LOGIC
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
16.
17.
18.
19.
www.vidyarthiplus.com
20.
21.
22.
23.
24.
25.
26.
27.
28.
29.
30.
31.
32.
33.
34.
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
UNIT-3
DESIGN WITH MSI DEVICES
1.
2.
3.
4.
5.
6.
7.
8.
What is a decoder
What do you mean by encoder
What is a priority encoder
What is a multiplexer
Give application of MUX
How can a decoder be converted into a demultiplexer
Implement the logic function f=AB+A1B1 using a suitable multiplexer
Explain how parity can be used for error detection
www.vidyarthiplus.com
9.
10.
11.
12.
13.
14.
15.
16.
17.
18.
19.
20.
21.
22.
23.
24.
25.
26.
27.
28.
29.
30.
31.
www.vidyarthiplus.com
What is the difference between decoder and demultiplexers
What is a sequential circuit
How is the design of combinational and sequential logic circuits possible with PLA
Is the PAL same as the PLA? Justify or distinguish between them
Define priority encoder
What is meant by static and dynamic memories
What is FPLA
Name any two random access memories
Differentiate between SRAM and DRAM
What is PLA
Give any two application of PLAs
What is a decoder and obtain the realtion between the number of inputs n and outputs m of a decoder
List basic types of programmable logic devices
Define address and word
What are the types of ROM
What is programmable logic array?how it differs from ROM
What is field programmable logic array
Mention some major applications of multiplexers
Mention the uses of decoders
Write data flow description of a 2 to 1 MUX using condition operator
Implement the logic function f=(0,2,3,6) using a decoder
How can a multiplexer be used to convert 8 bit paralled data into serial form
What is the maximum range of a memory that can be accessed using 10 address lines?
16 marks
1. A combination circuit is defined by the function F1=m(3,5,7) F2 =m(4,5,7) implement the circuit with a PLA
having 3 inputs, 3 product terms and two outpus
2. Implement the following Boolean function using 8:1 MUX F(P,Q,R,S)= m (0,1,3,4,8,9,15)
3. Implement the following Boolean function using 8:1 multiplexer F(A,B,C,D)=A1BD1+ACD+B1CD+A1C1D
4. Realize F(w,x,y,z)= (1,4,6,7,8,9,10,11,15) using 4-to-1 MUX
5. Tabulate the PAL programming table for the four Boolean function listed below. A(x,y,z)= (1,2,4,6) B(x,y,z)=
(0,1,6,7) c(x,y,z)= (2,6) D(x,y,z)= (1,2,3,5,7)
6. Implement the following Boolean function using a 8 to 1 multiplexer and 4 to 1 multiplexer F(A,B,C)= (0,1,5,7)
7. Implement the following Boolean function using 8:;1 multiplexer F(A,B,C,D)=A1BD1+ACD+B1CD+A1C1D
8. A combinational circuit is defined by the function F1(A,B,C)= (3,5,6,7) F2(A,B,C)= (0,2,4,7) implement the
circuit with a PLA
9. A combination circuit is described by the functions F1=m(3,4,5,7,10,14,15), F2=m(1,5,7,11,15) implement the
circuit with a PLA having 4 inputs 6 product terms and two outputs
10. Write the structural VHDL description for 2 to 4 decoder and explain it in detail
11. Design and explain the working of a 1 to 8 demultiplexer
12. Draw a 4:1 MUX and implement the following function F=(0,1,2,4,6,9,12,14) write a HDL program for 2 to 1
MUX
13. Write the structural VHDL description for 4 to 1 multiplexer also draw the internal diagram of the multiplexer
14. A combinational circuit is defined by the functions F1=m(3,5,7) F2=(4,5,7) implement the circuit with a PLA
having 3 inputs 3 product terms and two outputs
15. Implement the Boolean function using 4 to 1 MUX F(w,x,y,z)= (1,2,3,6,7,8,11,12,14)
16. A combitational circuit is defined by the functions F1=m(1,3,5)
F2=m(5,6,7) implement the circuit with a
PLA having 3 inputs and 3 product terms and two output
www.vidyarthiplus.com
www.vidyarthiplus.com
UNIT-4
SYNCHRONOUS SEQUENTIAL LOGIC
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
16.
17.
18.
19.
20.
21.
22.
23.
24.
25.
26.
27.
28.
29.
30.
31.
32.
33.
16 marks
1. Using D flip flops design a synchrounous counter which counts in the sequence binary 0 to 7 then 0
2. Using JK flip flop design a synchronous counter which counts in the sequence 0 to 7 then 0
3. Design a binary counter using T flip flops to count pulses in the following sequence 0 t0 7 then 0 , next order
0,4,7,2,3,0
4. Explain the working of master slave flip flop
5. Write short notes on the following slip flops i)JK ii)D iii) T flip flop
6. Explain the functional operation of a binary ripple counter with its logical diagram
7. Draw a 4 bit serial in serial out shift register and draw its waveforms
8. Draw a 4 bit serial in parallel out and explain its operation
9. What are the general capabilities of universal shift register? And write the HDL code for the same
10. Explain the operation of BCD counter
www.vidyarthiplus.com
11.
12.
13.
14.
15.
16.
17.
www.vidyarthiplus.com
Design an asynchronous BCD down counter using JK flip flop and verify its operation
Design a synchronous mod-8 down counter and implement it
Design and explain the working of a up down counter
Explain the operation of D type edge triggered flop flop and how can a d flip flop converted into a T flip flop
Using JK flip flop design a synchronous counter which counts in the sequence 2,6,1,7,5,4 and repeat
Design a mod 5 asynchrounous counter draw the wave form
Using RS flip flop design a paralled counter which counts in the sequence 0,3,5,6,1,2,0 and repeat
UNIT-5
ASYNCHRONOUS SEQUENTIAL CIRCUITS
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
16.
17.
18.
19.
20.
21.
22.
23.
24.
16 marks
1.
2.
3.
4.
6.
7.
8.
9.
10.
11.
www.vidyarthiplus.com
Y2=x2+x1y1y2+x1y1
Z=x2+y1
Give a hazard free realization for the following Boolean function F(A,B,C,D)= m(1,3,6,7,13,15) and summarize
the design procedure for asynchronous sequential circuit
An asynchronous sequential circuit is described by the following excitation and output function
Y=X1X2+(X1+X2)Y
i)draw the logic diagram ii) derive the transition table and output map iii)
describe the behavior of the circuit
An asynchronous network has twoinputs and one output. The input sequence X1X2=00,01,11 causes the output
to become 1. The next input change then causes the output to return to 0. No other input sequence will produce
a
1 output. Construct the state diagram using primitive flow table.
Design a circuit with inputs A dn B to give an output Z equal to 1 when AB=11 but only if A become 1 before B,
by drawing total state diagram, primitive flow table and output map in which transient stae is included
Design a circuit with primary input A and B to give an output Z equal to 1 when a become 1 if B is already 1.
Once Z=1 it will remain so until a goes to
Draw waveform diagrams, total state diagram, primitive flow table for desigining the circuit
An asynchronous circuit described by the following excitation and output function Y=X1X2+(X1+X2)Y Z=Y
Draw the logic diagram of the circuit. Derive the transition table and output map. Describe the behavior of the
circuit
12. Design a asynchronous sequential circuit with 2 inputs X and Y and with one output Z whenever Y is 1 inmput X
is transferred to Z. when Y is 0 the output does not change for an change in X. use SR latch for implemention of
the circuit.
13. What is a merger graph. How it is used to reduced state in the incompletely specified state.
14. What are the problems in asynchronous circuits and what are essential hazards and static hazards how it can be
eliminated.
15. Design T flip flop from logic gates
16. Give the hazard free realization for the following function i)NAND ii) NOR gates f(a,b,c,d)=m (1,5,7,14,15)
17. Design a sequence detector circuit with a single input line and a single output line. Whenever the input consists
of the sequence 101, the output should be 1 for example if the input is 001100101then the ouput is
000000101.. in other words, over lapping sequence are allowed. Use any type of flip flop
18. Give the hazard free realization for the following function f(a,b,c,d)= m(1,3,6,7,13,15)
19. Summarize the design procedure for asynchronous sequential circuit
20. An asynchronous circuit described by the following excitation and output function X=(Y1.Z11W2)X+(Y11Z1W21)
S=X1 DRAWS the logic diagram of the circuit. Derive the transition table and output map. Descirb the behavirour
of the circuit
21. Explain essential, static and dynamic hazards in digital circuit. Give the hazard free realization for the following
functions F(I,J,K,L)= m(1,3,4,5,6,7,9,11,15)
www.vidyarthiplus.com