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A Zero-Voltage-Transition Bidirectional
DC/DC Converter
Serkan Dusmez, Student Member, IEEE, Alireza Khaligh, Senior Member, IEEE, and
Amin Hasanzadeh, Member, IEEE

AbstractA three-level (TL) bidirectional dc/dc converter is a suitable choice for power electronic systems with
a high-voltage dc link, as the voltage stress on the switches
is half and inductor current ripple frequency is twice the
converters switching frequency. This study proposes a
zero-voltage transition (ZVT) TL dc/dc converter to enable operation with higher switching frequency in order
to achieve higher power density and enhance efciency.
Two identical ZVT cells, each one composed of two resonant inductors, a capacitor, and an auxiliary switch, are
integrated with the conventional TL topology to enable
soft switching in all four switches in both buck and boost
operation modes. In addition, a variable dead-time control is proposed to increase the effective duty ratio at
heavy loads. The proposed soft-switching feature has been
demonstrated under different loading conditions. A 650-W
prototype is designed and fabricated, which exhibits 95.5%
at full load.
Index TermsBidirectional three-level (TL) converter,
nonisolated dc/dc converter, power electronics, zerovoltage transition (ZVT) cell.

I. I NTRODUCTION

N bidirectional nonisolated buck/boost dc/dc converter applications, a two-quadrant nonisolated buck/boost converter
has been preferred in many studies due to its simple two-switch
structure, low cost, and high efficiency [1][6]. However, in
high-voltage (400600 V) and medium- to high-power applications such as the dc/dc bidirectional converter in electric
vehicles, the two-switch structure exhibits several shortcomings: 1) low efficiency at light load due to high-power losses
Manuscript received June 22, 2014; revised September 22, 2014;
accepted October 12, 2014. Date of publication February 19, 2015; date
of current version April 8, 2015. This work was supported in part by
the National Science Foundation Division of Electrical, Communications
and Cyber Systems under Grant 1307228 and in part by Genovation
Cars, Inc.
S. Dusmez was with the Power Electronics, Energy Harvesting and
Renewable Energies Laboratory, Electrical and Computer Engineering
Department, University of Maryland, College Park, MD 20742 USA. He
is now with the Electrical and Computer Engineering Department, The
University of Texas at Dallas, Richardson, TX 75080 USA.
A. Khaligh is the Director of the Power Electronics Energy Harvesting
and Renewable Energies Laboratory, Institute for System Research,
and Electrical and Computer Engineering Department, University of
Maryland, College Park, MD 20742 USA (e-mail: khaligh@ece.
umd.edu).
A. Hasanzadeh was with the Power Electronics, Energy Harvesting
and Renewable Energies Laboratory, Electrical and Computer Engineering Department, University of Maryland, College Park, MD 20742 USA.
Color versions of one or more of the figures in this paper are available
online at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TIE.2015.2404825

associated with the parasitic capacitances of the switches;

2) utilization of insulated-gate bipolar transistors (IGBTs)
instead of metaloxidesemiconductor field-effect transistors
(MOSFETs) in high-voltage applications, whereas the switching frequency of the converter is limited by the IGBTs maximum switching frequency under hard switching. As a result,
the passive components such as the inductors and capacitors
render a large volume. To increase the input current ripple frequency, interleaved structures are studied [7][9]. Interleaving
reduces the size of the passive components but still requires
high-voltage rating switches. In order to equally distribute the
voltage stress among the switches and to use MOSFETs at
high voltages while still increasing the inductor current ripple
frequency to twice the switching frequency, a three-level (TL)
output voltage buck/boost dc/dc converter has been proposed
and suggested for use in high-voltage applications [10].
To increase power density through higher switching frequencies without sacrificing converter efficiency, soft-switching
techniques are employed [11][13]. A common way to achieve
soft switching is to use interleaving circuits where the stored
energy in the interleaving inductor is used to discharge the
parasitic capacitances of the switches [14][17]. Similarly, an
auxiliary inductor can be coupled to the main inductor to reduce
the cost of the circuit [18][22].
Another method to effectively achieve soft switching is
through employing an auxiliary switch to store the switching
energy in the auxiliary capacitor, which is then used to softswitch the main switch either during turn-on or turn-off instants. Soft-switching cells, consisting of an auxiliary switch,
a resonant inductor, and a capacitor, are common [23][26]. In
[23], the soft-switching cell is used to turn off the switch under
zero current and turn on the auxiliary switch under near-zero
current. Another ZCS was introduced in [24] for the boost converter, which is then generalized for other converter types such
as buck, buck/boost, SEPIC, and Cuk. In [25], unified analysis
for these soft-switching cells was explored. In [26], a similar
soft-switching cell used in this paper has been proposed for
bidirectional nonisolated buck/boost dc/dc converter. However,
no soft-switched nonisolated TL converter has been explored in
the literature.
Reducing the switching losses is critical to achieve higher
efficiency. In this regard, this paper proposes a zero-voltage
transition (ZVT) TL bidirectional dc/dc converter for a wide
load range, as illustrated in Fig. 1. Two identical soft-switching
cells are deployed for each pair of switches, ensuring that all
four switches are turned on under zero voltage in both boost

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See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.

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TABLE I
S UMMARY OF THE ZVT O PERATION

Fig. 1. Proposed bidirectional TL dc/dc converter with an auxiliary

ZVT cell.

and buck modes. Thus, the proposed ZVT TL converter can

be operated at higher switching frequencies, the input current
ripple frequency can be doubled, and the size of the inductor
can be significantly reduced.
The common issue with the soft-switching converters is
the limited soft-switching operation range due to the output
current dependence of the soft-switching operation. When the
ZVT cell designed for a light-load condition operates under
heavy load, the effective on-time of the switches becomes less
than the reference. To partially compensate this negative effect
on the duty ratio of the main switch, the auxiliary switch
is controlled through adjusting the dead time with respect to
peak inductor current. The improvement on the effective duty
ratio using the proposed variable dead-time control is analyzed
and compared with the conventional fixed dead-time approach
within the content of this paper. Although the improvement on
the duty ratio is analyzed in this paper, the proposed technique
is a possible solution for secondary control objectives, such as
capacitor voltage balancing.
II. P ROPOSED B IDIRECTIONAL ZVT
TL DC/DC C ONVERTER
The proposed converter achieves ZVT for all the switches
during turn-on instants in all operation modes. The ZVT cell
contains two resonant inductors, one resonant capacitor, and an
auxiliary switch to eliminate the turn-on losses of switches by
creating a resonance between the inductor and the capacitor.
The energy stored in the auxiliary inductor during normal
operation is transferred to the capacitor when the main switch is
turned off. This energy is then recycled through the body diode
of the main switch before it is turned on. An identical ZVT cell

is placed between switches S3 and S4 to soft-switch the bottom

two switches. The basic operation principle of the ZVT cell is
identical in each transition mode for both boost and buck operations. Table I summarizes the ZVT cell operation depending
on the buck and boost modes, used resonant inductor, auxiliary
switch, and soft-switched MOSFET.
The equivalent circuits and operation waveforms are given
in Figs. 2 and 3, respectively. Here, the operation principle
will be given for the turning-on instant of S2 in boost mode
when d > 0.5. It should be noted that Lr3 is not involved
during this switching-state transition and can be assumed as
an additional contributing inductance to Lin . For the sake of
symmetrical operation, the resonant inductors are chosen equal,
i.e., Lr1 = Lr2 = Lr3 = Lr4 = Lr .
Operation Interval 1 [t < t0 ]: Before t0 , both S2 and S3
are on, Lin stores energy, and the converter operates in boost
operation mode of the TL converter. In this mode, iLr1 (t0) = 0.
If the on-time of the auxiliary switch is equal to the quarter of
the resonance period, the resonant capacitor voltage becomes
zero at t0 , (vCr1 (t0 ) = 0). This will be explained in latter
sections. The current of Lr2 is equal to
iLr2 (t) = iLr2 (t7 ) +

Vin
t.
Lin + 2Lr

(1)

This time interval is determined by the effective on-time duty

ratio of S2 .
Operation Interval 2 [t0 t < t1 ]: At t = t0 , S2 is turned
off. The current of Lr2 begins to resonate in the resonance tank
composed of Lr1 Lr2 Cr1 . The sum of the voltages of the
inductors vL1 + vL2 is equal to vcr1 . During this short time
interval, the parasitic capacitance of the upper switch, i.e., C1 ,
discharges over the output capacitor and transfers its energy
while C2 is charged as vS1 (to ) = Vo /2, and vS1 + vCr1 +
vS2 = Vo /2 during t01 . The initial conditions can be noted as


Vin
iLr2 (t0 ) = iLr2 (t7 ) +
(2)
t70
Lin + 2Lr
iLr1 (t0 ) = 0

(3)

vCr1 (t0 ) = 0.

(4)

The natural frequency of the resonant tank is expressed as

1
=
.
2Lr Cr1

(5)

Operation Interval 3 [t1 t < t2 ]: C1 is completely discharged at the end of operation interval 2, as current begins

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Fig. 2. Operation intervals and equivalent circuits. (a) Operation interval 1: t < t0 . (b) Operation interval 2: t0 < t < t1 . (c) Operation interval 3:
t1 < t < t2 . (d) Operation interval 4: t2 < t < t3 . (e) Operation interval 5: t3 < t < t4 . (f) Operation interval 6: t4 < t < t5 . (g) Operation interval 7:
t5 < t < t6 . (h) Operation interval 8: t6 < t < t7 .

commutating from Lr2 to Lr1 , and D1 conducts. C2 continues

to get charged. This interval occurs very quickly as C1 is
typically on the order of several hundreds of picofarads and
is not included in the calculations for simplicity. The energy
stored in Lr2 is transferred to resonant capacitor Cr1 through
Da1 . For this interval, the resonant inductor currents can be
expressed as

At t = t2 , iLr2 becomes zero as it transfers all its energy to the

resonant capacitor
iLr2 (t2 ) = 0.
From this final state condition, t02 can be found as
t02 =

iLr2 (t) = iLr2 (t0 ) cos(t)

(6)

iLr1 (t) = iLr2 (t0 ) (1 cos(t)) .

(7)

The resonant capacitor voltage can be written as

vCr1 (t) =

iLr2 (t0 )
sin(t).
Cr1

(8)

(9)

.
2

(10)

Operation Interval 4 [t2 t < t3 ]: At t = t2 , the resonant

inductor current iLr1 is the same as iLr2 (t0). The resonant capacitor voltage can be found from the energy transfer between
vcr1 and iLr2 as

2Lr 2
i (t0 ).
(11)
vCr1 (t2 ) =
Cr1 Lr2

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3155

Operation Interval 6 [t4 t < t5 ]: When the energy stored

in the resonant capacitor is completely transferred via Sa1 ,
C2 quickly discharges to zero. This time interval can be
expressed as



C2 Vo2
2
8Lr iLr2 (t4 ) iLr2 (t4 ) 8Lr
.
(17)
t45 =
Vo
At t = t5 , the current of D1 increases to approximately twice
the load current.
Operation Interval 7 [t5 t < t6 ]: When vS2 reaches to
0.7 V, the body diode of S2 conducts. This time period is
the ZVT period. S2 can be turned on at any time during this
interval. At t = t5 , the initial conditions are

2 (t )
Cr1 vCr1
2
(18)
iLr2 (t5 ) =
2Lr
iLr1 (t5 ) = iLr1 (t4 ) + Cr1 vCr1 (t4 ) sin(t4 )

(19)

where vLr2 is equal to Vo /4, and iLr2 linearly decreases, i.e.,

Fig. 3. Switching scheme and circuit waveforms of the proposed ZVT

converter.

The energy stored in vcr1 will be used to achieve soft switching

in the latter stage. In this time interval, the resonant inductor
current iLr1 can be written as


Vo /2 Vin
iLr1 (t) = iLr1 (t2 )
t.
(12)
Lin + Lr
Operation Interval 5 [t3 t < t4 ]: Before S2 is turned on,
the auxiliary switch, i.e., Sa1 , is turned on to transfer the energy
stored in the capacitor to the resonant inductor, i.e., iLr2 . Sa1
is turned on under zero current; thus, there is no switching
turn-on loss for the auxiliary switches. vLr2 is half the vCr1 ,
and iLr2 sinusoidally increases. C2 is first quickly charged to
vCr1 + Vo /2 and then discharged as vCr1 decreases. At t = t3 ,
the initial conditions are as follows: iLr2 (t3 ) = 0, vcr1 (t3) =
vcr1 (t2 ). In this interval, the resonant inductor currents and
capacitor voltage are
vCr1 (t) = vCr1 (t3 ) cos(t)

(13)

iLr2 (t) = Cr vCr1 (t3 ) sin(t)

(14)

iLr1 (t) = iLr1 (t3 ) + Cr vCr1 (t3 ) sin(t)

(15)

t34 =

.
2

At the end of this mode, vCr1 (t4 ) = vCr1 (t0 ) = 0.

(16)

iLr2 (t) = iLr2 (t5 ) +

Vo
4Lr

(20)

iLr1 (t) = iLr1 (t5 )

Vo
t.
4Lr

(21)

Operation Interval 8 [t6 t < t7 ]: This interval starts after

the main switch S2 is turned on. At t = t6 , the main switch S2
is turned on while its body diode is conducting. The ZVT can
be achieved at this instant. With the assumption of negligible
t45 in comparison to t56 , t46
= t56 , the ZVT time interval can
be expressed as
t56 =

4Lr (iLr2 (t6 ) iLr2 (t5 ))

.
Vo

(22)

First, the current of the body diode of S2 reaches to zero. In this

time interval, S2 begins to conduct, and input current commutes
from Lr1 to Lr2 . At t = t6 , iLr1 is
iLr1 (t6 ) = iLr1 (t5 )

Vo
t56 .
4Lr

(23)

The resonant inductor currents for this interval can be

expressed as
iLr1 (t) = iLr1 (t6 )

Vo
t
4Lr

(24)

iLr2 (t) = iLr2 (t6 ) +

Vo
t.
4Lr

(25)

At t = t7 , the input current commutation from Lr1 to Lr2 is

completed, and iLr1 becomes zero. This time interval can be
expressed as
t67 =

4Lr (iLr2 (t7 ) iLr2 (t6 ))

.
Vo

(26)

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III. D ESIGN C ONSIDERATIONS FOR ZVT F EATURE

The time between the turning-off action of Sa1 and the
turning-on action of the main switch S2 , which is denoted by
t46 , should be as short as possible to achieve ZVT with the
smallest amount of energy stored in the resonance tank. This
would minimize the size of the resonant tank elements and
allows achieving higher efficiency as the circulating current in
the resonant tank would be less. To achieve ZVT, the auxiliary
switch should be turned on at least t36 before the main switch
is turned on. It should be highlighted that t34 is the time
duration in which the stored energy in the auxiliary capacitor is
transferred to the auxiliary inductor, and t45 is the time required
to discharge the parasitic capacitance of the switch. For the
ideal case, the minimum required time is t35 . t56 is the time
duration added to guarantee the soft switching of the main
switch taking the mismatch between the actual and datasheet
values of the switch. Considering this added time margin, the
auxiliary switch should be turned on at least t36 before the
main switch is turned on. Once t46 is determined, Lr can be
calculated accordingly.
A. Constant Power Loads
The minimum value of Lr can be determined for constant
power loads with predefined Po , Vo , Vin , and Lin and steadystate duty ratio (D). For simplicity in calculations, it is assumed
that iLr2 does not vary during t45 , and |iLr2 (t5)| = |iLr2 (t0 )|,
which yields
Vo
t46 .
4iLr2 (t0 )

Lr

(27)

In order to have zero voltage across Cr1 from t = t4 to t =

t0 , the reverse resonance time, i.e., t34 , should be equal to
one fourth of the natural resonance period, i.e., t02 , which is
initiated by turning on Sa1 . If t34 is forced to be shorter than
t02 , vCr1 (t0 ) would be higher than zero. Cr1 can be calculated
from (5) and (10), by equalizing t34 and t02 time periods, as
Cr1

2 2
=
t .
Lr 2 02

(28)

Since two quarter resonance periods take place during the offtime of the switch, their sum should be shorter than (1 D)Ts ,
where Ts represents the switching period
t02 <

Ts (1 D)
.
2

(29)

As the quarter resonance period t02 increases, the required

capacitance also increases while the voltage stress on S2 reduces. The additional voltage stress across S2 is equal to that of
vcr1 (t2 ) and can be expressed as

2Lr
vcr1 (t2 ) = iLr2 (t0 )
.
(30)
Cr1
B. Variable Power Loads
From (27), it can be observed that the ZVT feature is dependent on the load current as it determines the stored energy in the

Fig. 4. Illustration of ZVT operation with fixed and variable dead times
for evaluation of t67 . (a) Fixed dead time. (b) Variable dead time.

resonant inductor. Therefore, for wide-load-range applications,

the minimum input current at which the ZVT feature is desired
should be determined for the given application, i.e.,
tZV T tdt + tm

(31)

where tdt denotes the selected dead time, and tm is the time
margin, representing the time from turn-on instant of the main
switch until iLr2 becomes zero, and should be included in
the calculations ensuring that the switch is switched under
zero voltage. Minimum Lr for variable power loads can be
determined as
Lr

Vo
tZV T .
4iLr2 (t0 )

(32)

In case the auxiliary switch is turned off tdt seconds before

the main switch is turned on, D1 would conduct for the time
duration of tZV T .
The selected Lr should be sufficiently large to achieve soft
switching for S2 at minimum load current. However, the selected Lr would cause losing effective on-time of the switch
as the load gets heavier. This issue is illustrated in Fig. 4(a).
Here, it is assumed that the load current is larger than I_min ,
and Lr is found using (27) for the ideal case, assuming tdt = 0.
As shown in the figure, the reduction in the duty ratio, which
is denoted by DL , increases under heavy load. The reduction
in the duty cycle should be compensated similar to dead-time
compensation applied in three-phase inverters [27]. To reduce
this effect, the phase of the gating signal of the auxiliary switch
should be varied such that the main switch is turned on right
before the current of the main-switch body diode reaches zero.
In this regard, a variable dead-time control is proposed in this
paper, as shown in Fig. 4(b). The gating signals for the auxiliary
switches are practically achieved by right-aligned pulsewidth
modulation (PWM) signal with inserted fixed dead time. At
heavy loads, instead of turning off the auxiliary switch with

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TABLE II
D ESIGN PARAMETERS

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before the main switch is turned on. This way, the resonant
current will become zero after tm + tdt = 50 ns. The ZVT
time period corresponds to 1% of the switching period. The
reduction in the duty cycle, i.e., t67 /DTs , can be expressed as
DL =

fixed tdt seconds, before the main switch is turned on, the
discharging of the resonant capacitor can be initiated earlier
by adjusting the dead time between the main and auxiliary
switch signals. Hence, the resonant inductor current crosses
zero tm seconds after the main switch is turned on. At the ideal
case, i.e., tm = 0, this could reduce DL to DL /2, as illustrated
in Fig. 4(b).
It is important to note that the proposed variable dead-time
approach can be used for achieving supplementary control
objectives such as dc-link capacitor voltage balancing. The variable dead time has not been considered in any soft-switching
literature because it may not be necessary in two-level converters. One of the difficulties in TL converters is the unbalanced
dc-link capacitor voltages, which may occur due to the unsymmetrical circuit layout, differences in the equivalent series
capacitance of capacitors, delays in the gate driver circuit, etc.
The unbalanced voltage problem could be solved by controlling
the duty cycles of the main switches independently, letting capacitors charge/discharge more or less with respect to the other
dc-link capacitors. However, the common approach is to use
the same PWM duty-cycle generator for both of the switches
due to its simple control and, more importantly, for stable
operation. In this regard, developed secondary variable deadtime control can be adopted to balance the dc-link capacitors as
well as contribute to the duty-cycle compensation, correcting
the unbalanced ZVT current injection due to unsymmetrical
ZVT circuit parameters and so on. However, in this paper, only
partial duty-cycle compensation has been studied, and capacitor
voltage balancing is out of the scope of this paper.
C. Example Application
This section provides a ZVT cell design procedure for a
variable power load. The example design specifications are
provided in Table II. The converter operates in CCM at fullload range.
The first design parameter to be determined is tZV T . As previously discussed, t45 is relatively short, on the order of several
nanoseconds. The variation of t45 at minimum load current according to Lr is plotted in Fig. 5(a) for maximum and minimum
output voltages. As the output voltage increases, more energy
is stored in the parasitic capacitances of the switches, which
extends the discharge time to 5 ns. At Po = 250 W, the dead
time, i.e., tdt , is chosen as 30 ns. This would be 5 ns for an ideal
case; however, it is reasonable to insert a dead time to ensure
that soft switching will be robust to the mismatch of the actual
and datasheet values as well as to compensate the previous
simplifications. Since the switching period is 5 s and considering the turn-on and turn-off time of MOSFETs, tm is chosen
as 20 ns to ensure that the auxiliary switch turns off 30 ns

(tdt + 2tm )
.
DTs

(33)

To find Lr , the worst condition should be considered; that

is, Po = Po,min , and Vo = Vo,max . Assuming that Lin is large
enough and input current is constant, iLr2 (t0 ) in (32) can be
approximately equal to the input current. For this example, Lr
is calculated as 1 H. The highest ZVT time, i.e., t57 /2, is
50 ns for minimum load at Vo = Vo,max . At maximum load,
the ZVT period increases to 130 ns. For Vo = Vo,min , the ZVT
period for minimum load is 55 ns, and at maximum output
power, it increases up to 145 ns. The same amount of time is
required for the main switch current to reach the input current,
i.e., t57 /2. For a fixed tdt of 30 ns, t67 can be calculated
using t57 tdt as 70 and 230 ns for the lightest and heaviest
load conditions at Vo = Vo,max , respectively. Similarly, when
Vo = Vo,min , t67 becomes 80 and 260 ns for the lightest and
heaviest load conditions, respectively.
In CCM, the duty ratios for Vo = Vo,min and Vo = Vo,max
are 44% (corresponding to 2.22 s) and 50% (corresponding to
2.5 s). Using (33), DL is calculated as 3.6% and 11.6% for
light- and heavy-load conditions at Vo = Vo,min , respectively.
Similarly, for Vo = Vo,max , it is calculated as 2.8% and 9.6%,
respectively. Using the proposed variable dead-time approach,
DL can be effectively reduced as shown in Fig. 5(b). The
dead-time curve used to accomplish DL reduction is given in
Fig. 5(c).
The acquired data are summarized in Table III. It can be seen
that DL is reduced from 11.6% to 7.4% for low output voltage
and heavy-load conditions. If tm is chosen smaller at the initial
step, DL can be reduced even further, to half the DL value
with fixed dead time at the ideal case, when tm = 0. However,
further duty-cycle compensation is still required.
Once tdt and Lr are determined, Cr can be determined
from (28) and (29). As mentioned before, the pulsewidth of
Sa1 should be equal to t02 to have zero voltage across vcr at
t = t0 . When a dead time is inserted, (29) should be modified
to incorporate tdt . Thus,
t02 <

Ts (1 D)
tdt .
2

(34)

The highest tdt is achieved when output power is maximum

and output voltage is lowest. However, for this case, Ts (1
D)/2 tdt for the Vo = Vo,max condition is smaller; hence,
t02 should be determined based on maximum output voltage.
This determines the upper bound for choosing t02 , which is
calculated as 1.14 s. The variation of the capacitance value
and voltage stress of the resonant capacitor for various t02
values from 0.1 to 1.14 s is given for the heaviest load
condition in Fig. 6. Here, Cr can be determined based on the
tradeoff between the capacitance value and the voltage stress.
In addition, there should be sufficient margin for duty-cycle
compensation. Once t02 is determined, the duty ratio of Sa1
can be found by dividing t02 by Ts .

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Fig. 5. Curves for the ZVT operation. (a) Switch parasitic capacitance discharge time according to various Lr . (b) Reduction in effective duty
ratio for various output power values when Lr = 1 H. (c) Required dead time for the proposed variable dead-time control at various output
power values.
TABLE III
ACQUIRED DATA FOR ZVT O PERATION

Fig. 6. Capacitance and voltage stress variation of the resonant capacitor at various t02 values.

IV. S IMULATION AND E XPERIMENTAL R ESULTS

Here, simulation and experimental results are provided to
verify the operation of the converter. The switching frequency
of the main and auxiliary switches is 200 kHz, where the
frequency of the inductor and output capacitor current ripples
is 400 kHz. The resonant inductors, i.e., Lr , are 1 H, and
the resonant capacitors, i.e., Cr , are 100 nF each. Only boost
operation mode is presented here, as buck operation is similar
to boost operation.
The simulation waveforms for d = 0.53 and d = 0.4 using
ideal switches are given in Fig. 7(a) and (b), respectively. In
boost operation, only S2 and S3 are switched while body diodes
of S1 and S4 conduct. The additional voltage stress on the
main switches can be clearly observed. The duty ratio of the
auxiliary switch calculated from the analysis match with one
fourth of the resonant period, such that the resonant capacitor

voltage is almost zero. The simulation waveforms agree with

the theoretical analysis.
The simulation waveforms for boost operation utilizing nonideal switches when d = 0.4 are presented in Fig. 7(c). In
the figures, it can be clearly seen that Coss of the switches,
particularly that of the auxiliary switches, causes to form a
resonant tank between Lr Lr Cr Coss . Without including the internal resistances, this oscillation keeps circulating
back and forth. As seen from the input inductor voltage, this
oscillation causes inductor current to have a small oscillating
current in addition to the linearly increasing current.
A 650-W proof-of-concept prototype, shown in Fig. 8, is
designed to serve as a proof-of-concept and to show ZVT operation of the circuit. The circuit parameters are the same as those
of the simulation. The current ratings of the switches are chosen
based on the root mean square (rms) value. As the ZVT circuit
does not impose additional current stress on the main switches,
the main-switch rms current can be found as in a traditional
TL converter [10]. The voltage rating of the main switches is
the sum of half the output voltage and the resonant capacitor
voltage, which was given in (30). It can be expressed as

2Lr
Vo
+ iLr2 (t0 )
.
(35)
Vmain =
2
Cr1
On the other hand, the current rating of the auxiliary switch
is equal to

2+
.
(36)
Iaux,rms = iLr2 (t0 )
8Ts
The component parameters used in the experiments are given
in Table IV. Fig. 9 presents the input inductor current waveform
and gatesource voltages of S2 and S3 . This figure illustrates
the boost mode operation of the TL converter, where the current
ripple frequency is twice the switching frequency.
The ZVT operation of the converter has been presented in
the experimental results provided in Figs. 10 and 11. Fig. 10
presents the ZVT operation during boost mode of operation
for d < 0.5 under low current. The peak value of IS2 is approximately 2.2 A. As depicted before, the auxiliary switch
is turned on before the main switch is turned on to conduct
the body diode of the main switch. The ZVT can be clearly
observed in Fig. 10(b). In Fig. 10(c), auxiliary current and

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Fig. 7. Simulation waveforms for boost operation mode. (a) d = 0.53 with ideal switches. (b) d = 0.4 with ideal switches. (c) d = 0.4 with nonideal
switches.

TABLE IV
C OMPONENT PARAMETERS

Fig. 8.

Photograph of the designed experimental prototype.

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Fig. 9. Experimental waveforms of normal boost operation; gatesource

voltages S2 and S3 and inductor current for (a) d < 0.5 and (b) d > 0.5.

voltage waveforms are presented, from which ZCS operation

can be clearly seen. The experimental waveforms agree with
the simulation results presented in Fig. 7(c). Different than
simulation, the oscillations are damped due to the internal
resistances of the components in the experiments. Likewise,
ZVT operation for boost mode for d < 0.5 under higher current
(peak switch current of 4 A) profile is given in Fig. 11.
It should be noted that the proposed ZVT cell causes some
undesirable oscillations on the drainsource voltage as well as
the current of the main switches. These oscillations are due to
the output parasitic capacitance of the auxiliary switches, i.e.,
Coss . In the experiments, a low Coss switch with rated Coss of
140 pF at Vds = 200 V is utilized to minimize the oscillation
amplitude and increase the resonance frequency. However,
these oscillations are inevitable as there is Lr Lr Cr
Coss resonant network. Meanwhile, half the output voltage
is equal to the sum of Vs1 , Vs2 , Vcr1 , and Vsa1 . Therefore,
any oscillation within the resonant network affects the switch
voltage and current waveforms. Nevertheless, this energy keeps
oscillating back and forth until it is damped by the internal
resistances of the resonant tank components.
The equivalent capacitance involved in the oscillations is
equal to (Cr Coss )/(Cr + Coss ), which makes it close to the
value of Coss . The energy stored in Coss starts to resonate.
Considering its capacitance, the stored energy is very small.
The voltage of Cr , which can be observed from the additional
voltage stress on the main switches, remains almost the same

Fig. 10. Experimental waveforms of ZVT operation boost mode when

d < 0.5 (low current). (a) Gatesource and drainsource voltages and
current of S2 and gatesource voltage of Sa1 for two switching periods.
(b) Zoomed-in snapshot. (c) Gatesource and drainsource voltages
and current of Sa1 and gatesource voltage of S2 .

between charging and discharging instants of Cr , which also

shows that energy is conserved and not wasted. This can also be
observed from the auxiliary switch current given in Figs. 10(c)
and 11(c), which is the same as the resonant capacitor current.
The peak values of the resonant capacitor current are the same
for charging and discharging instants. This also verifies that this
oscillation does not cause significant power loss. Consequently,
it can be concluded that this oscillation 1) does not create any
additional voltage stress on the components, 2) causes very
small current stress on the inductors and switches, and 3) results
in very small circulating energy, most of which is not wasted.

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Fig. 12. Efficiency curve of (a) the proposed topology at Vo = 180 V

and Vo = 220 V and (b) the hard-switched TL converter.

frequency oscillations on the gate signals are completely due to

the differential probe parasitics.
The efficiency curves for two different output voltage levels,
along with hard-switched converter efficiency, are presented
in Fig. 12. It can be seen that the designed prototype exhibits 95.5% at full load, whereas the peak efficiency of the
hard-switched converter is 91%. Considering the typical efficiencies of industrial nonisolated bidirectional dc/dc converters,
which are between 90% and 95%, the proposed ZVT converter
provides competitive efficiency to its counterparts. In addition,
it should be noted that the proposed ZVT converter inherently
reduces the required input boost inductance and output filter
capacitance by half due to the TL structure, in comparison to
the state-of-the-art converters. Moreover, it allows using lowvoltage rated switch.
V. C ONCLUSION

Fig. 11. Experimental waveforms of ZVT operation boost mode when

d < 0.5 (high current). (a) Gatesource and drainsource voltages and
current of S2 and gatesource voltage of Sa1 for two switching periods.
(b) Zoomed-in snapshot. (c) Gatesource and drainsource voltages
and current of Sa1 and gatesource voltage of S2 .

In this paper, a ZVT bidirectional TL dc/dc converter, employing two identical ZVT cells to fully soft-switch all four
switches in bidirectional power flow during turning-on instants
of the main switches, has been introduced. The design procedures of the ZVT cell components were provided. Furthermore,
an actively controlled variable dead-time approach has been
introduced to minimize the reduction in the duty ratio due
to the soft-switching period, during the converters operation
under heavy loads. A 650-W prototype has been designed to
demonstrate the operation of the converter. The peak efficiency
at 200-kHz switching frequency is recorded as 95.5%.

In addition, the very high frequency oscillation observed on

the gate signals is due to the high parasitic capacitance of the
differential probe. Since the grounds of the probes should be
isolated, a regular and a differential voltage probe are used
for sensing gates of the signals. To prove this claim, the
regular and differential probes have been connected to the gate
source terminal of S2 (purple waveform) and Sa1 (green waveform) in Fig. 10(b), respectively. As it can be seen, the very
high frequency oscillations are only on the Sa1 gate signal.
In Fig. 10(c), these two probes are replaced. This time, the
oscillations are observed on the S2 gate signal. Thus, the high-

[1] A. Khaligh, A. Miraoui, and D. Garret, Guest editorial: Special section

on vehicular energy-storage systems, IEEE Trans. Veh. Technol., vol. 58,
no. 8, pp. 38793881, Oct. 2009.
[2] A. Khaligh and Z. Li, Battery, ultracapacitor, fuel-cell, hybrid energy
storage systems for electric, hybrid electric, fuel cell, plug-in hybrid
electric vehicles: State-of-art, IEEE Trans. Veh. Technol., vol. 59, no. 6,
pp. 28062814, Jul. 2010.
[3] O. Onar and A. Khaligh, A novel integrated magnetic structure based
dc/dc converter for hybrid battery/ultra-capacitor energy storage systems,
IEEE Trans. Smart Grid, vol. 3, no. 1, pp. 296307, Mar. 2012.
[4] A. A. Ferreira, J. A. Pomilio, G. Spiazzi, and L. de Araujo Silva, Energy
management fuzzy logic supervisory for electric vehicle power supplies
system, IEEE Trans. Power Electron., vol. 23, no. 1, pp. 107115,
Jan. 2008.

R EFERENCES

3162

IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 62, NO. 5, MAY 2015

[5] S. Dusmez and A. Khaligh, A supervisory power splitting approach for

a new ultracapacitor-battery vehicle deploying two propulsion machines,
IEEE Trans. Ind. Informat., vol. 10, no. 3, pp. 19601971, Aug. 2014.
[6] S. Dusmez and A. Khaligh, Generalized technique of compensating lowfrequency component of load current with parallel bidirectional dc/dc
converter in electric vehicles, IEEE Trans. Power Electron., vol. 29,
no. 11, pp. 58925904, Nov. 2014.
[7] H. Wang, Highly efficient SiC based onboard chargers for plug-in electric
vehicles, Ph.D. dissertation, Elect. Comput. Eng. Dept., Univ. Maryland,
College Park, MD, USA, Jul. 2014.
[8] H. Kosai, J. Scofield, S. McNeal, B. Jordan, and B. Ray, Design and
performance evaluation of a 200 C Interleaved Boost Converter, IEEE
Trans. Power Electron., vol. 28, no. 4, pp. 16911699, Apr. 2013.
[9] M. B. Camara, H. Gualous, F. Gustin, A. Berthon, and B. Dakyo, DC/DC
Converter design for supercapacitor and battery power management in
hybrid vehicle applicationsPolynomial control strategy, IEEE Trans.
Ind. Electron., vol. 57, no. 2, pp. 587597, Feb. 2010.
[10] P. J. Grbovic, P. Delarue, P. L. Moigne, and P. Bartholomeus, A bidirectional three-level DCDC converter for the ultracapacitor applications,
IEEE Trans. Ind. Electron., vol. 57, no. 10, pp. 34153430, Oct. 2010.
[11] J.-W. Yang and H.-L. Do, High-efficiency bidirectional dcdc converter
with low circulating current and ZVT characteristic throughout a full
range of loads, IEEE Trans. Ind. Electron., vol. 61, no. 7, pp. 32483256,
Jul. 2014.
[12] A. K. Rathore and U. R. Prasanna, Analysis, design, experimental results
of novel snubberless bidirectional naturally clamped ZCS/ZVS currentfed half-bridge DC/DC converter for fuel cell vehicles, IEEE Trans. Ind.
Electron., vol. 60, no. 10, pp. 44824491, Oct. 2013.
[13] U. R. Prasanna and A. K. Rathore, Extended range ZVT active-clamped
current-fed full-bridge isolated dc/dc converter for fuel cell applications:
Analysis, design and experimental results, IEEE Trans. Ind. Electron.,
vol. 60, no. 7, pp. 26612672, Jul. 2013.
[14] W. Yu, H. Qian, and J.-S. Lai, Design of high-efficiency bidirectional
DCDC converter and high-precision efficiency measurement, IEEE
Trans. Power Electron., vol. 25, no. 3, pp. 650658, Mar. 2010.
[15] L. Ni, D. J. Patterson, and J. L. Hudgins, A high power, current sensorless, bi-directional, 16-phase interleaved, DCDC converter for hybrid
vehicle application, in Proc. IEEE ECCE, 2010, pp. 36113617.
[16] J. Zhang, J.-S. Lai, R.-Y. Kim, and W. Yu, High-power density design of a
soft-switching high-power bidirectional DCDC converter, IEEE Trans.
Power Electron., vol. 22, no. 4, pp. 11451153, Jul. 2007.
[17] B.-R. Lin and C.-H. Chao, Analysis, design, implementation of a softswitching converter with two three-level PWM circuits, IEEE Trans.
Power Electron., vol. 28, no. 4, pp. 17001710, Apr. 2013.
[18] H.-L. Do, Nonisolated bidirectional zero-voltage-switching DCDC
converter, IEEE Trans. Power Electron., vol. 26, no. 9, pp. 25632569,
Sep. 2011.
[19] S. D. G. Jayasinghe, D. M. Vilathgamuwa, and U. K. Madawala, Diodeclamped three-level inverter-based battery/super-capacitor direct integration scheme for renewable energy systems, IEEE Trans. Power Electron.,
vol. 26, no. 12, pp. 37203729, Dec. 2011.
[20] R. K. Singh and S. Mishra, A magnetically coupled feedback-clamped
optimal bidirectional battery charger, IEEE Trans. Ind. Electron., vol. 60,
no. 2, pp. 422432, Feb. 2013.
[21] H. Wu, J. Lu, W. Shi, and Y. Xing, Nonisolated bidirectional DCDC
converters with negative-coupled inductor, IEEE Trans. Power Electron.,
vol. 27, no. 5, pp. 22312235, May 2012.
[22] S.-S. Lee, Step-down converter with efficient ZVT operation with load
variation, IEEE Trans. Ind. Electron., vol. 61, no. 1, pp. 591597,
Jan. 2014.
[23] H. Bodur and A. F. Bakan, An improved ZCT-PWM DCDC converter
for high-power and frequency applications, IEEE Trans. Ind. Electron.,
vol. 51, no. 1, pp. 8995, Feb. 2004.
[24] H.-S. Choi and B. H. Cho, Novel Zero-Current-Switching (ZCS) PWM
switch cell minimizing additional conduction loss, IEEE Trans. Ind.
Electron., vol. 49, no. 1, pp. 165172, Feb. 2002.
[25] J. Abu-Qahouq and I. Batarseh, Unified steady-state analysis of softswitching DCDC converters, IEEE Trans. Power Electron., vol. 17,
no. 5, pp. 684691, Sep. 2002.

[26] P. Das, B. Laan, S. A. Mousavi, and G. Moschopoulos, A nonisolated

bidirectional ZVS-PWM active clamped DCDC converter, IEEE Trans.
Power Electron., vol. 24, no. 2, pp. 553558, Feb. 2009.
[27] Z. Zhang and L. Xu, Dead-time compensation of inverters considering
snubber and parasitic capacitance, IEEE Trans. Power Electron., vol. 29,
no. 6, pp. 31793187, Jun. 2014.

Serkan Dusmez (S11) received the B.S.

(Hons.) and M.S. degrees in electrical engineering from Yildiz Technical University, Istanbul,
Turkey, in 2009 and 2011, respectively. He received the M.S. degree in electrical engineering
from Illinois Institute of Technology, Chicago, IL,
USA, in 2013. He is currently working toward
the Ph.D. degree at The University of Texas at
Dallas, Richardson, TX, USA.
During 20122013, he was a Faculty Research Assistant with the Power Electronics,
Energy Harvesting and Renewable Energies Laboratory, Electrical and
Computer Engineering Department, University of Maryland, College
Park, MD, USA. He is the author/coauthor of over 35 journal and
conference papers. His research interests include design of power
electronic interfaces and energy management strategies for renewable
energy sources, integrated power electronic converters for plug-in electric vehicles, and real-time fault diagnosis of power converters.

Alireza Khaligh (S04M06SM09) is the Director of the Power Electronics, Energy Harvesting and Renewable Energies Laboratory
in the Electrical and Computer Engineering Department and the Institute for Systems Research at the University of Maryland
(UMD), College Park, MD, USA. He is an author/
coauthor of over 130 journal and conference
papers.
Dr. Khaligh is a recipient of various awards
and recognitions, including the 2013 George
Corcoran Memorial Award from the Electrical and Computer Engineering Department of UMD, the 2013 Best Vehicular Electronics Award from
the IEEE Vehicular Technology Society, and the 2010 Ralph R. Teetor
Educational Award from the Society of Automotive Engineers. He is the
Program Chair of the 2015 IEEE Applied Power Electronics Conference
and Exposition. He was the General Chair of the 2013 IEEE Transportation Electrification Conference and Exposition and the Program Chair
of the 2011 IEEE Vehicle Power and Propulsion Conference. He is an
Editor of the IEEE T RANSACTIONS ON V EHICULAR T ECHNOLOGY and
an Associate Editor of the IEEE T RANSACTIONS ON T RANSPORTATION
E LECTRIFICATION. He was a Guest Editor or a Guest Associate Editor
of various IEEE Transactions including the IEEE T RANSACTIONS ON
P OWER E LECTRONICS and the IEEE T RANSACTIONS ON I NDUSTRIAL
E LECTRONICS.

Amin Hasanzadeh (M11) received the B.Sc. degree from Sharif University of Technology, Tehran, Iran, the M.Sc. degree from Khajeh Nasir
Toosi University of Technology, Tehran, Iran, and the Ph.D. degree from
Sharif University of Technology, in 1999, 2001, and 2009, respectively,
all in electrical engineering.
He was a Post-Doctoral Research Associate with the Power Electronics, Energy Harvesting and Renewable Energies Laboratory, Electrical
and Computer Engineering Department, University of Maryland, College
Park, MD, USA.