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# 9/16/2015

Fundamental
Concepts
Ferdinand M. Fernando
Asst. Professor I
F. M. Fernando

URSM-College of Engineering

INPUTS

OUTPUTS

C. L.
MEMORY
ELEMENTS

## A block diagram of a sequential circuit shown consists of a

combinational logic (CL) circuit to which memory elements are
connected to form a feedback path. The binary information
stored in the memory at any given time defines the state of the
sequential circuit at that time. The next state of the storage
elements is a function of external inputs and the present state.
Thus, a sequential circuit is specified by a time sequence of
inputs, outputs, and internal states.
F. M. Fernando

URSM-College of Engineering

9/16/2015

## Types of Sequential Circuits

1. Synchronous can be defined from the
knowledge of its signals at a discrete instants
of time. Synchronization is achieved by a
clock generator that provides a periodic train
of clock pulses.
2. Asynchronous behavior depends upon the
input signals at any instant of time and the
order in which the inputs change. Maybe
regarded as a combinational circuit with
feedback that may become unstable at times.
F. M. Fernando

URSM-College of Engineering

INPUTS

OUTPUTS

C. L.
CLOCK
PULSES

FLIP-FLOPS

## The storage elements used in a clocked sequential

circuits are Flip-Flops (FFs). The outputs can come
either from the C.L. or from the FFs or both. The state of
the FFs can change only during a clock pulse transition.
Thus, the transition from one state to the next occurs only
at predetermined time intervals triggered by the clock
pulses.
F. M. Fernando

URSM-College of Engineering

9/16/2015

## LATCHES vs. FLIP-FLOPS

The most basic types of FFs operate with signal
levels and are referred to as LATCHES.
LATCHES are the basic circuits from which all FFs
are constructed.
Although LATCHES are useful for storing binary
information and for the design of asynchronous
sequential circuits, they are NOT practical for use
in synchronous sequential circuits.
The storage elements used in clocked sequential
circuits can ONLY be implemented using FFs.
F. M. Fernando

URSM-College of Engineering

## Clock Response in LATCH and FF

The key to proper operation of a FF (unlike a
latch) is to trigger it only during a clock
transition, either from 0 to 1 or vice versa.
0
1

A positive transition is defined as the positiveedge () and the negative transition as the
negative-edge ().

F. M. Fernando

URSM-College of Engineering

9/16/2015

## Two Ways LATCHES Can be Modified to Form FFs

1. Employ two latches
in a special
configuration that isolates the output of
the FF from being affected while its
inputs is changing.
2. Produce a FF that triggers only during a
signal transition (from 0 to 1 or from 1
to 0), and is disabled during the rest of
the clock pulse duration.
F. M. Fernando

URSM-College of Engineering

Memory Elements

F. M. Fernando

URSM-College of Engineering

9/16/2015

Memory Elements

F. M. Fernando

URSM-College of Engineering

Memory Elements

F. M. Fernando

URSM-College of Engineering

10

9/16/2015

In Summary

F. M. Fernando

URSM-College of Engineering

11

Q ue stions
1. List down the differences, in terms of circuit
components function of asynchronous and
synchronous sequential logic circuit.
2. Define a latch and a FF. In what terms are they
the same and different?
3. What is a clock pulse transition?
4. Give the ways how latches can be modified to
form FFs.
5. What are examples of bistable logic devices?
F. M. Fernando

URSM-College of Engineering

12