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CMOS Analog Circuit Design (2 nd Ed.) Homework Solutions : 9/20/2002

1

Chapter 1 Homework Solutions

1.1-1

(b 4 b 3 b 2 b 1 b 0 ordering).

Using Eq. (1) of Sec 1.1, give the base-10 value for the 5-bit binary number 11010

From Eq. (1) of Sec 1.1 we have

b N-1 2 -1 + b N-2 2 -2 + b N-3 2 -3 +

N

+ b 0 2 -N =

i=1

b N-i 2 -i

1 × 2 -1 + 1× 2 -2 + 0 × 2 -3 + 1 × 2 -4 + 0 × 2 -5 =

1

2 + 4 + 8

1

0 + 16 + 32

1

0

=

16 + 8 + 0 + 2 + 0

32

= 26

32 = 13

16

1.1-2

Process the sinusoid in Fig. P1.2 through an analog sample and hold. The sample

points are given at each integer value of t/T. 15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
12345678
9
10
11
Sample times
Amplitude

t

T

Figure P1.1-2

1.1-3

Digitize the sinusoid given in Fig. P1.2 according to Eq. (1) in Sec. 1.1 using a

four-bit digitizer.

CMOS Analog Circuit Design (2 nd Ed.) Homework Solutions : 9/20/2002

2

 15 14 13 12 11 Amplitude 10 9 8 7 6 5 4 3 2 1 0 Sample times 1111
1110
1101
1100
1010
1000
1000
0110
0101
0011
0010
0010
12345678
9
10
11

t

T

Figure P1.1-3

The figure illustrates the digitized result. At several places in the waveform, the digitized value must resolve a sampled value that lies equally between two digital values. The resulting digitized value could be either of the two values as illustrated in the list below.

 Sample Time 4-bit Output 0 1000 1 1100 2 1110 3 1111 or 1110 4 1101 5 1010 6 0110 7 0011 8 0010 or 0001 9 0010 10 0101 11 1000

1.1-4

Use the nodal equation method to find v out /v in of Fig. P1.4.

CMOS Analog Circuit Design (2 nd Ed.) Homework Solutions : 9/20/2002

3 A
B
R 1
R 2
R
v in
R 3
v 1
g m v 1
4
v out
Figure P1.1-4
Node A:
0 = G 1 (v 1 -v in ) + G 3 (v 1 )
+
G 2 (v 1 - v out )

v 1 (G 1 + G 2 + G 3 ) - G 2 (v out )

Node B:

= G 1 (v in )

0 = G 2 (v out -v 1 ) +

g m1 (v 1 ) + G 4 ( v out )

 v 1 (g m1 - G 2 ) + v out (G 2 + G 4 )    G 1 +G 2 +G 3 g m1 - G 2 = 0 G 1 v in 0    v out =    G 1 +G 2 +G 3 g m1 - G 2 - G 2 G 2 + G 4   

1.1-5 v
G 1 (G 2 - g m1 )
out
v in
=
G 1 G 2
+ G 1 G 4 + G 2 G 4 + G 3 G 2 + G 3 G 4 + G 2 g m1
Use the mesh equation method to find v out /v in of Fig. P1.4.
R 1
R 2
R
v in
i a
R 3
v 1
g m v 1
4
v out
i c
i b

Figure P1.1-5

CMOS Analog Circuit Design (2 nd Ed.) Homework Solutions : 9/20/2002

4

0 = -v in + R 1 (i a + i b + i c ) + R 2 (i b + i c ) + v out

v out

R 4

i c =

i b = g m v 1 = g m i a R 3

0

0

= -v in + R 1 i a + g m i a R 3 + v out

R 4

= -v in + R 1 i a + g m i a R 3 + v out

R 4

+

+

R

3 i a

R 2 g

v in = i a (R 1 + R 3 + g m R 1 R 2 ) + v out

R 1

R 4

R 4

m i a R 3 + v out

v in = i a (R 1 + g m R 1 R 3 + g m R 2 R 3 ) + v out  

R 1 + R 2 + R 4

R

4

+ v out

v out =

R 1 +R 3 + g m R 1 R 3

  R 1 + g m R 1 R 3 + g m R 2 R 3

v

v

in

in

R 1 + R 3 + g m R 1 R 3

  R 1 + g m R 1 R 3 + g m R 2 R 3

R 1 / R 4

(R 1 + R 2 +R 4 ) / R 4

v out =

v in R 3 R 4 (1 - g m R 2 )

(R 1 + R 3

+ g m R 1 R 3 ) (R 1 + R 2 + R 4 ) - (R 2 + g m R 2 R 3 + g m R 1 R 2 R 3 )

1

1

v out =

v in R 3 R 4 (1 - g m R 2 )

R 1 R 2

+ R 1 R 4 + R 1 R 3 + R 2 R 3 + R 3 R 4 + g m R 1 R 3 R 4

v

out

v in

R 3 R 4 (1 - g m R 2 )

= R 1 R 2

+ R 1 R 4 + R 1 R 3 + R 2 R 3 + R 3 R 4 + g m R 1 R 3 R 4

1.1-6 Use the source rearrangement and substitution concepts to simplify the circuit shown in Fig. P1.6 and solve for i out /i in by making chain-type calculations only.

CMOS Analog Circuit Design (2 nd Ed.) Homework Solutions : 9/20/2002

5 i
R 2
r m i
i in
R 1
v 1
R 3
i out

i

i

in

in

i R 2
r m i
R 1
v 1 R 3

m i

r

i   R 2
R-r m
R 1
v 1 R 3

m i

r

i out =

-r m

R 3

i

i =

R 1

R + R

1 - r m i in

i

out

-r m R 1 /R 3

i in

= R + R 1 - r m

Figure P1.1-6

1.1-7

Find v 2 /v 1 and v 1 /i 1 of Fig. P1.7.

i

i

out

out

CMOS Analog Circuit Design (2 nd Ed.) Homework Solutions : 9/20/2002

6 g
m (v 1 -v 2 )
i
1
v 1
R L
v 2

v 2

v 1

= g m (v 1 - v 2 ) R L

v 2 (1 + g m R L ) = g m R L v 1

v

2

g m R L

v 1

= 1 + g m R L

v 2 = i 1 R L

substituting for v 2 yields:

i 1 R L

g m R L

v 1

v 1

= 1 + g m R L

R L ( 1 + g m R L )

i

1

=

g m R L

Figure P1.1-7

v 1 1 = R L +

i

1

g m

1.1-8

Use the circuit-reduction technique to solve for v out /v in of Fig. P1.8.

CMOS Analog Circuit Design (2 nd Ed.) Homework Solutions : 9/20/2002

7 A v (v in - v 1 )
v in
R 1
v 1
R 2
v out
N 1
N 2
A v v 1
A v v in
v in
R 1
v 1
R 2
v out

Multiply R 1 by (A v + 1)

Figure P1.1-8a A v v in
v in
v 1
R 2
v out
R 1 (A v +1)
Figure P1.1-8b
-A v v in R 2
v out =
R 2 + R 1 (A v +1)
v
-A v R 2
out

v in

= R 2 + R 1 (A v +1)

CMOS Analog Circuit Design (2 nd Ed.) Homework Solutions : 9/20/2002

8

v

out

-A -A v + 1 R 2

v

v

in

=

R

2

A v

+ 1 + R 1

As A v approaches infinity,

v out

v

in

-R 2

=

R

1

1.1-9

Use the Miller simplification concept to solve for v out /v in of Fig. A-3 (see

Appendix A).

v in R 1
R 3
r m i a
R
v 1
v
2
out
i a
i b

Figure P1.1-9a (Figure A-3 Mesh analysis.) -r m i a
-r m
v out
K =
=
=
v 1
i a R 2
R 2
R 3
Z 1 =
1 + r m
R
2

Z 2 =

-r m

R

-

3

R

r m

2

- 1

R

2

CMOS Analog Circuit Design (2 nd Ed.) Homework Solutions : 9/20/2002

9

Z 2 =

R 3 r m
R 2
R 3
=
r m
R 2
+ 1
+ 1
R 2
r m
R 1
r m i a
v
in
R 2
Z 1
Z 2
v out
i a

i a =

(R 2 || Z 1 ) + R 1

v in (R 2 || Z 1 )

1

R

2

v out = -r m i a

Figure P1.1-9b

v out =

-v in r m (R 2 || Z 1 ) (R 2 || Z 1 ) + R 1

1

R

2

v

out

(R 2 || Z 1 ) + R 1

-r m (R 2 || Z 1 )

1

R

2

v

in

=

v out

-r m R 3

v in

= (R 1 R 2 + R 1 R 3 + R 1 r m + R 2 R 3 )

1.1-10 Find v out /i in of Fig. A-12 and compare with the results of Example A-1.

i in R
1
v
R' 2
R
v
1
3
out
g
m v 1

Figure P1.1-10

CMOS Analog Circuit Design (2 nd Ed.) Homework Solutions : 9/20/2002

10

v 1 = i in (R 1 || R

'

2 )

v out = -g m v 1 R 3 = -g m R 3 i in (R 1 || R

'

2 )

v

out

i in

= -g m R 3 (R 1 || R

'

2 )

'

R 2 =

R

2

1 + g m R 3

R 1 || R

'

2 =

R 1 R 2

1 + g m R 3

(1 + g m R 3 ) R 1 + R 2

1 + g m R 3

R 1 || R

'

2 =

R

1 R 2

(1 + g m R 3 ) R 1 + R 2

v

out

i in

-g m R 1 R 2 R 3

= R 1 + R 2 + R 3 + g m R 1 R 3

The A.1-1 result is:

v out

R 1 R 3 - g m R 1 R 2 R 3

i in

= R 1 + R 2 + R 3 + g m R 1 R 3

if g m R 2 >> 1

then the results are the same.

1.1-11 Use the Miller simplification technique described in Appendix A to solve for the output resistance, v o /i o , of Fig. P1.4. Calculate the output resistance not using the Miller simplification and compare your results.

v in R 1
R 2
R
R 3
v 1
g m v 1
4
v out
Figure P1.1-11a

CMOS Analog Circuit Design (2 nd Ed.) Homework Solutions : 9/20/2002

11

Z o with Miller

K = -g m R 4

Z 2 = -R 2 g m R 4 1 = R 2 g m R 4

-g m R 4 -

1 + g m R 4

Z 0 = R 4 || Z 2 =

g

m R 2 R

2

4

1 + g m R 4

(1 + g m R 4 ) R 4 + g m R 2 R

2

4

1 + g m R 4

Z 0 = R 4 || Z 2 =

g m R 2 R

2

4

R 4 + g m R 4 ( R 4 + R 2 )

Z o without Miller i T
R 2
R 1 || R 3
v 1
g m v 1
R 4
v T
Figure P1.1-11b
v 1 = (R 1 || R 3 )  i + g m v 1 - v T 
R
4 

v 1 [1 + g m (R 1 || R 3 )] = ( R 1 || R 3 ) i T + - v T

4

R

(1)

(R 1 || R 3 ) (i T R 4 + - v T )

v 1 =

R 4 [1 + g m (R 1 || R 3 )]

CMOS Analog Circuit Design (2 nd Ed.) Homework Solutions : 9/20/2002

12

(2)

v T (R 1 || R 3 )

v 1 =

R 1 || R 3 + R 2

Equate (1) and (2)

v T

(R 1 || R 3 )

R 1 || R 3 + R 2

v T

R 1 || R 3 + R 2

(R 1 || R 3 ) (i T R 4 - v T )

= R 4 [1 + g m (R 1 || R 3 )]

i T R 4 - v T

= R 4 [1 + g m (R 1 || R 3 )]

v

T

R 4 [1 + g m (R 1 || R 3 )] + R 2 + R 1 ||R 3

Z 0 =

R 4 (R 2 + R 1 ||R 3 )

R 2 + R 4 + g m R 4 (R 1 ||R 3 ) + R 1 ||R 3

Z 0 =

R 4 R 2

+

R 1 R 3 R 4 R 1 + R 3

R 2 +

R 4 + g m R 4 R 1 R 3 + R 1 R 3

R

1 +R 3

= i T R 4 (R 2 + R 1 ||R 3 )

Z 0 =

R 4 R 2 (R 1 + R 3 )

+ R 1 R 3 R 4

(R 2 + R 4 ) (R 1 + R 3 ) + R 1 R 3 + g m R 1 R 3 R 4

Z 0 =

R 1 R 2 R 4 + R 2 R 3 R 4 + R 1 R 3 R 4

R 1 R 2 + R 2 R 3 + R 3 R 4 + R 1 R 4 + R 1 R 3 + g m R 1 R 3 R 4

1.1-12

Consider an ideal voltage amplifier with a voltage gain of A v = 0.99. A resistance R = 50 kis connected from the output back to the input. Find the input resistance of this circuit by applying the Miller simplification concept.

CMOS Analog Circuit Design (2 nd Ed.) Homework Solutions : 9/20/2002

13 i
R=50K
v 1
0.99v 1
v out

R in =

R

1

- K

K = 0.99

R in =

50 K

1

- 0.99

=

Figure P1.1-12

50 K

0.01 = 5 Meg

CMOS Analog Circuit Design (2 nd Ed.) Homework Solutions: 9/21/2002

1

Chapter 2 Homework Solutions

Problem 2.1-1 List the five basic MOS fabrication processing steps and give the purpose or function of each step.

Oxidation: Combining oxygen and silicon to form silicondioxide (SiO 2 ). Resulting SiO 2 formed by oxidation is used as an isolation barrier (e.g., between gate polysilicon and the underlying channel) and as a dielectric (e.g., between two plates of a capacitor).

Diffusion: Movement of impurity atoms from one location to another (e.g., from the silicon surface to the bulk to form a diffused well region).

Ion Implantation: Firing ions into an undoped region for the purpose of doping it to a desired concentration level. Specific doping profiles are achievable with ion implantation which cannot be achieved by diffusion alone.

Deposition: Depositing various films on to the wafer. Used to deposit dielectrics which cannot be grown because of the type of underlying material. Deposition methods are used to lay down polysilicon, metal, and the dielectric between them.

Etching: Removal of material sensitive to the etch process. For example, etching is used to eliminate unwanted polysilicon after it has been laid out by deposition.

Problem 2.1-2 What is the difference between positive and negative photoresist and how is photoresist used?

Positive: Exposed resist changes chemically so that it can dissolve upon exposure to light. Unexposed regions remain intact.

Negative: Unexposed resist changes chemically so that it can dissolve upon exposure to light. Exposed regions remain intact.

Photoresist is used as a masking layer which is paterned appropriately so that certain underlying regions are exposed to the etching process while those regions covered by photoresist are resistant to etching.

Problem 2.1-3 Illustrate the impact on source and drain diffusions of a 7° angle off perpendicular ion implant. Assume that the thickness of polysilicon is 8000 Å and that out diffusion from point of ion impact is 0.07 µm.

CMOS Analog Circuit Design (2 nd Ed.) Homework Solutions: 9/21/2002

2 Ion implantation
o
7
Polysilicon
Gate
(a) Polysilicon
After ion implantation
Implanted ions
Gate
(b) After diffusion
Polysilicon
Gate
Polysilicon
Gate
Implanted ions

No overlap of gate to diffusion

Significant overlap of polysilicon to gate

diffused

(c)

Figure P2.1-3

Problem 2.1-4 What is the function of silicon nitride in the CMOS fabrication process described in Section 2.1

CMOS Analog Circuit Design (2 nd Ed.) Homework Solutions: 9/21/2002

3

The primary purpose of silicon nitride is to provide a barrier to oxygen so that when deposited and patterned on top of silicon, silicon dioxide does not form below where the silicon nitride exists.

Problem 2.1-5 Give typical thickness for the field oxide (FOX), thin oxide (TOX), n + or p + , p-well, and metal 1 in units of µm. FOX: ~ 1 µm TOX: ~ 0.014 µm for an 0.8 µm process N+/p+: ~ 0.2 µm Well: ~ 1.2 µm Metal 1: ~ 0.5 µm

Problem 2.2-1 Repeat Example 2.2-1 if the applied voltage is -2 V.

N A = 5 × 10 15 /cm 3, N D = 10 20 /cm 3

φ o = kT ln

q

N A N D = 1.381×10 -23 ×300

2

n

i

1.6×10 -19

5×10

(1.45×10 10 ) 2

15

×10 20

ln

= 0.9168

x n =  

2ε

si (φ o v D )N A

qN D (N A + N D )

1/2

x p =  

2ε

si (φ o v D )N D

qN A (N A + N D )

2×11.7×8.854×10 -14 (0.9168 +2.0) 5×10 15

=

1.6×10 -19 ×10 20 ( 5×10 15 + 10 20 )

1/2

= 43.5×10 -12 m

1/2

2×11.7×8.854×10 -14 (0.9168 +2.0) 10 20

=

1.6×10 -19 ×5×10 15 ( 5×10 15 + 10 20 )

1/2

= 0.869 µm

x d = x n x p = 0 + 0.869 µm = 0.869 µm

C j0 =

dQ j

dv D = A 2(N A + N D ) (φ o )

si qN A N D

ε

1/2

C j0 = 1×10 -3 ×1×10 -3

11.7×8.854×10 -14 ×1.6×10 -19 ×5×10 15 ×1×10 20

 

2(5×10 15 +1×10 20 ) (0.917)

1/2

= 21.3 fF

CMOS Analog Circuit Design (2 nd Ed.) Homework Solutions: 9/21/2002

4

C j0 =

C

j0

21.3 fF

1 φ 0

D

v

1/2 =

1

-2

0.917

1/2 = 11.94 fF

Problem 2.2-2 Develop Eq. (2.2-9) using Eqs. (2.2-1), (2.2-7), and (2.2-8).

Eq. 2.2-1

x d = x n x p

Eq. 2.2-7

x n =  

2ε

si (φ o

v D )N A

qN D (N A + N D )

1/2

Eq. 2.2-8

x p = −  

2ε

si (φ o

v D )N D

qN A (N A + N D )

1/2

x d =

2

2ε si (φ o v D )N

A

+

2

D

2ε si (φ o v D )N

qN A N D (N A + N D )

x d = (φ o v D ) 1/2

  qN A N D (N A + N D )

2ε si

2

2

 

N

A

+ N

D

1/2

1/2

Assuming that 2N A N D << (N A + N D ) 2

Then

x d = (φ o v D ) 1/2  

2ε

si (

N A + N D

)

2

qN A N D (N A + N D )

x d = (φ o v D ) 1/2

2ε

si (

N A + N D

)

qN A N D

1/2

1/2

Problem 2.2-3 Redevelop Eqs. (2.2-7) and (2.2-8) if the impurity concentration of a pn junction is given by Fig. 2.2-2 rather than the step junction of Fig. 2.2-1(b).

CMOS Analog Circuit Design (2 nd Ed.) Homework Solutions: 9/21/2002

5

Referring to Figure P2.2-3 N D - N A (cm -3 )
N D
0
x
N D - N A = ax
-N A
ρ(x)
qN D
x p
0
x
x n
-qN A
E(x)
x
E 0
V(x)
φ 0 − v D
x
x d

Figure P2.2-3

Using Poissons equation in one dimension

2 V = - ρ(x)

d

dx

2

ε

ρ(x)= qax ,

2 V = - qax

d

dx

2

ε

when

x p < x < x n

E(x) = - dV = qa

dx

2ε x 2 + C 1

CMOS Analog Circuit Design (2 nd Ed.) Homework Solutions: 9/21/2002

6

then

E(x p ) = E(x n ) = 0

0 =

qa

2ε x

2

p

+ C 1

C 1 =

2

p

- qa

2ε x

E(x) = qa

2ε x 2 qa 2ε x

2

p

=

qa

2ε

x 2 x

p

2

The voltage across the junction is given as

V = −

x

n

x

n

E(x)dx = − qa

x

p

2ε

x

p

x 2 - x

p

2

dx

V

V

V

=

=

=

qa   x

2ε

3

3

2

p x

x

  

x n

x p

qa

2ε

3

n

x

3

3

p

2

x

3

x

p x n

 

 

2

x

p x p

 

3

n

x

qa

2ε

3

x

2

3

p

x

p x n

3 1

1

   

=

3

n

qa

x

2ε

3

2

p

x

Since -x p = x n

V =

3

x p

qa

2ε

3

+

3 2

x p +

3

p

3 x

  =

qa

 

2ε x p

3

1 2

3

3

+

1 +

=

V

=

2qa

3

p

3ε x

x n

+

2

3 x

3

p

qa

2ε x p 3

3

4

CMOS Analog Circuit Design (2 nd Ed.) Homework Solutions: 9/21/2002

7

φ 0 V D = 2qa

3

p

3ε x

3ε

2qa

x p = x n =

1/3

(φ 0 V D ) 1/3

Problem 2.2-4 Plot the normalized reverse current, i RA /i R , versus the reverse voltage v R of a silicon pn diode which has BV = 12 V and n = 6. i RA
1 
 
i R
= 
1 − (v R /BV) n
12
10
8
i
RA /i R
6
4
2
0
0
2
4
6
8
10
12
14

V R

Figure P2.2-4

Problem 2.2-5 What is the breakdown voltage of a pn junction with N A = N D = 10 16 /cm 3 ?

CMOS Analog Circuit Design (2 nd Ed.) Homework Solutions: 9/21/2002

8

BV ε si (N A + N D ) 2qN A N D

E 2

max

BV 11.7×8.854×10 -14 (10 16 + 10 16 ) 2×1.6×10 -19 ×10 16 ×10 16

(3×10 5 ) 2 = 58.27 volts

Problem 2.2-6 What change in v D of a silicon pn diode will cause an increase of 10 (an order of magnitude) in the forward diode current?

i D = I s exp

v D

1 V t

10 i D

I s exp  

V t

D1

v

I s exp

v D

V t

exp  

V t

D1

v

i

10

D

=

I s exp  

V t

D2

v

= exp  

v D1 - v D2

V

t

=

exp

V t

D2

v

V t ln(10) = v D1 - v D2

= exp  

v D1 - v D2

V

t

25.9 mV × 2.303 = 59.6 mV = v D1 - v D2

v D1 - v D2 = 59.6 mV

Problem 2.3-1 Explain in your own words why the magnitude of the threshold voltage in Eq. (2.3-19) increases as the magnitude of the source-bulk voltage increases (The source-bulk pn diode remains reversed biased.)

Considering an n-channel device, as the gate voltage increases relative to the bulk, the region under the gate will begin to invert. What happens near the source? If the source is at the same potential as the bulk, then the region adjacent to the edge of the source inverts as the rest of the bulk region under the gate inverts. However, if the source is at a higher potential than the bulk, then a greater gate voltage is required to overcome the electric field induced by the source. While a portion of the region under the gate still inverts, there is no path of current flow to the source because the gate voltage is not large enough to invert right at the source edge. Once

CMOS Analog Circuit Design (2 nd Ed.) Homework Solutions: 9/21/2002

9

the gate is greater than the source and increasing, then the region adjacent to the source can begin to invert and thus provide a current path into the channel.

Problem 2.3-2 If V SB = 2 V, find the value of V T for the n-channel transistor of Ex. 2.3-1.

2φ F = -0.940 γ = 0.577 V T0 = 0.306 V T = V T0 + γ (
|−2φ F + v SB | −
|−2φ F |)

V T = 0.306 + 0.577 ( |0.940 + 2| −

V T = 0.736 volts |0.940|) = 0.736 volts

Problem 2.3-3 Re-derive Eq. (2.3-27) given that V T is not constant in Eq. (2.3-22) but rather varies linearly with v(y) according to the following equation.

V T = V T0 + a v(y)

<< correction to book

L

v

DS

v

DS

i D dy = Wµ n Q I (y) dv(y) = Wµ n C ox [v GS v(y) V T (y)] dv(y)

0

0

0

V T (y)= V T0 + a v(y)

v DS

i D L = Wµ n C ox [v GS v(y) V T0 a v(y)] dv(y)

0

v DS

i D L = Wµ n C ox

[v GS V T0 v(y) (1 + a)] dv(y)

0

i D L = Wµ n C ox (v GS V T0 )v(y) (1 + a)

v(y) 2

2

v

DS

0

CMOS Analog Circuit Design (2 nd Ed.) Homework Solutions: 9/21/2002

10

i D =

Wµ n C ox

L

(v GS V T0 ) v DS (1 + a)

2

v

DS

2

Problem 2.3-4 If the mobility of an electron is 500 cm 2 /(Vs) and the mobility of a hole is 200 cm 2 /(Vs), compare the performance of an n-channel with a p-channel transistor. In particular, consider the value of the transconductance parameter and speed of the MOS transistor.

Since K’ = µC ox , the transconductance of an n-channel transistor will be 2.5 time greater than the transconductance of a p-channel transistor. Remember that mobility will degrade as a function of terminal conditions so transconductance will degrade as well. The speed of a circuit is determined in a large part by the capacitance at the terminals and the transconductance. When terminal capacitances are equal for an n-channel and p-channel transistor of the same dimensions, the higher transconductance of the n-channel results in a faster circuit.

Problem 2.3-5 Using Ex. 2.3-1 as a starting point, calculate the difference in threshold voltage between two devices whose gate-oxide is different by 5% (i.e., t ox = 210 Å).

φ F (substrate) = −0.0259 ln  

3× 10

16

= −0.377 V