Beruflich Dokumente
Kultur Dokumente
Notice
1.
2.
3.
4.
5.
6.
7.
All information included in this document is current as of the date this document is issued. Such information, however, is
subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please
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Descriptions of circuits, software and other related information in this document are provided only to illustrate the operation of
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P121
PM12
Port mode register 12
0: Output, 1: Input
1
500KHz to 10MHz
Oscillation can be stopped
by the STOP instruction
P
121
500KHz to 10MHz
Oscillation can be stopped
by the STOP instruction.
P122/X2 pin can be used for port functions.
Address: FFF3h
Read/Write
After reset: 02h
P122/X2
Address: FFFBh
Read/Write
After reset: 02h
PM12
Port mode register 12
0: Output, 1: Input
2
P122
Address: 0080h
Read/Write
After reset:
Undefined
P12
Port register 12
P123
PM
123
PCC
1
DEFO DEFO
STS1 STS0
RMCE
Address: FFF4h
Read/Write
After reset:
Undefined
PM12
Port mode register 12
0: Output, 1: Input
3
P
123
0
0
1
1
Option byte
VDD
LVI
ON
Selector
LSR
STOP
LVI
MD
LVI
F
CALLT23
CALLT22
CALLT21
CALLT20
CALLT19
CALLT18
CALLT17
CALLT16
Package code :
Thickness :
Nominal dimensions :
Terminal width :
CALLT13
CALLT10
CALLT9
CALLT8
Outline dimension
8-bit timer H
INTTMH1
CALLT1
Reserved
PSW
Program status word
13
12
AC
CY
11
10
Selector
INTP2
PRM001
PRM000
P31
P31
fxp/4
fxp/256
Read
After reset : 0000h
15
IF1
Interrupt request
flag register 1
P
30
P3
Port register 3
12
11
14
13
12
11
14
12
11
Address: FF60h
Read/write
After reset : 00h
P30
TM00
16-bit timer
/event
counter 00
P40
P41/INTP3
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
INTTM000
signal
3
Address: FF63h
Read/write
After reset : 00h
7
0
TMC00
16-bit timer mode
control register 00
No change
No change
<A>
<B>
<A>
<B>
Interrupt
request generation
Not generated
Not generated
Generated on <A>
Generated on <A>
Generated on <A>
Generated on <A>
Generated on <A>
Generated on <A>
CRC00
Capture/compare control
register 00
P41
7
ES
110
6
ES
100
TOC00
16-bit timer output
control register00
Address: FF61h
Read/write
After reset : 00h
5
ES
010
4
ES
000
P21
TMC80
8-bit timer mode control
register 80
Clock selection
[0:0] fxp/64
[0:1] fxp/256
[1:0] fxp/1024
[1:1] fxp/65536
0
0
1
1
0
1
0
1
ANI2
HALT mode
(CPU operation is
stopped.
The oscillation of the
system clock
continues.)
STOP mode
(CPU operation is
stopped.
The oscillation of the
system clock is
also stopped.)
I/O port
16-bit timer
8-bit timer 80
A/D converter
UART6
CPU
8-bit timer H1
Note 1
WDT(Watchdog)
Note 2
Note 2
ES
31
ES
30
ES
21
ES
20
ES
11
ES
10
ES
01
ES
00
1
0
PRM PRM
001 000
7
1
PRM00
Prescaler Mode Register 00
PPG (Programmable
Pulse Generator)
Function
This function outputs
pulses by setting CR000
as the cycle value and
CR010 as the duty value.
ANI3
14
13
P
22
PU2 VDD
Pull-up resistor option
register 2
When the P23 pin is 3
used as an input
PU
port, an on-chip
23
pull-up resistor can
connected.
P-Ch
PMC2
Port mode control
Register 2
0: Port, 1: A/D input
PMC
23
P23
PM2
Port mode register 2
0: Output, 1: Input
3
P23
3
PM
23
P
23
P2
Port resistor 2
INTP3
INTP2
TM80
A/D
SRE TMIF
PIF3 PIF2
IF6
80
TMH1
P13
Port register 13
Address: FFECh
Read/Write
After reset: 00h
INTM0
External interrupt
mode register 0
LVI
PU4 VDD
Pull-up resistor option
Register 4
5
ST
SR SRE TMMK
PMK3 PMK2
MK6 MK6 MK6 80
Address: FFE0h
Read/Write
After reset: 00h
AD TMMKTMMKTMMK
LVI
PMK1 PMK0
MK 010 000 H1
MK
P
130
INTP1
16-bit
timer
0
P130
Address: FFE4h
Read/Write
After reset: FFh
IF0
Interrupt request
flag register0
PU
45
P-Ch
P45
PM4
Port mode register 4
0: Output, 1: Input
5
MK0
Interrupt mask
flag register 0
P45
5
PM
45
P
45
P4
Port register 4
7 6 5 4 3 2 1
Interruption priority
PU4
Pull-up resistor option
Register 4
4
0
RxD6
Reception
6
Error occurrence
INTSRE6 signal
PS
60
CL
6
P44
SL ISRM
6
6
VDD
PU
44
PM4
Port mode register 4
0: Output, 1: Input
4
Error
detector
P-Ch
P44
Reception completion
4
PM
44
P
44
P4
Port register 4
PE
FE OVE
0
0
0
0
0
6
6
6
In case of error
0: INTSRE6 occurs.
1: Parity error
[0:0] Parity bit
Reading
this
1: INTSR6 occurs.
1: Framing error
not output.
register clears
1: Enable transmission
0: Number of stop bits = 1, 1: 2
[0:1] 0 parity.
1: Overrun error
bits to 0.
1: Enable reception [1:0] Odd parity. 0: Character length of data = 7 bits, 1: 8 bits
[1:1] Even parity.
TXS6 Transmit shift register 6
7
6
5
4
3
2
1
0
Transmission completion
1: Enable operation
LIN (Local
Interconnect Network)
The UART6 supports
the LIN bus, which is
mainly used for
automotive networks.
In LIN reception,
wakeup signals are
detected by an
external interrupt
(INTP0), and the SF
length is measured by
a 16-bit timer (TM00).
However this interrupt
and timer do not have
to be connected
externally because of
internal switching
by the ISC register.
Continuous
Transmission
Function
Transmission can be
continued without
disruption even during
an interrupt period, by
writing the next data to
the TXB6 register after
data has been shifted
from the TXB6 register
to the TXS6 register.
SBF length
1: transmission trigger
1: SBF reception trigger
4
0
1
0
DIR TXDLV
6
6
Transmission
INTP1
TxD6
ASIF6 ASI transmission status register 6
Address: FF95h , Read/Write, After reset: 00h
3
2
1
0
TPS TPS TPS TPS
63
62
61
60
When the 43
pin is used as
an input port,
an on-chip pullup resistor can
connected.
VDD
3
PU
43
P-Ch
P43
1
0
TXBF TXSF
6
6
PM4
Port mode register 4
0: Output, 1: Input
3
3
PM
43
12
P
43
P4
Port register 4
fxp/2L.
ISC
1
ISC
0
PU4
Pull-up resistor option
Register 4
0
CMP01
8-bit timer H
compare register 01
INTTMH1 signal
Match
fxp
fxp/16
fxp/64
Match
Address: FF0Fh
Read/Write
After reset: 00h
fxp/4096
fRL/128
TMH1
8-bit timer
counter H1
TMHMD1
8-bit timer H mode register 1
0
0
1
1
0
0
0
1
0
1
0
1
fxp
0: Timer output level is low level. 1: High level.
fxp/4
fxp/16 00: Interval timer mode
fxp/64 10: PWM output mode
fxp/4096 Count clock selection
fRL/128 (A setting other than a table is prohibition.)
VDD
2
PU
42
P-Ch
P42
PM4
Port mode register 4
0: Output, 1: Input
2
Output
controller
CMP11
8-bit timer H
compare register 11
7
6
5
4
3
2
1
0
Address: FF70h
TMHE CKS CKS CKS TM TM TO TO
Read/Write
1
12
11
10 MD11 MD10 LEV1 EN1
After reset: 00h
PWM (Pulse Wise
Modulator) Function
This function outputs
pulses by setting
CMP01 as the cycle
value and CMP11 as
the duty value.
PU4
Pull-up resistor option
Register 4
P43
fxp/4
One-shot Pulse Function
When a trigger is input,
this function outputs an
inactive level until the
level reaches the value of
compare register 1
(CR010). After that, this
function outputs an active
level until the level
reaches the value of
compare register 0
(CR000). Finally, this
function outputs an
inactive level again.
PM
22
P2
Port resistor 2
WDTM
WDT mode register
Notes 1.
Operable when the low-speed RingOSC clock is selected.
Notes 2.
Operable when the low-speed RingOSC stoppage is disabled by the
option byte.
Operable when the low-speed RingOSC stoppage is enabled by the
option byte.
PM2
Port mode register 2
0: Output, 1: Input
2
15
P-Ch
P22
WDTE
WDT enable register
SR
IF6
PU2
VDD
Pull-up resistor option
register 2
When the P22 pin is 2
used as an input
PU
port, an on-chip
22
pull-up resistor can
connected.
PMC2
Port mode control
PMC
Register 2
22
0: Port, 1: A/D input
16
P
21
ST
IF6
PM
21
P2
Port resistor 2
TCL TCL
801 800
17
PM2
Port mode register 2
0: Output, 1: Input
1
WD WD WD WD WD
CS4 CS3 CS2 CS1 CS0
Interruption to CPU
INTST6 signal
TO00 inversion
timing selection
13 12 11 10 9 8
18
P21
TM00
16-bit timer
Counter 00
<A> Match between TM00 and CR000 or match between TM00 and CR010
<B> Match between TM00 and CR000, match between TM00 and CR010, or TI000 pin valid edge
Address: FF62h
Read/write
After reset : 00h
Address: FFE5h
Read/Write
After reset: FFh
INTTM010
signal
0
1
0
1
0
1
0
1
PMC2
PMC
Port mode control
21
Register 2
0: Port, 1: A/D input
Compare
(FF16h)
P-Ch
TM80
8-bit timer counter 80
INTSR6 signal
Match
6
Selection of
operation mode and
clear mode
P30
PM4
Port mode register 4
0: output, 1: input:
1
P
41
P4
Port register 4
(FF12h)
10
UART6 - Asynchronous
serial I/F(ASI)
Match
In the case of
a compare
8
7
6
Address: FFE1h
Read/Write
After reset: 00h
CR000
16-bit timer capture/
compare register 000
3
2
1
0
CR010
16-bit timer capture/
compare register 010
INTP0
PU4
Pull-up resistor option
register 4
When the P41
1
pin is used as
Address: FFEDh
Read/Write
After reset: 00h
(FF14h)
10
ANI1
P42
P
42
P4
Port register 4
2
PM
42
11
P42/TOH1
PM
41
In the case of
a compare
13
Output
controller
P41
1
10
(FF17h)
P4
Port register 4
P-Ch
(FF13h)
PM4
Port mode register 4
0: output, 1: input:
0
an input port,
an on-chip pullup resistor can
connected.
In the case of
a capture
P40
PU
41
Read/write
After reset : 0000h
PU4
Pull-up resistor option
register 4
0
When the P40
pin is used as
PU
an input port,
40
an on-chip pullup resistor can
connected.
P
40
10
In the case of
a capture
15
PM3
Port mode register 3
0: output, 1: input:
0
13
System clock
Interrupt Control
MK1
Interrupt mask
flag register 1
0800h
07FFh
(FF15h)
P3
Port register 3
PU3
Pull-up resistor option
register 3
When the P30
0
pin is used as
PU
an input port,
30
an on-chip pullup resistor can
connected.
14
Selector
P31/TI010/TO00/INTP2
15
PU2
VDD
Pull-up resistor option
register 2
When the P21 pin is 1
used as an input
PU
port, an on-chip
21
pull-up resistor can
connected.
P43/TxD6/INTP1
P30/TI000/INTP0
CRC001
0
1
0
1
0
1
0
1
(0: No interrupt requests are generated. 1: An interrupt request is generated, and the request is being made.)
Read/write
After reset : 0000h
P
31
INTM1
External interrupt
mode register 1
1000h
0FFFh
0000h
PM3
Port mode register 3
0: output, 1: input:
1
10
6.650.15
Use prohibited
Use prohibited
Program Counter
PU3
Pull-up resistor option
register 3
When the P31
1
pin is used as
PU
an input port,
31
an on-chip pullup resistor can
connected.
UART6
Interrupt enabled
Carry flag
0: Interrupt disabled (DI)
0: Non-existent
1: Interrupt enabled (EI)
1: Existent
Zero flag
0: Used to be a value other than 0 Auxiliary carry flag (carry from bit 3)
0: Non-existent
1: Used to be 0
1: Existent
14
8.10.2
FE00h
IE
SP Stack pointer
15
6.10.2
Reset input
FE80h
Conversion time
selection
0
0
1
1
0
0
1
1
External interrupt
Memory Space
64-KB
Address Space
FFFFh
ADM
A/D converter mode register
CR80
8-bit compare register 80
Address: FF48h
Read/Write
After reset: 67h
11
A
10
LVI(Low-voltage detector)
11
ADCE
: Operable
: Operation stops.
MC-5A4
1.2mm
7.62mm(300)
0.65mm
16-bit timer
INTTM010
FF00h
INTP0 signal
19
P
20
P2
Port resistor 2
INTLVI signal
FR
0
INTP1 signal
FR
1
INTTMH1 signal
FR
2
INTTM000 signal
X
12
10
INTAD signal
13
INTTM010 signal
11
INTP2 signal
PM
20
Standby Function
INTP3 signal
Reserved
Sample
&
hold
circuit
P20
INTTM80 signal
E
3
12
WDT Watchdog
Timer
INTSRE6 signal
13
0.65
CALLT0
A/D Converter
INTAD
Reserved
ADS ADS
1
0
P22
INTST6 signal
WDT
16-bit counter
INTSR6 signal
Address: FF49h
Read/Write
After reset: 9Ah
20
UART6 transmission
completion INTST6
Low-volt-age detection
INTLVI
D
7
General-purpose registers
(When two of them are connected,
the connected registers can be
used as a 16-bit register.)
PM2
Port mode register 2
0: Output, 1: Input
0
INTP0
INTP1
14
CALLT2
External interrupt 2
INTP2
External interrupt 0
INTP0
INTP2
14
INTP3
External interrupt 3
INTP3
External interrupt 1
INTP1
Processor Registers
15
CALLT3
Program area
16-bit timer
INTTM000
CALLT24
8-bit timer 80
INTTM80
ADCS
Package information
Option
byte
CALLT25
P-Ch
P20
PD78F9221 PD78F9222
CALLT26
UART6 reception
completion INTSR6
20
0
PMC2
PMC
Port mode control
20
Register 2
0: Port, 1: A/D input
Generating a voltage
to be compared.
78K0S/KA1+
Protect
byte
CALLT4
LSB
CALLT27
CALLT5
7
Address: FFCCh
TCE
Read/Write
80
After reset: 00h
TCL801,
TCL800
One-page Manual
CALLT28
CALLT6
Address: FFCEh
Read
After reset: 00h
CALLT29
CALLT7
fxp/65536
CALLT14
fxp/1024
15
CALLT30
CALLT15
Match
ANI0
VSS
(FF18h)
fxp/256
CALLT31
VDD
Address: FFCDh
Write
After reset: Undefined
INTLVI signal
D/A
converter
fxp/64
Program area
000xh
PM
40
INTTM80 signal
7
6
5
4
3
2
1
0
Reset Source
(1) External reset input via RESET pin
WDT
LVI
0
0
0
0
0
0
(2) Internal reset by WDT (watchdog timer) program loop detection
RF
RF
(3) Internal reset by comparison of supply voltage and detection
voltage of POC (power-on-clear circuit)
1: WDT (Watchdog timer) reset
1: LVI (Low-voltage detection)
(4) Internal reset by comparison of supply voltage and detection
reset
voltage of LVI (low-voltage detector)
Reading this register clears bits to 0.
008xh
007xh
006xh
005xh
004xh
003xh
002xh
001xh
WDT(watchdog timer)
8-bit timer H1
Controls of Reset
P34
P-Ch
fRL
0
RING
Option byte OSC
Reset
VDD
9
MSB
0: Stops conversion
operation
1: Enable
0
0
0
0
1
The sampling time is included in
1
the conversion time in the table.
1
1
POC detection
2.10.1V
potential
2V
fCPU
1: Low-voltage is detected
The operation for low
(This bit is read-only)
voltage detection
0: Interrupt (INTLVI) generation
1: Reset generation
6 3.10.15V
8 2.60.15V
PM
30
10
CPU clock
0: Disables operation
1: Enables operation
9 2.350.15V
11
fxp
7 2.850.15V
P-Ch
12
7
1 4.10.2V
3V
VDD
13
0
1
0
1
5 3.30.15V
14
Address: FF80h
Read/Write
After reset: 00h
POC/LVI Power-on-clear/Low-voltage
LVIM Low voltage detect register
detection
Address: FF50h, Read/Write, After reset: 00H
PM
31
15
Address: FF81h
Read/Write
After reset: 00h
Processor
Clock
Control
(PCC)
1/4
0
0
1
1
210 clock
212 clock
215 clock
217 clock
4 3.50.2V
Voltage comparator
INTAD signal
Selector PCC
3 3.70.2V
P-Ch
Successive approximation
register(SAR)
PPCC
Ring-OSC
2 3.90.2V
VDD
(FF19h)
1/4
1/1
P34/RESET pin
0: Used as P34,
1: Used as RESET pin
4V
1/2
Selector
0 4.30.2V
P34/RESET
1/1
PCC
PCC register
0
1
0
1
P123
5V
RMCE
fx
The oscillation stabilization time that elapses after the STOP mode
P12
Port register 12
Option byte
(FF1Ah)
System clock
Low-speed Ring-OSC
0: A stop by the program is possible.
1: A stop is impossible.
210 clock
212 clock
215 clock
217 clock
PU
123
P-Ch
PU12
Pull-up resistor option
register 12
3
0: 1/1, 1: 1/4
P
122
VDD
Selector
PPCC
Pre-PCC register
PPCC PPCC
1
0
[0:0] 1/1
[0:1] 1/2
[1:0] 1/4
P122
fRH
X2
8MHz(typ.)
Oscillation can be stopped
by the STOP instruction.
P122/X2 pin can be used for port functions.
P121
P12
Port register 12
PM
122
X2
Can be used
for port functions.
7
MSB
Selector
1
PM
121
X2
Can be used
for port functions.
Oscillation/Stop setting of
High-Speed Ring-OSC
When the high-speed
Ring-OSC clock is not
selected with the option
byte, the clock
automatically stops
oscillation to reduce
power consumption.
Selector
X2
X1
Can be used
for port functions.
Selector
P121/X1
X1
X1
External
clock
PU2
VDD
Pull-up resistor option
register 2
When the P20 pin is 0
used as an input
PU
port, an on-chip
20
pull-up resistor can
connected.
P44/RxD6
X1
10-bit/8-bit mode
A/D Conversion Result
This A/D converter
generates a binary result
and stores the results in the
following two registers.
ADCRH: 8-bit A/D result
ADCR: 10-bit A/D result
P45
fRH
P130
Ring-OSC
P23/ANI3
Vss
P22/ANI2
Vss
P21/ANI1
Vss
High-speed Ring-OSC
(typ 8MHz)
P20/ANI0
AVREF
VSS