Beruflich Dokumente
Kultur Dokumente
.HITACHI
INDEX
5
7
12
20
23
29
DATA SHEETS__________________________________________________________________________________________________________________________________________________________
8-bit Microcomputer HM CS6800 Single-chip Series ____________________________________________________________________________________
HD6801S0
Microcomputer Unit ________________________________________________________________________________________________________________
HD6801 S5
Microcomputer Unit ________________________________________________________________________________________________________________
HD680 1VO
Microcomputer Unit __________________________________________________________________________________ ,_____________________________
HD680 1V5
Microcomputer Unit __________________________________________________________________________________1_________________________ _____
HD6803
Micro Processing Unit ____________________________________________________________________________________________________________
HD6803-1
Micro Processing Unit ____________________________________________________________________________________________________________
HD6805S 1
Microcomputer Unit ________________________________________________________________________________________________________________
HD6805Ul
Microcomputer Unit ________________________________________________________________________________________________________________
HD6805Vl
Microcomputer Unit ________________________________________________________________________________________________________________
HD6805WO
Microcomputer Unit ________________________________________________________________________________________________________________
HD6805XO
Microcomputer Unit ________________________________________________________________________________________________________________
HD630 1VO (CMOS)
Microcomputer Unit ________________________________________________________________________________________________
HD63AO 1VO (CMOS) Microcomputer Unit ________________________________________________________________________________________________
HD63 BO 1VO (CMOS) Microcomputer Unit ________________________________________________________________________________________________
Micro Processing Unit ____________________________________________________________________________________________
HD6303 (CM OS)
HD63A03 (CMOS)
Micro Processing Unit ____________________________________________________________________________________________
HD63B03 (CMOS)
Micro Processing Unit ____________________________________________________________________________________________
Microcomputer Unit ________________________________________________________________________________________________
HD63 L05 (CMOS)
HD68POIS0
Microcomputer Unit ________________________________________________________________________________________________________________
HD68POIV05 Microcomputer Unit ________________________________________________________________________________________________________________
HD68PO 1V07 Microcomputer Unit ________________________________________________________________________________________________________________
HD68P05V05 Microcomputer Unit ________________________________________________________________________________________________________________
HD68P05V07 Microcomputer Unit ________________________________________________________________________________________________________________
8,-bit Microcomputer HMCS6800 Multi-chip Series __________________________________________________________________________________
HD6800
Micro Processing Unit ____________________________________________________________________________________________________________
HD68AOO
Micro Processing Unit ____________________________________________________________________________________________________________
HD68BOO
Micro Processing Unit ____________________________________________________________________________________________________________
HD6802
Microprocessor with Clock and RAM ______________________________________________________________________________
HD6802W
Microprocessor with Clock and RAM ______________________________________________________________________________
HD6809
Micro Processing Unit ____________________________________________________________________________________________________________
HD68A09
Micro Processing Unit ____________________________________________________________________________________________________________
HD68B09
Micro Processing Unit ____________________________________________________________________________________________________________
HD6809E
Micro Processing Unit ____________________________________________________________________________________________________________
HD68A09E
Micro Processing Unit ____________________________________________________________________________________________________________
HD68B09E
Micro Processing Unit ____________________________________________________________________________________________________________
HD6821
Peripheral Interface Adapter ________________________________________________________________________________________________
HD68A21
Peripheral Interface Adapter ________________________________________________________________________________________________
HD68B21
Peripheral Interface Adapter ________________________________________________________________________________________________
HD6840
Programmable Timer Module ______________________________________________________________________________________________
HD68A40
Programmable Timer Module ______________________________________________________________________________________________
HD68B40
Programmable Timer Module ______________________________________________________________________________________________
HD6843
Floppy Disk Controller __________________________________________________________________________________________________________
HD68A43
Floppy Disk Controller __________________________________________________________________________________________________________
31
31
33
33
67
67
101
101
128
148
169
190
218
220
220
220
247
247
247
249
276
276
276
313
313
335
337
337
337
368
380
392
392
392
423
423
423
455
455
455
472
472
472
486
486
HD6844
Direct Memory Access Controller ......................................................................................
HD68A44
Direct Memory Access Controller ......................................................................................
HD68B44
Direct Memory Access Controller ......................................................................................
HD6845S
CR T Controller ........................................................................................................................
HD68A45S
CR T Controller ........................................................................................................................
HD68B45S
CR T Controller ........................................................................................................................
HD6846
Combination ROM 110 Timer ............................................................................................
HD6850
Asynchronous Communication Interface Adapter ........................................................
HD68A50
Asynchronous Communication Interface Adapter ........................................................
HD6852
Synchronous Serial Data Adapter ......................................................................................
HD68A52
Synchronous Serial Data Adapter ......................................................................................
HD46508
Analog Data Acquisition Unit.. ............................................................................................
HD46508-1
Analog Data Acquisition Unit ..............................................................................................
HD46508A
Analog Data Acquisition Unit.. ............................................................................................
HD46508A -1
Analog Data Acquisition Unit.. ............................................................................................
HD146818 (CMOS)
Real Time Clock Plus RAM ................................................................................
Peripheral Interface Adapter ................................................................................
HD6321 (CMOS)
Peripheral Interface Adapter ................................................................................
HD63A21 (CMOS)
HD63B21 (CMOS)
Peripheral Interface Adapter ................................................................................
HD6340 (CMOS)
Programmable Timer Module ..............................................................................
Programmable Timer Module ..............................................................................
HD63A40 (CMOS)
Programmable Timer Module ..............................................................................
HD63B40 (CMOS)
HD6350 (CMOS)
Asynchronous Communication Interface Adapter ........................................
Asynchronous Communication Interface Adapter ........................................
HD63A50 (CMOS)
Asynchronous Communication Interface Adapter ........................................
HD63B50 (CMOS)
16-bit Microcomputer HMCS68000 Multi-chip Series ..............................................................................
HD68000-4
Micro Processing Unit ............................................................................................................
HD68000-6
Micro Processing Unit ............................................................................................................
HD68000-8
Micro Processing Unit ............................................................................................................
HD68000-10
Micro Processing Unit ............................................................................................................
HD68450
Direct Memory Access Controller ......................................................................................
513
513
513
546
546
546
585
606
606
616
616
630
630
630
630
649
665
665
665
666
666
666
667
667
667
669
671
671
671
671
752
NOTICE
The example of an applied circuit or combination with other equipment shown
herein indicates characteristics and performance of a semiconductor-applied
products. The Company shall assume no responsibility for any problem involving a
patent caused when applying the descriptions in the example.
GENERAL
INFORMATION
Type and Package Information
Reliability and Quality Assurance
Design Procedure and Support
Tools for 8-bit Single-chip
Microcomputer
HMCS6800 Family Instruction Set
.8-bit Microcomputers for Industrial
Application
Plastic Mold
HD68XX~
HD68XX
HD68XX.f
" No indication
Clip Division
Type No.
Package *
PinNo.
40
HD6801 SO
HD6801S5
HD6801VO
HD6803
HD6803-1
HD6805S1
HD6805Vl
HD6805WO
HD6805XO
HD6301VO
40
HD63B01VO
40
HD6303
HD63A03
40
40
HD6801V5
HD6805Ul
8-bit Single-chip
Function
HD63A01VO
HD63B03
HD6333
HD63A33
HD63B33
HD63L05
HD68P01SO
HD68P01V05
HD68P05V05
HD68P05V07
HD68P01V07
40
Microcomputer Unit
40
40
40
40
28
40
40
Microcomputer Unit
40
64
40
40
40
40
60
40**
40**
Microcomputer Unit
40**
40**
40**
* The package codes of C, P, and F are applied to the package materials as follows.
C: Side-brazed Ceramic DIP, P: Plastic DIP, F: Flat Package.
*. EPROM on the package.
40
(to be continued)
Chip Division
Type No.
HD6800
HD468AOO
HD68BOO
HD468BOO
HD6802
HD46802
HD6802W
HD6809
40
40
40
40
40
40
40
HD68A09E
40
HD68B09E
40
HD6821
HD46821
HD68A21
HD468A21
HD68B21
HD468B21
HD6840
HD68A40
HD68B40
HD6843
HD46503S
HD68A43
HD46503S-1
HD6844
HD46504
HD68A44
HD46504-1
HD68B44
HD6845S
HD46504-2
HD46505S
40
40
40
Peripheral Interface Adapter
40
40
28
28
28
40
40
40
40
40
40
HD68A45S
HD46505S-1
CRT Controller
40
HD68B45S
HD6846
HD46505S-2
HD46846
40
24
HD6850
HD46850
HD68A50
HD468A50
HD6852
HD46852
HD68A52
HD468A52
HD46508
HD46508-1
HD146818
HD68000-4
HD68000-6
HD68000-10
HD68450
HD46508A
HD46508A-1
16-bit Multichip
Package*
Pin No.
HD6809E
HD68B09
8-bit Multi-chip
HD46800D
HD68AOO
HD68A09
Function
HD68000-8
40
24
24
24
40
40
40
40
24
64
64
64
64
* The package codes of C, P, and F are applied to the package materials as follows.
C; Side-brazed Ceramic DIP, P; Plastic DIP, F: Flat Package.
64
DC-24
N
W
o.oo.
DC-40
DC-28
o
19
o. oo ...
I.tr""--~:;---,
DC-64
2
3
4
5
6
7
9
10
II
12
10
14
15
16
17
II
19
20
21
22
23
24
25
26
27
2'
29
30
31
32 'l---,--~~
22.56
Applicable LSIs
DC-24
DC-28
DC-40
HD6801SOC, HD6803C, HD6800, HD68AOO, HD68BOO, HD6802, HD6809, HD68A09, HD68B09, HD6809E,
HD68A09E, HD68B09E, HD6821, HD68A21, HD68B21, HD6843, HD68A43, HD6844, HD68A44, HD68B44,
HD6845S, HD68A45S, HD68B45, HD6846
DC-40P
DC-64
DP-24
:
R
DP-28
1.1.4
'S 24
.
2.S4mln
a-IS'
_o20-038
DP-40
2.54min
5.06max
I--"""'J---'
OP-64
~
~
~
~
:~
'2
'l
'4
'5
I ~:l
~:~
~~
> ~~
56
53
52
5.
50
:t
::
20
45
..
.9
2.
~L~~
r-24
25
26
27
21
29
30
3.
47
46
..
:~
4.
40
39
31
37
36
35
34
321!=",=====""""""",~33--'L
Applicable LSls
DP24
0.20-0.36
0'-'5'
DP28
DP-40
DP64
HD6805XOP
10
Flat Package
'-i
Applicable LSI
FP-60A
Marking
There are two kinds of marking. One has a new ordering
No. (Case I) and the other has both new and old ordering No.
(Case II). They are listed on the List of 8/16-bit Microcomputer LSI Package. Case I is applied to the LSI which has
HD63l05
only new ordering No. listed in the List of 8/16-bit Microcomputer LSI Package and Case II is applied to the LSI
which has both Ordering No.
I. 'mOB
.~~~
(d)
'. mOB
(e)
B D~BBOBSB
(d)
(c)
D~B~r5J
B DB8~BSB
11
Hitachi mark
(b)
lot Code
(e)
(d)
Japan mark
(e)
(f)
ROM Code
proved, recently their applications have been expanded to automobiles measuring and control systems, and computer terminal
equipment operated under relatively severe conditions.
ActuaUy, field application data has revealed that their failure
rates in a commercial environment are equivalent to those
of the hermetic sealed type.
However, in a view of reliability guarantee, the hermetic
sealed type passes a leak test 100%. Due to poor screening
technology, the plastic type may exhibit moisture absorption or
permeation inherent to their plastic materials.
Therefore, Hitachi recommends users employ the hermetic
sealed type for certain systems which require hjgh durability
against severe conditions, long service life and high reliability.
On the other hand, production output and application of
plastic molded type continue to increase.
To meet such requirements, Hitachi has considerably improved moisture resistance, operation stability, and chip and
plastic manufacturing process.
Plastic and side-braze package type structure are shown in
Figure 1 and Table 1.
2.1 Package
Packages are generally classified into 2 types; one is the
hermetic sealed type using metal or glass and the other is the
plastic molded type. Hitachi 8-bit microcomputer are produced
in plastic package or side-braze package.
Selection of package type should be done considering the
application, environment, reliability, cost and other factors of
the system.
The reliability of plastic molded type has been greatly im-
(21 Plastic
(11 Side-braze
Bonding wire
Side-braze
Item
Package
Alumina
epoxy
Lead
Seal
AuSn Alloy
N.A
Die bond
Au-Si
Au-Si
Wire bond
Ultrasonic
Thermo compression
Wire
AI
Au
12
Drain
Source
FET1
Drain
SiGate CMOS
SiO,
Source
Drain
Source
FET2
FET2
P-channel
EMOS
N-channel
DMOS
N-channel
EMOS
N-channel
EMOS
Test Condition
125C,1000hr
1005,2
1008,1
Temperature Cycling
Temperature Cycling
Thermal Shock
Soldering Heat
Mechanical Shock
Vibration Fatigue
Valiable Frequency
Constant Acceleration
Lead Integrity
1010,4
13
1011,3
2002,2
2005,1
2007,1
2001,2
2004,3
Device
----
Sample Size
Component Hour
Failure
H06800
H06802
H06809
H06801
H06803
H06805
248
452
85
146
45
114
248000
153712
85000
146000
45000
114000
0
1
0
0
0
0
H06821
H06850
HD6852
H06846
399
158
170
69
266368
158000
125816
69000
1
0
0
0
H~~
00
~~
80
88
64
140
69000
55000
64000
140000
0
0
0
0
2324
1793896
H06844
H06845S
H06840
H046508
--------------------------------------------------------------------Peripheral Total
1234
1002184
- - -- - - - - - - - - - - -- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -- --
-- - - - - - - - - - - - - - -- - Total
temperature-humidity bias test, 8S C/8S% RH biased condition. The result of this test is shown in Table 4.
Device
Sample Size
Component Hore
Failure
MPU
Peripheral
132
226
132000
204000
0
0
--------------------------------------------------------------------------Total
358
336000
0
3.2.3 Storage Life Test
These tests evaluate the effect of storage at high temperature, low temperature or high humidity without bias.
(I) Plastic Package
Test Items
High Temp, High Humidity
High Temp, High Humidity
Presser Cooker
High Temp, Storage
Low Temp, Storage
Condition
Sample Size
65C/95%RH, 1000hrs
80C/90%RH,1000hrs
2atm 121C, 100hrs
Ta = 150C, 1000hrs
Ta = -55C, 1000hrs
14
288
88
266
85
34
Failure
o
o
o
o
o
Test Items
High Temp, High Humidity
High Temp, Storage
Low Temp, Storage
Sample Size
65C/95%RH, 1000hrs
Ta = 150C, 1000hrs
Ta = -55C, 1000hrs
Failure
o
o
o
90
313
86
Side-braze
Test Item
Condition
Temperature Cycling
4159
4920
Thermal Shock
826
110
1
0
359
175
0
0
260C, 10sec
1500G 0.5 ms
3 times/X, Y, Z
60Hz,20G
32hrs/X, Y, Z
20 ,.., 2000Hz 20G
4 min/X, Y, Z
Bending Tention Fatigue
180
110
0
0
117
189
0
0
110
167
110
167
102 pins
Soldering Heat
Mechanical Shock
Vibration Fatigue
Vibration Variable Freq.
Lead Integrity
Sample Size
Failure
65 pins
Sample Size
Failure
Condition
Sample Size
Failures
30
20
0
0
Ta = 295C, 1000hrs
15
20
105
45
22
22
22
22
22
22
0
0
0
0
0
0
0
0
Process
Flow
Wafer process
Probe test
Dicing/Break
Chip visual
Die bonding
Patroll inspection
once/day/machine visual
Wire bonding
once/day/machine visul1l
once/week/machine bond dimension
bond strength
Internal visual
Molding
Temperature cycling
Lead trim & form
Solder dipping
External visual
Mark
Burn-in
Electrical test
External visual
Lot acceptance
Warehouse
Test/Inspection process
Production process
QC and QA operation
16
Flow
Process
Wafer process
Probe test
Dicing/Break
Chip visual
Die bonding
Wire bonding
Patrol inspection
once/day/machine visual
once/week/machine
bond dimention
bond strength
Internal visual
Seal
Temperature cycling
Leak test
Plating
Lead cutting
External visual
Mark
Burn-in
Electrical test
External visual
Lot acceptance
Warehouse
8o
Figure 4 Quality Plan in Side-braze Package Process
17
Test/Inspection process
Production process
QC and QA operation
(1) Use containers or jigs which will not induce static electric-
Figure 5
6. PRECAUTION
6.1 Storage
It is preferable to store semiconductor devices in the following ways to prevent detrioration in their electrical characteristics, solderability, and appearance, or breakage.
(1) Store in an ambient temperature of 5 to 30C, and in a
relative humidity of 40 to 60%.
(2) Store in a clean air environment, free from dust and active
gas.
(3) Store in a container which does not induce static electricity.
(4) Store without any physical load.
(5) If semiconductor devices are stored for a long time, store
them in the unfabricated form. If their lead wires are
formed beforehand, bent parts may corrode during storage.
(6) If the chips are unsealed, store them in a cool, dry, dark,
and dustless place. Assemble them within 5 days after unpacking. Storage in nitrogen gas is desirable. They can be
stored for 20 days or less in dry nitrogen gas with a dew
point at -30C or lower. Unpacked devices must not be
stored for over 3 months.
(7) Take care not to allow condensation during storage due to
rapid temperature changes.
Avoid static electricity, noise and surge-voltage when semiconductor devices are measured. It is possible to prevent breakage by shorting their terminal circuits to equalize electrical
potential during transportation. However, when the devices are
to be measured or mounted, their terminals are left open to
provide the possibility that they may be accidentally touched
by a worker, measuring instrument, work bench, soldering iron,
belt conveyor, etc. The device will fail if it touches something
which leaks current or has a static charge. Take care not to
allow curve tracers, synchroscopes, pulse generators, D.C.
stabilizing power supply units etc. to leak current through their
terminals or housings.
Especially, while the devices are being tested, take care not
to apply surge voltage from the tester, to attach a clamping
circuit to the tester, or not to apply any abnornal voltage
through a bad contact from a current source.
During measurement, avoid miswiring and short-circuiting.
When inspecting a printed circuit board, make sure that no
soldering bridge or foreign matter exists before turning on the
power switch.
Since these precautions depend upon the types of semiconductor devices, contact Hitachi for further details.
6.4 Soldering
Semiconductor devices should not be left at high temperatures for a long time. Regardless of the soldering method,
soldering must be done in a short time and at the lowest possible temperature. Soldering work must meet soldering heat test
conditions, namely, 260C for 10 seconds and 350C for 3
seconds at a point I to 1.5 mm away from the end of the device
package.
Use of a strong alkali or acid flux may corrode the leads,
deteriorating device characteristics. The recommended soldering.
iron is the type that is operated with a secondary voltage supplied by a transformer and grounded to protect from lead
current. Solder the leads at the farthest point from the device
package.
6.2 Transportation
18
19
Cross Assembler
Evaluation Kit
H68SD5
Intel MDS
IBM370
No
-- ------- ---
------~
Evaluation Kit
Evaluation Board
H68SD5
EPROM on the Package
H D68POl SO
HD68P01V05
HD68P01V07
[ HD68P05V05
HD68P05V07
(Explanation)
CD When the user programs the system, the predetermined functions are
assigned to the I/O pin and the RAM before the programming.
@A flow chart is designed to achieve the predetermined functions and the flow
chart is coded by using the prenumeric code_
@ The coded flow chart is punched into the card or the paper tape or written
into
The company provides three kinds of hardware, H68SD5, the evaluation kit and
the evaluation board. The consumers are able to choose the best suitable tool.
of EPROM or the
object tape.
20
Resident System
Type No.
Evaluation Kit
HD6801S0
HD6801S5
HD6801VO
HD680'tV5
Evaluation
Board
Cross System
H68SD5 + Emulator Set
(Hardware + Software)
~
IBM370
Intel
MDS220/230
H61 EVOO*
HD68P01S0
H68SD5 + H61MIX1*
H61 EV01 *
HD68P01V05
HD68P01V07
H68SD5 + H61MIX1 *
H65EVOO*
HD68P05V05
HD68P05V07
H68SD5 + H65MIX1
H65EV01*
HD68P05V05
HD68P05V07
H68SD5 + H65M I X 1
H65EV02*
H68SD5 + H65MIX2
H31 EVOO*
H68SD5 + H31MIX1 *
H3L5EVOO*
H68SD5 + H3L5MIX1*
+
S31MIX1R (Software)
H65EVT2 (Hardware)
HD6805S1
+
S65MIX1R (Software)
HD6805U1
HD6805V1
EPROM on
the Package
H65EVT2 (Hardware)
+
S65MIX1R (Software)
H65EVT3* (Hardware)
HD6805WO
+
S65MIX1R (Software)
HD6301VO
HD63A01VO
HD63B01VO
S31MIX1R (Software)
H3L5EVT1 * (Hardware)
HD63L05
+
S65MIX1R (Software)
* Under development
21
series.
Disk based low cost system
56kbyte RAMs
Features
Module
System Configuration
H68SD5
FDD*
FDD
EPROM Writer*
HD6801/6805 familY}
Emulator Module* {
HMCS40 series
* Option
22
HD6801S
HD6801V
HD6803
Operations
Mnemonic
Booleanl
Arithmetic
Operation
Add
ADDA A+M--+A
ADDB B+M--B
Add
Double
A:B+M:M+1
ADDD --+A:B
Add
Accumulators ABA
Add with
Carry
Subtract
ADCA
ADCB
SUBA
SUBB
A+M+C--+A
B+M+C--+B
A-M--+A
B-M--+B
A:B-M:M+1
SUBD --+A:B
Subtract
Accumulator
SBA
Increment
Decrement
Clear
Compare
Compare
Double
INC
INCA
INCB
DEC
DECA
DECB
ClR
ClRA
ClRB
CMPA
CMPB
And
Or
00 00
00 00
~O
<w
-J:2
w:2
0:_
00 00
00 00
00 00
00 DO
00 00
00 00
00 00
00 00
0
00 00
00 00
00 00
00 00
00 00
00 00
00 00
0
00 00
00 00
00 00
00 000
00 000
00 000
00 00
00 00
0
0
00
00
0
00
0
0
00
00 00
00 00
0
00 00
0
0
00 00
0
0
00
00
00 00
00 00
0
0
0
0
0
00 00
00
00
00
00 00
00
0
0
0
00 000
00 000
0
00
00
00
0
0
00 00
00 00
0
0
0
000
000
000
000
0
00 00
0
00
00
00
00
00
00 000
0
00
0
00 00
>
~O ~x 0 0
~x 0
U
w Z-J <w U w ZZ -J~
~o..
-J:2
~o..-J
~o
~O x~
w
w:2 o~ ww
X:2
:2
_ 0:_
_0:
o~ w
00 00
0
HD6809
HD6809E
01-0
00 00
0
0
00 00
00 00
0
0
00 000 ._-00 000
00 000
A-B
TST
TSTA
TSTB
ANDA
ANDB
M-OO
A-OO
B-OO
A'M--+A
B M--+B
00 00
00 00
00 00
00 00
00 00
00 00
00 00
00 00
-00 0 0"0
0
00 000
00 00 0
ORAA
ORA
A+M--+A
00 00
00 00
00 00
00 00
00 00
00 00 0
B+M--+B
00 00
00 00
NBM--+A
BG3M--+B
M--+M
A--+A
-S---+B
OO-M--+M
OO-A--+A
OO-B--+B
AM
B M
00 00
00 00
00
00 00 0
00 bo 0
00 00 0
00 00
ORAB
ORB
Exclusive Or
00 00
00 00
00 00
00 00
00 00
00 00
Decimal Adjust
Accumulator
M+1--+M
A+1--+A
B+1--B
M-1--+M
A-1--+A
B-1--B
O--+M
O--+A
O--B
A-M
B-M
CMPD A:B-M:M+1
Compare
Accumulators CBA
Test Zero or
Minus
00 00
00 00
00 00
A-B--+A
A-M-C--+A
B-M-C--+B
AxB--+A:B
HD6800
HD6802
HD6802W
HD63l05
A+B--A
Subtract
Double
HD6301V
EORA
EORB
Complement COM
1's
COMA
COMB
Complement NEG
2's (Negate) NEGA
NEGB
. Bit Test
BITA
BITB
00
00
0
0
00
00
0
0
00 00
00 00
00 00
00 00
00
00
0
0
00
0
00
0
0
00 00
00 00
00
00 00
00
0
00 00
0
0
0
00
0
0
00 00
00 00
00 00
00 00
00
00
0
0
0
0
00
0
00 00
00 00
0
0
00 00
00 00
0
0,-.
0
00 o O-+Q
00 OO!O
Q.t--
(to be continued)
23
HD6801S
HD6801V
HD6803
Operation
Bit Clear
Bit Set
1----------
Boolean/
Arithmetic
Operation
Mnemonic
HD6301V
HD6800
HD6802
HD6802W
HD63l05
HD6809
HD6809E
I-
01-
X O
wU w
Z
~~ 01_ w
~_ 0 zX
>
-J~
Il..-J
~w
_0:
01-
O
wU X
w Z
~~ 01_ w
~_ 0 zX
>
-J~
Il..-J
~w
_0:
01-
X O
wU w
Z
~w 01~!:!:
_ W
_ 0 zX
>
-J~
Il..-J
~w
_0:
0
0
01-
O
wU X
w Z
~w 01~!:!:
_w
_ 0 zX
>
-J~
Il..-J
~w
_0:
>
01-
X O
wU w
Z
~w 01~!:!:
_ 0 ZX
_w
i=
U
w
-J<t
Il..-J ~w
_0
_0: ~!:!:
~w
e: >
OlO
wU X
w Z ~-J~
01- I-Il..-J
zX
_ w
~~w
_0:
0
0
0
into A
r.--------- - - -----load
lDAA M->A
lDA
1-----
00 00
------
Store
00 00
00 00
00 00
00 00
00 00
STAA A->M
STA
000
STAB
STB
B->M
000
000
A:B->M:M+ 1
000
000
---
- - - - - - - - - - -------- 1-----
Exchange
Push Data
00 000
00 00
00 000
000
00 000
000
000
000
00 00
000
00 00
Register 1
-+Register 2
--- - - 1-----------------A--->B
TAB
'=------- -_. -_ .. _ - - - - - - B--+A
TBA
00 00
0
TFR
0
0
00 00
f-----
SID
Transfer
00 00
-.----~-
lDAB M->B
LDB
Register 1
->Register 2
EXG
-------
0
0
0
0
... _------_._ ..
A-+Ms
PSHA S-1->S
B->Ms
S-1->S
------
PSHB
- - - - 1-------
Registers-+Ms
PSHS S--n->S
----- ------
PSHU Registers-+Mu
U-n->U
----~-----
Pull Data
---------1--
Ms->A
S+1->S
PULA
----
-~----.-
Ms-+B
S+ 1->S
PUlB
-- ----- - - -
Ms->Registers
S+n-+S
PUlS
_._--- 1--------------
--. - ._------
Shift Left
Arithmetic
----------
Shift Right
Arithmetic
PUlU MU->RLJisters
U+n->
----
ASL
'A"SLA
~LB
ASLD
'ASR--
ASRA
1------
tsLBlSR
lSRA
~-
A
B
00
CI:iSJ--o
RORB
0
0
00
00
0
0
00
0
0
00 00
0
0
0
0
00 00
00
0
0
0
MSB LSB
00
00
0
0
0
I'~
MSB LS6 C
A:B
ROl
ROlA
-----ROlB
I-c-------- - - - Rotate Right ROR
--RORA
-----
00
0
00 00
00
00
0
0
0
00
~o
00
0
0
0
00
0
0
0
1--
LS8
M
C
0
00
MSB LS8 C
MT
- - - - - - - - 1-----
Shift Right
logical
o-cC:::rJ- 0
C MSR
A
B
ASRB
lSl
1-----lSlA A
B
1 - - - - - - - - - 1---------
Shift Left
logical
"r'M-l
A
B
A:B
: l~
: l~
00
00
00
0
00
0
0
00
00
0
0
00
0
0
0
0
0
00 00
0
0
00
00
0
0
00 00
0
0
00
00
0
0
00
00
0
0
0
0
0
00 00
0
0
0
0
(to be continued)
24
Operations
Mnemonic
Boolean/
Arithmetic
Operation
HD6805S
HD6805U
HD6805V
HD6805W
-,----,---
HD6801S
HD6801V
HD6803
'--,-,-,,-
HD6800
HD6802
HD6802W
HD63l05
HD6301V
II
w
w
I
> 01- O
~o
o
~ 0101- X 01 ~o I-x 0
O
X
wU
wU X
wU wZ-I !;(w ~w Z-I !;(w I-x
Z
Z-I!;(
wZ-I
-I~
w
~w
~w 01-0...
~w 01-0... -I~
a:0 1-0... -I~ a:0 1-10...
-I ~w 01- 0...-1 ~!:f
~!:f
x~w ~!:f _w ~w
w~
w_ a:_
_a: _0 ~GS~
_0 _zx~
o~ GS~ ~~ o~ w_a: _0 zX
w
HD6809
HD6809E
&3
!:E
>
~O I-x OC
!;(w ~w Z~-I!;(
-I~
w~
a:
_
a:0 1-1-0...-1
xx~w
o~ ww_a:
00
00
00
00
MIMMED->M
M+MMED->M
MlJIMMEO->M
1----MIMMED
Operations
Mnemonic
Branch Test
olJ
HD6805S
HD6805U
HD6805V
HD6805W
HD6301V
H06800
H06802
H06802W
HD63l05
-,-
w
I ~ JI- O > o 1-' 10 w
>
~ 01O
X Z -I~ wux z -I~ 01wU GS~-I
wU X Z
10
w ~ GSIZ -I !;(
~a:ol-o...-I
~-zx~w
_O_w_a:
HD6809
HD6809E
I-
W!U w
C=1
Z=1
tBNE-
Z=O
BGE
'lBGE
BGT
N(t)V=O
Z+(N(;V)=O
Z+(N(;V)= 1
BHI
'lBHI
Branch if Higher BHS
or same(unsigned) 'lBHS
BlS
Branch if
lower or Same
Branch if lowe BlO
(unsigned)
'lBlO
BPl
Branch if
Plus
BMI
Branch if
Minus
'lBMI
BVC
Branch if
I
Overflow Clear lBVC
,BVS
Branch if
Overflow Set lBVS
C+Z=O
Branch if Half
BHCC
Carry Clear
H=O
H=1
1=0
Branch if Interrupt
BMS
Mask Set
Branch if Interrupt
BIH
Line High
~~
Branch if
Carry Set
UcS
lBCC
BCS
BEQ
lBEQ
Branch if Not BNE
Equal Zero
Branch
if=Zero
f---
Branch
if;GZero
Branch
if>Zero
1----
LBGT
Branch
if<Zero
BlT
- - N8:N= 1
Branch
if;:;i;Zero
f-CBLE
lBlT
BlE
Branch
if Higher
ULS
UwL
C+Z=1
0
0
C=1
0
0
C=O
N=O
N=1
V=O
V=1
1=1
INT=1
C=O
Branch if
Carry Clear
I-
>
> 01- O ~
X Z 15
-I~ wU
~-I ~
~w w
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
-- I-----
(to be continued)
25
H06801S
H06801V
H06803
Operations
Mnemonic
INT=O
Re~urn from
Su routine
No Operation
Software
Interrupt
Return from
Interrupt
Wait
Synchronize
to Interrupt
Sleep
BSR
LBsR
(..J
~o I-x 0
~o I01uX
wU
~w
Z-J !;;(w WW
:!:w ~~-J
ol-Q. -J:i!: ~w
~o I-Q. -J:i!: ~o
:!:~
_ 25~
w:i!: 25~ w_
w:i!:
x:i!: a:
w,_ a:_
_0 _ZX:!:
BRA
laRA
Branch Never BRN
taRN
Branch to
Subroutine
Jump
Jump to
Subroutine
Branch
Always
H06809
H06809E
I-
8ranch Test
01wU
:!:w
:!:~
_0
Branch if Interrupt Bil
UneLow
H06800
H06802
H06802W
H063l05
H06301V
>
05
1=
ZZ -J<
I-j: Q.-J
~i'J') :i!:w
~
-~
0
0
0
.- 0
(5
JMP
00
000
00
000
00
00 00
JSR
000
000
000
000
00
00 00
RTS
NOP
SWI
SWI2
SWI3
0
0
0
0
0
0
0
0
--~ " -
RTI
WAI
CWAI
0
0
0
0
0
SYNC
SlP
HD6801S
H06801V
HD6803
Operations
Mnemonic
Boolean/
Arithmetic
Operation
01-
w
~ 01-
~~~Z-J!;;(
a:ol-Q.-J
Increment
Decrement
ADD with B
Clear
Negate
Complement 1's
Shift left
Arithmetic
Shift Right
Arithmetic
INX
DEX
ABX
ClRX
NEGX
COMX
X+ 1---X
X-l---X
B+X---X
O---X
OO-X---X
FF-X--X
ASlX
o.a:==IJ-o
ASRX
CiJ::=.-Il--D
C MSB
MSB
Shift Right
logical
lSRX
LSB
LSB C
~-rr:=::IJ.a
MSB
LSB C
HD6301V
------,--,---r- r---r--r-.--.-- r -
w
~ JI-
HD6800
HD6802
HD6802W
HD63l05
wU~z-J!;;(
t1SZ~!(
:!:~ol-Q..-J
01-
-'rrr:
~ frli1S ~I;[ ~
2!: 01-
wU~z-J!;;(
HD6809
HD6809E
-r-T-,-'-r-,--
I I~ll~
W ~ w'ZI~I-JI<
:!:~ol-Q..-J
:i!:~ol-Q..-J
:i!: IX: 0ll-il-lQ..l-J
W :i!:
_ ~
0 ~IXI:i!:
_ w,_ IX:
X"x'i:i!:
W
~25~~~~ ~25~~~~ ~25~~~~ ~ 25 ~ ~ ~,~ :i!:
- 25 Z
_WjW
_,~
0
0
0
0
0
-,-0
0
0
0
0
t---fc) 0
0
-0
0
0
0
0
0
.. ---
W-t+-~+rff:
+,t r
It+~
0
0
10
jI
! I I
I I
,---t-l i -
'-
I I
iii
(to be continued)
26
HD6801S
HD6801V
HD6803
Operations
Booleani
Arithmetic
Operation
Mnemonic
r-r-rrn0>-1 0 ~
HD6800
HD6802
HD6802W
HD6301V
HD63L05
f---~I~~I~
--'l--~rT-
HD6809
HD6809E
0,
~ Iw
:rr~rT
w
~
> o ~ 0 ~ i2:
0
2:
O i=
I
Iw
IUX
0>-1 01 ~ ~~~Z..J~
w~~z..J~ ~~~Z..J~ wU~z..J~
w ~ ~ z ~ ..JI~
r--'-~~~~-
o~
:Ea:o~~..J
o~
2:
:E~o~~..J
a:o~~..J
a:o~~..J
~~~~c[~
:Ea:o~~~..J
-Iz X :E w ~-zX:Ew
_O_w_a:
_O_w_a: ~o~~GS~~
~ l~ ~ ~ ~ ~o~~~~ ~ 0 ~ ~I~ ~ :E
Shift Left
Logical
D-U~ =:])--0
LSLX
MSH
01
LSH
f---
Rotate Left
ROLX
c;:~:rr----=n::
C
MSH
10
LSH
- - _._--
0
I
Rotate Right
RORX
Test
Compare
Load
StC>re
~ective
Address
!;J-o:=.-_:o.1
C
~ISH
ISH
TSTX X-OO
CPX
CMPX X-M:M+ 1
CMPY Y-M:M+ 1
LDX
M:M+1---X
LDY
M:M+1---Y
STX
X---M:M+1
Y-M:M+1
STY
LEAX
LEAY
I
c--- --.
LEAU
00 100
00 0
-
000
+-
000
f---
- QOO
-f---
00 000
00 000
00 00 0 f--- f-00 00 (5
00 00
00 00
00 00
--
000
I
0
10
0
0
--
0
0
.-
I
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
;
it
00
~~~~~~:---U
t1 L
I
--
TG6x ACCD<-+X -
00 00
tt-j
00 00
-i-if --to
'0 00
f-
~~~~~~:---Y
~-
00 00'
000
,-
~fJ~~~~:---x
00 00
00 00
00 00
.-
00 00
m--
Exchange
I '
f---
Push
PSHX X---Ms
r-:--:-----Pull
PULX Ms---X
Transfer X.A TAX f-.
~x
X---A
Transfer X.S TSX
S---X
TXS
X---S
Increment
INS
S+1---S
S-1---S
Decrement
DES
Reset
RSP
$7F---S
Compare
CMPS S-M:M+ 1
CMPU U-M:M+ 1
LDS
Load
M:M+1---S
00
M:M+1---U
c--STS-- S---M:M+1
Store
U---M:M+1 -STU
I
Load effective
Effective
LEAS Address ---S
Address
'-----
-=----_. .-
00 00
00 00
f-------.--
Lou
10
000
00
t----
--
()
__
00 000
00 000
00 000
00 000
00 00
00 00
0
I
Clear Carry
HD6301V
HD63L05
HD6800
HD6802
HD6802W
HD6809
HD6809E
Mne- Boolean
monic Operation
CLC
~~~~lnterruPt CLI
O---C
-------_.0---1
(to be continued)
27
Operations
Mnemonic
SET-----------------HD6805S
HD6805U
HD6805V
HD6801S
HD6801V
HD6803
-....,.--,._.,-,--,-
r-':I-~~~~--,-
Boolean
Operation
>
HD6800
HD6802
HD6802W
HD63l05
HD6301V
>
>
>
-:--r-r-r--r-
I~
I
X O
HD6809
HD6809E
- , -,--r ---T----r~
01010101o~
o~
O
X O
X O
X O
wU X
Z - J i=
-J~ wU
w Z Q..-J
wU w Z -J~ wU w Z -J~ wU w Z -J~ wU
~w 01~w w
01- Q..-J ~w 01- Q..-J ~w 01- Q..-J ~w 01- Q..-J ~w
~2:
~2:
~w _
_0 zX
_w ~w
_a: ~2:
_ 0 ZX
_a: ~2:
_w ~w
_w ~w
_a: ~2:
_ 0 ZX
_w _a:
_a: ~2:
_ 0 zX
0 zX
_w ~w
_0
Clear
Overflow
O-+V
rsEc
1-+1
SEI
- - - c---1-+V
SEV
TAP
A-+CC
~PA "CC-+A
c--------------- And CC
~DCC CCimm-+CC
-6r-CC-CC+imm-->CC
ClV
'--=:----~-----
Set Interrupt
Mask
-------Set Overflow
f----------Transfer A.
CC
0
0
0
0
0
0
LEGEND
S
U
<!>
M
Ms
Mu
CC
Accumulator A
Accumulator B
Index Register
Index Register (6809 only)
Stack Pointer
User Stack Pointer (6809 only)
Transfer into
Arithmetic Plus
Arithmetic Minus
800lean AND
800lean Inclusive OR
Boolean Exclusive OR
Connection Area
Complement of M
Stack area pointed by S.
Stack area pointed by U.
Condition Code Register
0
0
0
0
0
0
'DRce
A
B
X
y
28
~
g;
w
>
O o
X
Z
~-J~
w
01- ~Q..-J
zX
_w w~~
Memory
c
0
.~
Po
V1H IEXTAL)
IlinIIEXTAL)
ISBB
ROM (k Byte)
RAM (Byte)
I/O
Timer (bit)
SCI
u.
Other Features
HD6801S0PJ
HD6801SOCJ
NMOS
DP-40
DC-40
5V O.25V
--40-+85C
HD6801VOPJ
2.2V
1.2mA
10mA
2
128
29
16
Yes
Data
Retention
Capability
2.2V
1.2mA
10mA
4
128
29
16
Yes
Data
Retention
Capability
NMOS
DP-40
5V 0.25V
--40-+85C
HD6803PJ
HD6803CJ
NMOS
DP-40
DC-40
5V 0.25V
--40-+85C
HD6805S1PJ
HD6805U1PJ
HD6805V1PJ
HD6805WOPJ"
NMOS
NMOS
NMOS
NMOS
HD6301VOPJ"
HD63A01VOPJ*
CMOS
DP28
DP-40
DP-40
DP-40
DP-40
5.25V 0.5V
--40-+85C
800mW
5.25V O.5V
--40-+85C
800mW
5.25V i O.5V
-40-+85C
800mW
5.25V O.5V
--40-+85C
5V 0.5V
--40-+85C
1.1
64
20
8"""
No
2
96
32
8"""
No
2.2V
1.2mA
10mA
128
13
16
Yes
Multiplexed
Address and
Data
Vectored
Interrupts
Self-<:heck
Mode
Master
Reset
4
96
32
S"""
No
Voltage
Comparator
Vectored
Interrupts
Self-<:heck
Mode
Master Reset
Voltage
Comparator
Vectored
Interrupts
Self-<:heck
Mode
Master Reset
128
96
29
29
16
8"""x2
No
Yes
Sleep
Voltage
Operation
Comparator
Low power
Vectored
Interrupts
Consumption
Self-check
Mode
Master Reset
* Preilmlnaly
". Electrical Characteristics shown here is for the industrial grade which is different from standard specification. So refer to each data sheet for details .
Timer; 8Bit programmable timer with 7Bit programmable pre-scaler.
Function
Vee
Topr
Package
Po
HD6800PJ
SV 0.25V
-40 - +8SoC
DP-40
HD6802PJ
SV 0.25V
-40 - +8SoC
DP-40
HD6802WPJ
SV 0.25V
-40 - +8SoC
DP-40
HD6809PJ*
HD68A09PJ*
HD68B09PJ*
SV 0.25V
-40 - +8SoC
DP-40
HD6809EPJ*
HD68A09EPJ*
HD68B09EPJ*
SV 0.25V
-40 - +8SoC
DP-40
HD6821PJ
SV 0.25V
-40 - +8SoC
DP-40
HD6840PJ
HD68A40PJ
HD68B40PJ
SV 0.25V
-40 - +8SoC
DP-28
HD6846PJ
SV 0.25V
-40 - +8SoC
HD46508PJ
HD46S08PJ-1
HD46S08PAJ
HD46508PAJ-1
1000mW
DP-40
SV O.25V
( Analog Input)
0 - S.OV
-40 - +8SoC
DP-40
SV O.25V
(AnalOg Input)
0 - 5.0V
-40 - +8SoC
DP-40
Under development
Electrical Characteristics shown here is for the industrial grade which is differant from standard specification.
.*
29
30
DATA
SHEETS
8-BIT MICROCOMPUTE
HMCS6800 SINGLE-CHI
SERlE
31
Preliminary data sheets herein contain information on new products. Specifications and information are subject to change without notice.
Advance Information data sheets herein contain information on a product
under development. Hitachi reserves the right to change or discontinue these
products without notice.
32
HD6801S0,HD6801S5
MCU (Microcomputer
Unit)
FEATURES
Expanded HMCS6800 Instruction Set
8 x 8 Multiply
On-Chip Serial Communications Interface (S.C.I.)
Object Code Compatible With The HD6800 MPU
16-Bit Timer
Single Chip Or Expandable To 65k Words
2k Bytes Of ROM
128 Bytes Of RAM (64 Bytes Retainable On Power
Down)
(DP-40)
(DC40)
PIN ARRANGEMENT
BLOCK DIAGRAM
Vee
POl
(Top View)
t-----Pto
I:===::~:~
t-----Pu
1:===::
~:;
I-----p"
TYPE OF PRODUCTS
MCU
t----Pp
33
Bus Timing
HD6801S0
1 MHz
HD6801 S5
1.25 MHz
HD6801S0, HD6801S6---------------------------------------------
Vee
V in
Input Voltage
Operating Temperature
Unit
V
-0.3 - +7.0
0 -+ 70
V
c
- 55 -+150
ELECTRICAL CHARACTERISTICS
Topr
Tstg
Storage Temperature
Value
-0.3 - +7.0
Symbol
Supply Voltage
Symbol
RES
Allinputs*
P40 - P47
SCt
EXTAL
Ilinl
Ilinl
PIO -P I7 ,P 30 -P 37
P20 - P24
P30 - P37
P40 ...... P47 , E, SCI. SC 2
Other Outputs
Input Capacitance
Vee Standby
Standby Current
Test Condition
V IL
All Outputs
IITslf
Vin
= 0- 2.4V
V in
= 0- Vee
= 0"" 5.25V
V in
V in
= 0.5 -
2.4V
= -205 J.l.A
= -145J.1.A
I LOAD = -100 J.l.A
I LOAD = 1.6 mA
V out = 1.5V
I LOAD
V OH
VOL
V 1H
Other Inputs*
=0 -
-loH
I LOAD
Po
-
P47 , SCI
Cin
Vin
f
= OV, Ta = 25C,
= 1.0 MHz
min
typ
max
Unit
4.0
Vee
2.0
-0.3
Vee
0.8
0.5
0.8
0.8
mA
2.5
J.l.A
10
100
J.l.A
2.4
2.4
2.4
0.5
1.0
10.0
mA
mW
1200
12.5
10.0
Powerdown
V SBB
4.0
Operating
V SB
4.75
5.25
Powerdown
ISBB
8.0
34
V SBB
= 4.0V
5.25
pF
V
mA
------------------------------------------------HD6801S0, HD6801S5
AC CHARACTERISTICS
BUS TIMING (Vee
Item
Symbol
Cycle Time
Test Condition
HD6801S0
typ
max
10
1
200
min
tCyc
PW ASH
tAsr
tASf
tASD
tEr
tEf
PWEH
PW EL
5
60
I
J
I
Non-Multiplexed Bus
Multiplexed Bus
Oscillator stabilization Time
Processor Control Set-up Time
Peripheral Read
Access Time
tASED
tAD
tAOL
tosw
tOSR
tHR
tHW
tASL
tAHL
tAH
5
5
450
450
60
Fig. 1
Fig.2
tRC
tpcs
50
50
50
260
270
20
20
(610\
(600)
_.
ns
20
20
ns
ns
ns
(410)
(400)
100
200
ms
ns
typ
ns
ns
350
ns
350
ns
Fig.4
400
ns
tCMos
Fig.4
2.0
p.s
tPWIS
Fig. 6
200
ns
tlH
Fig. 6
50
Fig. 6
20
ns
tOS01
Fig. 5
tos02
Fig. 5
Port 1, 2*,3,4
tpwD
.*
Port 2**, 4
port 3
Port 3
tiS
-Except P21
ns
ns
ns
ns
ns
260
260
115
70
10
20
50
115
-- -"--m
200
ns
ns
200
Fig. 3
50
50
Fig. 3
Port 1, 2,3,4
ns
ns
.'---ns
Unit
tposu
t pOH
Port 1, 2, 3, 4
ns
max
min
iJ~
-- .. --
Test Condition
_.
Symbol
Item
.-
5
5
340
350
f---.
-30
100
50
35
Unit
.C---
200
5
30
Fig. 10
--
50
Fig. 11
225
80
10
20
60
(tACCN)
(tACCM)
HD6801S5
typ
max
0.8
10
- - ..
150
5
50
min
ns
Item
Symbol
tpWT
t TOD
Test Condition
typ
max
ns
600
ns
Fig. 7
tscvc
tpWSCK
min
tcyc +200
Unit
0.4
0.6
t cvc
tScvc
typ
max
Unit
V MPL
V MPH
4.0
1.7
-
3.0
tcyc
tcyc
Symbol
Item
RES "Low"
Test Condition
Fig. 8
PW RSTL
Pulse Width
Mode Programming Set-up Time
2.0
tMPS
t MPH
150
tc:yc:
'7
Address Strobe
(AS)
...
-PWASH -
O.6V] ....
- -\
-- -
-tASr
I-tASf
tASO
2.4 vj
Enable
(E)
~~
ASEC
.,'fJ
~V
PWEL
O.5V~r-
-tAO-
(Sell'
....
-tEr
}~2.2V
Do-D,.A.-A,
(Port 3)
}
~
..tAHL
t06w-
-'I
2.2V
Address \
Valid
/
O.6V
)
~
2.2V
MPU Read
0.-0,. A.-A,
(Port 3)
Data Valid
-tOSR-
}~iJ:ress \
) Valid
O.6V
~I
(tACCM)
-tAH
......
-+
-tHW
~
~
-tHR
~~
)~2.0V
Data Valid
O.8V
36
O.6V
-tAOL-
.-tEf
O.6V
tASL ....
Address Valid
(Port4)
MPU Write
t\
-
R/W Ar-Ar.
'""r
PWEH
,~
ns
---------------------------------------------HD6801S0. HD8801S6
.
27vJ~
Enable
lEI
~
.-(
-
PWEL
0.5V ~
Ao--A,(Port4 )
ms
(SC21
(SCI)
'f-
:~
PWEH
~[
--tAO-
Rii/il
tcyc
--tEr
-tEf
-tAH
-~I\
2.2V;JAddress Valid
O.6V~
.,~
-tosw-
MPUWrite
2.2V J-'"
0.-0,
(Port 3)
O.6V\."
-tHW
-::l~
"]t....
-tOSA-
ItACCNI
,
\
Data Valid
-IHR
Oala Valid
0.-0,
(Port 3)
O.SV
r-MPURead
Enable(E)
MPUWrite
Enable(E)
--tcMos_1
P IO - P"
P20 - P2
p. o - p.,
_tpwo
All Data - - - - - - - - "
Port Outputs
InpulS
PJO - P"
Inputs
2.2V 0 t V I'd
O.6V a a a I
2.0V
____~~~~________~~0~.8V
(NOTE)
1. 10 kn Pullup resistor required for Port 2 to reach 0.7 Vee
2. Not applicable to P I
0)
Figure 3
Figure 4
Addres,
Bu,
053-----....;.
p)O -
P)7
Inputs
Access matches Output Strobe Select (055 = 0, a read;
055 = 1, a write)
Figure 5
Figure 6
37
HD6801S0, HD6801S6---------------------------------------------Enable
(E)
Timer
Counter
------'
VMPH
(P, P".P,.I
P"
Output
Figure 8
Vcc
Test Point
RLZ2.2kO
O..-----r...,130PF
Test Point
lS2074
Or Equlv.
I .,
Cvcle
L... Instructoon _ _
Internal
Add' ... Bu.J'\_--l"""_-4"-....,.....J''-_-J'-_-J'-_..J'~_~_ _ J\ _ _''''_ _'''''_ _'''"_.....J'--.J''--J\-_J\._ _
'iRQ,
*----.. . .
NMlor IRO)
Inlernal~r--~,._-~--'\r--'\r-....,.,...-"'""\,...-"""",._-~,.--_v--_v--'V'--"""\.,...-_v--'V'--"'-
Da .. Bu. J'......_ J \_ _.A._ _"-_ _"-_.J'-_..J''-_~_ _..J\_ _''''_ _J\._.....A . - _ J ' ,...._J\._ _J\. _ _' ' " ' _
Internal R/ii
InterruPt\'"-------------------~1
Figure 10 Interrupt Sequence
Va;
-5.25V
,10-\--------------1,'
"I
tAC--------,-----oL.TvtPCS
~ --------1,~t----------------~.~
,. 1..- - - - - - - - - - - -
A;,rn:,
, ... u.
In,.rnal RIW
\\\\\\\\\\\\\\\\\\\\\~ }ss\\\\\S\\S\\\\\\\Ss\\\\sv---V~.
~~ ~
FFFEFFFE
\\\\\\\\\\\\\\\\\\\'{ ~\S\S\\\\\\\\\SSS\\\\\\\\S\Y
:::x=r-
~:tt:r;~: ~\\\\\\\\\\\\\\\\\\\10%\\\\\\\\\\\S\S~ ~
~
PCB-PCI5 PCO-PC7 Forst
Instruction
~NotValtd
38
------------------------------------------------HD6801S0, HD6801S6
SIGNAL DESCRIPTIONS
Reset (RES)
This input is used to reset and start the MPU from a power
down condition, resulting from a power failure or an initial
startup of the processor. On power up, the reset must be held
"Low" for at least 100 ms. During operation, RES, when
brought "Low", must be held "Low" at least 3 clock cycles.
When a "High" level is detected, the MPU does the following:
I) All the higher order address lines will be forced "High".
2) I/O Port 2 bits, 2, I, and 0 are latched into programmed
60ntrol bits PC2, PC 1 and PeO.
3) The last two ($FFFE, $FFFF) locations in memory will
be used to load the program addressed by the program
counter.
4) The interrupt mask bit is set, must be cleared before the
MPU can recognize maskable interrupts.
Enable (E)
This supplies the external clock for the rest of the system
when the internal oscillator is used. It is a single phase, TTL
compatible clock, and will be the divide by 4 result of the
crystal frequency. It will drive one TTL load and 90 pF.
4 MHz
5 MHz
Co
7 pF max.
4.7 pF max.
Rs
son max.
30ntyp.
Item
XTAL~--~------~
CJ
EXTAL
I - - -.....~
C L1 = C L2 =22pF 20%
(3.2 - 5 MHz)
+r
CL1
tL2
Vee Standby
Vee Standby
39
Lowest
Priority
PORTS
There are four I/O ports on the HD680lS MCU; three 8bit
ports and one 5-bit port. There are two control lines associated
with one of the 8bit ports. Each port has an associated write
only Data Direction Register which allows each I/O line to be
programmed to act as an input or an output*. A "I" in the
corresponding Data Direction Register bit will cause that I/O
line to be an output. A "0" in the corresponding Data Direction
Register bit will cause that I/O line to be an input. There are
four ports: Port 1, Port 2, Port 3, and Port 4. Their addresses
and the addresses of their Data Direction registers are given in
Table 2.
Interrupt
MSB
LSB
FFFE
FFFF
rn
FFFC
FFFO
NMI
FFFA
FFFB
FFF8
FFF9
FFF6
FFF7
FFF4
FFF5
FFF2
FFF3
FFFO
FFFl
Ports
Port Address
I/O Port 1
$0002
$0003
$0006
$0007
1/0 Port 2
1/0 Port 3
1/0 Port 4
Data Direction
Register Address
$0000
$0001
$0004
$0005
I/O Port 1
This is an 8bit port whose individual bits may be defined as
inputs or outputs by the corresponding bit in its data direction
register. The 8 output buffers have three-state capability,
allOWing them to enter a high impedance state when the
peripheral data lines are used as inputs. In order to be read
properly, the voltage on the input lines must be greater than 2.0
V for a logic "1" and less than 0.8 V for a logic "0". As outputs, these lines are TTL compatible and may also be used as
a source of up to 1 rnA at 1.5 V to directly drive a Darlington
base. After Reset, the I/O lines are configured as inputs. In all
three modes, Port 1 is always parallel I/O.
I/O Port 2
This port has five lines that may be defined as inputs or
outputs by its data direction register. The 5 output buffers have
three-state capability, allowing them to enter a high impedance
state when used as an input. In order to be read properly, the
voltage on the input lines must be greater than 2.0 V for a
logic "1" and less than 0.8 V for a logic "0". As outputs, this
port has no internal pullup resistors but will drive TTL inputs
directly. For driving CMOS inpu~s, external pullup resistors are
required. After Reset, the I/O lines are configured as inputs.
Three pins on Port 2 (pins 10, 9, and 8 of the chip) are used
to program the mode of operation during reset. The values of
these pins at reset are latched into the three MSB's (bits 7 6
and 5) of Port 2 which are read only. This is explained in th~
Mode Selection Section.
In all three modes, Port 2 can be configured as I/O and
provides access to the Serial Communications Interface and the
Timer. Bit 1 is the only pin restricted to data input or Timer
output.
I/O Port 3
This is an 8bit port that can be configured as I/O, a data bus,
or an address bus multiplexed with the data bus - depending on
the mode of operation hardware programmed by the user at
reset. As a data bus, Port 3 is bi-directional. As an input for
peripherals, it must be supplied regular TTL levels, that is,
greater than 2.0 V for a logic "1" and less than 0.8 V for a logic
"0"
40
----------------------------------------------HD8801S0, HD8801S6
Its TTL compatible three-state output buffers are capable of
driving one TTL load and 90 pF. In the Expanded Modes, after
reset, the data direction register is inhibited and data flow
depends on' the state of the R/W line. The input strobe (IS3)
and the output strobe (OS3) used for handshaking are explained
later.
In the three modes, Port 3 assumes the following characteristics:
Single Chip Mode: Parallel Inputs/Outputs as programmed by
its associated Data Direction Register. There are two control
lines associated with this port in this mode, an input strobe and
an output strobe, that can be used for handshaking. They are
controlled by the I/O Port 3 Control/Status Register explained
at the end of this section. Three options of Port 3 operations
are sumarized as follows: (1) Port 3 input data can be latched
using IS3 (SC 1) as a control signal, (2) OS3 can be generated by
either an MPV read or write to Port 3's Data Register, and (3)
and IRQ7 interrept can be enabled by an IS3 nagative edge.
Port 3 latch and strobe timing is shown in Fig. 5 and Fig. 6.
Expanded Non-Multiplexed Mode: In this mode, Port 3
becomes the data bus (Do -D 7).
Expanded Multiplexed Mode: In this mode, Port 3 becomes
both the data bus (Do -D 7) and lower bits of the address bus
(Ao-A7)' An address strobe output is true when the address is
on the port.
IS3
$OOOF
Bit 0;
Bit 1;
Bit 2;
Bit 3;
Bit 4;
Bit 5;
Bit 6;
Bit 7;
FLAG
IS3
OSS
LATCH
o
X
PC21 PC1
IRQ1
ENABLE
OPERATION MODES
The mode of operation that HD6801 S will operate in after
Reset is detennined by hardware that the user must wire on pins
10, 9, and 8 of the chip. These pins are the three LSB's (I/O 2,
I/O 1, and I/O 0 respectively) of Port 2. They are latched into
programmed control bits PC2, PCI, and PCO when reset goes
high. I/O Port 2 Register is shown below.
76543210
load and 90 pF. After reset, the lines are configured as inputs.
To use the pins as addresses, therefore, they should be
programmed as outputs. In the three modes, Port 4 assumes the
following characteristics:
Single Chip Mode: Parallel Inputs/Outputs as programmed by
its associated Data Direction Register.
Expanded Non-Multiplexed Mode: In this mode, Port 4 is
configured as the lower order address lines (A o-A 7) by writing
one's to the data direction register. When all eight address lines
are not needed, the remaining lines, starting with the most
significant bit, may be used as I/O (inputs only).
Expanded Multiplexed Mode: In this mode, Port 4 is
configured as the higher order address lines (A 8 -A 1s ) by writing one's to the data direction register. When all eight address
lines are not needed, the remaining lines, starting with the most
significant bit, may be used as I/O (inputs only).
ENABLE
Not used.
Not used.
Not used.
LATCH ENABLE. This controls the input latch for I/O
Port 3. If this bit is set "High" the input data will be
latched with the falling edge of the Input Strobe, IS3.
This bit is cleared by reset, and the latch is "re-opened"
with MCV read Port 3.
OSS. (Output Strobe Select) This bit will select if the
Output Strobe should be generated at 053 (SC 1 ) by a
write to I/O Port 3 or a read ofI/O Port 3. When this bit
is cleared the strobe is generated by a read Port 3. When
this bit is set the strobe is generated by a write Port 3.
Not used.
iS3 IRQl ENABLE. When set, interrupt will be enabled
whenever IS3 FLAG is set; when clear, interrupt is
inhibited. This bit is cleared by RES.
IS3 FLAG. This is a read only status bit that is set by
the falling edge of the input strobe, IS3 (SCd. It is
cleared by a read of the Control/Status Register followed by a read or write of I/O Port 3. Reset will clear
this bit.
I/O Port 4
This is an 8-bit port that can be configured as I/O or as
address lines depending on the mode of operation. In order to
be read properly, the voltage on the input lines must be greater
than 2.0 V for a logic "1" and less than 0.8 V for a logic "0"
As outputs, each line is TTL compatible and can drive 1 TTL
41
HD6801S0, HD6801S6---------------------------------------------Vee
(
R~
>
R. R. R.
RES
I I I
A B
HD6801S
Xo
Yo
Zo
X.
PlO (PCO)
Pl. (PC1)
10
Pl2 (PC2)
Y.
Z.
(
(.
???
~
Mode
Control
Switch
HD14053B
Inh
J,
1) Mode 7 as shown
2) RC""Reset time constant
3) RI =10kS1
(NOTES)
Inh
Select
Inhibit
A
8
C
C B A
Xo
XI
Yo
YI
Zo
ZI
X
Y
Z
On Switch
HD14053B
Zo Yo Xu
Zo Yo XI
1 0
Zo Y. Xo
Zo Y I X.
1 0
ZI Yo Xo
1 0
ZI Yo "XI
1 0
ZI YI Xo
Z. Y I X.
X X X
Vee
Vee
2
40
Enable
Enable
Port 1
8 Parallel I/O
Port 3
8110 Lines
Port 1
8110 Lines
Port 2
5 Parallel 110
SCI
Timer
Port 2
5110 Lines
Port 4
8110 Lines
Vss
SCI
Timer
Port 3
8 Data Lines
Port 4
To 8 Address
Lines or To
7 I/O Lines
(Inputs Only)
42
----------------------------------------------HD6801SQ. HD6801S6
Vee
Enable
Port 1
8 I/O Lines
8 Lines
Multiplexed
Data I Address
Address Strobe
Port 2
Port 4
To 8 Address
Lines or To
7 110 Lines
(Inputs Only)
51/0 Lines
SCI
Timer
AS
J
0,
Port 3
Address/Data
G OC
0,
08
Function Table
74LS373
Output
Control
08
Enable
0
Output
0
L
L
L
H
H
X
X
L
00
Z
0 ... 0,-0,
This section gives a description of the MCU signals for the various modes. SCI and SCl are signals which vary with the mode
that the chip is in.
PORT 1
Eight Lines
PORT 2
Five Lines
PORT3
Eight Lines
PORT4
Eight Lines
SCI
SCl
SINGLE CHIP
I/O
I/O
I/O
I/O
IS3 (I)
OS3(0)
EXPANDED MUX
I/O
I/O
ADDRESS BUS
(Ao-A7 l
DATA BUS
(0 0 -0 7 )
ADDRESS BUS
(As-Au)
AS(O)
R/W(O)
EXPANDED NON-MUX
I/O
I/O
DATA BUS
(0 0 -0 7 )
ADDRESS BUS
(Ao-A 7 )
10S(0)
R/W"(O)
MODE
-These lines can be substituted for I/O (Input Only) statting with the most significant address line.
I .. Input
m = Input Strobe
SC .. Strobe Control
o - Output
0S3 .. Output Strobe
AS = Address Strobe
ANI .. Aead/Write
105" 1/0 Select
43
HD8801S0.
Mode
7
6
5
4
3
2
1
0
(~t22)
P21
(PC1)
H
H
H
H
L
L
L
L
H
H
L
L
H
H
L
L
(P~O)
ROM
RAM
H
L
H
I
I
I
I
I
I
L
H
L
H
L
1(2)
1(1)
E
E
I
I
E
I
I
I
LEGEND:
I - Internal
E - External
MUX - Multiplexed
NMUX - Non-Multiplexed
L - Logic "0"
H - Logic "1"
Interrupt
Vectors
I
I
I
I
E
E
E
1(3)
Port
Port
Port
Port
Address
00
01
02
03
0405
06
07
08
OC
00
OE
OF-
10
11
12
13
I
MUX(S)
NMUX(S)
I
MUX
MUX
MUX
MUX
Operating
Mode
Single Chip
Multiplexed/Partial Decode
Non-Multiplexed/Partial Decode
Single Chip Test
Multiplexed/No RAM & ROM
Multiplexed/RAM
Multiplexed/RAM & ROM
Multiplexed Test
(NOTES)
1) Internal RAM is addressed at $XX80
2) Internal ROM is disabled
3) RES vector is externai for 2 cycles after RES goes "High"
4) Addresses associated with Ports 3 and 4 are considered external in Modes 0,
1,2, and 3
5) Addresses associated with Port 3 are considered external in Modes 5 and 6
6) Port 4 default is user data input; address output is optional by writing to Port 4
Data Direction Register
MEMORY MAPS
The MeV can provide up to 65k byte address space depending on the operating mode. A memory map for each operating
mode is shown in Figure 20. The fust 32 locations of each map
are reserved for the MeV's internal register area, as shown in
Table 4. With exceptions as indicated.
Port
Port
Port
Port
Bus
Mode
09
OA
OB
14
15-1F
44
INTERRUPT FLOWCHART
The Interrupt flow chart is depicted in Figure 24 and is common to every interrupt excluding reset.
---------------------------------------------HD8801S0, HD8801S6
HD6801S
Mode
HD6801S
Mode
$0000(1 )
$0000(1)
Internal Registers
Internal Registers
$001F
$001F
$0080
Internal RAM
Internal RAM
$OOFF
$OOFF
$F800
$F800
Internal ROM
$FFEF
Internal ROM
$FFFO
$FFFF(2)
[NOTES)
1) Excludes the following addresses which may
be used externally: $04, $05, $06, $07 and $OF.
2) Addresses $FFFE and $FFFF are considered
external if accessed within 2 cycles alter a
positive edge of RES and internal at all other
times.
3) After 2 MPU cycles, there must be no overlapping of internal and external memory
spaces to avoid driving the data bus with more
than one device.
4) This mode is the only mode which may be used
to examine the interrupt vectors in internal
ROM using an external Reset vector.
$ F F F F - - - -....
[NOTES)
1) Excludes the following addresses which may
be used externally: $04, $05, $06, $07 and
$OF.
2) Internal ROM addresses $FFFO to $FFFF are
not usable.
45
HD6801S0, H D 6 8 0 1 S 6 - - - - - - - - - - - - - - - - - - - - - - -
HD6801S
Mode
HD6801S
Mode
Multiplexed/RAM
$0000(1)
$0000(1)
} Internal Registers
Internal Registers
$OO1F
$001F
Internal RAM
$OOFF
$FFFO 1-----4~}
$FFFF '--_ _ _..I
$FFFO ~----1
$FFFF _ _ _ _... } External I nterrupt Vectors
(NOTE]
1) Excludes the following addresses which may
be used externally: $04, $05, $06, $07, and
$OF.
(NOTE]
1) Excludes the fOllowing addresses which may
be used externally: $04, $05, $06, $07 and
$OF.
46
(Continued)
----------------------------------------------HD8801S0. HD8801S6
HD6801S
Mode
HD6801S
Mode
} Intp.rnal Registers
Internal Registers
$001F
$0080
} Internal RAM
$OOFF
$0100
$01 FF _ _..--_"
U
1)(4)
$F800
Internal ROM
$XX80
$XXFF
Internal RAM
} Internal Interrupt Vectors
$FFFF
[NOTES]
1) The internal ROM is disabled.
2) Mode 4 may be changed to Mode 5 without
having to assert RESET by writing a "1" into
the peo bit of Port 2 Data Register.
3) Addresses As to AI 5 are treated as "don't
cares" to decode internal RAM.
4) Internal RAM will appear at $XX80 to $XXFF.
[NOTES]
1) Excludes the following addresses which may
not be used externally: $04, $06, and $OF.
(No IDS)
2) This mode may be entered without going
through RES by using Mode 4 and subsequently writing a "1" into the peo bit of
Port 2 Data Register.
3) Address lines Ao - A. will not contain addresses until the Data Direction Register for Port 4
has been written with "1 '5" in the appropriate
bits. These address lines will assert "1's" until
made outputs by writing the Data Direction
Register.
47
HD8801S0, HD8801S6---------------------------------------------
HD6801S
Mode
HD6801S
Mode
Single Chip
Multiplexed/Partial Decode
$0000(1)
$001F
$0000
Internal Registers
} Internal Registers
$001F
External Memory Space
$0080
$0080
Internal RAM
} Internal RAM
$OOFF
$OOFF
$F800
$FFFF
Internal ROM
Internal ROM
[NOTES)
1) Excludes the following address which may be
used externally: $04, $06, $OF.
2) Address lines As-A.! will not contain
addresses until the Data Direction Register for
Port 4 has been written with "1's" in the
appropriate bits. These address lines will
assert "1's" until made outputs by writing the
"Data Direction Register.
48
----------------------------------------------HD6801S0, HD6801S5
PROGRAMMABLE TIMER
The HD680 I S contains an on-chip 16-bit programmable
timer which may be used to perform measurements on an input
waveform while independently generating an output waveform.
Pulse widths for both input and output signals may vary from a
few microseconds to many seconds. The timer hardware consists
of
an 8-bit control and status register,
a 16-bit free running counter,
a 16-bit output compare register, and
a 16-bit input capture register
A block diagram of the timer registets is shown in Figure 21.
Free Running Counter ($0009:000A)
The key element in the programmable timer is a 16-bit free
running counter which is driven to increasing values by E (Enable). The counter value may be read by the MPU software at
any time. The counter is cleared to zero on RES and may be
considered a read-only register with one exception. Any MPU
write to the counter's address ($09) will always result in preset
value of $FFF8 being loaded into the counter regardless of the
value involved in the write. This preset figure is intended for
testing operation of the part, but may be of value in some
applications.
Output Compare Register ($OOOB:OOOC)
The Output Compare Register is a 16-bit read/write register
which is used to control an output waveform. The contents of
this register are constantly compared with the current value of
the free running counter. When a match is found, a flag is set
(OCF) in the Timer Control and Status Register (TCSR) and the
current value of the Output Level bit (OLVL) in the TCSR is
clocked to the Output Level Register. Providing the Data
Direction Register for Port 2, Bit 1 contains a "1" (Output),
the output level register value will appear on the pin for Port 2
Bit I. The values in the Output Compare Register and Output
level bit may then be changed to con trol the ou tpu t level on the
next compare value. The Output Compare Register is set to
$FFFF during RES. The Compare function is inhibited for
one cycle following a write to the high byte of the Output
Compare Register to insure a valid l6-bit value is in the register
before a compare is made.
Input Capture Register ($OOOD:OOOE)
The Input Capture Register is a J6-bit read-only register used
to store the current value of the free running counter when the
proper transition of an external input signal occurs. The input
transition change required to trigger the counter transfer is
controlled by the input Edge bit (IEDG) in the TCSR. The Data
Direction Register bit for Port 2 Bit 0, shouId* be clear (zero)
in order to gate in the external input signal to the edge detect
unit in the timer.
r--.......~=-.OE
Output Input
Level
Edge
B;t'
Bit 0
Po,t 2 Pon 2
Figure 21
49
ICF I OCF
TOF
I I
EICI
EOCI I ETOII'EOG
OLVLI $0008
MPU via the data bus and with the outside world via pins 2, 3,
and 4 of Port 2. The hardware, software, and registers are explained in the following paragraphs.
Wake-Up Feature
In a typical multi-processor application, the software
protocol will usually contain a destination address in the initial
byte(s) of the message. In order to permit non-selected MPU's
to ignore the remainder of the message, a wake-up feature is
included whereby all further interrupt processing may be
optionally inhibited until the beginning of the next message.
When the next message appears, the hardware re-enables (or
"wakes-up") the for the next message. The "wake-up" is
automatically triggered by a string of ten consecutive l's which
indicates an idle transmit line. The software protocol must
provide for the short idle period between any two consecutive
messages.
Programmable Options
The following features of the HD680 I S serial I/O section are
programmable:
format - standard mark/space (NRZ)
Clock - external or internal
baud rate - one of 4 per given MPU <P2 clock frequency or
external clock x8 input
wake-up feature - enabled or disabled
Interrupt requests - enabled or masked individually for
transmitter and receiver data registers
clock output - internal clock enabled or disabled to Port
2 (Bit 2)
Port 2 (bits 3 and 4) - dedicated or not dedicated to serial
I/O individually for transmitter and receiver.
Serial Communications Hardware
The serial communications hardware is controlled by 4
registers as shown in Figure 22. The registers include:
an 8-bit control and status register
a 4-bit rate and mode control register (write only)
an 8-bit read only receive data register and
an 8-bit write only transmit data register.
In addition to the four registers, the serial I/O section utilizes
bit 3 (serial input) and bit 4 (serial output) of Port 2. Bit 2 of
Port 2 is utilized if the internal-clock-out or external-clock-in
options are selected .
76543210
ROREI ORFE
I I I I I I wu I
TORE
RIE
RE
50
TIE
TE
AOOR : $0011
----------------------------------------------HD6801S0. HD6801S6
Bit 7
I I I I
CCI
CCO
SSl
Bit 0
SSO
1$10
$12
Port 2
Receive Shift Register
Clock
10
Bit ....---':..:c-_
_____
14----E
12
$13
6
X
CC1
cco
51
0
SS1
sso
ADDR : $0010
HD6801S0,
Bit 0 SSO
Bit 1 SSl
HD6801S6----------------~---------------------------
Bit 2 CCO Clock Control and Format Select - this 2-bit field
Bit 3 CCl controls the format and clock select logic. Table 6
defines the bit field.
2.4576 MHz
4.0 MHz
614.4 kHz
4.9152 MHz*
1.0 MHz
1.2288 MHz
E"," 16
26 J,Ls/38,400 Baud
16 J,Ls/62,500 Baud
13 J,LsI76,800 Baud
E"," 128
E"'" 1024
E"," 4096
* HD6801S5 Only
Format
00
- ,
01
NRZ
Port 2 Bit 2
Port 2 Bit 3
**
**
Internal
Not Used
**
**
Clock Source
Port 2 Bit 4
10
NRZ
Internal
Output*
**
**
11
NRZ
External
Input
**
**
Transmit Operations
The transmit operation is enabled by the TE bit in the
Transmit/Receive Control and Status Register. This bit when
set, gates the output of the serial transmit shift register to Port 2
Bit 4 and takes unconditional control over the Data Direction
Register value for Port 2, Bit 4.
Following a RES the user should configure both the Rate
and Mode Control Register and the Transmit/Receive Control
and Status Register for desired operation. Setting the TE bit
during this procedure initiates the serial output by first
transmitting a ten-bit preamble of 1'so Following the preamble,
internal synchronization is established and the transmitter
section is ready for operation.
At this point one of two situation exist:
I) if the Transmit Data Register is empty (TORE = 1), a
continuous string of ones will be sent indicating an idle
line, or,
2) if data has been loaded into the Transmit Data Register
(TORE = 0), the word is transferred to the output shift
register and transmission of the data word will begin.
During the transfer itself, the 0 start bit is first transmitted.
Then the 8 data bits (beginning with bit 0) followed by the stop
bit are transmitted. When the Transmitter Data Register has
be~n emptied, the hardware sets the TORE flag bit.
If the HD680IS fails to respond to the flag within the proper
time, (TORE is still set when the next normal transfer from th~
parallel data register to the serial output register should occur)
then a 1 will be sent (instead of a 0) at "Start" bit time,
followed by more 1's until more data is supplied to the data
register. No O's will be sent while TORE remains a I.
52
----------------------------------------------HD6801S0, HD8801S6
Condition code register manipulation instructions - Table 10
Instructions Execution times in machine cycles - Table
Receive Operation
II
115
15
SP
115
PC
Overflow
Zero
Negative
Interrupt
8
Jump and branch instructions - Table 9
53
Add
Add Double
Mnemonic
~---r-----
IMMED.
DIAECT
Aegister
------,-INDEX
EXTEND
IMPLIED
OP
OP
ADDA
8B
9B
AB
2 BB
A+ B ..... A
ADDB
CB
DB 3
EB
FB
B+M ..... B
ADDD
C3
D3
.5
i:3
F3
2 99
2 D9
A9
B9
A+M+C ..... A
E9
F9
B+M+C ..... B
2 94
A4
AM ..... A
2 B4
2 F4
BM ..... B
OP
1B
A + B ..... A
Add Accumulators
ABA
ADCA
89
ADCB
C9
2
2
ANDA
84
ANDB
C4
2 2
D4
E4
BITA
85
95
A5
B5
AM
BIT B
C5
D5
E5
F5
6F
7F
BM
00 ..... M
AND
Bit Test
ClA
Clear
Compare
ClAA
4F
1 00 ..... A
ClAB
5F
1 00 ..... B
CMPB
C1
3 ,2
E1
Fl
B-M
A-B
63
73
M ..... M
A ..... A
COMA
43
COMB
53
1 B -+ B
60
70
3
40
50
19
DECA
4A
DECB
5A
DAA
I
6A
DEC
7A
EOAA
88
98
A8
B8
EOAB
C8
D8
E8
F8
6C
7C
INCA
4C
INCB
5C
lDAA
86
9.6
A6
B6
lDAB
C6
D6
E6
F6
load Double
Accumulator
lDD
CC
DC 4
EC
FC
Multiplv Unsigned
MUl
OA, Inclusive
OAAA
2 9A 3
CA 2 2 DA 3
AA 4
BA 4
EA 4
FA 4
OAAB
3D 10 1
8A
PSHA'
36
PSHB
37
PULA
32
PUlB
33
49
59
AOAA
46
AOAB
56
AOl
69
79
AOlA
AOLB
..
~
~ :
~ :
: f
f f
A S
A S
A S
A-M
INC
Aotate Aight
4 3
NEGA
NEGB
Aotate left
f
f
t
f
B1
(Negate)
Pull Data
f
f
f
f
f
f
NEG
Push Data
Complement, 2's
load
Accumulator
A1
COM
Increment
Complement, 1's
Exclusive OA
11
AOA
66
76
1 0
2 91
D1
I N Z V
81
CBA
Decrement
CMPA
Compare
Accumulators
Decimal Adjust, A
OP
OP
Boolean/
Arithmetic Operation
OO-M ..... M
OO-A ..... A
OO-B ..... B
Converts binary add of BCD
characters into BCD format
M-1 ..... M
A - l ..... A
B-1 ..... B
A@M ..... A
B 0 M-+ B
M+1-+M
A+1-+A
B+1-+B
M-+A
M-+B
M + 1 ..... B, M ..... A
AxB-+A:B
A+M-+A
B + M-+ B
A -+ Msp, SP - 1 -+ SP
B -+ Msp, SP - 1 -+ SP
SP + 1 -+ SP, Msp -+ A
SP + 1 -+ SP, Msp ..... B
~}
lo-1
I I i I I I liJ
bo
B
C b7
:}
4}:j
I I I I I I liJ
bO
B
C b7
f
f
A
A
A
A
54
f
f
f
f
A A
A A
t
f
f
t A S
t
t
t
t
A S
A S
CV@
(j)@
t
t t
\V @
t @
t
t
t
t
t t
t t
t t
t t
t t
t A
~
~
t
t
A
A
t () f
t t (~ f
t t t
t ~ () t
t f () t
t t 11 t
(Continued)
The Condition Code Aeglster notes are listed after Table 10.
A A
t f
t f
----------------------------------------------HD6801S0. HD6801S6
Table 7 Accumulator & Memory Instructions
(Continued)
Condition Code
Register
Addressing Modes
Operations
Mnemonic
IMMED,
OP
Shift Left
Arithmetic
Double Shift
Left, Arithmetic
Shift Right
Arithmetic
Shift Right
Logical
Double Shift
Right Logical
INDEX
DIRECT
OP
OP
68
ASL
EXTEND
IMPLIED
OP
# OP
78
ASLA
Booleanl
Arithmetic Operation
48
M}
__
D--I II II I II
ASLB
58
ASLD
05
1 ~
67
77
ASRA
47
ASRB
57
44
64
LSR
74
LSRB
54
LSRD
04
AO 87
~} C?I
b7
Ao-oillllllll-\J
b7
0--1
ACC
A7
97
A7
B7
STAB
07
E7
F7
B ..... M
Store Double
Accumulator
STD
DO 4
ED 5
FD 5
A ..... M
B ..... M+ 1
Subtract
SUBA
80
90
AO
BO
A-M ..... A
SUBB
CO
DO
EO
FO
B -M ..... B
Double Subtract
SUBD
83
93
A3
B3
Subtract
Accu mu lators
SBA
bO
ACeS
AI
AO
STAA
87
A-B ..... A
Subtract
With Carry
SBCA
82
92
A2
B2
A-M-C-+A
SBCB
C2
02
E2
F2
B-M-C-+B
Trensfer
Accumulators
TAB
16
A-+B
TBA
17
B-+A
Test Zero or
Minus
TST
TSTA
40
A -00
TSTB
50
B -
70
The Condition Code Re!;Iister notes are listed after Table 10,
~
80
60
80
IIIII !bO~
A ..... M
Store
Accumulator
1-0
bO
M}
LSRA
b7
A7
ASR
M-OO
5
H
00
I N Z
t t
1 0
V
*
@*
*
*
* * *
t t @*
* * !,; *
t t @ t
t 6 t
*t * @t
t * @t
t * @t
R * @t
t *R
t t R
*t t
t
t t
t
t t t t
*t tt
'. *
t t
t t t
t t R
t t R
t t R R
t R R
*t
R R
eight bits in the Meu. The carry is then added to the higher
order eight bits of the index register. This result is then used to
address memory. The modified address is held in a temporary
address register so there is no change to the index register. These
are two-byte instructions.
Implied Addressing
In the implied addressing mode the instruction gives the
address (i.e., stack pOinter, index register, etc.). These are
one-byte instructions.
Relative Addressing
In relative addressing, the address contained in the second
byte of the instruction is added to the program counter's lowest
eight bits plus two. The carry or borrow is then added to the
high eight bits. This allows the user to address data within a
range of -126 to + 129 bytes of the present instruction. These
are two-byte instructions.
Direct Addressing
In direct addressing, the address of the operand is contained
D.\ the second byte of the instruction. Direct addressing allows
the user to directly address the lowest 256 bytes in the machine
i.e., locations zero through 255. Enhanced execution times are
achieved by storing data in these locations. In most configurations, it should be a random access memory. These are two-byte
instructions.
Extended Addressing
In extended addressing, the address contained in the second
byte of the instruction is used as the higher eight-bits of the
address of the operand. The third byte of the instruction is used
as the lower eight-bits of the address for the operand. This is an
absolute address in memory. These are three-byte instructions.
Indexed Addressing
In indexed addressing, the address contained in the second
byte of the instruction is added to the index register's lowest
55
HD6801S0, HD6801S6---------------------------------------------
New Instructions
In addition to the existing 6800 Instruction Set, the following new instructions are
incorporated in the HD6801S Microcomputer.
ABX
Adds the 8-bit unsigned accumulator B to the 16-bit X-Register taking into account
the possible carry out of the low order byte of the X-Register.
ADDD Adds the double precision ACCD* to the double precision value M: M+ 1 and places
the results in ACCD.
ASLD Shifts all bits of ACCD one place to the left. Bit 0 is loaded with zero. The C bit is
loaded from the most significant bit of ACCD,
LDD
Loads the contents of double precision memory location into the double
accumulator A:B. The condition codes are set according to the data.
LSRD Shifts all bits of ACCD one place to the right. Bit 15 is loaded with zero. The C bit
is loaded from the least significant bit to ACCD.
MUL
Multiplies the 8 bits in accumulator A with the 8 bits in accumulator B to obtain a
16-bit unsigned number in A:B, ACCA contains MSB of result.
PSHX The contents of the index register is pushed onto the stack at the address contained
in the stack pointer. The stack pointer is decremented by 2.
PULX The index register is pulled from the stack' beginning at the current address
contained in the stack pointer + 1. The stack pointer is incremented by 2 in total.
STD
Stores the contents of double accumulator A:B in memory. The contents of ACCD
remain unchanged.
SUBD Subtracts the contents of M:M + I from the contents of double accumulator AB
and places the result in ACCD.
BRN
Never branches. If effect, this instruction can be considered a two byte NOP (No
operation) requiring three cycles for execution.
CPX
Internal processing modified to permit its use with any conditional branch instruction.
*ACCD is the 16 bit register (A:B) formed by concatenating the A and B accumulators. The A-accumulator is the most significant byte.
Addressing Modes
Pointer Operations
Mnemonic
IMMED.
DIRECT
OP
OP
8C
9C
AC 6
IMPLIED
EXTND
INDEX
OP
OP
2 BC 6
Boolean!
Arithmetic Operation
OP
09
1 SP - 1 -+ SP
CPX
DEX
DES
34
INX
08
X + 1 .... X
INS
31
SP + 1 -+ SP
LOX
CE
LOS
8E
STX
2 EE 5 2 FE
AE 5 2 BE
OF 4 2 EF 5 2 FF
9F 4 2 AF 5 2 BF
DE 4
9E
4 2
X-M: M + 1
X-1-+X
M -+ SP H , (M+ 1) -+ SP L
X H -+ M, XL -+ (M + 1)
STS
TXS
35
X-1-+SP
TSX
30
SP + 1 -+ X
Add
ABX
3A
B+X-+X
Push Data
PSHX
3C
XL -+ M sp , SP - 1 -+ SP
X H .... M sp , SP - 1 -+ SP
Pull Data
PULX
38
The Condition Code Register notes are listed after Table 10.
56
XL
N Z
1 0
V C
.(j) +
.(j) f
(j)f
R
R
I(j) f R
R
----------------------------------------------HD6801SQ, HD6801S6
Table 9 Jump and Branch Instructions
Condition Code
Register
Addressing Modes
Operations
Mnemonic
,------,-----
RELATIVE
OP
DIRECT
OP
INDEX
OP
EXTND
#
OP
Branch Test
IMPLIED
OP
Branch Always
BRA
Branch Never
BRN
21
BCC
24
C=O
BCS
25
C=l
Z=l
20
None
Branch If = Zero
BEQ
27
BGE
2C
N()V=O
> Zero
BGT
2E
Z+(N()V)=O
Branch If Higher
BHI
22
BLE
2F
Branch If
Branch If Lower Or
Same
Branch If
< Zerc
r-- i----
23
C+ Z = 1
2D
NGlV=l
Branch If Minus
BMI
2B
N= 1
BNE
26
Z=O
Branch If Overflow
Clear
BVC
28
v=o
BVS
29
V =1
Branch If Plus
BPL
2A
N=O
80
Branch To Subroutine
BSR
Jump
JMP
Jump To Subroutine
JSR
No Operation
NOP
01
RTI
3B 10 1
Return From
Subroutine
RTS
39
Software Interrupt
SWI
3F
12 1
WAI
3E
7E
AD 6
BD 6
6E
90
Table10
Mnemonic
OP
OC
Cli
OE
0-1
Clear Overflow
CLV
OA
O-V
Set Carry
SEC
00
l-C
SEI
OF
1-1
Set Overflow
SEV
OB
l-V
TAP
06
A .... CCR
TPA
07
CCR - A
S
.
O-+C
R
S
@)
57
S
S
Condition Code Register Notes: (Bit set it test is true and cleared otherwise)
(Bit V)
(Bit C)
(Bit C)
(Bit V)
(Bit V)
(Bit V)
(Bit N)
(All)
(Bit I)
@ (All)
(Bit C)
IMPLIED
CLC
@
@
@
@
@
(j)
@
@
Clear Carry
CD
1
V
--@-
IAddressingModes
Operations
N Z
Z + (N Gl V) = 1
BLS
C+Z=O
BLT
None
--r---
5
H
HD880180, HD880186--------------------------------------------Table 11
ABA
ABX
ADC
ADD
ADDD
AND
ACCX
I~::-
ASL
ASLD
ASR
BCC
BCS
BEQ
BGE
BGT
BHI
BIT
BLE
BLS
BLT
BMI
BNE
BPL
BRA
BRN
BSR
BVC
BVS
CBA
CLC
CLI
CLR
CLV
CMP
COM
CPX
DAA
DEC
EOR
INC
INS
DES
DEX
2
4
2
Direct
3
3
5
3
te~~~
Indexed
1mplied
2
2
3
3
Relative
ACCX
INX
JMP
JSR
LOA
LDD
LOS
LOX
LSR
LSRD
MUL
NEG
NOP
ORA
PSH
PSHX
PUL
PULX
ROL
ROR
RTI
3
3
3
3
6
3
3
RTS
3
3
SBA
SBC
SEC
SEI
SEV
STA
STD
STS
STX
SUB
SUBD
SWI
TAB
TAP
2
2
TBA
TPA
TST
TSX
TXS
WAI
58
3
3
3
5
3
5
5
5
5
5
5
6
4
4
Implied
Relative
.'
10
5
2
5
5
5
5
5
5
4
6
4
4
3
5
3
10
2
2
2
12
2
2
2
3
3
9
-----------------------------------------------HD8801S0, HD8801S6
Addres~
Bus
Data Bus
IMMEDIATE
ADC
ADD
AND
BIT
CMP
EOR
LOA
ORA
SBC
SUB
1
2
Op Code Address
Op Code Address + 1
LOS
LOX
1
2
Op Code Address
Op Code Address + 1
Op Code Address + 2
CPX
SUBD
ADDD
--------
3
1
2
3
4
Op Code
Operand Data
1
1
---~-
---.-~
.. -
--
1
1
1
Op Code
Operand Data (High Order Byte)
Operand Data (Low Order Byte)
Op Code Address
Op Code Address + 1
Op Code Address + 2
Address Bus F F F F
1
1
1
1
Op Code
Operand Data (High Order Byte)
Operand Data (Low Order Byte)
Low Byte of Restart Vector
Op Code Address
Op Code Address + 1
Address of Operand
1
1
1
Op Code
Address of Operand
Operand Data
1
1
------- .._--------
-------
DIRECT
ADC
ADD
AND
BIT
CMP
EOR
LOA
ORA
SBC
SUB
1
2
--r-----
STA
LDS
LDX
LDD
1
2
3
1
2
3
4
Op Code Address
Op Code Address + 1
Destination Address
Op Code
Destination Address
Data from Accumulator
Op Code Address
Op Code Address + 1
Address of Operand
Operand Address + 1
1
1
1
1
Op Code
Address of Operand
Operand Data (High Order Byte)
Operand Data (Low Order Byte)
Op Code Address
Op Code Address + 1
Address of Operand
Address of Operand + 1
1
1
0
0
Op Code
Address of Operand
Register Data (High Order Byte)
Register Data (Low Order Byte)
Op Code Address
Op Code Address + 1
Operand Address
Operand Address + 1
Address Bus F F F F
1
1
1
1
1
Op Code
Address of Operand
Operand Data (High Order Byte)
Operand Data (Low Order Byte)
Low Byte of Restart Vector
Op Code Address
Op Code Address + 1
Subroutine Address
Stack Pointer
Stack Pointer + 1
1
1
1
Op Code
Irrelevant Data
First Subroutine Op Code
Return Address (Low Order Byte)
Return Address (High Order Byte)
.~-~
STS
STX
STD
1
2
3
4
CPX
SUBD
ADDD
1
2
3
4
5
JSR
1
2
3
4
5
0
0
(Continued)
59
Address Bus
Data Bus
INDEXED
JMP
1
2
3
ADC
ADD
AND
BIT
CMP
EOR
LOA
ORA
SBC
SUB
3
4
4
STA
1
2
1
2
3
4
LOS
LDX
LDO
STS
STX
STD
ASL
ASR
CLR
COM
DEC
INC
1
2
3
4
5
1
2
3
4
5
LSR
NEG
ROL
ROR
TST*
1
2
3
4
5
6
CPX
SUBD
AODD
JSR
1
2
3
4
5
6
1
2
3
4
5
6
Op Code Address
Op Code Address + 1
Address Bus F F F F
1
1
1
Op Code
Offset
Low Byte of Restart Vector
Op Code Address
Op Code Address + 1
Address Bus FFFF
Index Register Plus Offset
1
1
1
1
Op Code
Offset
Low Byte of Restart Vector
Operand Data
Op Code Address
Op Code Address + 1
Address Bus FFFF
Index Register Plus Offset
1
1
1
0
Op Code
Offset
Low Byte of Restart Vector
Operand Data
1
1
1
1
1
Op Code
Offset
Low Byte of Restart Vector
Operand Data (High Order Byte)
Operand Data (Low Order Byte)
1
1
1
0
0
Op Code
Offset
Low Byte of Restart Vector
Operand Data (High Order Byte)
Operand Data (Low Order Byte)
..
_ - - - - - - - - _...-
--------
Op Code Address
Op Code Address + 1
Address Bus FFFF
Index Register Plus Offset
Index Register Plus Offset + 1
,...----
_._------
Op Code
Offset
Low Byte of Restart Vector
Current Operand Data
Low Byte of Restart Vector
New Operand Data
Op Code Address
Op Code Address + 1
Address Bus FFFF
Index Register Plus Offset
Address Bus F F F F
Index Register Plus Offset
1
-1
1
1
1
0
Op Code Address
Op Code Address + 1
Address Bus F F F F
Index Register + Offset
Index Register + Offset + 1
Address Bus F F F F
1
1
1
1
1
1
Op Code
Offset
Low Byte of Restart Vector
Operand Data (High Order Byte)
Operand Data (Low Order Byte)
Low Byte of Restart Vector
Op Code Address
Op Code Address + 1
Address Bus F F F F
Index Register + Offset
Stack Pointer
Stack Pointer - 1
1
1
1
1
0
0
Op Code
Offset
Low Byte of Restart Vector
First Subroutine Op Code
Return Address (Low Order Byte)
Return Address (High Order Byte)
*In the TST instruction, R/iN line of the sixth cycle is "1" level, and AB
60
= FFFF,
DB
Vector.
(Continued)
----------------------------------------------HD6801S0, HD6801S6
Table 12 Cycle by Cycle Operation (Continued)
Address Mode &
Instructions
Address Bus
Data Bus
EXTENDED
JMP
1
2
--
ADC
ADD
AND
BIT
CMP
EOR
LOA
ORA
SBC
SUB
STA A
STA B
3
1
2
1
2
3
4
LOS
LOX
LDD
STS
STX
STD
ASL
ASR
CLR
COM
DEC
INC
1
2
3
4
5
1
2
3
4
5
LSR
NEG
ROL
ROR
TST*
1
2
3
4
5
6
CPX
SUBD
ADDD
JSR
1
1
1
Op Code Addre~s
Op Code Address + 1
Op Code Address + 2
Address of Operand
1
1
1
1
~---
3
4
4
Op Code Address
Op Code Address + 1
Op Code Address + 2
1
2
3
4
5
6
1
2
3
4
5
6
Op Code
Op Code
Op Code
Operand
Address
Address + 1
Address + 2
Destination Address
1
1
1
Op Code
Jump Address (High Order Byte)
Jump Address (Low Order Byte)
- - f------Op Code
Address of Operand
Address of Operand (Low Order Byte)
Operand Data
Op Code
Destination Address (High Order Byte)
, Destination Address (Low Order Byte)
Data from Accumulator
Op Code Address
Op Code Address + 1
Op Code Address + 2
Address of Operand
Address of Operand + 1
1
1
1
1
1
Op Code
Address of Operand
Address of Operand
Operand Data (High
Operand Data (Low
Op Code Address
Op Code Address + 1
Op Code Address + 2
Address of Operand
Address of Operand + 1
1
1
1
Op Code
Address of Operand
Address of Operand
Operand Data (High
Operand Data (Low
0
0
Op Code Address
Op Code Address + 1
Op Code Address + 2
Address of Operand
Address Bus FFFF
Address of Operand
Op Code
Address of Operand (High Order Byte)
Address of Operand (Low Order Byte)
Current Operand Data
Low Byte of Restart Vector
New Operand Data
Op Code Address
Op Code Address + 1
Op Code Address + 2
Operand Address
Operand Address + 1
Address Bus FFFF
1
1
1
1
1
1
Op Code
Operand Address (High Order Byte)
Operand Address (Low Order Byte)
Operand Data (High Order Byte)
Operand Data (Low Order Byte)
Low Byte of Restart Vector
1
1
1
1
Op Code
Address of Subroutine (High Order Byte)
Address of Subroutine (Low Order Byte)
Op Code of Next Instruction
Return Address (Low Order Byte)
Address of Operand (High Order Byte)
1
1
1
1
1
a
a
"In the TST instruction. R/W line of the sixth cycle is "'" level. and AB=FFFF. DB=Low Byte of Reset Vector,
61
(Continued)
Data Bus
Address Bus
IMPLIED
ABA
ASL
ASR
CBA
CLC
CLI
CLR
CLV
COM
DAA
DEC
INC
LSR
NEG
NOP
ROL
ROR
SBA
SEC
SEI
SEV
TAB
TAP
TBA
TPA
TST
ABX
ASLD
LSRD
DES
INS
INX
DEX
PSHA
PSHB
TSX
1
2
3
1
2
3
1
2
3
1
2
3
1
2
3
1
2
3
TXS
2
3
PULA
PULB
1
2
3
4
PSHX
1
2
3
4
PULX
WAI**
1
1
Op Code
Op Code of Next Instruction
Op Code Address
Op Code Address + 1
Address Bus F F F F
1
1
1
1
1
1
Op Code
Irrelevant Data
Low Byte of Restart Vector
1
1
1
1
1
1
Op Code
Op Code of Next Instruction
Irrelevant Data
1
1
Op Code Address
Op Code A.ddress + 1
Address Bus F F F F
Op Code Address
Op Code Address + 1
Previous Register Contents
Op Code Address
Op Code Address + 1
Address Bus F FFF
Op Code
Op Code of Next Instruction
Low Byte of Restart Vector
Op Code
Op Code of Next Instruction
Accumulator Data
Op Code Address
Op Code Address + 1
Stack Pointer
1
1
1
Op Code
Op Code of Next Instruction
Irrelevant Data
Op Code Address
Op Code Address + 1
Address Bus F F F F
1
1
1
Op Code
Op Code of Next Instruction
Low Byte of Restart Vector
Op Code Address
Op Code Address + 1
Stack Pointer
Stack Pointer + 1
1
1
1
1
Op Code
Op Code of Next Instruction
Irrelevant Data
Op Code Address
Op Code Address + 1
Stack Pointer
Stack Pointer - 1
1
1
Op Code
Irrelevant Data
Index Register (Low Order Byte)
Index Register (High Order Byte)
0
0
3
4
5
1
2
3
4
1
1
1
1
1
1
1
1
1
Stack Pointer + 2
1
2
Op Code Address
Op Code Address + 1
Stack Pointer
Stack Pointer - 1
1
1
3
4
Op Code
Irrelevant Data
Low Byte of Restart Vector
Op Code Address
Op Code Address + 1
Stack Pointer
Op Code Address
Op Code Address + 1
Stack Pointer
Stack Pointer + 1
Stack Pointer +2
Op Code Address
Op Code Address + 1
Stack Pointer
Stack Pointer + 1
RTS
Op Code Address
Op Code Address + 1
62
0
0
OpCode
Irrelevant Data
Irrelevant Data
Index Register (High Order Byte)
Index Register (Low Order Byte)
Op Code
Irrelevant Data
Irrelevant Data
Address of Next Instruction
(High Order Byte)
Address of Next Instruction
(Low Order Byte)
Op Code
Op Code of Next Instruction
Return Address (Low Order Byte)
Return Address
IHiah Order Bvtel
(Continued)
-------------------------------------------HD8B01S0, HD8801S6
Table 12 Cycle by Cycle Operation (Continued)
Address Mode &
Instructions
WAI**
Cycles.
Cycle
#
5
6
7
8
9
MUL
10
SWI
10
12
Stack
Stack
Stack
Stack
Stack
Pointer
Pointer
Pointer
Pointer
Pointer
2
3
4
5
6
R/W
Line
0
0
0
0
0
Data Bus
Index Register (Low Order Byte)
Index Register (High Order Byte)
Contents of Accumulator A
Contents of Accumulator B
Contents of Condo Code Register
Op Code Address
Op Code Address + 1
Address Bus F F F F
Address Bus F F F F
Address Bus F F F F
Address Bus F F F F
Address Bus F F F F
Address Bus FFFF
Address Bus FFFF
Address Bus F F F F
1
1
1
1
1
1
1
1
1
1
Op Code
Irrelevant
Low Byte
Low Byte
Low Byte
Low Byte
Low Byte
Low Byte
Low Byte
Low Byte
Op Code Address
Op Code Address + 1
Stack Pointer
Stack Pointer + 1
1
1
1
1
Stack Pointer + 2
Stack Pointer + 3
Stack Pointer + 4
Stack Pointer + 5
Stack Pointer + 6
10
Stack Pointer + 7
OpCode
Irrelevant Data
Irrelevant Data
Contents of Condo Code Reg.
from Stack
Contents of Accumulator B
from Stack
Contents of Accumulator A
from Stack
Index Register from Stack
(High Order Byte)
Index Register from Stack
(Low Order Byte)
Next Instruction Address from
Stack (High Order Byte)
Next Instruction Address from
Stack (Low Order Byte)
1
2
3
4
Op Code Address
Op Code Address + 1
Stack Pointer
Stack Pointer - 1
1
1
0
0
5
6
7
10
11
Stack Pointer Stack Pointer Stack Pointer Stack Pointer Stack Pointer Stack Pointer Vector Address
2
3
4
5
6
7
FFFA (Hex)
0
0
0
0
0
1
1
12
1
2
3
4
5
6
7
8
9
RTI
Address Bus
10
1
2
3
4
8
9
Data
of Restart
of Restart
of Restart
of Restart
of Restart
of Restart
of Restart
of Restart
Vector
Vector
Vector
Vector
Vector
Vector
Vector
Vector
Op Code
Irrelevant Data
Return Address (Low Order Byte)
Return Address
(High Order Byte)
Index Register (Low Order Byte)
Index Register (High Order Byte)
Contents of Accumulator A
Contents of Accumulator B
Contents of Condo Code Register
Irrelevant Data
Address of Subroutine
(High Order Byte)
Address of Subroutine
(Low Order Byte)
**While the MPU is in the "Wait" state, its bus state will appear as a series of MPU reads of an address which is seven locations less than the
original contents of the Stack Pointer. Contrary to the HD6800, none of the ports are driven to the high impedance state by a WAI instruction.
(Continued)
63
HD6801S0, HD6801S6---------------------------------------------Table 12
Data Bus
Address Bus
RELATIVE
Bce
BCS
BEQ
BGE
BGT
BRN
BHT
BlE
BLS
BlT
BMT
BNE
BPL
BRA
BVC
BVS
BSR
1
2
3
Op Code Address
Op Code Address + 1
Address Bus FFFF
1
1
1
Op Code
Branch Offset
Low Byte of Restart Vector
Op Code Address
2
3
4
Op Code Address + 1
Address Bus FFFF
Subroutine Starting Address
Stack Pointer
Stack Pointer - 1
1
1
1
1
Op Code
Branch Offset
Low Byte of Restart Vector
Op Code of Next Instruction
Return Address (Low Order Byte)
Return Address (High Order Byte)
5
6
When the op codes (4E, 5E) are used to execute, the MPU
continues to increase the program counter and it will not stop
until the Reset signal enters. These op codes are used to test the
Table 13
H06aal S
ACC
A
~
0000
0001
1
2
0010
0011
0100
0101
0110
-------
0001
0010
3
TSX
CBA
BRN
INS
BHI
PULA (+1)
BLS
PULB (+1)
BCC
DES
ASLD (+1)
BCS
TXS
TAP
TAB
BNE
PSHA
0111
TPA
TBA
BEQ
PSHB
1000
INX (+1)
BVC
PULX (+2)
1001
DEX (+1)
DAA
BVS
RTS (+2)
1010
CLV
BPL
ABX
1011
SEV
ABA
BMI
RTI (+7)
1100
CLC
BGE
PSHX (+1)
1101
SEC
/'
BLT
MUL (+7)
1110
CLI
BGT
WAI (+6)
1111
SEI
BLE
SWI (+9)
112
1/2
2/3
1/3
BYTE/CYCLE
[NOTES)
ACCA orSP
EXT
-----------4
2
BRA
--
ACC IND
B
LSRD (+1)
Op codes Map
0011
SBA
NOP
LSI.
MICROCOMPUTER INSTRUCTIONS
OP
CODE
0000
a
a
IMM
DIR
IND
1000 1001
ACCB or X
EXT
1010 1011
A
IMM
DIR
IND
1100 1101
EXT
1110 1111
E
F
0
SUB
NEG
=------==
COM
CMP
SBC
SUBD (+2)
ADDD (+2)
3
4
LSR
AND
BIT
ROR
LDA
ASR
STA
STA
EOR
ASL
ROL
ADC
DEC
ORA
INC
TST
--- .. ---
JMP (-3)
1/2
2/6
ADD
CPX (+2)
r;4~
JSR (+2)
3/6
2/2
2/4
"
3/4
2/2
STX(+l1
2/3
~.
3) The instructions shown below are all 3 bytes and are marked with ".".
Immediate addressing mode of SUBD, CPX, LOS, ADDD, LDD and LDX instructions, and undefined op codes
(SF, CD, CF).
64
D
E
LOX (+1)
) indicate that the number in parenthesis must be added to the cycle count for that instruction.
4) The Op codes (4E, 5E) are 1 byte/oo cycles instructions, and are marked with " ".
STD(+l1
(+11
STS (+1)
2/3
B
LDD(+1)
: (+1)
LDS (+1)
: (+1)
CLR
1/2
2/4
3/4
en
01
*SCI
= TIETORE + RIE(RORF
+ ORFE)
Vector .... PC
NMI
FFFC FFFO
Non-Maskable Interrupt
SWI
FFFA FFFB
Software Interrupt
IRQ,
ICF
OCF
TOF
SCI
FFF8 FFF9
FFF6
FFF4
FFF2
FFFO
FFF7
FFF5
FFF3
FFF1
:r:
CO
( I)
:r:
c
m
CO
o
Figure 24 Interrupt Flowchart
( I)
en
HD6801SQ, HD6801S6
vee
vee
t::I
Enable
Enable
NMI
iiiMi
IRQ,
Vee Standby
Port 3
8 Transfer
RES
Lines
Port 1
8110
Port 1
8110 L,nes
Lines
Port 2
51/0 Lines
Port 4
8 I/O Lines
SCI
Vss
VSS
Figure 25
Port 4
8110 Lohes
Port 2
5110 Lines
SCI
HD6801S
MCU
Address
Bus
Data
Bus
Address Bus
Data Bus
66
HD6801VO,HD6801V5
MCU (Microcomputer Unit)
The HD6801V MCV is an 8-bit microcomputer system which
is compatible with the HD6801S except the ROM size. The
HD6801V MCV is object code compatible with the HD6800
with improved execution times of key instructions plus several
new 16-bit and 8-bit instructions including an 8x8 unsigned
multiply with 16-bit result. The HD6801V MCV can operate as
a single chip microcomputer or be expanded to 65k words. The
HD6801V MCV is TTL compatible and requires one +5.0 volt
power supply. The H0680 1V MCV has 4k bytes of ROM and
128 bytes of RAM on chip. Serial Communications interface
(SCI), and parallel I/O as well as a three function 16-bit timer.
Features and Block diagram of the HD6801V include the
following:
-PRELIMINARY-
HD6801VOP
HD6801V5P
(DP-40)
FEATURES
Expanded HMCS6800 Instruction Set
8 x 8 Multiply
On-Chip Serial Communications Interface (SCI)
16-Bit Timer
Single Chip Or Expandable To 65k Words
4k Bytes Of ROM
128 Bytes Of RAM (64 Bytes Retainable On Power
Down)
P"
P"
P lO
P"
P"
P"
BLOCK DIAGRAM
PIN ARRANGEMENT
SC,
SC,
P
'O
P"
P"
P"
P"
HD6801V
P"
1 P,.
P 17
p,.
P"
P"
P"
P"
P"
P'6
P.,
1 Vcc Standby
(Top View)
~--+-j---+- P20
~~---+-P21
~1-r-------P22
1--Hf-+..t-P23
P2.
TYPE OF PRODUCTS
MCU
67
Bus Timing
HD6801VO
1 MHz
HD6801V5
1.25 MHz
HD6801VO, HD6801V5---------------------------------------------
Vee
V in
Input Voltage
Operating Temperature
*
*
Topr
Tstg
. Storage Temperature
*
Value
Unit
-0.3 - +7.0
-0.3 - +7.0
0 -+70
V
c
- 55 -+150
Symbol
Supply Voltage
ELECTRICAL CHARACTERISTICS
Symbol
RES
V 1H
Other Inputs*
All Inputs*
P40 - P47
SCI
EXTAL
Ilinl
lIinl
VIL
P30
P40
P37
P47 , E, SCI, SC 2
All Outputs
Pl7
typ
max
Vee
2.0
-0.3
Vee
0.8
Vin = 0 - 2.4V
V in = 0 - 5.25V
IITsd
V in = 0.5 - 2.4V
V OH
I LOAD = -205p.A
I LOAD = -145p.A
2.4
2.4
2.4
VOL
-IOH
V out = 1.5V
pther Outputs
Output "Low" Voltage
min
4.0
V in = 0- Vee
Test Condition
P47 , SCI
Cin
Operating
VSBB
V SB
Powerdown
ISBB
68
mA
2.5
10
p.A
100
1.0
V in = OV, Ta = 25C,
f = 1.0 MHz
V SBB = 4.0 V
0.8
0.8
0.5
Po
"'"
Unit
p.A
0.5
10.0
mA
1200
mW
12.5
4.0
5.25
4.75
5.25
8.0
10.0
pF
V
rnA
----------------------------------------------HD6801VO, HD8801V5
AC CHARACTERISTICS
BUS TIMING (Vee = 5.0V5%, Vss = OV, Ta = 0 - +70C, unless otherwise noted.)
Symbol
Item
Cycle Time
Address Strobe Pulse Width "High"
tCYC
PW ASH
tASr
tASf
tASD
tEr
tEf
PW EH
PW EL
I
I
Non-Multiplexed Bus
Multiplexed Bus
Oscillator stabilization Time
50
60
5
5
50
-
50
50
30
50
50
-
5
5
340
350
50
50
30
260
260
60
tDSR
tHR
tHW
80
10
ns
ns
ns
20
50
ns
20
ns
10
20
60
20
ns
20
ns
(410)
(400)
ns
100
ms
200
ns
(tACCM)
(610)
(600)
100
ns
ns
--
200
liS
115
70
20
5
5
260
270
-
Fig. 10
Fig. 11
150
Unit
ns
ns
ns
ns
ns
ns
ns
ns
(tACCN)
tRC
tpcs
tAHL
tAH
tASL
HD6801V5
typ
max
10
225
min
0.8
tDsw
Peripheral Read
Access Time
HD6801VO
typ
max
10
200
Fig. 1
Fig. 2
tADL
Read
Write
min
1
450
450
tASED
tAD
Test Condition
Symbol
Test Condition
min
typ
max
Port 1, 2,3,4
t posu
Fig. 3
200
ns
Port 1, 2,3,4
tpOH
Fig. 3
200
ns
tOS01
Fig. 5
350
ns
tOS02
Fig. 5
350
ns
Port 1, 2*,3,4
tpwo
Fig.4
400
ns
*
Port 2**, 4
tCMos
Fig.4
2.0
/.ls
ns
Item
tPWIS
Fig. 6
200
tlH
Fig. 6
50
Port 3
tiS
Fig. 6
20
*Except P 2t
69
Unit
ns
ns
HD6801VO, HD6801V5---------------------------------------------TIMER, SCI TIMING (Vee = 5.0V 5%, Vss = OV, Ta = 0'" +70C, unless otherwise noted.)
Item
Timer Input Pulse Width
Delay Time, Enable Positive Transition to
Timer Out
SCI Input Clock Cycle
SCI Input Clock Pulse Width
Symbol
Test Condition
tpWT
Fig. 7
tTOD
tSCyc
max
-
Unit
ns
600
ns
0.6
tcyC
tScYc
0.4
tPWSCK
Item
Mode Programming Input "Low" Voltage
Mode Programming Input "High" Voltage
RES "Low" Pulse Width
Mode Programming Set-up Time
Mode Programming Hold Time
Symbol
VMPL
VMPH
PW RSTL
t MPS
tMPH
Test Condition
Fig. 8
min
4.0
3.0
2.0
150
~---------------------t~----------------------~
Address Strobe
(ASI
2.2V
Enable
(EI
R/Vii, Ar-Ae
(SC~
typ
min
2t cyc +200
(port41
MPUWrite
Do-D"A.-A,
(Pori 31
MPU Read
0.-0,. A.-A,
(Pori 31"
70
typ
-
max
1.7
-.
Unit
V
V
tcyC
tcyc
ns
----------------------------------------------HD6801VO. HD6801V6
L
tcyc
'(..
2.4V
Enable
(EI
PWEL
Ao--A,(Port4 )
Rfji
iOS
(5C2)
(5C,)
-J
O.5V-~
I+--tAO-
-'r-
PWEH
--
I+-tEr
-'~
-tEf
1-
2.2V~""
\.
Address Valid
0.6V'
-tosw-
MPUWrite
2. 2V f"
j
0.-0,
(Port3)
0.6V\+--tOSR-
0.-0,
(Port 3)
-.
2.0V
------------------------------------------(1
-tHW
..
Data Valid
(tACCNI
MPU Read
-tAH
,~
-tHR
Data Valid
O.SV I'-------------Jj
rMPUWrite
r-MPURead
Enable(E)
Enable(E)
PIO - PI'
P,o - p ..
p. o - P.,
All Data
Port Outputs
Inputs
_ _ _ _ _ _ _J
~.~~
Data Valid
P so - P"
Inputs"
(Note)
1. 10
Figure 3
2. Not applicable to P I
3. Port 4 cannot be pulled above Vee
Figure 4
Enable(E)
Address
Sus
0 5 3 - - - - -......
PSO
P"
Inputs
Figure 5
Figure 6
71
HD8801V'O, H D 8 8 0 1 V 5 - - - - - - - - - - - - - - - - - - - - - - -
Enable
(E)
Timer
Counter
----oJ
(~~~,'~;~:: 1-----.;.;;.;.-<:1
i"""------JJ
P"
Output
Figure 8
Figure 7
Vee
Test Point
O-----r. .
RL =2.2kO
Test Point
130PF
lS2074
or Equlv.
Lo.' In"'uwon
_I
.,
Cycl~
.1
M3
I ..
Inleo,nal
Add,e"
NMi or
8Ui-"'---+'~
_+','--_"...--''----''-_''__ _''___
_''_~r'__...J'Io..__J\._...J'__
_''_~~_....,.,'___
*----..,
IRO:
~ !--'PCS
Data
8us.~--"--..J'.......-"'-_~"--...
Op Code
Inlt,nal R/ii
IRQ2
.--
Internal Interrupt
ACeS
\~----------------------------~I
Vector
MSB
Vector
LSB
First Inst. of
Interrupt Routine
=,
PCS-PCIS Pca-PC]
F""
InstruCllon
~NOlvarld
72
------------------------------------------------HD6801VO, HD6801V5
SIGNAL DESCRIPTIONS
Vcc
and
vss
These two pins are used to supply power and ground to the
chip. The voltage supplied will be +5 volts 5%.
XT AL and EXT AL
4 MHz
5 MHz
Co
7 pF max.
4.7 pF max.
Rs
60n max.
30n typo
Item
XTAL~--~------~
c L1 = CL2 = 22pF
20%
(3.2 - 5 MHz)
EXT A L
~--
___--,
Jr
CL1
tL2
Vcc Standby
This pin will supply +5 volts 5% to the standby RAM on the
chip. The first 64 bytes of RAM will be maintained in the power
down mode with 8 rnA current max. The circuit of figure 13
can be utilized to assure that Vee Standby does not go below
VSBB during power down.
To retain information in the RAM during power down the
following procedure is necessary:
1) Write "0" into the RAM enable bit, RAM E. RAM E is bit
6 of the RAM Control Register at location $0014. This
disables the standby RAM, thereby protecting it at power
down.
2) Keep Vee Standby greater than VSBB.
Reset (RES)
This input is used to reset and start the MPU from a power
down condition, resulting from a power failure or an initial
startup of the processor. On power up, the reset must be held
"Low" for at least 100 ms. During operation, RES, when
brought "Low" must be held "Low" at least 3 clock cycles.
When a "High" level is detected, the MPU does the following:
I) All the higher order address lines will be forced "High".
2) I/O Port 2 bits, 2, 1, and 0 are latched into programmed
control bits PC2, PC 1 and PCO.
3) The last two ($FFFE, $FFFF) locations in memory will
be used to load the program addressed by the program
counter.
4) The interrupt mask bit is set, must be cleared before the
MPU can recognize maskable interrupts.
Enable (E)
This supplies the external clock for the rest of the system
when the internal oscillator is used. It is a single phase, TTL
compatible clock, and will be the divide by 4 result of the
crystal frequency. It will drive one TTL load and 90 pF.
A low-going edge on this input requests that a non-maskableinterrupt sequence be generated within the processor. As with
interrupt Request signal, the processor will complete the current
instruction that is being executed before it recognizes the NMI
signal. The interrupt mask bit in the Condition Code Register
has no effect on NMI.
In response to an NMJ interrupt, the Index Register, Program
Counter, Accumulators, and Condition Code Register are stored
on the stack. At the end of the sequence, a 16-bit address will
be loaded that points to a vectoring address located in memory
locations $FFFC and $FFFD. An address loaded at these locations causes the MPU to branch to a non-maskable interrupt
service routine in memory.
A 3.3 krl external resistor to Vee should be used for
wire-OR and optimum control of interrupts.
Inputs IRQ, and NMI are hardware interrupt lines that are
sampled during E and will start the interrupt routine on the
E following the completion of an instruction.
Highest
Priority
Lowest
Priority
PORTS
There are four I/O ports on the HD680 1V MCV; three 8-bit
ports and one 5-bit port. There are two control lines associated
with one of the 8-bit ports. Each port has an associated write
only Data Direction Register which allows each I/O line to be
programmed to act as an input or an output*. A "1" in the
corresponding Data Direction Register bit will cause that I/O
line to be an output. A "0" in the corresponding Data Direction
Register bit will cause that I/O line to be an input. There are
four ports: Port 1, Port 2, Port 3, and Port 4. Their addresses
and the addresses of their Data Direction registers are given in
Table 2.
Interrupt
LSB
FFFE
FFFF
RES
FFFC
FFFD
NMI
FFFA
FFFB
FFF8
FFF9
FFF6
FFF7
FFF4
FFF5
FFF2
FFF3
FFFO
FFF1
The following pins are available in the Single Chip Mode, and
are associated with Port 3 only.
Ports
Port Address
Data Direction
Register Address
1/0 Port 1
$0002
$0000
1/0 Port 2
$0003
$0001
1/0 Port 3
$0006
$0004
I/O Port 4
$0007
$0005
I/O Port 1
This is an 8-bit port whose individual bits may be defined as
inputs or outputs by the corresponding bit in its data direction
register. The 8 output buffers have three-state capability,
allowing them to enter a high impedance state when the
peripheral data lines are used as inputs. In order to be read
properly, the voltage on the input lines must be greater than 2.0
V for a logic "1" and less than 0.8 V for a logic "0". As outputs these Jines are TTL compatible and may also be used as
a source of up to 1 rnA at 1.5 V to directly drive a Darlington
base. After Reset, the I/O lines are configured as inputs. In all
three modes, Port 1 is always parallel I/O.
I/O Port 2
This port has five lines that may be defined as inputs or
outputs by its data direction register. The 5 output buffers have
three-state capability, allowing them to enter a high impedance
state when used as an input. In order to be read properly, the
voltage on the input lines must be greater than 2.0 V for a
logic "I" and less than 0.8 V for a logic "0". As outputs, this
port has no internal pullup resistors but will drive TTL inputs
directly. For driving CMOS inputs, external pull up resistors are
required. After Reset, the I/O lines are configured as inputs.
Three pins on Port 2 (pins 10, 9, and 8 of the chi p) are used
to program the mode of operation during reset. The values of
these pins at reset are latched into the three MSB's (bits 7 6
and 5) of Port 2 which are read only. This is explained in ~h~
Mode Selection Section.
In all three modes, Port 2 can be configured as I/O and
provides access to the Serial Communications Interface and the
Timer. Bit 1 is the only pin restricted to data input or Timer
output.
I/O Port 3
This is an 8-bit port that can be configured as I/O, a data bus,
or an address bus multiplexed with the data bus - depending on
the mode of operation hardware programmed by the user at
reset. As a data bus, Port 3 is bi-directional. As an input for
peripherals, it must be supplied regular TTL levels, that is,
greater than 2.0 V for a logic "1" and less than 0.8 V for a logic
"0"
74
----------------------------------------------HD6801VO, HD6801V5
Its TTL compatible three-state output buffers are capable of
driving one TTL load and 90 pF. In the Expanded Modes, after
reset, the data direction register is inhibited and data flow
depends on the state of the R/W line. The input strobe (IS3)
and the output strobe (OS3) used for handshaking are explained
later.
In the three modes, Port 3 assumes the following characteristics:
Single Chip Mode: Parallel Inputs/Outputs as programmed by
its associated Data Direction Register. There are two control
lines associated with this port in this mode, an input strobe and
an output strobe, that can be used for handshaking. They are
controlled by the I/O Port 3 Control/Status Register explained
at the end of this section. Three options of Port 3 operations
are sumarized as follows: (1) Port 3 input data can be latched
using IS3 (SC,) as a control signal, (2) OS) can be generated by
eithe~ MPV read or write to Port 3's Data Register, and (3)
and IRQ, interrupt can be enabled by an IS3 negative edge.
Port 3 latch and strobe timing is shown in Fig. 5 and Fig. 6.
Expanded Non-Multiplexed Mode: In this mode, Port 3
becomes the data bus (Do -D 7).
Expanded Multiplexed Mode: In this mode, Port 3 becomes
both the data bus (D o-D 7) and lower bits of the address bus
(Ao-A7)' An address strobe output is true when the address is
on the port.
153
$ooOF
Bit 0;
Bit 1;
Bit 2;
Bit 3;
Bit 4;
Bit 5;
Bit 6;
Bit 7;
FLAG
153
055
LATCH
IRQ l
ENABLE
o
X
OPERATION MODES
7654
load and 90 pF. After reset, the lines are configured as inputs.
To use the pins as addresses, therefore, they should be
programmed as outputs. In the three modes, Port 4 assumes the
following characteristics:
Single Chip Mode: Parallel Inputs/Outputs as programmed by
its associated Data Direction Register.
Expanded Non-Multiplexed Mode: In this mode, Port 4 is
configured as the lower order address lines (Ao ...... A, ) by writing
one's to the data direction register. When all eight address lines
are not needed, the remaining lines, starting with the most
Significant bit, may be used as I/O (inputs only).
Expanded Multiplexed Mode: In this mode, Port 4 is
configured as the higher order address lines (A s ...... A1s ) by writing one's to the data direction register. When all eight address
lines are not needed, the remaining lines, starting with the most
Significant bit, may be used as I/O (inputs only).
PC2
PCl
I IlIa
PCO
210
411/0 311/0 211/0 1
IlIa
ENABLE
Not used.
Not used.
Not used.
LATCH ENABLE. This controls the input latch for I/O
Port 3. If this bit is set "High" the input data will be
latched with the falling edge of the Input Strobe, IS3.
This bit is cleared by reset, and the latch is "re-opened"
with MCV read Port 3.
OSS. (Output Strobe Select) This bit will select if the
Output Strobe should be generated at OS3 (SC 2 ) by a
write to I/O Port 3 or a read of I/O Port 3. When this bit
is cleared the strobe is generated by a read Port 3. When
this bit is set the strobe is generated by a write Port 3.
Not used.
IS3 IRQl ENABLE. When set, interrupt will be enabled
whenever IS3 FLAG is set; when clear, interrupt is
inhibited. This bit is cleared by RES.
IS3 FLAG. This is a read only status bit that is set by
the falling edge of the input strobe, IS3 (SC d. It is
cleared by a read of the Control/Status Register followed by a read or write of I/O Port 3. Reset will clear
this bit.
In the Single Chip Mode the Ports are configured for I/O.
This is shown in Figure 16 the single Chip Mode. In this
mode, Port 3 will have two associated. control lines, an input
strobe and an output strobe for handshaking data.
I/O Port 4
75
HD6801VO. HD6801V5-----------------------------------------------Vee
0
')
RI RI RI
6
IJI
A B C
HD6801V
Xo
...--
Yo
Zo
XI
RES
9
10
P20 (PCO)
P21 (PC1)
P22 (PC2)
YI
ZI
C
???
~
Mode
Control
Switch
HD14053B
Inh
[NOTES)
Jr
1) Mode 7 as shown
2) RC'-'Reset time constant
3) R I =10kn
Inh
Binary to 1-of-2
Decoder with
Inhibit
A
B
C
Xocr-----------------K~~~+-~~
XI~------------------~~-+~--~
Y0
)------------K':>I+--I--+_~
ylcr-----------------~~~-~
Zocr------------------~~--,
Zlcr-------------------------~~~
x
y
On Switch
Select
Inhibit
HD14053B
B A
Zo Yo XI
1 0
Zo Y I Xo
Zo VI XI
1 0
ZI Yo Xo
1 0
ZI Yo XI
1 0
ZI Y I Xo
ZI Y I XI
X X X
Zo Yo Xu
Vee
Vee
40
Port 1
8 I/O Lines
Port 3
8 I/O Lines
Port 4
8 I/O Lines
Port 2
5 I/O Lines
Vss
Enable
Enable
SCI
Timer
Port 1
8 Parallel I/O
Port 3
8 Data Lines
Port 2
5 Parallel I/O
SCI
Timer
Port 4
To 8 Address
Lines or To
7 I/O Lines
(Inputs Onlv)
76
------------------------------------------------HD6801VO, HD6801V5
Vee
Enable
8 lines
Multiplexed
Data/Address
Port 1
8 I/O Lines
Port 2
5 I/O Lines
SCI
Timer
Port 4
To 8 Address
Lines or To
7 I/O Lines
(Inputs Only)
Vss
GND
AS
G DC
0,
Port 3
Address/Data
Q,
Os
Function Table
Add"" A, -A,
74LS373
Qs
Output
Control
Enable
0
L
L
L
H
H
L
Output
X
X
D", D,-D,
This section gives a description of the MCU signals for the various modes. SCI and SC 2 are signals which vary with the mode
that the chip is in.
MODE
SINGLE CHIP
PORT 1
Eight Lines
PORT 2
Five Lines
I/O
PORT 3
Eight Lines
PORT 4
Eight Lines
SCI
SC 2
I/O
I/O
I/O
IS3 (I)
OS3 (0)
ADDRESS BUS*
(As-A Is )
AS(O)
Rm(O)
ADDRESS BUS*
(Ao -A 7 )
10S(0)
RIW(O)
EXPANDED MUX
I/O
I/O
ADDRESS BUS
(Ao -A7 )
DATA BUS
(0 0 -0 7 )
EXPANDED 'NON-MUX
I/O
I/O
DATA BUS
(0 0 -0 7 )
*These lines can be substituted for 110 (Input Only) starting with the most significant address line.
I = Input
153 = Input Strobe
SC = Strobe Control
o = Output
OS3 = Output Strobe
AS = Address Strobe
R/W = Read/Write
IDS = 110 Select
77
HD6801VO,
P11
(PC2)
P11
(PClI
P20
(PCO)
ROM
RAM
H
H
I
MUX(6)
NMUX(6)
1(2)
1(1)
MUX
MUX
Multiplexed/RAM
MUX
1(3)
MUX
Multiplexed Test
MoCile
LEGEND:
I-Internal
E - External
MUX - Multiplexed
NMUX - Non-Multiplexed
L - Logic "0"
H - Logic "1"
Interrupt
Vectors
MEMORY MAPS
Single Chip
Multiplexed/Partial Decode
Non-Multiplexed/Partial Decode
Single Chip Test
Register
Address
Port
Port
Port
Port
1 Data
2 Data
1 Data
2 Data
Direction Register***
Direction Register***
Register
Register
00
01
02
03
Port
Port
Port
Port
3
4
3
4
Direction Register***
Direction Register*"
Register
Register
04*
05**
06*
07**
08
09
OA
OB
OC
00
OE
OF*
10
11
12
13
INTERRUPT FLOWCHART
The Interrupt flowchart is depicted in Figure 24 and is common to every interrupt excluding reset.
Operating
Mode
[NOTES)
1) Internal RAM is addressed at $XX80
2) Internal ROM is disabled
3) RES vector is external for 2 cycles after RES goes "High"
4) Addresses associated with Ports 3 and 4 are considered external in Modes O.
1.2. and 3
5) Addresses associated with Port 3 are considered external in Modes 5 and 6
6) Port 4 default is user data input; address output is optional by writing to Port 4
Data Direction Register
The MCU can provide up to 65k byte address space depending on the operating mode. A memory map for each operating
mode is shown in Figure 20. The rust 32 locations of each map
are reserved for the MCU's internal register area, as shown in
Table 4. With exceptions as indicated.
Data
Data
Data
Data
Bus
Mode
14
15-1F
78
------------------------------------------------HD6801VO, HD6801V5
HD6801V
Mode
HD6B01V
Mode
$0000(1)
$0000(1)
Internal Registers
Internal Registers
$001F
$001F
$0080
Internal RAM
Internal RAM
$OOFF
$OOFF
$FOOO
Internal ROM
$FFEF
Internal ROM
$FFFO
Internal Interrupt Vectors(2
[NOTES)
$FFFF-----
[NOTES]
1) Excludes the following addresses which may
be used externally; $04, $05, $06, $07 and
$OF.
2) Internal ROM addresses $FFFOto $FFFF are
not usable.
79
HD8801VO, HD8801V6----------------------------------------------
HD6801V
Mode
HD6801V
Mode
Multiplexed/RAM
$0000(1)
$0000(1)
} Internal Registers
Internal Registers
$001F
$OOlF
Internal RAM
$OOFF
$FFFO 1 - - - - - 1 .
$FFFF ' -_ _ _.... }
[NOTE]
1) Excludes the following addresses which may
be used externally: $04, $05, $06, $07, and
[NOTE]
1) Excludes the following addresses which may
be used externally: $04, $05, $06, $07 and
$OF.
$OF.
80
------------------------------------------------HD6801VO, HD6801V5
HD6801V
HD6801V4
Mode
Mode
Non-Multiplexed/Partial Decode
$0000(1)
$0000
Internal Registers
Internal Registers
$001F
$001F
$0080
}
$OOFF
$0100
$01 FF
U
Internal RAM
~_,.-_""
(1)(4)
$FOOO
Internal ROM
$XX80
$XXFF
Internal RAM
Internal Interrupt Vectors
$FFFF
(NOTES]
1) Excludes the following addresses which may
not be used externally': $04, $06, and $OF.
(No 105)
2) This mode may be entered without going
through RES by using Mode 4 and subsequently writing a "1" into the PCO bit of
Port 2 Data Register.
3) Address lines Ao -A? will not contain addresses until the Data Direction Register for Port 4
has been written with "1's" in the appropriate
bits. These address lines will assert "1's" until
made outputs by writing the Data Direction
Register.
(NOTES]
1) The internal ROM is disabled.
2) Mode 4 may be changed to Mode 5 without
having to assert RESET by writing a "1" into
the PCO bit of Port 2 Data Register.
3) Addresses As to AI5 are treated as "don't
cares" to decode internal RAM.
4) Internal RAM will appear at $XX80 to $XXF F.
81
HD6801VO, HD6801V5----------------------------------------------
HD6801V7
Mode
HD6801V6
Mode
Single Chip
Multiplexed/Partial Decode
$0000(1)
$OOlF
Internal Registers
Internal Registers
$0080
Internal RAM
$OOFF
$OOFF
$FOOO
$FFFF
$FOOO
Internal ROM
Internal ROM
[NOTES]
1) Excludes the following address which may be
used externally: $04, $06, $OF.
2) Address lines A8 -A,s will not contain
addresses until the Data Direction Register for
Port 4 has been written with "l's" in the
appropriate bits. These address lilies will
assert "l's" until made outputs by writing the
Data Direction Register.
82
------------------------------------------------HD6801VO, HD6801V5
PROGRAMMABLE TIMER
the output level register value will appear on the pin for Port 2
Bit 1. The values in the Output Compare Register and Output
level bit may then be changed to control the output level on the
next compare value. The Output Compare Register is set to
$FFFF during RES. The Compare function is inhibited for
one cycle following a write to the high byte of the Output
Compare Register to insure a valid 16-bit value is in the register
before a compare is made.
IRO,
,.-_ _ _-., OE
Output Input
Level
Edge
Bit 1
Bit 0
Port 2 Port 2
Figure 21
83
7
ICF
6
OCF
OLVLI $0008
MPU via the data bus and with the outside world via pins 2,3,
and 4 of Port 2. The hardware, software, and registers are explained in the following paragraphs.
Wake-Up Feature
In a typical multi-processor application, the software
protocol will usually contain a destination address in the initial
byte(s) of the message. In order to permit non-selected MPU's
to ignore the remainder of the message, a wake-up feature is
included whereby all further interrupt processing may be
optionally inhibited until the beginning of the next message.
When the next message appears, the hardware re-enables (or
"wakes-up") for the next message. The "wake-up" is automatically triggered by a string of ten consecutive 1's which
indicates an idle transmit line. The software protocol must
provide for the short idle period between any two consecutive
messages.
Programmable Options
The following features of the HD680 1V serial I/O section are
programmable:
format - standard mark/space (NRZ)
Clock - external or internal
baud rate - one of 4 per given MPU 2 clock frequency or
external clock x8 input
wake-up feature - enabled or disabled
Interrupt requests - enabled or masked individually for
transmitter and receiver data registers
clock output - internal clock enabled or disabled to Port
2 (Bit 2)
Port 2 (bits 3 and 4) - dedicated or not dedicated to serial
I/O individually for transmitter and receiver.
Serial Communications Hardware
The serial communications hardware is controlled by 4
registers as shown in Figure 22. The registers include:
an 8-bit control and status register
a 4-bit rate and mode control register (write only)
an 8-bit read only receive data register and
an 8-bit write only transmit data register.
In addition to the four registers, the serial I/O section utilizes
bit 3 (serial input) and bit 4 (serial output) of Port 2. Bit 2 of
Port 2 is utilized if the internal-clock-out or external-clock-in
options are selected .
Transmit/Receive Control and Status (TRCS) Register
The TRCS register consists of an 8-bit register of which all 8
bits may be read while only bits 0"'4 may be written. The
register is initialized to $20 on RES. The bits in the TRCS
register are defined as follows:
_W_u---'1 AD DR : $0011
R_D_R_FI...o_R_F_E...
I_T_D_R_E....I_R_'E---li.-..R_E_ _T_'_E-""_T_E.....
,-I
84
------------------------------------------------HD6801VO, HD6801V5
Bit 7
I I I I
CCl
CCO
SSl
Bit 0
SSO
1$10
$12
Port 2
Receive Shift Register
....- - - E
Tx
Bit
12
4
$13
Bit 0 WU
CC1
cco
85
o
SS1
SSO
ADDR : $0010
HD6801V5------------------------------~----------------
HD6801VO,
Bit 0 S50
Bit 1 S51
Bit 2
Bit 3
ceo
eel
2.4576 MHz
4.0 MHz
614.4 kHz
1.0 MHz
SSl : SSO
0
0
1
0
1
0
E + 16
E + 128
E + 1024
E +4096
4.9152 MHz*
1.2288 MHz
16 ps/62,500 Baud
26 ps/38,400 Baud
208 ps/4,800 Baud
1.67 ms/600 Baud
13 ps/76,800 Baud
104.2 ps/9,600 Baud
33.3 ps/l,200 Baud
*HD6801 V5 Only
Format
Clock Source
Port 2 Bit 2
Port 2 Bit 3
Port 2 Bit 4
Not Used
Output*
**
**
**
**
**
**
**
00
01
10
11
NRZ
NRZ
NRZ
Internal
Internal
External
Input
**
86
Transmit Operations
The transmit operation is enabled by the TE bit in the
Transmit/Receive Control and Status Register. This bit when
set, gates the output of the serial transmit shift register to Port 2
Bit 4 and takes unconditional control over the Data Direction
Register value for Port 2, Bit 4.
Following a RES the user should configure both the Rate
and Mode Control Register and the Transmit/Receive Control
and Status Register for desired operation. Setting the TE bit
during this procedure initiates the serial output by first
transmitting a ten-bit preamble of 1'so Following the preamble,
internal synchronization is established and the transmitter
section is ready for operation.
At this point one of two situation exist:
1) if the Transmit Data Register is empty (TDRE = 1), a
continuous string of ones will be sent indicating an idle
line, or,
2) if data has been loaded into the Transmit Data Register
(TDRE = 0), the word is transferred to the output shift
registtr and transmission of the data word will begin.
During the transfer itself, the 0 start bit is first transmitted.
Then the 8 data bits (beginning with bit 0) followed by the stop
bit are transmitted. When the Transmitter Data Register has
be~n emptied, the hardware sets the TDRE flag bit. If the HD680 1V fails to respond to the flag within the proper
time, (TDRE is still set when the next nonnal transfer from the
parallel data register to the serial output register should occur)
then a 1 will be sent (instead of a 0) at "Start" bit time,
followeq by more 1's until more data is supplied to the data
register. No O's will be sent while TDRE remains a 1.
------------------------------------------------HD6801VO, HD6801V5
Condition code register manipulation instructions - Table 10
Instructions Execution times in machine cycles- Table
11
Summary of cycle by cycle operation - Table 12
Summary of undefined instructions operation
Op codes Map - Table 13
Receive Operation
15
15
SP
115
PC
Zero
Negative
Interrupt
Half Carry (From Bit 3)
87
Addressing Modes
Mnemonic
Operations
Add
AB
DB
03
OP
ADDA
8B
2 2
9B
ADDB
CB
C3
ADDD
ABA
ADCA
Clear
OP
Add Double
Bit Test
89
ADCB
C9
ANDA
84
ANDB
Compare
Accumulators
Complement, 1's
OP
BB
A+B-+A
EB
FB
B+M-+B
E3
F3
A9
B9
F9
B4
2 2
09
E9
94
A4
C4
04
E4
BITA
85
95
A5
BIT B
C5
05
E5
6F
7F
F4
B5
AM
2 F5
BM
BM -+ B
00 -+ M
CMPA
81
91
A1
B1
A-M
CMPB
C1
01
3 ,2
E1
F1
B-M
11
CBA
NEGA
NEGB
Decimal Adjust, A
DAA
Decrement
DEC
73
70
7A
EORB
C8
43
53
40
1 OO-A-+A
50
19
4A
A-1-+A
5A
B-1-+B
M-1-+M
B8
A@M-+A
F8
B @ M-+ B
6C
7C
M+1-+M
4C
2 1 A+ 1 ..... A
5C
2 1 B+1-+B
M ..... A
C6
M ..... B
CC
FC
86
LDAB
Load Double
Accumulator
LDD
Multiply Unsigned
MUL
OR, Inclusive
ORAA
8A
ORAB
CA
DC 4
EC
2 2 9A 3 2 AA 4
2 2 DA 3 2 EA 4
FA 4
37
B -+ Msp, SP - 1 ..... SP
32
~}
lG-i
II
B
C b7
PSHB
Pull Data
PULA
PULB
33
69
79
ROLA
49
ROLB
59
RORA
46
RORB
56
66
76
88
~J C{j:i
I
C b7
t
t
t
t
i III
t
t
t
t
t
R
R
R
t
t
t
R
f
R S R R
R S R R
R S R R
t
t
t t t
t t t
t t
t t
t t R S
t t R S
t t CD@)
t t CD
t t CD@)
R S
t
t
t
t
t
t
t
t
t
36
PSHA
t
t t
t
t
t
t @
t @
t
t
t
B + M ..... B
t
t
t
t
t t R
t t R
2 BA 4 3
2
M + 1 ..... B, M ..... A
3D 10 1
Push Data
2 2 96 3 2 A6 4 2 B6
2 2 06 3 2 E6 4 2 F6
LDAA
OO-B-+B
INCB
ROR
B -+ B
OO-M-+M
INC
Rotate Right
A -+A
2 98 3 2 A8
2 2 08 3 2 E8
2
INCA
ROL
A-B
M-+M
DECB
88
DECA
EORA
I
6A
t
t
t
t
t
t
1 00 -+ B
(Negate)
t
t
t
t
t
B+M+C-+B
5F
60
t
t
A+M+C-+A
CLRB
N Z
1 00 -+ A
63
A+B-+A
COM
A:B+M:M+1-+A:B
4F
NEG
Rotate Left
AM -+ A
COMB
Load
Accumulator
CLRA
Complement,2's
Increment
OP
3
4 "3
COMA
Exclusive OR
99
Boolean/
Arithmetic Operation
IMPLIED
1B
CLR
Compare
Register
EXTEND
INDEX
DIRECT
OP
Add Accumulators
AND
IMMED.
liJ
bo
I I I I I I~
bo
t t @ t
t t
t
t t
t
<t
t
t
t
(~j
(6)
'6 t
t
(Continued)
----------------------------------------------HD6801VO, HD6801V5
Table 7 Accumulator & Memory Instructions
(Continued)
Condition Code
Register
Addressing Modes
Operations
Mnemonic
IMMED.
OP
Shift Left
Arithmetic
Double Shift
Left, Arithmetic
Shift Right
Arithmetic
INDEX
DIRECT
OP
ASL
EXTEND
OP
OP
68
78
Double Shift
Right Logical
IMPLIED
OP
48
58
ASLD
05
__
b7
67
77
3
47
57
LSRA
44
LSRB
54
ASRA
64
LSR
74
04
LSRD
AO B7
1I1111f-.Q
bO
~104j
B
I I I II
b7
b7
o~
A7
AO
97
A7
B7
A~M
07
E7
F7
B~M
Store Double
Accumulator
STD
DO 4
ED
FD 5
A~M
B ~ M+1
Subtract
SUBA
90
AO
BO
A-M
~A
~B
"--9
bO
-----+
ACC AI ACCB
STAB
80
BO
~} C?I
B
STAA
Store
Accumulator
bO
A7
ASR
B7
~
BO
SUBB
CO
DO
EO
FO
B - M
Double Subtract
SUBD
83
93
A3
B3
A:B-M:M+1-+A:B
Subtract
Accu mu lators
SBA
10
A -
B~
Subtract
With Carry
SBCA
82
92
A2
B2
A-M-C~A
SBCB
C2
02
E2
F2
B-M-C-+B
Transfer
Accumulators
TAB
16
A~B
TBA
17
B~A
Test Zero or
Minus
TST
TSTA
40
A -00
TSTB
50
B - 00
60
70
M -00
A [J+111111111-0
B
C
~
A~~ A7 A~~ Ei 1_0
M}
ASLB
5
H
ASLA
ASRB
Shift Right
Logical
Boolean!
Arithmetic Operation
N Z
1 0
V
t t @t
t t @t
t t ~t
t t
t t
t
t
t t
t t
t
t t ) t
t t t
t t @ t
R
t @ t
t t t t
t t t t
t t t t
t t t t
t t t
t t t t
t t
t t
t t
t t
t t
R
R
R R
R R
R R
The Condition Code Register notes are listed after Table 10.
Direct Addressing
In direct addressing, the address of the operand is contained
in the second byte of the instruction. Direct addressing allows
the user to directly address the lowest 256 bytes in the machine
Le., locations zero through 255. Enhanced execution times are
achieved by storing data in these locations. In most configurations, it should be a random access memory. These are two-byte
instructions.
Extended Addressing
In extended addressing, the address contained in the second
byte of the instruction is used as the higher eight-bits of the
address of the operand. The third byte of the instruction is used
as the lower eight-bits of the address for the operand. This is an
absolute address in memory. These are three-byte instructions.
I ndexed Addressing
In indexed addressing, the address contained in the second
byte of the instruction is added to the index register's lowest
89
eight bits in the Mev. The carry is then added to the higher
order eight bits of the index register. This result is then used to
address memory. The modified address is held in a temporary
address register so there is no change to the index register. These
are two-byte instructions.
Implied Addressing
In the implied addressing mode the instruction gives the
address (Le., stack pointer, index register, etc.). These are
one-byte instructions.
Relative Addressing
In relative addressing, the address contained in the second
byte of the instruction is added to the program counter's lowest
eight bits plus two. The carry or borrow is then added to the
high eight bits. This allows the user to address data within a
range of -126 to + 129 bytes of the present instruction. These
are two-byte instructions.
HD6801VO, HD6801V5-----------------------------------------------
New Instructions
In addition to the existing 6800 Instruction Set, the following new instructions are
incorporated in the HD6801V Microcomputer.
ABX
Adds the 8-bit unsigned accumulator B to the 16-bit X-Register taking into account
the possible carry out of the low order byte of the X-Register.
ADDD Adds the double precision ACCD* to the double precision value M:M+I and places
the results in ACCD.
ASLD Shifts all bits of ACCD one place to the left. Bit 0 is loaded with zero. The C bit is
loaded from the most significant bit of ACCD.
LDD
Loads the contents of double precision memory location into the double
accumulator A:B. The condition codes are set according to the data.
LSRD Shifts all bits of ACCD one place to the right. Bit 15 is loaded with zero. The C bit
is loaded from the least significant bit to ACCD.
MUL
Multiplies the 8 bits in accumulator A with the 8 bits in accumulator B to obtain a
16-bit unsigned number in A:B, ACCA contains MSB of result.
PSHX The contents of the index register is pushed onto the stack at the address contained
in the stack pointer. The stack pointer is decremented by 2.
PULX The .index register is pulled from the stack beginning at the current address
contained in the stack pointer +1. The stack pointer is incremented by 2 in total.
STD
Stores the contents of double accumulator A:B in memory. The contents of ACCD
remain unchanged.
SUBD Subtracts the contents of M:M + 1 from the contents of double accumulator AB
and places the result in ACCD.
BRN
Never branches. If effect, this instruction can be considered a two byte NOP (No
operation) requiring three cycles for execution.
CPX
Internal processing modified to permit its use with any conditional branch instruction.
*ACCD is the 16 bit register (A:B) formed by concatenating the A and B accumulators. The A-accumulator is the most significant byte.
Addressing Modes
Pointer Operations
Mnemonic
Booleanl
IMMED.
DIRECT
INDEX
IMPLIED
EXTND
OP
OP
8C
9C
2 AC 6 2 BC 6 3
OP
OP
# OP
Arithmetic Operation
#
X-M:M+1
CPX
DEX
09
DES
34
1 SP - 1 -+ SP
INX
08
X+1-+X
INS
31
SP + 1 -+ SP
LOX
CE
LOS
8E
STX
STS
DE
9E
2
2
OF 4 2
9F 4 2
X-1-+X
EE
FE
M-+XH.(M+1)-+XL
AE
BE
M-+ SP H , (M+1)-+SP L
2
2
EF 5 2
AF 5 2
FF
XH-+M,XL-+(M+1)
BF
SPH -+ M, SP L -+ (M+ 11
TXS
35
X-1-+SP
TSX
30
SP+1-+X
Add
ABX
3A
B+X-+X
Push Data
PSHX
3C
XL -+ Msp, SP - 1 -+ SP
1 0
I N Z V
5
H
t t
t ~
t
t
.(f) t
.(f) t
(f) t
.I~ t
R
R
PULX
38
SP + 1 -+ SP, Msp -+ X H
SP + 1 -+ SP, Msp -+ XL
The Condition Code Register notes are listed after Table 10.
90
------------------------------------------------HD6801VO, HD6801V6
Table 9 Jump and Branch Instructions
Condition Code
Register
Addressing Modes
Mnemonic
Operations
RELATIVE
OP
DIRECT
OP
INDEX
# OP
EXTND
OP
Branch Test
IMPLIED
OP
Branch Always
BRA
20
Branch Never
BRN
21
None
BCC
24
C=O
BCS
25
C=1
Branch If = Zero
BEQ
27
Z=1
None
Branch If
Zero
BGE
2C
N()V=O
Branch If
> Zero
BGT
2E
Z + (N () V) = 0
Branch If Higher
BHI
22
C+Z=O
BlE
2F
Z + (N () V) = 1
Branch If lower Or
Same
BlS
23
C+Z=1
BlT
2D
N()V=1
Branch If Minus
BMI
2B
N= 1
BNE
26
Z=O
Branch If Overflow
Clear
V=O
Branch If
< Zero
BVC
28
BVS
29
V= 1
Branch If Plus
BPl
2A
N=O
8D
Branch To Subroutine
BSR
Jump
JMP
Jump To Subroutine
JSR
No Operation
NOP
01
7E
AD 6
BD 6
6E
9D
RTI
3B 10 1
Return From
Subroutine
RTS
39
software Interrupt
SWI
3F 12 1
WAI
3E
N Z
S
.
Mnemonic
OP
IMPLIED
Clear Carry
ClC
OC
CLI
OE
0 ...... 1
Clear Overflow
ClV
OA
Set Carry
SEC
OC;>
0""" V
1 ...... C
SEI
OF
1 ...... 1
O ...... C
Set Overflow
SEV
OB
1 ...... V
TAP
06
A ...... CCR
TPA
07
CCR ...... A
R
R
S
S
---@
91
Condition Code Register Notes: (Bit set it test is true and cleared otherwise)
CD (Bit V)
(Bit C)
@ (Bit C)
@ (Bit V)
@ (Bit V)
@ (Bit V)
CJ) (BitN)
(All)
(Bit I)
@> (All)
(Bit C)
HD6801VO. HD6801V5----------------------------------------------Table 11
ExInACCX I~~:- Direct tended
dexed
ABA
ABX
ADC
ADD
AD DO
AND
ASL
ASLD
ASR
BCC
BCS
BEQ
BGE
BGT
BHI
BIT
BLE
BLS
BLT
BMI
2
2
3
5
avc
BVS
CBA
CLC
CLI
CLR
CLV
CMP
COM
CPX
DAA
DEC
DES
DEX
EOR
INC
INS
BNE
BPL
BRA
BRN
BSR
Implied
2
2
3
3
Re-
ACCX
lative
INX
JMP
JSR
LOA
LGD
LOS
LOX
LSR
LSRD
MUL
NEG
NOP
ORA
3
3
3
3
3
3
3
3
3
3
3
3
6
3
3
PSHX
STX
SUB
SUBD
SWI
TAB
TAP
TBA
TPA
TST
TSX
TXS
WAI
92
PSH
PUL
PULX
ROL
ROR
RTI
RTS
SBA
SBC
SEC
SEI
SEV
STA
STD
STS
3
3
Implied
lative
3
3
3
3
4
4
4
5
5
5
5
5
5
3
10
5
5
5
5
5
3
5
4
4
10
5
2
12
2
2
2
3
3
9
Re-
--------~--------------------------------------HD6801VO.
HD6801V5
Address Bus
Data Bus
IMMEDIATE
ADC
ADD
AND
BIT
CMP
EOR
LOA
ORA
SBC
SUB
1
2
Op Code Address
Op Code Address + 1
1
1
Op Code
Operand Data
LOS
LOX
1
2
Op Code Address
Op Code Address + 1
Op Gode Address + 2
1
1
1
Op Code
Operand Data (High Order Byte)
Operand Data (Low Order Byte)
CPX
SUBD
ADDD
Op Code Address
Op Code Address + 1
Op Code Address + 2
Address Bus FFFF
1
1
1
1
Op Code
Operand Data (High Order Byte)
Operand Data (Low Order Byte)
Low Byte of Restart Vector
Op Code Address
Op Code Address + 1
Address of Operand
1
1
1
Op Code
Address of Operand
Operand Data
Op Code Address
Op Code Address + 1
Destination Address
1
1
0
Op Code
Destination Address
Data from Accumulator
Op Code Address
Op Code Address + 1
Address of Operand
Operand Address + 1
1
1
1
1
Op Code
Address of Operand
Operand Data (High Order Byte)
Operand Data (Low Order Byte)
Op Code Address
Op Code Address + 1
Address of Operand
Address of Operand + 1
1
1
0
0
Op Code
Address of Operand
Register Data (High Order Byte)
Register Data (Low Order Byte)
Op Code Address
Op Code Address + 1
Operand Address
Operand Address + 1
Address Bus FFFF
1
1
1
1
1
Op Code
Address of Operand
Operand Data (High Order Byte)
Operand Data (Low Order Byte)
Low Byte of Restart Vector
Op Code Address
Op Code Address + 1
Subroutine Address
Stack Pointer
Stack Pointer + 1
1
1
1
0
0
Op Code
Irrelevant Data
First Subroutine Op Code
Return Address (Low Order Byte)
Return Address (High Order Byte)
3
1
2
3
4
DIRECT
ADC
ADD
AND
BIT
CMP
EOR
LOA
ORA
SBC
SUB
1
2
STA
LOS
LOX
LDD
STS
STX
STD
CPX
SUBD
ADDD
JSR
1
2
3
1
2
3
4
1
2
3
4
1
2
3
4
5
1
2
3
4
5
(Continued)
93
Address Bus
Data Bus
INDEXED
1
2
3
Op Code Address
Op Code Address + 1
Address Bus FFFF
1
1
1
Op Code
Offset
Low Byte of Restart Vector
1
2
3
4
Op Code Address
Op Code Address + 1
Address Bus FFFF
Index Register Plus Offset
1
1
1
1
Op Code
Offset
Low Byte of Restart Vector
Operand Data
STA
1
2
3
4
Op Code Address
Op Code Address + 1
Address Bus FFFF
Index Register Plus Offset
1
1
1
Op Code
Offset
Low Byte of Restart Vector
Operand Data
LDS
LDX
LDD
1
2
3
4
5
Op Code Address
Op Code Address + 1
Address Bus FFFF
Index Register Plus Offset
Index Register Plus Offset + 1
1
1
1
1
1
Op Code
Offset
Low Byte of Restart Vector
Operand Data (High Order Byte)
Operand Data (Low Order Byte)
STS
STX
STD
1
2
3
4
Op Code Address
Op Code Address + 1
Address Bus FFFF
Index Register Plus Offset
Index Register Plus Offset + 1
1
1
1
Op Code
Offset
Low Byte of Restart Vector
Operand Data (High Order Byte)
Operand Data (Low Order Byte)
JMP
ADC
ADD
AND
BIT
CMP
EOR
LDA
ORA
SBC
SUB
5
ASL
ASR
CLR
COM
DEC
INC
LSR
NEG
ROL
ROR
TST*
CPX
SUBD
ADDO
1
2
3
4
5
6
6
1
2
3
4
5
6
JSR
1
2
3
4
5
0
0
Op Code Address
Op Code Address + 1
Address Bus F F F F
Index Register Plus Offset
Address Bus FFFF
Index Register Plus Offset
Op Code
Offset
Low Byte of Restart Vector
Current Operand Data
Low Byte of Restart Vector
New Operand Data
Op Code Address
Op Code Address + 1
Address Bus FFFF
Index Register + Offset
Index Register + Offset + 1
Address Bus F F F F
1
1
1
1
1
1
Op Code
Offset
Low Byte of Restart Vector
Operand Data (High Order Byte)
Operand Data (Low Order Byte)
Low Byte of Restart Vector
Op Code Address
Op Code Address + 1
Address Bus F F F F
Index Register + Offset
Stack Pointer
Stack Pointer - 1
1
1
1
1
0
0
Op Code
Offset
Low Byte of Restart Vector
First Subroutine Op Code
Return Address (Low Order Byte)
Return Address (High Order Byte)
1
1
1
1
1
* In the TST instruction, R/W line of the sixth cycle is "1" level, and AB=FFFF, DB=Low Byte of Reset Vector.
94
(Continued)
------------------------------------------------HD6801VO, HD6801V5
Table 12 Cycle by Cycle Operation (Continued)
Address Mode &
Instructions
Data Bus
Address Bus
EXTENDED
ADC
ADD
AND
BIT
CMP
Op Code Address
Op Code Address + 1
Op Code Address + 2
1
1
1
Op Code
Jump Address (High Order Byte)
Jump Address (Low Order Byte)
1
2
3
4
Op Code Address
Op Code Address + 1
Op Code Address + 2
Address of Operand
1
1
1
1
Op Code
Address of Operand
Address of Operand (Low Order Byte)
Operand Data
1
2
Op Code
Op Code
Op Code
Operand
1
1
1
Op Code
Destination Address (High Order Byte)
Destination Address (Low Order Byte)
Data from Accumulator
Op Code Address
Op Code Address + 1
Op Code Address + 2
Address of Operand
Address of Operand + 1
1
1
1
1
1
Op Code
Address of Operand
Address of Operand
Operand Data (High
Operand Data (Low
Op Code Address
Op Code Address + 1
Op Code Address + 2
Address of Operand
Address of Operand + 1
1
1
1
Op Code
Address of Operand
Address of Operand
Operand Data (High
Operand Data (Low
JMP
EOR
LDA
ORA
SBC
SUB
STA A
STA B
1
2
3
4
LDS
LDX
LDD
STS
STX
STD
ASL
ASR
CLR
COM
DEC
INC
1
2
3
4
5
1
2
3
4
5
LSR
NEG
ROL
ROR
TST*
1
2
3
4
5
6
CPX
SUBD
ADDD
JSR
1
2
3
4
5
6
1
2
3
4
5
6
Address
Address + 1
Address + 2
Destination Address
0
0
Op Code Address
Op Code Address + 1
Op Code Address + 2
Address of Operand
Address Bus F F F F
Address of Operand
Op Code
Address of Operand (High Order Byte)
Address of Operand (Low Order Byte)
Current Operand Data
Low Byte of Restart Vector
New Operand Data
Op Code Address
Op Code Address + 1
Op Code Address + 2
Operand Address
Operand Address + 1
Address Bus F FF F
1
1
1
1
1
1
Op Code
Operand Address (High Order Byte)
Operand Address (Low Order Byte)
Operand Data (High Order Byte)
Operand Data (Low Order Byte)
Low Byte of Restart Vector
Op Code Address
Op Code Address + 1
Op Code Address + 2
Subroutine Starting Address
Stack Pointer
Stack Pointer - 1
1
1
1
1
Op Code
Address of Subroutine (High Order Byte)
Address of Subroutine (Low Order Byte)
Op Code of Next Instruction
Return Address (Low Order Byte)
Address of Operand (High Order Byte)
1
1
1
1
1
0
0
* In the TST instruction, RtW line of the sixth cycle is "1" level, and AB = FFFF, DB = Low Byte of Reset Vector.
95
(Continued)
Data Bus
Address Bus
IMPLIED
ABA
ASL
ASR
CBA
CLC
CLI
CLR
DAA
DEC
INC
LSR
NEG
NOP
ROL
CLV ROR
COM SBA
ABX
ASLD
LSRD
SEC
SEI
SEV
TAB
TAP
TBA
TPA
TST
Op Code
Op Code of Next Instruction
Op Code Address
Op Code Address + 1
1
2
3
Op Code Address
Op Code Address + 1
Address Bus FFFF
1
1
Op Code Address
Op Code Address + 1
Address Bus FFFF
I Op Code
1
1
i Op Code
!,rrelevant Data
I Low Byte of Restart Vector
I Irrelevant Data
DES
1
Op Code Address
1
i Op Code
3
2
Op Code Address + 1
1
Op Code of Next Instruction
INS
______________~--------~-3~--+_P-re-v-io-u~s-R-e~gLis~t-er--C-o-nt-e_n_ts~1_--~l--_+-'-rr-e-'e--vantData
1
Op Code Address
1
Op Code
INX
3
DEX
2
Op Code Address + 1
1
Op Code of Next Instruction
1
Low Byte of Restart Vector
3
Address Bus F F F F
PSHA
1
Op Code Address
1
Op Code
3
PSHB
2
Op Code Address + 1
1
Op Code of Next Instruction
Stack Pointer
0
Accumulator Data
3
1
Op Code Address
1
Op Code
TSX
3
2
Op Code Address + 1
1
Op Code of Next Instruction
Stack Pointer
1
Irrelevant D_a_t_a___________
3
TXS
PULA
PULB
2
3
1
2
3
4
Op Code Address
Op Code Address. + 1
Address Bus F F F F
Op Code Address
Op Code Address + 1
Stack Pointer
Stack Pointer + 1
1
1
1
1
1
-P-S-H-X------~--4--~--1-~-O-p-C-o-de--A-d-d-re-s-s--------~---1--
3
4
PULX
1
2
3
4
Op Code Address
Op Code Address + 1
Stack Pointer
Stack Pointer + 1
Stack Pointer +2
Op Code Address
Op Code Address + 1
Stack Pointer
Stack Pointer + 1
Stack Pointer + 2
1
2
3
4
Op Code Address
C p Code Address + 1
Stack Pointer
Stack Pointer - 1
1
2
3
4
5
RTS
WAI**
Op Code Address + 1
Stack Pointer
Stack Pointer - 1
96
II
Op Code
Op Code of Next Instruction
Low Byte of Restart Vector
Op Code
Op Code of Next Instruction
Irrelevant Data
---L
I O--~---C-od-e---------------
1
0
I Irrelevant Data
1
1
1
1
1
1
1
1
1
1
1
o
o
------------------------------------------------HD6801VO, HD6801V5
Table 12 Cycle by Cycle Operation (Continued)
Address Mode &
Instructions
Cycles
Cycle
#
5
6
7
WAI**
8
9
MUL
10
SWI
10
12
Stack
Stack
Stack
Stack
Stack
Pointer
Pointer
Pointer
Pointer
Pointer
2
3
4
5
6
R/W
Line
0
0
0
0
0
Data Bus
Index Register (Low Order Byte)
Index Register (High Order Byte)
Contents of Accumu lator A
Contents of Accumulator B
Contents of Condo Code Register
10
Op Code Address
Op Code Address + 1
Address Bus FFFF
Address Bus F F F F
Address Bus FFFF
Address Bus FFFF
Address Bus FFFF
Address Bus F F F F
Address Bus FFFF
Address Bus FFFF
1
1
1
1
1
1
1
1
1
1
Op Code
Irrelevant
Low Byte
Low Byte
Low Byte
Low Byte
Low Byte
Low Byte
Low Byte
Low Byte
1
2
3
4
Op Code Address
Op Code Address + 1
Stack Pointer
Stack Pointer + 1
1
1
1
1
Stack Pointer + 2
Stack Pointer + 3
Stack Pointer + 4
Stack Pointer + 5
Stack Pointer + 6
10
Stack Pointer + 7
Op Code
Irrelevant Data
Irrelevant Data
Contents of Condo Code Reg.
from Stack
Contents of Accumulator B
from Stack
Contents of Accumulator A
from Stack
Index Register from Stack
(High Order Byte)
Index Register from Stack
(Low Order Byte)
Next Instruction Address from
Stack (High Order Byte)
Next Instruction Address from
Stack (Low Order Byte)
1
2
3
4
Op Code Address
Op Code Address + 1
Stack Pointer
Stack Pointer - 1
1
1
0
0
5
6
7
10
11
Stack Pointer Stack Pointer Stack Pointer Stack Pointer Stack Pointer Stack Pointer Vector Address
2
3
4
5
6
7
F F FA (Hex)
0
0
0
0
0
1
1
12
1
2
3
4
5
6
7
8
9
RTI
Address Bus
8
9
Data
of Restart
of Restart
of Restart
of Restart
of Restart
of Restart
of Restart
of Restart
Vector
Vector
Vector
Vector
Vector
Vector
Vector
Vector
Op Code
Irrelevant Data
Retu rn Address (Low Order Byte)
Return Address
(High Order Byte)
Index Register (Low Order Byte)
Index Register (High Order Byte)
Contents of Accumulator A
Contents of Accumulator B
Contents of Condo Code Register
Irrelevant Data
Address of Subroutine
(High Order Byte)
Address of Subroutine
(Low Order Byte)
**While the MPU is in the "Wait" state, its bus state will appear as a series of MPU reads of an address which is seven locations less than the
original contents of the Stack Pointer. Contrary to the HD6800, none of the ports are driven to the high impedance state by a WAI instruction.
(Continued)
97
Data Bus
Address Bus
RELATIVE
BCC BHT BNE
3
BCS BlE BPL
BEQ BLS BRA
BGE BL T BVC
BGT BMT BVS
BRN
------------- BSR
6
1
2
3
Op Code Address
Op Code Address + 1
Address Bus FFFF
1
1
1
Op Code
Branch Offset
Low Byte of Restart Vector
1
2
3
Op Code Address
Op Code Address + 1
Address Bus FFFF
Subroutine Starting Address
Stack Pointer
Stack Pointer - 1
1
1
1
1
0
0
Op Code
Branch Offset
Low Byte of Restart Vector
Op Code of Next Instruction
Return Address (Low Order Byte)
Return Address (High Order Byte)
4
5
6
When the op codes (4E, 5E) are used to execute, the MPU
continues to increase the program counter and it will not stop
until the Reset signal enters. These op codes are used to test the
LSI.
MICROCOMPUTER INSTRUCTIONS
OP
CODE
ACC
A
:~~
0000
0001
0010
0011
0100
0000
0001
BRA
TSX
CBA
BRN
INS
BHI
PULA (+1)
NOP
LSRO (+1)
0011
SBA
----------
0010
BLS
PULB (+1)
BCC
DES
0101
ASLO (+1)
BCS
TXS
0110
TAP
TAB
BNE
PSHA
0111
7
8
TPA
TBA
BEQ
PSHB
INX (+1)
BVC
PULX (+2)
1001
DEX (+1)
OAA
BVS
RTS (+2)
1010
CLV
BPL
ABX
1000
1011
SEV
ABA
BMI
RTI (+7)
1100
CLC
BGE
PSHX (+1)
1101
SEC
BLT
MUL (+7)
1110
CLI
---1---
1111
F
-----------BYTE/CYCLE
[NOTES]
/'
/
BGT
WAI (+6)
SEI
BLE
SWI (+9)
1/2
1/2
2/3
1/3
ACC IND
B
ACCA or SP
EXT
IMM
INO
1000 1001
OIR
1010 1011
A
----=-=
-----COM
OIR
INO
1100 1101
F
0
CMP
SBC
SUBO (+2)
AOOO (+2)
3
4
AND
BIT
ROR
LOA
-----
STA
7
8
STA
EOR
ASL
ROL
AOC
DEC
ORA
TST
~;47
JMP (-3)
**-
2/6
CPX (+2)
3/6
2/2
*
*
LOS (+1)
STS (+1)
2/3
2/4
LOO (+1)
~ (+1)
JSR (+2)
:.- (+1)
CLR
1/2
ADD
INC
2/2
2/3
) indicate that the number in parenthesis must be added to the cycle count for that instruction.
98
"**".
STX (+1)
3) The instructions shown below are all 3 bytes and are marked with "*".
Immediate addressing mode of SUBD, CPX, LOS, AOOO, LOO and LOX instructions, and undefined op codes
(SF, CD, CFI.
4) The Op codes (4E, 5E) are 1 byte/oo cycles instructions, and are marked with
LOX (+1)
:(+1)
3/4
STO (+1)
EXT
1110 1111
LSR
ASR
1/2
IMM
SUB
NEG
ACCB or X
EXT
2/4
3/4
co
co
*SCI
Vector
->
PC
NMI
FFFC FFFD
Non-Maskable Interrupt
SWI
IRQ,
FFFA FFFB
FFF8 FFF9
ICF
OCF
TOF
SCI
FFF6
FFF4
FFF2
FFFO
Software Interrupt
Maskable Interrupt Request 1
Input Capture Interrupt
Output Compare Interrupt
Timer Overflow Interrupt
FFF7
FFF5
FFF3
FFF1
+ RORF + ORFE)
:l:
C
~
CO
o...a
<
o
:l:
C
G)
CO
o...a
Figure 24 Interrupt Flowchart
<
CJI
HD6801VO, HD6801VS---------------------------------------------Vee
Vee
Enable
Enable
Vee Standby
NMI
Port 3
8 Transfer
Lines
RES
Port 1
81/0
Lines
Port 1
8 I/O Lines
Port 2
S I/O lines
Port 4
81/0 Lines
Port 4
8110 Lones
Port 2
S I/O lines
SCI
SCI
16 Bit Timer
Vss
Figure 25
Vss
HD6801V
MCU
Address
Bus
Data
Bus
Address Bus
Data Bus
100
H06803, H06803-1
M PU
HD6803C
(DC-40)
FEATURES
Expanded HMCS6800 Instruction Set
8 x 8 Multiply
On-Chip Serial Communications Interface (S.C.I.)
Object Code Compatible With The HD6800 MPU
16-Bit Timer
Expandable to 65k Words
Multiplexed Address and Data
128 Bytes Of RAM (64 Bytes Retainable On Power
Down)
HD6803P
HD6803P-l
(DP40)
PIN ARRANGEMENT
E
AS
RM
BLOCK DIAGRAM
0'0 lAo
DI'AI
D2/A2
D3.'A3
D., lA,
OslAs
D6'A.
0, A,
P"
As
Ag
AI"
POl
P"
P,.
PIS
AI.
A"
PI'
(Top View)
A.
Ag
AIO
All
t - - - -... p\O
t-----Pll
t - - - -... PI2
t - - - -... Pll
AI2
......- - - P I 4
Au
1------PI6
I - - - -.. Pll
All
Als ..
t-----Pl~
101
TYPE OF PRODUCTS
Type No.
Bus Timing
HD6803
1.0MHz
HD6803-1
1.25MHz
Symbol
Value
Unit
-0.3'" +7.0
Input Voltage
Vee *
V in *
-0.3'" +7.0
Operating Temperature
Topr
V
c
Storage Temperature
Tstg
Supply Voltage
'" + 70
- 55 - +150
ELECTRICAL CHARACTERISTICS
.-
RES
Other Inputs*
Test Condition
V 1H
Allinputs*
V 1L
EXTAL
PlO
Leakage Current
P20
As - A t5 , E, R/W, AS
II Ts "
Do/Ao - D7/A7
Other Outputs
Output" Low" Voltage
All Outputs
P17
Input Capacitance
Vee Standby
Standby Current
V in = 0.5 - 2.4V
I LOAD = -205 JJ.A
V OH
I LOAD = -145/lA
ILOAD = -100 JJ.A
VOL
-loH
PD
Cin
I LOAD = 1.6 mA
V out = 1.5V
V in = OV, Ta = 25C,
f
= 1.0 MHz
10.0
5.25
Powerdown
V SBB
4.0
V SB
4.75
Powerdown
ISBB
102
max
Unit
Vee
V
2.0
Vee
-- f - - - -0.3
0.8
V
0.8
mA
----------J.1A
2:~ f------10
J.1A
100
2.4
2.4
V
2.4
0.5
V
1.0
10.0
mA
1200
mW
-
Operating
typ
4.0
Pt7
P24
min
VSBB
= 4.0V
5.25
8.0
pF
V
mA
--------------------------------------------------HD6803, HD6803-1
AC CHARACTERISTICS
BUS TIMING (Vee = 5.0V 5%, Vss = OV, Ta = 0'" +70C, unless otherwise noted.)
Item
Symbol
Cycle Time
'tcYc
PW ASH
tAs r
t ASf
Test
Condition
HD6803
min
HD6803-1
max
ns
50
50
50
60
30
ns
50
ns
50
ns
340
ns
115
70
10
5
450
t ASED
Fig. 1
60
10
50
tAD
260
tADL
270
tDS W
t DSR
Read
tHR
10
Write
20
tHW
t ASL
60
tAHL
20
tAH
20
(tACCM)
225
80
Fig. 7
100
Fig.8
200
150
50
ns
PW EL
tRc. t pcs
ns
50
450
0.8
max
tEf
PW EH
I
I
typ
Unit
min
200
tAS D
t Er
typ
(600)
350
30
20
50
20
20
100
200
10
ps
ns
ns
260
ns
260
ns
ns
ns
(410)
ns
ns
ns
ns
ns
ms
ns
PERIPHERAL PORT TIMING (Vee = 5.0V 5%, Vss = OV, Ta = 0'" +70C, unless otherwise noted.)
Item
Symbol
Test Condition
min
typ
max
Unit
Port 1,2
t pDSU
Fig.2
200
Port 1,2
tpDH
Fig.2
200
ns
Port 1,2*
tpWD
Fig.3
400
ns
* Except
P21
103
ns
Item
Symbol
tpWT
t TOD
typ
max
ns
600
ns
--
tcyC
0.4
0.6
tScyC
min
2t cyc +200
Fig. 4
tSCYC
tPWSCK
Test Condition
Unit
typ
max
Unit
V MPL
1.7
VMPH
PW RSTL
4.0
tcyc
Item
Symbol
Test Condition
t MPS
2.0
tMPH
150
3.0
Fig. 5
tcyc
''I
Address Strobe
(AS)
....
-PW ASH -
06Vt-
2.4 V~
Enable
(E)
--
--
O.5V
-tASr
~~
I--tASf
l - ASED '--.
tASD
-,~
,V
PWEL
j,...
-tAD-
MPU Write
Do/A" - D7/A7
(Port 3)
1\
I--tEr
I--tEf
2.2V
-tAH
...
\
Address Valid
O.6V
l+-
tASL-
'-
~tAHL
)~ ~;:'ess ~~
)
Valid
O.6V
~2.2V
Valid
O.6V
(tACCM)
~~O.8V
-..
I-tHR
...
Data Valid
104
~tHW
Data Valid
}.,...2.0V
,If
O.6V
......---tOSR---"
} ~J:ress ~~
~
-tDSW-
-tADLMPU Read
Do Ao-07 A7
(Port 3)
'\
-'~
PWEH
-,f
V
tcyc
ns
--------------------------------------------------H06803, H06803-1
r-MPU Read
Enable (E)
MPUWrite
os:'t:::.,wo I
Enable (E)
Not applicable to P 21
Figure 2
~2-.2~V----_
All Oat:
Port Outputs
Enable (E)
Timer
Counter
(~~~~,I~~~::
)_______
""""<
~------------~
P"
Output
Vee
Test POlOt
o-.....~........-+
lS2074
or Equlv
TTL Load
105
H06803, H06803-1-------------------------------------------------
Last Instruction
Cycle
#,
Enable (El
Internal
Address Bus -"-......I"'-_~
NMI or IRG,
r--
Internal...,..,__--.v--...,.-_..,.r----,..--'"'V--"'V"--""--~,..-__,..r_-_,...-...,.,,......-_..,,_-"_\.,__-""\~--.....
______________________________-JI
Enable(EI
~~\\~\\\\\\\~ ~\\\\%\\\\"\\
LJlJ4
-----------~S
v~ ~,~_4_.7_5V_____________________
-S.25V
or
, )-\
r-
tRC
f1-fl-fl-J
,t
'1
~Jeo-T4,~OV.,.-tP-cs-------- t
--------------~l~l--------------------------~5~
Ad~r~rn:~s .\\\\\\\\\\\\\\\\\\\(1 5\s\\\\\\\\SS\\\\\\S\\\\\\\w----V '--I'~--"'--.....J"--_"-_
ss
"'~
~FFFE
,-
RES
Internal Rm \\\\\\\\\\\\\\\\\\\\\:;:
o.sv
tpcs
_''__"'''''l
l\S\\\\\S\\\\\\\\\\\\\\\S\\\y
c..-..J'\_-I'___
-"'-----'''-_'''-_,,_~
pc::x:::x::
Instruction
~NotValid
SIGNAL DESCRIPTIONS
Vee andVSS
--.....
4 MHz
~I
~"!1
These two pins are used to supply power and ground to the
chip. The voltage supplied will be +5 volts 5%.
XTAL and EXTAL
These connections are for a parallel resonant fundamental
crystal, AT cut. Devided by 4 circuitry is included with the
internal clock, so a 4 MHz crystal may be used to run the
system at 1 MHz., The de vide by 4 circuitry allows for use of the
inexpensive 3.58 MHz Color TV crystal for non-time critical
applications. Two 22pF capacitors are needed from the two
crystal pins to ground to insure reliable operation. EXTAL may
be driven by an external TTL compatible source with a 50%
(lo%) duty cycle. It will devided by 4 any frequency less than
or equal to 5 MHz. XTAL must be grounded if an external
clock is used. The following are the recommended crystal
parameters:
106
5 MHz
~~~J??~~~_X'14.7PF max.
RS
I 60n max,
30n typo
XTA L 1----.....- - - - ,
C Ll
= C L2 = 22pF
20%
(3.2 - 5 MHz)
EXT A L 1 - - -__--,
tL2
~CLl
--------------------------------------------------HD6803, H06803-1
Vee Standby
This pin will supply +5 volts 5% to the standby RAM on the
chip. The first 64 bytes of RAM will be maintained in the power
down mode with 8 rnA current max. The circuit of figure 13
can be utilized to assure that Vee Standby does not go below
V SBB during power down.
To retain information in the RAM during power down the
following procedure is necessary:
1) Write "0" into the RAM enable bit, RAM E. RAM E is bit
6 of the RAM Control Register at location $0014. This
disables the standby RAM, thereby protecting it at power
down.
2) Keep Vee Standby greater than VSBB.
Lowest
Priority
MSB
LSB
FFFE
FFFF
FFFC
FFFO
FFFA
FFFB
Interrupt
RES
NMI
Software Interrupt (SWI)
FFF8
FFF9
IRQ l
FFF6
FFF7
FFF4
FFF5
FFF2
FFF3
FFFO
FFF1
Enable (E)
This supplies the external clock for the rest of the system
when the internal oscillator is used. It is a single phase, TTL
compatible clock, and will be the divide by 4 result of the
crystal frequency. It will drive one TTL load and 90 pF.
Reset (RES)
This input is used to reset and start the MPU from a power
down condition, resulting from a power failure or an initial
startup of the processor. On power up, the reset must be held
"Low" for at least 100 ms. During operation, RES, when
brought "Low", must be held "Low" at least 3 clock cycles.
When a "High" level is detected, the MPU does the following:
1) All the higher order address lines will be forced "High".
2) I/O Port 2 bits, 2, 1, and 0 are latched into programmed
control bits PC2, PC 1 and PCO.
3) The last two ($FFFE, $FFFF) locations in memory will
be used to load the program addressed by the program
counter.
4) The interrupt mask bit is set, must be cleared before the
MPU can recognize maskable interrupts.
A low-going edge on this input requests that a non-maskableinterrypt sequence be generated within the processor. As with
interrupt Request signal, the processor will complete the current
instruction that is being executed before it recognizes the NMI
signal. The interrupt mask bit in the Condition Code Register
has no effect on NMI.
In response to an NMI interrupt, the Index Register, Program
Counter, Accumulators, and Condition Code Register are stored
on the stack. At the end of the sequence, a 16-bit address will
be loaded that points to a vectoring address located in memory
locations $FFFC and $FFFD. An address loaded at these locations causes the MPU to branch to a non-maskable interrupt
service routine in memory.
A 3.3 kU external resistor to Vee should be used for
wire-OR and optimum control of interrupts.
Inputs IRQl and NMI are hardware interrupt lines that are
sampled during E and will start the interrupt routine on the
E following the completion of an instruction.
107
ReadlWrite (RM)
There are two I/O ports on the HD6803 MPU; one 8-bit
port and one 5-bit port. Each port has an associated write
HD6803, HD6803-1------------------------------------------------only Data Direction Register which allows each I/O line to be
programmed to act as an input or an output*. A "I" in the
corresponding Data Direction Register bit will cause that I/O
line to be an output. A "0" in the corresponding Data Direction
Register bit will cause that I/O line to be an input. There are
two ports: Port I, Port 2. Their addresses and the addresses of
their Data Direction registers are given in Table 2.
Port Address
Data Direction
Register Address
I/O Port 1
$0002
$0000
I/O Port 2
$0003
$0001
Value
8
9
10
I/O Port 1
[NOTES]
L; Logical "0"
H; Logical "1"
I/O Port 2
INTERRUPT FLOWCHART
The Interrupt flowchart is depicted in Figure 16 and is common to every interrupt excluding reset.
GND
AS
DJ
G OC
aJ
74LS373
D,
Functi0'l Table
Add,,,, A. -A,
Output
Control
a,
Dot., D. -0,
108
L
L
L
H
Enable
Output
H
H
L
H
L
H
L
x
x
ao
--------------------------------------------------HD6803, HD6803-1
MEMORY MAP
PROGRAMMABLE TIMER
1
2
1
2
Data
Data
Data
Data
Not
Not
Not
Not
Used
Used
Used
Used
Register
Direction Register**
Direction Register**
Register
Register
Address
00
01
02
03
08
09
OA
OB
OC
00
OE
OF*
10
11
12
13
14
15-1F
* External Address
** 1; Output, 0; Input
Multiplexed/RAM
$0000
04*
05*
06*
07*
Internal Registers
$001F
$FFFO I-----I~
_ _ __ } External Interrupt Vectors
$FFFF~
[NOTE]
Excludes the following addresses which may
be used externally: $04, $05, $06, $07, and
$OF.
109
HD6803, HD6803-1-------------------------------------------------
Output Input
Level
Edge
Bit 1
Bit 0
Port 2
Port 2
I I I
OCF
TOF
110
------------------------------------------------H08803, H08803-1
SERIAL COMMUNICATIONS INTERFACE
Bit 7
I I I I
CCl
Bit 0
sso
1$10
$12
Port 2
(Not Addressable)
Receive Shift Register
Clock
Bit
2
10
N-......:..:::-...-----~
"'---E
12
$13
Programmable Options
SSl
Wake-Up Feature
cco
Bit 0 WU
Bit 1 TE
Bit 2 TI E
Bit 3 RE
Bit 4 RIE
I I
RE
111
TIE'
TE
I I
WU
AOOR: $0011
HD8803,
HD8803-1-------------------------------------------------
CC1
CCO
I I I
0
S51
SSO
ADDR : $0010
format
clocking source, and
Port 2 bit 2 configuration
The register consists of 4 bits all of which are write-only and
cleared on RES. The 4 bits in the register may be considered as
a pair of 2-bit fields. The two low order bits control the bit rate
for internal clocking and the remaining tWQ bits control the
format and clock select logic. The register definition is as
follows:
Bit 0 SSO Speed Select - These bits select the Baud rate for
Bit 1 SS1 the internal clock. The four rates which may be
selected are a function of the MPU fP2 clock
frequency. Table 5 lists the available Baud rates.
Bit 2 CCO Clock Control and Format Select - this 2-bit field
Bit 3 CC1 controls the format and clock select logic. Table 6
defines the bit field.
2.4576 MHz
4.0 MHz
614.4 kHz
4.9152 MHz*
1.0 MHz
1.2288 MHz
E + 16
26 J.LS/38,400 Baud
16 J.Ls/62,500 Baud
E + 128
E + 1024
E + 4096
* HD6803-1 Only
Format
Clock Source
Port 2 Bit 2
Port 2 Bit 3,
Port 2 Bit 4
00
**
**
01
NRZ
Internal
Not Used
**
**
10
NRZ
Internal
Output*
**
**
11
NRZ
External
Input
**
**
112
------------------------------------------------HD6803, HD6803-1
Serial Operations
The serial I/O hardware should be initialized by the HD6803
software prior to operation. This sequence will normally consist
of;
writing the desired operation control bits to the Rate and
Mode Control Register and
writing the desired operational control bits in the Transmit/
Receive Control and Status Register.
The Transmitter Enable (TE) and Receiver Enable (RE) bits
may be left set for dedicated operations.
Transmit Operations
The transmit operation is enabled by the TE bit in the
Transmit/Receive Control and Status Register. This bit when
~t, gates the output of the serial transmit shift register to Port 2
BIt 4 and takes unconditional control over the Data Direction
Register value for Port 2, Bit 4.
Following a RES the user should configure both the Rate
and Mode Control Register and the Transmit/Receive Control
and. Statu~ Register for desired operation. Setting the TE bit
dunng. ~s proce~ure initiates the serial output by first
~ransm1tt1Dg a ten-bIt preamble of 1'so Following the preamble,
mternal. synchronization is established and the transmitter
section is ready for operation.
At this point one of two situation exist:
1) if t~e Transmit Data Register is empty (TDRE = 1), a
contmuous string of ones will be sent indicating an idle
line, or,
2) if data has been loaded into the Transmit Data Register
(TDRE = 0), the word is transferred to the output shift
register and transmission of the data word will begin.
During the transfer itself, the 0 start bit is first transmitted.
Then the 8 data bits (beginning with bit 0) followed by the stop
bit, are transmitted. When the Transmitter Data Register has
been emptied, the hardware sets the TDRE flag bit.
If the HD6803 fails to respond to the flag within the proper
time, (TDRE is still set when the next normal transfer from the
parallel data register to the serial output register should occu()
then a 1 will be sent (insteaq of a 0) at "Start" bit time,
followed by more I's until more data is supplied to the data
register. No O's will be sent while TDRE remains a 1.
Receive Operation
The receive operation is enabled by the RE bit which gates in
the serial input through Port 2, Bit 3. The receiver section
operation is conditioned by the contents of the Transmit/
Receive Control and Status Register and the Rate and Mode
Control Register.
The receiver bit interval is divided into 8 sub-intervals for
internal synchronization. In the NRZ Mode, the received bit
stream is synchronized by the first 0 (space) encountered.
The approximate center of each bit time is strobed during
the next 10 bits. If the tenth bit is not a 1 (stop bit) a framing
error is assumed, and bit ORFE is set. If the tenth bit as a 1 the
data is transferred to the Receive Data Register, and inte:rupt
flag RDRF is set. If RDRF is still set at the next tenth bit time
ORFE will be set, indicating an overrun has occurred. When th~
HD6803 responds to either flag (RDRF or ORFE) by reading
the status register followed by reading the Data Register RDRF
'
(or ORFE) will be cleared.
RAM CONTROL REGISTER
This register, which is addressed at $0014 gives status
information about the standby RAM. A 0 in th; RAM enable
bit (RAM E) will disable the standby RAM. thereby protecting
113
$001.1 S:J:
IRAM:FT~ Rt: 1
1X
HD8803,
115
01
15
SP
oJ
115
PC
01
Immediate Addressing
eerry/Borrow from MSB
Overflow
Zaro
Negative
Interrupt
Half eerry (From Bit 3)
114
--------------------------------------------------HD6803. HD6803-1
Table 7 Accumulator & Memory Instructions
Condition Code
Addressing Modes
Operations
Add
Mnemonic
IMMED.
OP
2 9B
CB
C3
OP
ADDA
8B
ADDB
INDEX
DIRECT
Register
EXTEND
IMPLIED
Boolean/
Arithmetic Operation
# OP
BB
A+M->A
EB
FB
B+M->B
E3
F3
OP
AB
DB 3
D3
OP
I N Z V C
A+B->A
Add Double
ADDD
ABA
ADCA
89
99
A9
B9
A+M+C->A
ADCB
C9
D9
E9
F9
B+M+C->B
ANDA
84
94
A4
B4
AM -> A
ANDB
C4
D4
E4
F4
BM -+ B
BIT A
85
95
A5
B5
AM
BIT B
C5
D5
E5
F5
BM
6F
7F
00-+ M
AND
Bit Test
Clear
1B
CLR
Compare
Compare
Accumulators
Complement, 1's
Complement, 2's
(Negate)
Decimal Adjust, A
Decrement
4F
1 00 -+ A
CLRB
5F
1 00 -+ B
A1
B1
A-M
CMPB
C1
D1
E1
F1
B-M
A-B
73
11
CBA
63
COM
M-+M
A -+A
COMA
43
COMB
53
1 B -+B
40
1 OO-A-+A
50
1 OO-B-+B
NEG
60
70
OO-M-+M
NEGA
NEGB
DAA
19
6A
DEC
6 2 7A 6 3
4A
1 A-1-+A
5A
1 B-1-+B
EORA
88
2 98
A8
B8
A(j)M-+A
EORB
C8
08
E8
F8
B <> M-+ B
6C
2 7C
INC
LDAA
86
96
A6
B6
LOAB
C6
06
E6
F6
LOO
CC
DC 4
EC
FC
2 9A
AA 4
BA 4
OA 3
EA 4
FA 4
M+1 -+M
ORAB
CA 2
5C
1 B+1-+B
PSHA
36
37
PULA
32
PULB
33
49
59
RORA
46
RORB
56
69
79
ROLA
ROLB
ROR
66
76
M->B
M+1-+8,M->A
AxB-+A:B
A + M-+ A
B + M-+ B
A -+ Msp, SP - 1 .... SP
B -+ Msp, SP - 1 .... SP
SP + 1 -+ SP, Msp-> B
:}
60
B I.o-l
C b7I I I I I I liJ
I I I I I ,HI
~}~bj
bO
B
M-+A
PSHB
ROL
A+1-+A
4C
3D 10 1
8A
..
t t
t t
MUL
Rotate Right
ORAA
Rotate Left
91
Multiply Unsigned
Pull Data
OR, Inclusive
Push Data
INCB
Load Double
Accumulator
t ~
t t t
~ t t
~
t t t t
81
INCA
Load
Accumulator
CMPA
OECB
Increment
CLRA
OECA
Exclusive OR
Add Accumulators
1 0
115
R 5 R R
R 5 R R
R 5 R R
t
t
t
R 5
t R 5
t R S
t t
~ t
t
t t
t t
t
<D@
<D@
t <D@
~ @
t @
t
t
t
t
t
t
t
t
t R
R
t @
t t
t t
t t
t t
R
R
t t R
t t R
t t @
t t @
t t @
t t @
t t @
t t @
(Continued)
t
t
t
+
t
t
HD6803,
Addressing Modes
Operations
Mnemonic
IMMED.
OP
Shift Left
Arithmetic
Double Shift
Left, Arithmetic
Shift Right
Arithmetic
INDEX
DIRECT
OP
ASL
EXTEND
OP
OP
68
78
Double Shift
Right Logical
I N Z
48
ASLB
58
ASLD
05
47
57
M} D-1llllllll.o
A
B
b7
B7
77
64
74
LSRA
44
LSRB
54
04
LSRD
STAA
97
STAB
D7
E7
F7
B .... M
Store Double
Accumulator
STD
DD 4
ED 5
FD 5
A .... M
B .... M+ 1
Subtract
SUBA
AO
BO
A-M .... A
Store
Accumulator
80
2 90
bO
A7
67
ASRA
LSR
Arithmetic Operation
~
A~~ 'AZ 'A~~ g 1_0
A7
AO 87
80
~}O-+l
I 1111111...g
bO
B
b7
A7
AO 87
80
A .... M
ASRB
Shift Right
Log ice I
IMPLIED
OP
ASLA
ASR
Booleanl
SUBB
CO
DO
EO
FO
B - M .... B
Double Subtract
SUBD
83
3 93
A3
B3
A:B-M:M+1-+A:B
Subtract
Accu mu lators
SBA
Subtract
With Carry
SBCA
82
92
A2
B2
A-M-C .... A
SBCB
C2
D2
E2
F2
B-M-C-+B
Transfer
Accumulators
TAB
16
TBA
17
Test Zero or
Minus
TST
10
6D
7D
1
1
A - B-+ A
A-+B
B-+A
M-OO
A -00
TSTA
4D
TSTB
5D
1 B - 00
..
The Condition Code ReDlster notes are listed after Table 10 .
Direct Addressing
In direct addressing, the address of the operand is contained
in the second byte of the instruction. Direct addressing allows
the user to directly address the lowest 256 bytes in the machine
i.e., locations zero through 255. Enhanced execution times are
achieved by storing data in these locations. In most configurations, it should be a random access memory. These are two-byte
instructions.
Extended Addressing
In extended addressing, the address contained in the second
byte of the instruction is used as the higher 8-bits of the address
of the operand. The third byte of the instruction is used as the
lower 8-bits of the address for the operand. This is an absolute
address in memory. These are three-byte instructions.
Indexed Addressing
In indexed addressing, the address contained in the secdnd
byte of the instruction is added to the index register's lowest
116
1 0
V
t t @t
t t @t
t t @t
t
t @ t
t
t
t
t
t
t
t t
t
t
t
t
t
t
t
t
) t
t
@ t
t t
t t
t t
t t t t
t t t t
t t t t
t t t t
t t t t
t t t t
t t R
t t R
t t R R
t t R R
t t -R R
--------------------------------------------------HD6803, HD6803-1
New Instructions
In addition to the existing 6800 Instruction Set, the following new instructions are
incorporated in the HD6803 Microcomputer.
Adds the 8-bit unsigned accumulator B to the 16-bit X.Register taking into account
the possible carry out of the low order byte of the X-Register.
ADDD Adds the double precision ACCD* to the double precision value M:M+I and places
the results in ACCD.
ASLD Shifts all bits of ACCD one place to the left. Bit 0 is loaded with zero. The C bit is
loaded from the most significant bit of ACCD.
LDD
Loads the contents of double precision memory location into the double
accumulator A:B. The condition codes are set according to the data.
LSRD Shifts all bits of ACCD one place to the right. Bit 15 is loaded with zero. The C bit
is loaded from the, least significant bit to ACCD.
MUL
Multiplies the 8 bits in accumulator A with the 8 bits in accumulator B to obtain a
16-bit unsigned number in A:B, ACCA contains MSB of result.
PSHX The contents of the index register is pushed onto the stack at the address contained
in the stack pointer. The stack pointer is decremented by 2.
PULX The .index register is pulled from the stack beginning at the current address
contained in the stack pointer +1. The stack pointer is incremented by 2 in total.
STD
Stores the contents pf double accumulator A:B in memory. The contents of ACCD
remain unchanged.
SUBD Subtracts the contents of M:M + 1 from the contents of double accumulator AB
and places the result in ACCD.
BRN
Never branches. If effect, this instruction can be considered a two byte NOP (No
operation) requiring three cycles for execution.
CPX
Internal processing modified to permit its use with any conditional branch instruction.
ABX
*ACCO'is the 16 bit register (A:B) formed by concatenating the A and B accumulators. The A-accumu
latoris the most significant byte.
Addressing Modes
Pointer Operations
Mnemonic
IMMED.
OP
CPX
DEX
BC
DIRECT
# OP
3
9C
INDEX
# OP
5 2 AC 6
IMPLIED
EXTND
# OP
# OP
2 BC 6 3
Boolean!
Arithmetic Operation
X-M:M+1
09
X-1"'X
DES
34
1 SP -1'" SP
INX
08
X+ 1 ..... X
INS
31
SP + 1'" SP
LOX
CE
LOS
BE
STX
2 EE 5 2
AE 5 2
OF 4 2 EF 5 2
9F 4 2 AF 5 2
DE 4
9E
5
H
FE
BE
M ... SP H , (M+1)"'SPL
FF
BF
STS
TXS
35
X-1"'SP
TSX
30
SP+ 1'" X
Add
ABX
3A
B + X ..... X
Push Data
PSHX
3C
2 1 0
I N Z
~
~
(J)
(j)
(j)
(j)
~
~
f
f
R
R
R
R
38
PULX
117
Addressing Modes
Operations
Mnemonic
RELATIVE
DIRECT
OP
....
# OP
...
INDEX
# OP
...
IMPLIED
EXTND
# OP
...
Branch Test
# OP
....
Branch Always
BRA
20
None
Branch Never
BRN
21
None
BCC
24
C=O
BCS
25
C=1
Branch If = Zero
BEQ
27
Z=1
BGE
2C
N~ V=O
BGT
2E
Z+ (N ~ V) = 0
Branch If Higher
BHI
22
C+Z=O
BlE
2F
Z+ (N ~ V) = 1
Branch If lower Or
Same
BlS
23
C+Z=1
BlT
20
N~V=1
Branch If Minus
BMI
2B
3 2
N .. 1
BNE
26
3 2
Z=O
Branch If Overflow
Clear
BVC
28
V=O
29
V=1
2A
N=O
80
BVS
Branch If Plus
BPl
Branch To Subroutine
BSR
Jump
JMP
Jump To Subroutine
JSR
No Operation
NOP
01
RT!
3B 10 1
Return From
Subroutine
RTS
39
Software Interrupt
SWI
3F 12 1
WAI
3E
90
6E 3 2 7E 3 3
2 AD 6 2 BD 6 3
1 0
I N Z
V C
5
H
IMPLIED
...
OC
O-+C
Clear Carry
ClC
Cli
OE
0-+1
Clear Overflow
ClV
OA
0 ..... V
Set Carry
SEC
00
1 ..... C
SEI
OF
1 -+ I
Set Overflow
OB
06
2
2
SEV
TAP
1-+V
A ..... CCR
CCR -+ Accumulator A
TPA
07
CCR ..... A
R
R
R
S
S
S
@
Condition Code Register Notes: (Bit set it test is true and cleared otherwise)
t (Bit V)
(Bit C)
(Bit C)
(Bit VI
(Bit V)
(Bit V)
(Bit N)
(All)
(Bit I)
(All)
(Bit C)
118
S
@
OP
-@-
AddressingModes
Mnemonic
Operations
-------------------------------------------------HD8803,
Table 11
ABA
ABX
ADC
ADD
ADDD
AND
ASL
ASLD
ASR
BCC
BCS
BEQ
BGE
BGT
BHI
BIT
BLE
BLS
BLT
BMI
BNE
BPL
BRA
BRN
BSR
BVC
BVS
CBA
CLC
CLI
CLR
CLV
CMP
COM
CPX
DAA
DEC
DES
DEX
EOR
INC
INS
2
2
3
3
5
3
Im-
HD8803-1
2
2
3
3
Relative
3
3
3
3
3
3
3
3
3
3
3
3
3
6
119
INX
JMP
JSR
LOA
LDD
LOS
LOX
LSR
LSRD
MUL
NEG
NOP
ORA
PSH
PSHX
PUL
PULX
ROL
ROR
RTI
RTS
SBA
SBC
SEC
SEI
SEV
STA
STD
STS
STX
SUB
SUBD
SWI
TAB
TAP
TBA
TPA
TST
TSX
TXS
WAI
5
3
2
2
3
3
3
4
4
4
6
6
6
6
5
5
5
2
4
4
5
5
5
4
5
5
5
lative
5
5
5
6
3
10
10
5
2
2
2
12
Re-
Implied
3
3
9
HD6803,
HD6803-1-------------------------------------------------
Data Bus
Address Bus
IMMEDIATE
2
1
2
Op Code Address
Op Code Address + 1
1
1
Op Code
Operand Data
LDS
LDX
1
2
Op Code Address
Op Code Address + 1
Op Code Address + 2
1
1
1
Op Code
Operand Data (High Order Byte)
Operand Data (Low Order Byte)
CPX
SUBD
ADDD
Op Code Address
Op Code Address + 1
Op Code Address + 2
Address Bus F F F F
1
1
1
1
Op Code
Operand Data (High Order Byte)
Operand Data (Low Order Byte)
Low Byte of Restart Vector
Op Code Address
Op Code Address + 1
Address of Operand
1
1
1
Op Code
Address of Operand
Operand Data
Op Code Address
Op Code Address + 1
Destination Address
1
1
Op Code
Destination Address
Data from Accumulator
Op Code Address
Op Code Address + 1
Address of Operand
Operand Address + 1
1
1
1
1
Op Code
Address of Operand
Operand Data (High Order Byte)
Operand Data (Low Order Byte)
Op Code Address
Op Code Address + 1
Address of Operand
Address of Operand + 1
1
1
0
0
Op Code
Address of Operand
Register Data (High Order Byte)
Register Data (Low Order Byte)
Op Code Address
Op Code Address + 1
Operand Address
Operand Address + 1
Address Bus F F F F
1
1
1
1
1
Op Code
Address of Operand
Operand Data (High Order Byte)
Operand Data (Low Order Byte)
Low Byte of Restart Vector
Op Code Address
Op Code Address + 1
Subroutine Address
Stack Pointer
Stack Pointer + 1
1
1
1
Op Code
Irrelevant Data
First Subroutine Op Code
Return Address (Low Order Byte)
Return Address (High Order Byte)
ADC
ADD
AND
BIT
CMP
EOR
LDA
ORA
SBC
SUB
3
1
2
3
4
DIRECT
ADC
ADD
AND
BIT
CMP
EOR
LDA
ORA
SBC
SUB
STA
1
2
1
2
3
LDS
LDX
LDD
STS
STX
STD
CPX
SUBD
ADDD
JSR
1
2
3
4
1
2
3
4
1
2
3
4
5
1
2
3
4
5
0
0
(Continued)
120
-------------------------------------------------HD6803, HD6803-1
Table 12 Cycle by Cycle Operation (Continued)
Address Mode &
Instructions
Data Bus
Address Bus
INDEXED
JMP
2
3
ADC
ADD
AND
BIT
CMP
EOR
LDA
ORA
SBC
SUB
STA
2
3
4
4
2
3
4
LDS
LDX
LDD
STS
STX
STD
ASL
ASR
CLR
COM
DEC
INC
2
3
4
5
1
2
3
4
5
LSR
NEG
ROL
ROR
TST*
2
3
4
5
6
CPX
SUBD
ADDD
JSR
2
3
4
5
6
1
2
3
4
5
6
Op Code Address
Op Code Address + 1
Address Bus FFFF
1
1
1
Op Code
Offset
Low Byte of Restart Vector
Op Code Address
Op Code Address + 1
Address Bus F F F F
Index Register Plus Offset
1
1
1
1
Op Code
Offset
Low Byte of Restart Vector
Operand Data
Op Code Address
Op Code Address + 1
Address Bus F F F F
Index Register Plus Offset
1
1
1
0
Op Code
Offset
Low Byte of Restart Vector
Operand Data
Op Code Address
Op Code Address + 1
Address Bus FFFF
Index Register Plus Offset
Index Register Plus Offset + 1
1
1
1
1
1
Op Code
Offset
Low Byte of Restart Vector
Operand Data (High Order Byte)
Operand Data (Low Order Byte)
Op Code Address
Op Code Address + 1
Address Bus FFFF
Index Register Plus Offset
Index Register Plus Offset + 1
1
1
1
0
0
Op Code
Offset
Low Byte of Restart Vector
Operand Data (High Order Byte)
Operand Data (Low Order Byte)
Op Code Address
Op Code Address + 1
Address Bus FFFF
Index Register Plus Offset
Address Bus FFFF
Index Register Plus Offset
1
1
1
1
1
0
Op Code
Offset
Low Byte of Restart Vector
Current Operand Data
Low Byte of Restart Vector
New Operand Data
Op Code Address
Op Code Address + 1
Address Bus F F F F
Index Register + Offset
Index Register + Offset + 1
Address Bus F F F F
1
1
1
1
1
1
Op Code
Offset
Low Byte of Restart Vector
Operand Data (High Order Byte)
Operand Data (Low Order Byte)
Low Byte of Restart Vector
Op Code Address
Op Code Address + 1
Address Bus FFFF
Index Register + Offset
Stack Pointer
Stack Pointer - 1
1
1
1
1
0
0
Op Code
Offset
Low Byte of Restart Vector
First Subroutine Op Code
Return Address (Low Order Byte)
Return Address (High Order Byte)
* In the TST instruction, R/W line of the sixth cycle is "1" level, and AB = FFFF, DB = Low Byte of Reset Vector.
121
(Continued)
Data Bus
Address Bus
EXTENDED
JMP
1
2
3
ADC
ADD
AND
BIT
CMP
EOR
LOA
ORA
SBC
SUB
1
2
3
4
4
STA A
STA B
1
2
3
4
LOS
LOX
LDD
1
2
3
4
5
5
STS
STX
STD
1
2
3
4
5
ASL
ASR
CLR
COM
DEC
INC
LSR
NEG
ROL
ROR
TST*
1
2
3
4
5
6
CPX
SUBD
ADDD
1
2
3
4
5
6
JSR
1
2
3
4
5
6
Op Code Address
Op Code Address + 1
Op Code Address + 2
1
1
1
Op Code
Jump Address (High Order Byte)
Jump Address (Low Order Byte)
Op Code Address
Op Code Address + 1
Op Code Address + 2
Address of Operand
1
1
1
1
Op Code
Address of Operand
Address of Operand (Low Order Byte)
Operand Data
Op Code Address
Op Code Address + 1
Op Code Address + 2
Operand Destination Address
1
1
1
Op Code
Destination Address (High Order Byte)
Destination Address (Low Order Byte)
Data from Accumulator
Op Code Address
Op Code Address + 1
Op Code Address + 2
Address of Operand
Address of Operand + 1
1
1
1
1
1
Op Code
Address of Operand
Address of Operand
Operand Data (High
Operand Data (Low
Op Code Address
Op Code Address + 1
Op Code Address + 2
Address of Operand
Address of Operand + 1
1
1
1
0
0
Op Code
Address of Operand
Address of Operand
Operand Data (High
Operand Data (Low
Op Code Address
Op Code Address + 1
Op Code Address + 2
Address of Operand
Address Bus FFFF
Address of Operand
1
1
1
1
1
0
Op Code
Address of Operand (High Order Byte)
Address of Operand (Low Order Byte)
Current Operand Data
Low Byte of Restart Vector
New Operand Data
Op Code Address
Op Code Address + 1
. Op Code Address + 2
Operand Address
Operand Address + 1
Address Bus FFFF
1
1
1
1
1
1
Op Code
Operand Address (High Order Byte)
Operand Address (Low Order Byte)
Operand Data (High Order Byte)
Operand Data (Low Order Byte)
Low Byte of Restart Vector
1
1
1
1
Op Code
Address of Subroutine (High Order Byte)
Address of Subroutine (Low Order Byte)
Op Code of Next Instruction
Return Address (Low Order Byte)
Address of Operand (High Order Byte)
Op Code Address
Op Code Address + 1
Op Code Address + 2
Subroutine Starting Address
Stack Pointer
Stack Pointer - 1
0
0
In the TST instruction, R/W line of the sixth cycle is "1" level, and AB =FFFF, DB = Low Byte of Reset Vector.
122
(Continued)
-------------------------------------------------HD8803,
HD8803-1
Address Bus
Data Bus
IMPLIED
ABA
ASL
ASR
CBA
CLC
CLI
CLR
CLV
COM
DAA
DEC
INC
LSR
NEG
NOP
ROL
ROR
SBA
SEC
SEI
SEV
TAB
TAP
TBA
TPA
TST
ABX
ASLD
LSRD
DES
INS
INX
DEX
PSHA
PSHB
TSX
TXS
PULA
PULB
1
2
3
1
2
3
1
2
3
1
2
Op Code
Irrelevant Data
Low Byte of Restart Vector
Op Code Address
Op Code Address + 1
Previous Register Contents
1
1
1
1
1
1
Op Code
Op Code of Next Instruction
Irrelevant Data
1
1
Op Code Address
Op Code Address + 1
Address Bus F F F F
Op Code
Op Code of Next Instruction
Low Byte of Restart Vector
1
1
1
Op Code
Op Code of Next Instruction
Low Byte of Restart Vector
Op Code Address
Op Code Address + 1
Stack Pointer
Stack Pointer + 1
1
1
1
1
Op Code
Op Code of Next Instruction
Irrelevant Data
Op Code Address
Op Code Address + 1
Stack Pointer
Stack Pointer - 1
1
1
0
0
Op Code
Irrelevant Data
Index Register (Low Order Byte)
Index Register (High Order Byte)
2
3
4
Op Code Address
Op Code Address + 1
Stack Pointer
Stack Pointer + 1
Stack Pointer +2
Op Code Address
Op Code Add ress + 1
Stack Pointer
Stack Pointer + 1
1
1
1
1
1
1
1
1
1
Stack Pointer + 2
Op Code Address
Op Code Address + 1
Stack Pointer
Stack Pointer - 1
1
1
1
2
1
2
2
3
4
5
1
1
1
Op Code Address
Op Code Address + 1
Address Bus FFFF
1
2
WAI**
Op Code Address
Op Code Address + 1
Address Bus FFFF
Op Code
Op Code of Next Instruction
Irrelevant Data
Op Code
Irrelevant Data
Low Byte of Restart Vector
1
1
1
RTS
1
1
1
Op Code Address
Op Code Address + 1
Address Bus F F F F
Op Code Address
Op Code Address + 1
Stack Pointer
1
2
PULX
Op Code
Op Code of Next Instruction
Op Code
Op Code of Next Instruction
Accumulator Data
1
1
Op Code Address
Op Code Address + 1
Stack Pointer
1
2
PSHX
Op Code Address
Op Code Address + 1
2
3
4
123
0
0
Op Code
Irrelevant Data
Irrelevant Data
Index Register (High Order Byte)
Index Register (Low Order Byte)
Op Code
Irrelevant Data
Irrelevant Data
Address of Next Instruction
(High Order Byte)
Address of Next Instruction
(Low Order Byte)
Op Code
Op Code of Next Instruction
Return Address (Low Order Byt~)
Return Address
(High Order Byte)
(Continued)
HD8803,
Cycles
Cycle
#
5
6
7
WAI**
8
9
MUL
10
1
2
3
4
5
6
7
SWI
10
12
Stack
Stack
Stack
Stack
Stack
Pointer
Pointer
Pointer
Pointer
Pointer
2
3
4
5
6
RIW
Line
0
0
0
0
0
Data Bus
Index Register (low Order Byte)
Index Register (High Order Byte)
Contents of Accumulator A
Contents of Accumulator B
Contents of Condo Code Register
10
Op Code Address
Op Code Address + 1
Address Bus FFFF
Address Bus F F F F
Address Bus FFFF
Address Bus FFFF
Address Bus FFFF
Address Bus F F F F
Address Bus FFFF
Address Bus FFFF
1
1
1
1
1
1
1
1
1
1
Op Code
Irrelevant Data
low Byte of Restart
low Byte of Restart
low Byte of Restart
low Byte of Restart
low Byte of Restart
low Byte of Restart
low Byte of Restart
low Byte of Restart
1
2
3
4
Op Code Address
Op Code Address + 1
Stack Pointer
Stack Pointer + 1
1
1
1
1
Stack Pointer + 2
Stack Pointer + 3
Stack Pointer + 4
Stack Pointer + 5
Stack Pointer + 6
10
Stack Pointer + 7
Up Code
Irrelevant Data
Irrelevant Data
Contents of Condo Code Reg.
from Stack
Contents of Accumulator B
from Stack
Contents of Accumulator A
from Stack
Index Register from Stack
(High Order Byte)
Index Register from Stack
(low Order Byte)
Next Instruction Address from
Stack (High Order Byte)
Next Instruction Address from
Stack (low Order Byte)
1
2
3
4
Op Code Address
Op Code Address + 1
Stack Pointer
Stack Pointer - 1
1
1
0
0
5
6
7
10
11
Stack Pointer Stack Pointer Stack Pointer Stack Pointer Stack Pointer Stack Pointer Vector Address
2
3
4
5
6
7
FFFA (Hex)
0
0
0
0
0
1
1
12
8
9
RTI
Address Bus
8
9
Vector
Vector
Vector
Vector
Vector
Vector
Vector
Vector
Op Code
Irrelevant Data
Return Address (low Order Byte)
Return Address
(High Order Byte)
Index Register (low Order Byte)
Index Register (High Order Byte)
Contents of Accumulator A
Contents of Accumulator B
Contents of Cond. Code Register
Irrelevant Data
Address of Subroutine
(High Order Byte)
Address of Subroutine
(low Order Byte)
(Continued)
** While the MPU is in the "Wait" state, its bus state will appear as a series of MPU reads of an address which is seven locations less than the
original contents of the Stack Pointer. Contrary to the HD6800, none of the ports are driven to the high impedance state by a WAI
instruction.
124
-------------------------------------------------HD6803, HD6803-1
Table 12 Cycle by Cycle Operation (Continued)
RELATIVE
Address Mode &
Instructions
BCC BHT BNE
BCS BLE BPL
BEQ BLS BRA
BGE BL T BVC
BGT BMT BVS
BRN
Cycles
Cycle
2
3
BSR
2
3
4
5
6
R/W
line
1
1
1
Address Bus
Op Code Address
Op Code Address + 1
Address Bus FFFF
Op Code Address
Op Code Address + 1
Address Bus FFFF
Subroutine Starting Address
Stack Pointer
Stack Pointer - 1
Data Bus
Op Code
Branch Offset
Low Byte of Restart Vector
1
1
1
1
0
0
Op Code
Branch Offset
Low Byte of Restart Vector
Op Code of Next Instruction
Return Address (Low Order Byte)
Return Address (High Order Byte)
When the op codes (4E, SE) are used to execute, the MPU
continues to increase the program counter and it will not stop
until the Reset signal enters. These op codes are used to test the
LSI.
ACC
A
~
LO
0000
0001
1
2
0010
0000
-------------
0001
0010
0011
SBA
BRA
TSX
CBA
BRN
INS
BHI
PULA (+1)
BLS
PULB (+1)
BCC
DES
ASLD(+1)
BCS
TXS
TAP
TAB
BNE
PSHA
NOP
0011
0100
0101
0110
0111
TPA
TBA
BEQ
PSHB
1000
INX (+1)
BVC
PULX (+2)
LSRD (+1)
1001
DEX (+1)
DAA
BVf
RTS (+2)
1010
CLV
BPL
ABX
1011
SEV
ABA
BMI
RTI (+7)
1100
CLC
BGE
PSHX (+1)
1101
SEC
1110
CLI
1111
SEI
1/2
BYTE/CYCLE
[NOTES]
BLT
MUL (+7)
BGT
WAI (+6)
BLE
SWI (+9)
1/2
2/3
1/3
ACC INO
B
ACCA orSP
EXT
------------4
IMM
OIR
1000 1001
INO
OIR
INO
NEG
F
0
CMP
SSC
SUBO (+2)
AODD (+2)
3
4
LSR
AND
BIT
ROR
LOA
ASR
STA
STA
EOR
ASL
ROL
ADC
8
9
DEC
ORA
INC
TST
--- .. ---
JMP (-3)
CLR
1/2
2/6
.
~:4~
.
ADD
CPX (+2)
3/6
2/2
LOS (+1)
2/4
LOX (+1)
3/4
2/2
2/3
) indicate that the number in parenthesis must be added to the cycle count for that instruction.
125
E
F
STX (+1)
3) The instructions shown below are all 3 bytes and are marked with ".".
Immediate addressing mode of SUBD, CPX, LOS, ADDD, LDD and LOX instructions, and undefined op codes
(8F, CD, CFI.
4) The Op codes (4E, 5E) are 1 byte/ oo cycles instructions, and are marked with " "
STD (+1)
~(+1)
STS (+1)
2/3
; (+1)
JSR (+2)
.: (+1)
B
LDD(+1)
EXT
1110 1111
SUB
COM
1/2
ACCB or X
EXT IMM
2/4
3/4
:z:
c
G
CD
:z:
c
G
CD
W
I
.....
I\)
0)
*SCI
Vector-. PC
NMI
FFFC FFFO
Non-Maskable Interrupt
SWI
IRQ J
ICF
OCF
TOF
SCI
FFFA FFFB
FFF8 FFF9
FFF6 FFF7
FFF4 FFF5 j
FFF2 FFF3
FFFO FFFl :
Software Interrupt
Maskable Interrupt Request 1
Input Capture Interrupt
Output Compare Interrupt
Timer Overflow Interrupt
------------------------------------------------HD8803, HD8803-1
Address Bus
Data Bus
127
HD6805S1
MCU
(Microcomputer Unit)
HD6805S1P
HARDWARE FEATURES
8-Bit Architecture
64 Bytes of RAM
~emory Mapped I/O
1100 Bytes of User ROM
Internal 8-Bit Timer with 7-Bit Prescaler
Vectored Interrupts - External and Timer
20 TTL/CMOS Compatible I/O Lines; 8 Lines LED
Compatible
(DP-28)
PIN ARRANGEMENT
Vss
Easy to Program
True Bit Manipulation
Bit Test and Branch Instructions
Versatile Interrupt Handing
Powerful Indexed Addressing for Tables
Full Set of Conditional Branches
Memory Usable as Registers/Flags
Single I nstruction Memory Examine/Change
TIMER
10 Powerful Addressing Modes
All Addressing Modes Apply to ROM, RAM and I/O
Compatible with MC6805P2
INT
A7
Vee
A,
XTAL
As
EXTAL
A.
NUM
A,
A2
TIMER
HD6805S1
Co
C.
Ao
C2
B7
C3
Bo
B,
B.
B,
B,
(Top View)
BLOCK DIAGRAM
Accumulator
CPU
Control
Inde.
Reg
Regist.r
Ao
A,
A,
A,
I/O A.
lines A,
A,
A,
Port
A
Port
Reg
Da.a
Oir
Reg
Data
Dir
Condition
Code
Regilter CC
Port
Reg
I.
B,
B,
P;-t
:: I/O
B. Li ....
B,
B,
CPU
Stack
5
Pointer
SP
Program
Count.r
"High" PCH
Program
Counter
"Low" PCL
1100.8
ROM
Self check
ROM
128
ALU
Co Port
C,
C
C, I/O
C, Li ....
--------------------------------------------------------HD6806S1
ABSOLUTE MAXIMUM RATINGS
Vee *
V ln *
Unit
Value
Symbol
Item
Supply Voltage
-0.3 - +7.0
-0.3-+7.0
-0.3 -+12.0
Operating Temperature
Top'
o -+70
Storage Temperature
T stg
- 55-+150
With respect to
(NOTE)
Permanent LSI damage may occur if maximum ratings are exceeded. Normal operation should be under
recommended operating conditions. If these conditions are exceeded. it could affect reliability of LSI.
ELECTRICAL CHARACTERISTICS
DC CHARACTERISTICS (Vcc=5.25V O.5V, Vss=GND, Ta=G-+70C, unless otherwise noted.)
Item
Input "High" Voltage
Symbol
min typ
Vee
INT
3.0
Vee
2.0
Vee
2.0
Vee
11.0
0.8
V
V
V IH
Timer Mode
Self-Check Mode
RES
INT
max Unit
4.0
All Other
Input "High" Voltage Timer
Test Condition
RES
XT AL(Crystal Mode)
All Other
V IL
-0.3
-0.3
0.8
0.6
0.8
Po
LVR
400 700
4.75
LVI
4.0
Power Dissipation
INT
Vin =O.4V-V ee
XT AL(Crystal Mode)
V
V
V
mW
V
V
20
p.A
-1200 -
50
p.A
p.A
-20
IlL
TIMER
Input Leak Current
-50
Symbol
Test Condition
min
typ
max Unit
Clock Frequency
fel
0.4
Cycle Time
1.0
10
p.s
teye
f EXT
2.7
4.0
MHz
tlWL
ns
tRWL
tcye+
250
t eye +
250
ns
tTWL
t eye +
250
ns
100
ms
100
ms
25
35
10
pF
pF
l
I
EXTAL
All Other
Rep =15.0H21%
tRHL
CL=22pF20%,
Rs =60n max.
External Cap. = 2.2 p.F
Cin
Vin=OV
tose
129
4.0 MHz
HD6806S1------------------------------------------------------- PORT ELECTRICAL CHARACTERISTICS (Vee = 5.25V 0.5V, Vss = GND, Ta = 0"" +70C unless otherwise noted.)
typ
max
Unit
Symbol
Test Condition
min
Item
IOH = -10,uA
3.5
IOH = -100,uA
2.4
IOH = -200,uA
2.4
IOH = -1 mA
1.5
Port C
IOH ;; -100,uA
2.4
Port A and C
IOL = 1.6 mA
Port A
Output "High" Voltage
Port B
Port B
VO H
IOL = 3.2 mA
VOL
IOL = 10mA
VIH
2.0
Port A, B, C
-0.3
VIL
Port A
IlL
Port B, C
Yin = 0.8V
-500
Yin = 2V
-300
- 20
V
V
V
V
V
0.4
0.4
1.0
Vee
0.8
V
,uA
20
,uA
,uA
Ii = 1.6 mA
Test Point
Test Point
2.4kn.
Vi
30 pF
40pF
24 kn.
(NOTE) 1. Load capacitance includes the floating capacitance of the probe and the jig etc.
2. All diodes are 152074 (8) or equivalent.
Figure 1 Bus Timing Test loads
SIGNAL DESCRIPTION
The input and output signals for the MCU shown in PIN
ARRANGEMENT are described in the following paragraphs.
Vee
andVss
INT
130
TIMER
RES
NUM
This pin allows resetting of the MCU at times other than the
automatic resetting capability already in the MCU. Refer to
RESETS for additional information.
This pin is not for user application and should be connected
to ground.
and one 4-bit port (C). All lines are programmable as either
inputs or outputs under software control of the data direction
registers. Refer to INPUTS/OUTPUTS for additional information.
---------------------------------------------------------HD6805S1
order three bits (PCH) are stacked. This ensures that the
program counter is loaded correctly as the stack pointer
increments when it pulls data from the stack: A subroutine call
will cause only the program counter (PCH, PeL) contents to be
pushed onto the stack.
MEMORY
7
000
7
$00o
I/O Ports
Timer
RAM
(128 Bytes)
127
128
255
256
$0 F
$10o
Not Used
ROM
(704 Bytes)
959
960
$3B F
$3C
$783
$7 84
Self Check
ROM
(116 Bytes)
2039
2040
0
$000
Port B
$001
$002
Port C
Not Used
Port A DDR
$004*
Port B DDR
$005*
$006*
Not Used
Main
ROM
(964 Bytes)
1923
1924
Port A
$07 F
Page Zero
ROM
(128 Bytes)
$003
Port C DDR
Not Used
$008
$009
$007
$OOA
Not Used (54 Bytes)
$7F 7
$7F 8
Interrupt
Vectors
ROM
(8 Bytes)
63
12
$7F F
2047
$03F
$040
$07F
n-4
Condition
11 Code Register
Accumu lator
n-3
..1 Accumulator
A
1......________
Pull
n+1
n+2
L..._ _ _ _
X_ _ _ _...llndex
10
n-2
n-1
n
Index Register
1
11
PCl*
PCH*
n+3
n+4
10
L..._ _ _ _ _ _PC
_ _ _ _ _ _ _...
5 4
Register
Program Counter
1
...... .1...... .1....--'-'_....1_,....1_1....1___s_p___I Stack Pointer
n"+5
'
'
Push
For subroutine calls, only PCH and PCl are stacked
Carry/Borrow
Zero
Negative
Interrupt Mask
Half Carry
131
HD8806S1-------------------------------------------------------
REGISTERS
Accumulator (A)
I nterrupt (I)
This bit is set to mask the timer and external interrupt (INT).
If an interrupt occurs while this bit is set it is latched and will be
processed as soon as the interrupt bit is reset.
Negative (N)
Zero (Z)
Carry/Borrow (C)
TIMER
<1>2
(Internal)
Timer
Input
Pin
r-----.,
I
,
IL _____ .JI
Manufacturing
Mask Options
. . - - - - - - - - -... Time
Out
Timer
t----=!!Oot-~-6-~ Interrupt Req.
Timer
t-~;:-- Interrupt Mask
o
Write
Read
T
U
Timer
Control Register
S
E
o
Figure 5 Timer Block Diagram
132
---------------------------------------------------------HD6806S1
source of the clock input is one of the options that has to be
specified before manufacture of the MCV. A prescaler option
can be applied to the clock input that extends the timing
interval up to a maximum of 128 counts before being applied to
the counter. This prescaling option must also be specified before
manufacturing begins. The timer continues to count past zero
and its present count can be monitored at any time by
monitoring the timer data register. This allows a program to
determine the length of time since a timer interrupt has occured
and not disturb the counting process.
At power up or reset the prescaler and counter are initiallied
with all logical ones; the timer interrupt request bit (bit 7) is
cleared and the timer interrupt request mask bit (bit 6) is set.
SELF CHECK
RESETS
The MCV can be reset three ways: by initial powerup, by
A, 27
INT
A6 26
28 RES
As 25
XTAL
A, 23
EXTAL
A, 21
TIMER
Ao 20
HD6805S1
(Register optioni
B, 19
NUM
:c 2.2~F
A4 24
A2 22
+9V
B6 18
Vee
Bs 17
B4 16
Vee
= Pin
Co
B, 15
C,
B2 14
10 C2
B, 13
11 C,
Bo 12
Vss = Pin 1
5V -------------~-------__,.
Vee
LVR
OV---------J
RES
Pin
---------------r
Internal
Reset
133
Vee--~AJ\~--~--~
2 .2/ol F
Part of
HD6805S1
MCU
P EXTAL
5 EXTAL
4~a~Z
CJ
HD6805S1
MCU
4 XTAL
HD6805S1
MCU
4 XTAL
22PF20%I
5 EXTAL
5 EXTAL
External
Clock
Input
R
4 XTAL
HD6805S1
MCU
XTAL
HD6805S1
MCU
No
Connection
External Clock
CRYSTAL OPTIONS
RESISTOR OPTIONS
~~
XTAL~~EXTAL
4
~f-----J
J:
>u
[\
c:
\II
;:,
C"
LL
10
15
20
25
30
Resistance Iknl
35
40
134
J.
Vee = 5.25V
TA = 25C -
45
50
----------------------------------------------------------HD6805S1
1-+1
7F -+SP
o -+DDR's
Stack
PC, X, A, CC
TIMER
Load PC From
Reset: 7FE: 7FF
Load PC From
SWI: 7FC, 7FD
mT':7FA,7FB
TIMER: 7F8, 7F9
Fetch
Instruction
SWI
Execute
Instruction
Output
Data Bit
1/0 Pin
Data
Direction
Register
Bit
Output
Data Bit
Output
State
Input to
MCU
3State
Pin
135
HD8806S1-------------------------------------------------------
INTERRUPTS
Priority
Vector Address
RES
SWI
INT
TIMER
1
2
3
4
BIT MANIPULATION
The MCU has the ability to set or clear any single random
access memory or input/output bit (except the data direction
registers) with a single instruction (BSET, BCLR). Any bit in
the page zero read only memory can be tested, using the BRSET
and BRCLR instructions, and the program branches as a result
of its state. This capability to work with any bit in RAM, ROM
or I/O allows the user to have individual flags in RAM or to
handle single I/O bits as control lines. The example in Figure 15
illustrates the usefulness of the bit manipulation and test
instructions. Assume that bit 0 of port A is connected to a zero
crossing detector circuit and that bit 1 of port A is connected to
the trigger of a TRIAC which powers the controlled hardware.
This program, which uses only seven ROM locations.
provides tum-on of the TRIAC within 14 microseconds of the
zero crossing. The timer could also be incorporated to provide
turn-on at some later time which would permit pulse-width
modulation of the controlled power.
INPUT/OUTPUT
Ao
Port A
Port B
B,
A,
Port A Programmed as outputls) driving CMOS and TTL Load directlv.
la)
+V
+V
Port B
Port C
10mA max
C3
B,
136
--------------------------------------------------------HD8806S1
SELF 1
Bit Set/Clear
The MCU has ten addressing modes available for use by the
programmer. They are explained and illustrated briefly in the
following paragraphs.
Immediate
Refer to Figure 16. The immediate addressing mode accesses
constants which do not change during program execution. Such
instructions are two bytes long. The effective address (EA) is
the PC and the operand is fetched from the byte following the
opcode.
Direct
Refer to Figure 17. In direct addressing, the address of the
operand is contained in the second byte of the instruction.
Direct addressing allows the user to directly address the lowest
256 bytes in memory. All RAM space, I/O registers and 128
bytes of ROM are located in page zero to take advantage of this
efficient memory addressing mode.
Extended
Refer to Figure 18. Extended addressing is used to reference
any location in memory space. The EA is the contents of the
two bytes following the opcode. Extended addressing instructions are three bytes long.
Relative
Refer to Figure 19. The relative addressing mode applies only
to the branch instructions. In this mode the contents of the
byte following the opcode is added to the program counter
when the branch is taken. EA=(pc)+2+Rel. ReI is the contents
of the location following the instruction opcode with bit 7
being the Sign bit. If the branch is not taken Rel=O, when a
branch takes place, the program goes to .somewhere within the
range of +129 bytes to -127 of the present instruction. These
instructions are two bytes long.
Indexed (No Offset)
Refer to Figure 20. This mode of addressing accesses the
lowest 256 bytes of memory. These instructions are one byte
long and their EA is the contents of the index register.
Indexed (8-bit Offset)
Refer to Figure 21. The EA is calculated by adding the
contents of the byte following the opcode to the contents of
the index register. In this mode, 511 low memory locations are
accessable. These instructions occupy two bytes.
Indexed (16-bit Offset)
Refer to Figure 22. This addressing mode calculates the EA
by adding the contents of the two bytes following the opcode
to the index register. Thus, the entire memory space may be
accessed. Instructions which use this addressing mode are three
bytes long.
137
HD8806S1-------------------------------------------------------EA
Memory
I
I
I
F8
Index
eo
I
Stack Point
Prog Count
A6
1-------4
05CO
F8
CC
I
I
I
I
I
I
I
CAT
FCB
32
LOA
CAT
OO4B
/'
Adder
'"
ol
PROG
20
OO4B
lEA
Memory
0520
B6
052E
4B
J
I
I
Stack Point
I
052F
CC
I
I
I
I
I
Prog Count
20
Index Reg
138
--------------------------------------------------------HD8806S1
Memory
I
I
I
~
I
PROG
LOA
CAT
~~ J
O4OA
06
040B
E5
64
40
Index Reg
Stack Point
FCB
Prog Count
CAT
0000
06E5
040C
40
CC
Memory
i
I
Index Reg
Stack Point
I
I
PROG
BEQ
PROG2
0000
18
04C1
@
,I
I,
Figure 19
139
HD8806S1---------------------------------------------------------
EA
OOB8
Memory
TABL
FCC
t Lit OOB8
4C
4C
49
Index Reg
B8
PROG
LOA
Stack Point
05F4~
Prog Count
05F5
CC
JEA
Melory
i
FCB
#BF
0089
BF
FCB
#86
008A
86
FCB
#DB
008B
DB
FCB
#CF
008C
CF
/'
Adder
i
I
PROG
008C
TABL
'"
_.A
l
CF
Index Reg
03
Stack Point
LOA
TABL. X 075B
E6
075C
89
I
I
I,
Prog Count
I,
Figure 21
140
075E
CC
--------------------------------------------------------HD8806S1
Memory
~
I
PROG
LOA
TABL. X 0692
0693
A
DB
Index Reg
02
~6
Stack Point
07
~---~
7E
0694
Prog Count
0695
TABL
CC
BF
FCB
#BF
077E
FCB
#86
077F
86
FCB
#OB
0780
DB
FCB
#CF
0781
CF
Memory
PORTB
Eau
BF
0001
0000
Index Reg
PROG BCLR 6. PORT B
058F J-_ _ _
10
_ _--I
0590
Stack Point
01
Prog Count
0591
I
CC
I
I
141
HD8806S1---------------------------------------------------------
PORT C
eau
0002
FO
Index Reg
0000
Stack Point
0574
0575
0576
.....
05
Prog Count
----~
0000
02
----~
10
.....
0594
cc
c
Memory
i
I
I
I
E5
Index Reg
I
E5
PROG
TAX
O~A~
Prog Count
05BB
cc
I
Figure 25
142
--------------------------------------------------------HD8806S1
Table 2 Register/Memory Instructions
Addressing Modes
Function
Mnemonic
Op
Op
Op
#
#
#
#
Code Bytes CVetes Code Bytes Cycles Code
Indexed
(8Bit Offset)
Indexed
(No Offset)
Extended
Direct
Immediate
Op
#
#
Bytes Cycles Code
Op
#
#
Bytes Cycles Code
Indexed
(l6-Bit Offset)
Op
#
#
Bytes Cycles Code
Bytes Cycles
LOA
A6
B6
C6
F6
E6
06
LOX
AE
BE
CE
FE
EE
DE
Store A in Memory
STA
C7
F7
E7
07
STX
87
Store X in Memory
BF
CF
FF
EF
OF
Add Mllmory to A
ADD
AB
BB
CB
FB
EB
DB
AOC
A9
B9
C9
F9
E9
09
FO
EO
DO
CO
C2
F2
E2
02
C4
F4
E4
04
BA
CA
FA
EA
OA
B8
C8
F8
E8
08
B1
C1
F1
E1
01
A3
B3
C3
F3
E3
03
BIT
A5
B5
C5
F5
E5
05
Jump Unconditional
JMP
BC
CC
EC
DC
JSR
FC
Jump to Subroutine
BO
CD
FO
ED
DO
Subtract Memory
Subtract Memory from
A with Borrow
AND Memory to A
OR Memory with A
EXClusive OR Memory
with A
Arithmetic Compare A
with Memory
Arithmetic Compare X
with Memory
Bit Test Memory with A
(Logical Compare)
BO
B2
B4
AA
EOR
A8
CMP
A1
CPX
SUB
AO
SBC
A2
AND
A4
ORA
Implied (A)
Mnemonic
Op
Code
Implied (X)
Op
#
#
Bytes Cycles Code
Indexed
(No Offset)
Direct
Op
#
#
Bytes Cycles Code
Op
#
#
Bytes Cycles Code
Indexed
(8Bit Offset)
Op
#
#
Bytes Cycles Code
Bytes Cycles
Increment
INC
4C
5C
3C
7C
6C
Decrement
DEC
4A
5A
3A
7A
6A
Clear
CLR
4F
5F
3F
7F
6F
Complement
COM
43
53
33
73
63
Negate
(2's Complement)
NEG
40
50
30
70
60
ROL
49
59
39
79
69
ROR
46
56
36
76
66
LSL
48
58
38
78
68
LSR
44
54
34
74
64
ASR
47
57
37
77
67
ASL
48
58
38
78
68
TST
40
50
3D
70
60
143
Mnemonic
Op
Code
Bytes
Cycles
4
Branch Always
BRA
20
Branch Never
BRN
21
Branch IF Higher
BHI
22
BlS
23
BCC
24
4
4
(BHS)
24
BCS
25
(Branch IF lower)
(BlO)
25
4
4
BNE
26
Branch I F Equal
BEQ
27
BHCC
28
BHCS
29
Branch IF Plus
BPl
2A
Branch I F Minus
BMI
2B
BMC
2C
BMS
20
Bil
2E
BIH
2F
Branch to Subroutine
BSR
AD
Mnemonic
Bit Set/Clear
Op
Code
8ytes
Cycles
Op
Code
Bytes
Cycles
10
2 n
01+2 n
10
Set Bit n
10+2 n
Clear bit n
11+2 n
Mnemonic
Op
Code
Bytes
Cycles
2
Transfer A to X
TAX
97
Transfer X to A
TXA
9F
SEC
99
ClC
98
SEI
9B
CLI
9A
Software Interrupt
SWI
83
11
RTS
81
RTI
80
RSP
9C
No-Operation
NOP
90
144
---------------------------------------------------------HD6805S1
Table 7 Instruction Set
Mnemonic
Implied
ADC
ADD
AND
ASL
ASR
BCC
BClR
BCS
BEQ
BHCC
BHCS
BHI
BHS
BIH
Bil
BIT
BlO
BlS
BMC
BMI
BMS
BNE
BPl
BRA
BRN
BRClR
BRSET
BSET
BSR
ClC
CLI
ClR
CMP
COM
CPX
DEC
EOR
INC
JMP
JSR
lOA
lOX
Immediate
x
x
x
Direct
x
x
x
x
x
Extended
Relative
x
x
Addressing Modes
Indexed Indexed Indexed
(No
(8 Bits) (16 Bits)
Offset)
x
x
x
x
x
x
x
x
x
x
x
x
x
Condition Code
Bit
Setl
Clear
Bit
Test &
Branch
1\
1\
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
1\
1\
1\
1\
1\
1\
1\
1\
1\
1\
1\
1\
1\
1\
1\
1\
1\
0
1
1\
0
1\
1\
1\
1\
1\
1\
1\
1\
1\ 1\
1\ 1\
1\ 1\
1\
1\
1\
1\
(to be continued)
C
1\
Carry Borrow
Test and Set if True, Cleared Otherwise
Not Affected
145
Implied
Immediate
x
x
x
x
Zero
Extended
Relative
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
Bit
Set/
Clear
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
Direct
Condition Code
Indexed
Indexed Indexed
(No
(8 Bits) (16 Bits)
Offset)
x
x
x
x
x
x
Bit
Test &
Branch
1\
Carry/Borrow
Test and Set if True, Cleared Otherwise
Not Affected
Load CC Register From Stack
146
1\ 1\ 1\
0 1\ 1\
1\ 1\ 1\
1\ 1\
1\ 1\ 1\
1\ 1\ 1\
?
1\ 1\ 1\
1
1
1\ 1\
1\ 1\
1\ 1\ 1\
1
1\ 1\
---------------------------------------------------------HD6805S1
Table 8
Bit Manipulation
Test &
Branch
Set/
Clear
Rei
olR
3
I
I
A
4
I
I
X
5
BSETO
BRA
NEG
1 BRCLRO
BCLRO
BRN
BRSET1
BSET1
BHI
I
I
3 BRCLR1
BCLR1
BLS
COM
BRSET2
BSET2
BCC
LSR
BRCLR2
BCLR2
BCS
BRSET3
BSET3
BNE
ROR
BRCLR3
BCLR3
BEQ
ASR
8
9
A
B
C
0
E
BRSET4
BSET4
BHCC
LSL/ASL
BRCLR4
BCLR4
BHCS
BRSET5
BSET5
BPL
BRCLR5
BCLR5
BMI
BRSET6
BSET6
BMC
INC
BRCLR6
BCLR6
BMS
TST
BRSET7
BSET7
BIL
F BRCLR7
BCLR7
BIH
(NOTE)
2/7
2/4
,XO
1 7
1/4
IMP
IMM
olR
..... HIGH
RTI*
RTS*
CMP
SBC
CPX
AND
BIT
5 W
LOA
SWI*
SUB
TAX
ROL
SEC
DEC
CLI
SEI
ADD
JMP(-1)
JSR(-3)
0
E
CLR
2/6
IMP
3/10
,X1
Register /Memory
Control
Read/Modify /Write
Branch
BRSETO
Opcode Map
1/4
I 2/7 I 1/6
CLC
RSP
J
BSR* I
-
NOP
TXA
1/*
1/2
2/2
STA(+1)
EOR
AoC
8
9
ORA
LOX
I
I
STX(+1)
2/4
3/5
3/6
I 2/5 I 1/4
147
HD6805U1
MCU (Microcomputer
Unit)
HD6805U1P
HARDWARE FEATURES
8Bit Architecture
96 Bytes of RAM
Memory Mapped I/O
2056 Bytes of User ROM
Internal 8-Bit Timer with 7Bit Prescaler
Vectored Interrupts - External and Timer
24 I/O Ports + 8 Input Port
(8 Lines LED Compatible; 7 Voltage Comparator Inputs)
OnChip Clock Circuit
SelfCheck Mode
Master Reset
Low Voltage Inhibit
Complete Development System Support by Evaluation Kit
5 Vdc Single Supply
(DP40)
SOFTWARE FEATURES
Similar to HD6800
Byte Efficient Instruction Set
Easy to Program
True Bit Manipulation
Bit Test and Branch Instructions
Versatile Interrupt Handing
Powerful Indexed Addressing for Tables
Full Set of Conditional Branches
Memory Usable as Registers/Flags
Single Instruction Memory Examine/Change
10 Powerful Addressing Modes
All Addressing Modes Apply to ROM, RAM and I/O
Compatible Instruction Set with MC6805P2
PIN ARRANGEMENT
A,
A,
A,
A,
A,
A,
A,
A.
B,
c,
BLOCK DIAGRAM
TIMER
8,
Accumuiltor
A
B,
8.
8,
8.
CPU
ContrOl
I, lin
A,
Port
A
1/0
A,
A1
A,
A.
Lines A,
A,
A,
POtt
B
I/O
Oa'i
Ott
RI9
Reglst.r CC
Stack
POint.,
B,
c,
B,
C,
B,
C,
Bu
D,
D,
D,
D,
D,
(Top View)
CPU
C,
Sp
Program
Count.,
"H;g/I" PCH
Progrlm
Count.,
B,
C,
B.
c-
B,
C,
B,
Condition
Port
A
Rot
C,
AlU
C,
C.
C,
C.
C.
C,
C,
Port
C
1/0
Lints
"Low" PCl
D,
D.
D. Port
20&6.8
ROM
D,
D
D. Input
D. Lints
D,
Soffcllock
ROM
D,
148
--------------------------------------------------------HD8806U1
ABSOLUTE MAXIMUM RATINGS
Value
Symbol
Item
Supply Voltage
Unit
Vee *
-0.3- +7.0
-0.3 - +7.0
-0.3 -+12.0
Operating Temperature
T opr
o -+70
V
c
Storage Temperature
T stg
- 55 - +150
Permanent LSI damage may occur if maximum ratings are exceeded. Normal operation should be under
recommended operating conditions. If these conditions are exceeded. it could affect reliability of LSI.
ELECTRICAL CHARACTERISTICS
DC CHARACTERISTICS (VCC=5.25V O.5V, VSS=GND, Ta=G-+70C, unless otherwise noted.)
Item
Symbol
Test Condition
min typ
RES
4.0
INT
3.0
All Other
V IH
2.0
Timer Mode
2.0
SelfCheck Mode
RES
INT
V IL
9.0
-0.3
-0.3
XT AL(Crystal Mode)
All Other
-0.3
-0.3
Po
LVR
LVI
Power Dissipation
-20
TIMER
INT
IlL
V in =0.4V-V ee
-50
XT AL(Crystal Mode)
-1200
max Unit
Vee
Vee
Vee
V
V
Vee
11.0
0.8
V
V
0.8
0.6
0.8
V
V
400 700
mW
4.75
4.0
20
p.A
50
/J. A
/J. A
AC CHARACTERISTICS (Vcc=5.25V O.5V, Vss=GND, Ta=O '" +70C, unless otherwise noted.)
Item
Symbol
min
Test Condition
Clock Frequency
fel
0.4
Cycle Time
teyc
1.0
fexT
tl WL
R ep =15.0kn1 %
typ
max Unit
10
/J.s
2.7
4.0
MHz
t cye +
250
ns
ns
4.0
MHz
tRWL
t cye +
250
tTWL
t eye +
250
ns
tose
100
ms
tRHL
100
ms
25
35
10
pF
pF
Input Capacitance
i\;':t.
I
I
EXTAL
All Other
Cin
149
C L=22pF20%,
Rs =60n max.
External Cap. = 2.2 /J.F
Vin=OV
Port
VOH
Port C
Port A and C
Output "Low" Voltage
Input "High" Voltage
Input "Low" Voltage
Port
VOL
Threshold Voltage
* Port 0
..
Unit
2.4
2.4
Port A,
and 0*
a, C,
Port 0**
(Do"" 0 6 )
Port 0**
(Do"'" 0 6 )
Port 0**(0,)
1.5
2.4
V
V
V
V
0.4
0.4
1.0
2.0
Vee
V IL
-0.3
0.8
-500
~A
-300
~A
20
~A
=0.8V
Vin = 2V
Vin = 0.4V"'" Vee
Vin
IlL
max
PortB,C,
and 0
Input "High" Voltage
typ
3.5
VIH
Port A
min
= -10~A
IOH = -100~A
IOH = -200~A
IOH = -1 mA
IOH = -100flA
IOL = 1.6 mA
IOL = 3.2 mA
IOL = 10mA
IOH
Port A
Output "High" Voltage
Test Condition
Symbol
Item
20
VIH
VTH+0.2
VIL
VTH-0.2
VTH
0. 8xV ee
as digital Input
** Port 0 as analog input
TTL Equiv. (Port A and C)
Vee
Ii = 3.2 rnA
...
Test Point
40 pF
(NOTE)
Ii = 1.6 rnA
Test Point
30 pF
12 kfl
2.4kfl
24 kfl
1. Load capacitance includes the floating capacitance of tt;i! probe and the jig etc.
2. All diodes are 1S20748 or equivalent.
SIGNAL DESCRIPTION
The input and output signals for the MCU shown in PIN
ARRANGEMENT are described in the following paragraphs.
Vee and Vss
Power is supplied to the MCU using these two pins. Vee
is +5 .25V 05V. V ss is the ground connection.
TIMER
INT
150
RES
NUM
_______________________________________________________ HD6806U1
MEMORY
The MCU memory is configured as shown in Figure 2. During
the processing of an interrupt, the contents of the MCU regi
sters are pushed onto the stack in the order shown in Figure 3.
Since the stack pointer decrements during pushes, the low order
byte (PCL) of the program counter is stacked first; then the
high order four bits (PCH) are stacked. This ensures that the
program counter is loaded correctly as the stack pointer in
crements when it pulls data from the stack. A subroutine call
will cause only the program counter (pCH, PCL) contents to
be pushed onto the stack.
These are 8~it input lines, which has two functions. Firstly,
these become TTL compatible inputs, by reading $003 address.
The other function of them is 7 Voltage comparators, by read
ing $007 address. Please refer to INPUT PORT for more detail.
o
$000
000
1/0 Ports Timer
RAM (128 Bytes)
$07
127
128
1,\
ROM
(128 Bytes)
$OF
$1
255
256
Not Used
Port A
Port B
$001
Port C
$002
Port D (digital)
$003"
Port A DDR
$004"
Port B DDR
$005"
Port C DDR
2047
2048
$7F
sa
$000
$006"
$007""
Port D (analog)
$008
$009
$OOA
0
Not Used (22 Bytes)
ROM
(1920 Bytes)
Sttek
12
3967
3968
4087
4088
$F7 F
$F 80
$FF 7
$FF 8
Self-Test
Interrupt Vectors
$07F
$FF
4095
$01F
$020
6
n-4
5
1
Condition
11 Code Register
Accumulator
n-3
Pull
n+1
n+2
11
n-2
n-1
n
Index Register
1
PCl*
PCH*
n+3
n+4
Accumulator
I
I
I
Index Register
0
PC
11
Program Counter
0
SP
Stack Pointer
n+5
Condition Code Register
Push
* For subroutine calls, only PCH and PCl are stacked.
Carry/Borrow
Zero
Negative
Interrupt Mask
Half Carry
151
HD8806U1-------------------------------------------------------
REGISTERS
Accumulator (A)
Interrupt (I)
Trus bit is set to mask the timer and external interrupt (INT).
If an interrupt occurs while this bit is set it is latched and will be
processed as soon as the interrupt bit is reset.
Negative (N)
Zero (Z)
Carry/Borrow (C)
TIMER
cf>2
(Internal)
Timer
Input
Pin
,.-----,
I
I
L
I _____ .II
Manufacturing
Mask Options
- - - - - - - - -... Time
Out
7
Timer
t---::~--t1-6-~ Interrupt Req.
Timer
t---fo'I;~- Interrupt Mask
N
Write
Read
T
U
Timer
Control Register
o
Figure 5 Timer Block Diagram
152
--------------------------------------------------------HD8806U1
the counter. This pre scaling option must also be specified before
manufacturing begins. The timer continues to count past zero
and its present count can be monitored at any time by monitoring the timer data register. This allows a program to determine
the length of time since a timer interrupt has occured and not
disturb the counting process.
The Timer Data Register is 8-bit Read/Write Register with
address $008 on Memory-Map. This Timer Data Register and
the prescaler are initialize with all logical ones at Reset time.
The Timer Interrupt Request bit (bit 7 of Timer Control
Register) is set to one by hardware when timer count reaches
zero, and is cleared by program or by hardware reset. The bit 6
of Timer Control Register is writable by program. Both of those
bits can be read by MPU.
SELF CHECK
RESETS
INT
REs
As 38
XTAL
A3 36
'--
A, 40
A. 39
T2.~F
A.E-
A, 35
A, 34
EXTAL
+9V
V cc
130n
7 NUM
10kn
AI\.
l~~v
v
10kn
~~,,-v
1~~
vv
= Pin4
Vss '" Pin 1
B. 31
B. 29
C.
3l0n ~ I::i\ 10
C.
A'-I\."
33an .~ 1 1 C.
~A
30
~ ~12 C 3
vv v
E-
Bs 30
r.::::i
A.
HD6805U1.
B,~
B, '17
8, 26
B. 25
13 C.
14 C
15
c.
16 C,
Re f er to Fi gure 9 about crystal option
V cc
Vec
OV--------------J
RES
Pin
--------r
Internal
Reset
153
HD8806U1-------------------------------------------------------
Vee
Part of
HD6805U1
MCU
6 EXTAl
6 EXTAl
M HZ
4 ma x
c:J 5 XTAl
HD6805U1
MCU
HD6805U1
MCU
5 XTAl
22P F20%T
,,,,,r__6.... EXT A l
6 EXTAl
External
Clock
Input
R
5 XTAl
HD6805U1
MCU
5 XTAl
HD6805U1
MCU
No
Connection
External Clock
CRYSTAL OPTIONS
RESISTOR OPTIONS
C,
XTAl~~EXTAl
5
~~
::I:
>
(.)
\,
C
II>
~
AT Co =
f=4
Rs =
u:
"-
".~
10
15
20
25
30
Resistance /kn)
"-
35
~~
40
154
Vee = 5.25V
T A = 25C -
45
50
________________________________________________________ HD8806U1
1 .... I
7F .... SP
o .... DDR's
Stack
PC,X,A,CC
TIMER
Load PC From
Reset: FFE, FFF
Load PC From
SWI: FFC, FFD
TNT: FFA, FFB
TIMER: FF8, FF9
Fetch
Instruction
SWI
Execute
Instruction
Output
Data Bit
1/0 Pin
Data
Direction
Register
Bit
155
Output
Data Bit
Output
State
Input to
MCU
1
1
3State
Pin
HD8806U1--------------------------------------~-------------
INTERRUPTS
Priority
Vector Address
RES
INPUT
SWI
TNT
BIT MANIPULATION
TIMER
The MCU has the ability to set or clear any single random
access memory or input/output bit (except the data direction
registers) with a single instruction (BSET, BCLR). Any bit in
the page zero read only memory can be tested, using the BRSET
and BRCLR instructions, and the program branches as a result
of its state. This capability to work with any bit in RAM, ROM
or I/O allows the user to have individual flags in RAM or to
handle single I/O bits as control lines. The example in Figure 16
illustrates the usefulness of the bit manipulation and test
INPUT/OUTPUT
Bo
Ao
Port A
Port B
(a)
(b)
+V
+V
Port B
Port C
10 mA max
(c)
156
---------------------------------------------------------HD8806U1
instructions. Assume that bit 0 of port A is connected to a zero
crossing detector circuit and that bit 1 of port A is connected to
the trigger of a TRIAC which power the controlled hardware.
This program, which uses only seven ROM locations, pro-
$003 Read
Internal Bus
(BitO - BitS)
$003 Read
Internal Bus
(Bit 7)
(a) The logic configuration of Port 0
Port
~-
C
0,
Reference Level
06
Port
Analog Input S
Do
0,
Port
06
t----Analog Input S
Do
t-----Analog Input 0
Analog Input 0
0,
VTH (= 3.5V)
06
3 Levels Input S
Port
0
\
Do
Input
Voltage
($003)
($007)
OV -O.SV
2.0V - 3.3V
1
1
3.7V - Vee
3 Levels Input 0
157
HD6806U1---------------------------------------------------------
SELF 1
Bit Set/Clear
The MCU has ten addressing modes available for use by the
programmer. They are explained and illustrated briefly in the
following paragraphs.
Implied
INSTRUCTION SET
ADDRESSING MODES
Immediate
Direct
Extended
Relative
Register/Memory Instructions
Read/Modity/Write Instructions
These instructions are used on any bit in the first 256 bytes
of the memory. One group either sets or clears. The other group
performs the bit test and branch operations. Refer to Table 5.
Control Instructions
Alphabetical Listing
158
------------------------------------------------------HD8806U1
Memory
I
I
I
Stack Point
.....------4
A6
Prog Count
F8
05CO
CC
~
I
I
I
I
lEA
Memory
I
I
I
I
I
I
I
I
I
I
CAT
FCB
32
LOA
CAT
004B
Adder
'"
oo~oo
20
OO4B
PROG
-I
B6
052E
4B
I
Stack Point
I
I
I
I
I
I
:
,
159
20
-1
Index Reg
0520
_I
I
I
Prog Count
052F
CC
HD880&U1-----------------------------------------------------
Memory
0000
A
40
PROG
LOA
CAT
Index Reg
Stack Point
Prog Count
CAT
FCB
64
06E5
. . .-----...j
40
040C
CC
EA
04C1
Memory
i
Index Reg
Stack Point
PROG
BEQ
PROG2
04A7
04A8
27
0000
1-------1
18
~
I
I
160
--------------------------------------------------------HD8806U1
EA
OOB8
Memory
TABL
4C
4C
49
Index Reg
B8
Stack Point
PROG
LOA
X
Prog Count
05F5
CC
Figure 21
lEA
Melory
TABL
FCB
#BF
0089
BF
FCB
#86
OOSA
86
FCB
#OB
oo8B
DB
FCB
#CF
008C
CF
I
LOA
008C
L'
1
Adder
I
I
t
PROG
'"
-.
CF
Index Reg
03
Stack Point
TABL. X 075B
E6
075C
89
I
I
Prog Count
161
075E
CC
HD8806U1------------------------------------------------------
Memory
i
I
DB
Index Reg
PROG
LOA
TABL. X 0692
0693
0694
02
~6
07
Stack Point
~______- J
7E
Prog Count
0695
I
TABL
CC
FCB
#BF
077E
BF
FCB
#86
077F
86
FCB
#OB
0780
DB
FCB
#CF
0781
CF
Memory
PORT B EQU
BF
0001
A
0000
Index Reg
10
0590
Stack Point
01
Prog Count
0591
I
CC
I
I
,I
Figure 24 Bit Set/Clear Addressing Example
162
-------------------------------------------------------HD8806U1
PORT C
Eau
0002
FO
Index Reg
0000
Stack Point
0574
0575
0576
05
Prog Count
02
0594
. . . -----....f
1--------1
10
CC
C
Memory
i
I
I
A
E5
Index Reg
ES
PROG
TAX
05BA~
Prog Count
05B8
CC
I
163
Mnemonic
Immediate
Indexed
(No Offset)
Extended
Direct
Op
Op
Op
#
#
#
#
Code Bytes Cycles Code Bytes Cycles Code
Op
#
#
Bytes Cycles Code
Indexed
(8-Bit Offset)
Op
#
#
Bytes Cycles Code
Indexed
06-Bit Offset)
Op
#
#
Bytes Cycles Code
Bytes Cycles
LOA
A6
B6
C6
F6
E6
06
LOX
AE
BE
CE
FE
EE
DE
Store A in Memory
STA
B7
C7
F7
E7
07
STX
'-
Store X in Memory
BF
CF
FF
EF
OF
Add Memory to A
ADD
AB
BB
CB
FB
EB
DB
AOC
A9
B9
C9
F9
E9
09
Subtract Memory
SUB
AO
BO
CO
FO
EO
DO
sec
A2
B2
C2
F2
E2
02
AND Memory to A
AND
A4
B4
C4
F4
E4
04
OR Memory with A
ORA
AA
BA
CA
FA
EA
OA
Exclusive OR Memory
with A
EOR
A8
B8
C8
F8
E8
08
Arithmetic Compare A
with Memory
CMP
A1
B1
C1
F1
E1
01
Arithmetic Compare X
with Memory
CPX
A3
B3
C3
F3
E3
03
BIT
A5
B5
C5
F5
E5
05
Jump Unconditional
JMP
CC
FC
EC
DC
JSR
BC
Jump to Subroutine
BO
CD
FO
ED
DO
Implied (A)
Mnemonic
Op
Code
Implied (X)
Op
#
#
Bytes Cycles Code
Indexed
(No Offset)
Direct
Op
Op
#
#
Bytes Cycles Code
Indexed
(8-Bit Offset)
Op
#
#
Bytes Cycles Code
Bytes Cycles
Increment
INC
4C
5C
3C
7C
6C
Decrement
DEC
4A
5A
3A
7A
6A
Clear
CLR
4F
5F
3F
7F
6F
Complement
COM
43
53
33
73
63
Negate
(2's Complement)
NEG
40
50
30
70
60
ROL
49
59
39
79
69
ROR
46
56
36
76
66
LSL
48
58
38
78
68
7
7
LSR
44
54
34
74
64
ASR
47
57
37
77
67
ASL
48
58
38
78
68
TST
40
50
3D
70
60
164
---------------------------------------------------------HD8806U1
Table 4 Branch Instructions
Relative Addressing Mode
Mnemonic
Function
Op
Code
Bytes
Cycles
Branch Always
BRA
20
Branch Never
BRN
21
Branch IF Higher
BHI
22
BlS
23
BCC
24
(BHS)
24
BCS
25
(Branch IF lower)
(BlO)
25
BNE
26
4
4
Branch I F Equal
BEQ
27
BHCC
28
BHCS
29
Branch I F Plus
BPl
2A
Branch IF Minus
BMI
2B
BMC
2C
BMS
20
Bil
2E
BIH
2F
Branch to Subroutine
BSR
AO
Mnemonic
Bit Set/Clear
Bytes
Cycles
Op
Code
Op
Code
Bytes
Cycles
2n
10
01+2n
10
Set Bit n
10+2n
Clear bit n
11+2n
Mnemonic
Op
Code
Bytes
Cycles
2
Transfer A to X
TAX
97
Transfer X to A
TXA
9F
SEC
99
ClC
98
SEI
9B
CLI
9A
Software Interrupt
SWI
83
11
RTS
81
RTI
80
RSP
9C
No-Operation
NOP
90
165
Immediate
Direct
Extended
ADC
ADD
x
x
AND
ASL
ASR
Relative
Condition Code
Indexed
Indexed Indexed
(No
(8 Bits) (16 Bits)
Offset)
x ,
x
x
Bit
Set/
Clear
BHCC
BHI
BHS
BIH
BIL
BIT
x
x
BLS
BMC
BMI
BMS
BNE
x
x
x
x
BPL
BRA
BRN
COM
EOR
x
x
x
CPX
DEC
x
x
x
x
x
x
x
x
x
x
x
JSR
x
x
x
x
x
x
x
x
x
x
LOA
LOX
1\
1\
1\
1\
1\
JMP
INC
1\
1\
1\
1\
CMP
1\
x
x
1\
1\
BSET
1\
x
x
CLR
BRCLR
CLI
1\
BRSET
BSR
BLO
1\
x
x
x
BHCS
BEQ
BCLR
BCS
x
x
BCC
CLC
Bit
Test &
Branch
x
x
x
x
x
1\
1\
1\
1\
1\
0
1
0
1\
1\
1\
1\
1\
1\
1\
1\
1\
1\
1\
1\ 1\
1\ 1\
1\ 1\
1\
(to be continued)
C
1\
Carry Borrow
Test and Set if True, Cleared Otherwise
Not Affected
166
---------------------------------------------------------HD8806U1
Table 7 Instruction Set
Addressing Modes
Mnemonic
LSL
LSR
NEG
NOP
ORA
ROL
ROR
RSP
RTI
RTS
SBC
SEC
SEI
STA
STX
SUB
SWI
TAX
TST
TXA
Implied
Immediate
x
x
x
Direct
Extended
Relative
x
x
x
Condition Code
Indexed
Indexed Indexed
(No
(8 Bits) (16 Bits)
Offset)
x
x
x
x
x
x
Bit
Set!
Clear
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
C
/\
Carry IBorrow
Test and Set if True, Cleared Otherwise
Not Affected
Load CC Register From Stack
167
Bit
Test & H
Branch
/\ /\ /\
0 /\ /\
/\ /\ /\
/\ /\
/\ /\ /\
/\ /\ /\
1
1
/\ /\ /\
1
/\ /\
/\ /\
/\ /\ /\
/\ /\
HD8806U1-----------------------------------------------------Table 8
Bit Manipulation
Control
Read/Modify /Write
Branch
Test &
Branch
Set/
Clear
Rei
OIR
0
BRSETO
BSETO
2
BRA
1 BRCLRO
BCLRO
Opcode Map
,XO
IMP
IMP
IMM
NEG
RTI
BRN
RTS
A
4
X
5
,Xl
6
BRSETI
BSET1
BHI
SWI
1 1
OIR
Register/Memory
EXT
I )(2
)(1
0
SUB
,XO
1F
+- HIGH
CMP
SBC
CPX
AND
BRCLAI
BCLRI
BLS
COM
BASET2
BSET2
BCC
LSR
BACLA2
BCLR2
BCS
BIT
5 W
6
7
BRSET3
BSET3
BNE
ROA
LOA
BACLR3
BCLR3
BEQ
ASR
TAX
6
7
8 BRSET4
9 BACLR4
BSET4
BHCC
LSL/ASL
BCLR4
BHCS
ROL
BASET5
BSET5
BPL
DEC
B BRCLR5
BCLR5
BMI
C BRSET6
BSET6
BMC
INC
BRCLR6
BCLA6
BMS
TST
E BRSET7
BSET7
BIL
F BRCLR7
BCLA7
BIH
CLR
3/10
(NOTE)
2/7
2/4
2)6
I 1/4
1/4
I 2/7
I 1/6
1/
STA(+I)
CLC
EOR
SEC
AOC
CLI
ORA
ADD
SEI
RSP
NOP
8
9
A
B
JMP(-ll
BSRI
JSR(-3)
LOX
STX(+l1
TXA
1/2
2/2
2/4
I 3/5
I 3/6
F
2/5
168
I 1/4
HD6805V1
MCU (Microcomputer
Unit)
HD6805V1P
HARDWARE FEATURES
8-Bit Architecture
96 Bytes of RAM
Memory Mapped I/O
3848 Bytes of User ROM
Internal 8-Bit Timer with 7-Bit Prescaler
Vectored Interrupts - External and Timer
24 I/O Ports + 8 Input Port
(8 Lines LED Compatible; 7 Voltage Comparator Inputs)
On-Chip Clock Circuit
Self-Check Mode
Master Reset
Low Voltage Inhibit
Complete Development System Support by Evaluation Kit
5 Vdc Single Supply
SOFTWARE FEATURES
Similar to HD6800
Byte Efficient Instruction Set
Easy to Program
True Bit Manipulation
Bit Test and Branch Instructions
Versatile Interrupt Handing
Powerful Indexed Addressing for Tables
Full Set of Conditional Branches
Memory Usable as Registers/Flags
Single Instruction Memory Examine/Change
10 Powerful Addressing Modes
All Addressing Modes Apply to ROM, RAM and I/O
Compatible Instruction Set with MC6805P2
BLOCK DIAGRAM
(DP40)
PIN ARRANGEMENT
A,
A,
A,
A.
A,
A,
A,
A,
B,
c,
C,
C,
C.
c,
C,
TIMER
c,
8,
Accumulator A
CPU
ContrOl
Index
RegISter
A,
A,
Pott
A
I/O
Lines
A,
A,
A.
AI
A.
A,
Condition
Port
D,,,
O'f
1'109
1'109
C_
RegIster CC
SlICk
POinter
Pr09r.m
Counter
"Low" PCL
3848.8
1/0
8, lin"
B.
B,
ALU
C.
C.
C.
C,
Port
C
1/0
Lines
0,
0,
0, Port
ROM
0,
D.
Input
OJ
Lin..
SelfctM:ck
O.
ROM
0,
D,
0,
D,
D.
(Top View)
C,
C,
C,
C,
Program
Counte,
.. H ...... PCH
Port
CPU
Sp
8,
8,
8,
B.
D,
Symbol
Item
Supply Voltage
Vee
V ln
*
*
Unit
-0.3- +7.0
-0.3-+7.0
-0.3 -+12:0
V
c
c
Operating Temperature
Top'
o -+70
Storage Temperature
Tstg
- 55 - +150
ELECTRICAL CHARACTERISTICS
DC CHARACTERISTICS (Vcc-5.25V O.5V, VSS-GND, Ta=G-+70C, unless otherwise noted.)
Item
Input "High" Voltage
Symbol
INT
3.0
max Unit
Vee
Timer Mode
2.0
9.0
Vee
11.0
Selt-Check Mode
-0.3
0.8
0.8
0.6
0.8
V
V
V ,H
2.0
INT
V ,L
-0.3
XTAL(Crystal Mode)
All Other
-0.3
-0.3
Power Dissipation
Po
LVR
LVI
-20
TIMER
INT
RES
Input "Low" Voltage
min typ
4.0
All Other
Input "High" Voltage Timer
Test Condition
RES
IlL
V in =0.4V-Vee
XT AL(Crystal Mode)
-50
-1200
Vee
Vee
400 700
4.0
mW
4.75
20
loLA
50
p.A
p.A
Symbol
Test Condition
min
Clock Frequency
fcl
0.4
Cycle Time
tCYC
1.0
fexT
typ
max Unit
4.0 MHz
10
p.s
2.7
4.0
MHz
t'WL
t2~
ns
tRWL
tc c+
2 0
ns
tTWL
t ;;
2
ns
tose
100
ms
ms
tRHL
I
I
EXTAL
All Other
Cin
170
R ep=15.0kn1%
C L=22pF20%,
Rs=60n max.
External Cap. = 2.2p.F
Vin=OV
100
25
6
35-
pF
10
p,F
---------------------------------------------------------HD6806V1
PORT ELECTRICAL CHARACTERISTICS (Vee = 5.25V 0.5V, Vss = GNO, Ta
Item
Symbol
Test Condition
IOH = -10JJ,A
Port A
IOH =-100JJ,A
Output "High" Voltage
IOH = -200JJ,A
VOH
Port B
IOH = -1 mA
Port C
IOH = -100'JJ,A
Port A and C
IOL = 1.6 mA
Output "Low" Voltage
IOL =3.2 mA
VOL
Port B
IOL = 10 mA
Input "High" Voltage
VIH
Port A, B, C,
and 0*
Input "Low" Voltage
VIL
I
Port A
..
Port B, C,
and 0
Port 0**
(Do'" 0 6 )
Port 0**
(Do'" 0 6 )
Port 0**(0,)
typ
max
0.4
0.4
1.0
Vee
0.8
Unit
V
V
V
V
V
V
V
V
V
V
JJ,A
JJ,A
- 20
20
JJ,A
VIH
VTH+0.2
VIL
VTwO.2
VTH
0. 8xV ee
Vin
Vin
IlL
Vin
=0.8V
=2V
=O.4V '" Vee
2.0
-0.3
-500
-300
Vee
Ii = 3.2 mA
..
Test Point
40pF
(NOTE)
C)
Ii
Test Point
30 pF
12 kn
= 1.6 mA
2.4kn
24 kn
SIGNAL DESCRIPTION
The input and output signals for the MCU shown in PIN
ARRANGEMENT are described in the following paragraphs.
Vee and Vss
Power is supplied to the MCU using these two pins. Vee
is +5.25V O.5V. Vss is the ground connection.
INT
XT AL and EXTAL
171
TIMER
RES
NUM
HD6806V1--------------------------------------------------------
MEMORY
The MCU memory is configured as shown in Figure 2. During
the processing of an interrupt, the contents of the MCU registers are pushed onto the stack in the order shown in Figure 3.
Since the stack pointer decrements during pushes, the low order
byte (PCL) of the program counter is stacked first; then the
high order four bits (PCH) are stacked. This ensures that the
program counter is loaded correctly as the stack pointer increments when it pulls data from the stack. A subroutine call
will cause only the program counter (pCH, PCL) contents to
be pushed onto the stack.
These 24 lines are arranged into three 8-bit ports (A, Band
C). All lines are programmable as either inputs or outputs under
software control of the data direction registers. Refer to INPUTS/OUTPUTS for additional information.
These are 8-bit input lines, which has two functions. Firstly,
these become TTL compatible inputs, by reading $003 address.
The other function of them is 7 Voltage comparators, by reading $007 address. Please refer to INPUT PORT for more detail.
000
$000
1/0 Ports Timer
RAM (128 Bytes)
Port A
Port B
$001
Port C
$002
$000
Port 0 (digitel)
$003**
Port A DDR
$004*
$005
Port BOOR
Port C DDR
$006*
Port 0 (analog)
$007**
$008
$009
ROM
(3840 Bytes)
3967
3968
$OOA
Not Used (22 Bytes)
Self-test
4087
4088
31
3
Interrupt
Vectors
(8 Bytes)
St~k
12
$07F
$FFF
4095
$01F
$020
6
n-4
5
1
1-,
Condition
Code Register
Pull
n+1
n-3
Accumulator
n+2
n-2
Index Register
n+3
11
n-1
n
11
PCl *
PCH*
n+4
P_C
_ _ _ _ _ _...... Program Counter
LI_ _ _ _ _ _ _
11
5 4
n'+5
Condition Code Register
Push
* For subroutine calls, only PCH and PCl are stacked.
Carry IBorrow
Zero
Negative
Interrupt Mask
Half Carry
172
---------------------------------------------------------HD6805V1
REGISTERS
Interrupt (I)
Negative (N)
This bit is set to mask the timer and external interrupt (00).
If an interrupt occurs while this bit is set it is latched and will be
processed as soon as the interrupt bit is reset.
Zero (Z)
TIMER
1/>2
(Internal)
Timer
Input
Pin
r-----.,
I
I
I
I _____ .1
L
I
I
, . . - - - - - - - - - - , Time
Out
7
Timer
t--~~--If-6-~ Interrupt Req.
Timer
I-~;:-- Interrupt Mask
Manufactu ring
Mask Options
o
Write
Read
T
U
Timer
Control Register
E
D
o
Figure 5 Timer Block Diagram
173
iNT
REs
SELF CHECK
RESETS
A, 40
A. 39
As 38
A. 37
2 .2#F
5 XTAL
A) 38
A, 35
A, 34
6 EXTAL
+9V
A. 33
HD6806V1.
B, 31
Bs 30
Vee
B. 29
Co
B) 28
10 C.
11 C,
B, 27
12 C,
B. 25
B,
13 C
4
10kO
10kn
1o.kn
14 C,
15 C,
16 C,
Refer to Figure 9 about crystal option
Vee=Pin4
Vss = Pin 1
Vee
OV--------------J
REs
Pin
----------------~
InterOll'
Reset
174
---------------------------------------------------------HD6805V1
Vee
Part of
HD6805V1
MCU
6 EXTAL
6 EXTAL
4 MHz
max
c::J
HD6805V1
MCU
5 XTAL
HD6805V1
MCU
5 XTAL
22PF:t20%T
6 EXTAL
6 EXTAL
R
External
Clock
Input
5 XTAL
HD6805V1
MCU
HD6805V1
MCU
XTAL
5
No
Connection
External Clock
CRYST AL OPTIONS
RESISTOR OPTIONS
,
1\
XTAL~~EXTAL
5
L---f~
II
C,
4
:I:
Vee = 5.25V
TA = 25C -
c:
Q)
::l
AT Co =
f=4
Rs =
cr
~
LL
~~
~~
10
15
20
25
30
Resistance (knl
35
40
175
45
50
HD6805V1---------------------------------------------------------
1 ..... 1
7F ..... SP
o ..... DDRs
Stack
PC,X,A,CC
TIMER
Load PC From
Reset: FFE, FFF
Load PC From
SWI: FFC, FFD
TNT: FFA, FFB
TIMER: FF8. FF9
Fetch
Instruction
SWI
Execute
Instruction
Output
Data Bit
I/O Pin
Data
Direction
Register
Bit
1
1
0
176
Output
Data Bit
Output
State
Input to
MCU
3-State
Pin
---------------------------------------------------------HD6805V1
programmed for outputs, it is capable of sinking 10 millamperes
on each pin (VOL = 1V max). All input/output lines are TTL
compatible as both inputs and outputs. Port A lines are CMOS
compatible as outputs while port Band C lines are CMOS compatible as inputs. Figure 14 provides some examples of port
connections.
INTERRUPTS
The MeU can be interrupted three different ways: through
the external interrupt (INT) input pin, the internal timer interrupt request. and a software interrupt instruction (SWI). When
any interrupt occurs, processing is suspended, the present MeU
state is pushed onto the stack, the interrupt bit (I) in the condition code register is set, the address of the interrupt routine is
obtained from the appropriate interrupt vector address, and the
interrupt routine is executed. The interrupt service routines
normally end with a return from interrupt (RTI) instruction
which allows the MeU to resume processing of the program
prior to the interrupt. Table 1 provides a listing of the interrupts, their priority, and the vector address that contain the
starting address of the appropriate interrupt routine.
A flowchart of the interrupt processing sequence is given
in Fig. 12.
INPUT
Port D is 8-bit input port, which has two functions. One of
them is usual digital signal input port and the other is voltage
compare type input port. In the former case, the input data
can be read by MPU at $003 address. In the latter case, D7
(pin 17) is the input pin of V1H (reference level), and the other
seven input pins (Do"'" 0 6 ) are analog level inputs, which are
compared with VTH (see Figure 15(a), (b.
"I" or "0" signals appear at internal data bus, if the input
levels are higher or lower respectively when $001 address is
read. This function is effective in such case that unusual logic
level inputs are used. A capacitive touch panel interface and
a diode isolated keyboard interface are the examples. Figure
IS( c) shows the application of Port D to A/D converter, and
Figure IS(d) shows 3 levels inputs.
Vector Address
$FFE and $FFF
SWI
1
2
TNT
TIMER
Interrupt
RES"
BIT MANIPULATION
The MCU has the ability to set or clear any single random
access memory or input/output bit (except the data direction
registers) with a single instruction (BSET, BCLR). Any bit in
the page zero read only memory can be tested, using the BRSET
and BRCLR instructions, and the program branches as a result
of its state. This capability to work with any bit in RAM, ROM
or I/O allows the user to have individual flags in RAM or to
handle single I/O bits as control lines. The example in Figure 16
illustrates the usefulness of the bit manipulation and test
INPUT/OUTPUT
There are 24 input/output pins. All pins are programmable
as either inputs or outputs under software control of the data
direction registers. When programmed as outputs, all I/O pins
read latched output data regardless of the logic level at the
output pin due to output loading (see Fig. 13). When port B is
Bo
Ao
Port A
Port B
Ie" hFE' 18
B,
Port A Programmed as output(s) driving CMOS and TTL Load directly.
(a)
Ib)
+V
+V
Bo
Port B
Port C
10mA max
B,
C,
Ie)
177
$003 Read
Input Port
(00- 0 6)
Internal Bus
(BitO - Bit6)
$003 Read
Internal Bus
(Bit 7)
(a) The logic configuration of Port 0
Port
~-
07
Reference Level
0,
Port
Analog Input 6
Do
0,
Port
0,
r-"----Analog Input 6
Do
r----Analog Input 0
Analog Input 0
10
VTH (= 3.5V)
0,
Port
3 Levels Input 6
Do
Input
Voltage
($003)
($007)
OV-0.8V
2.0V - 3.3V
1
1
3.7V- V CC
3 Levels Input 0
178
----------------------------------------------------------HD6805V1
SELF 1
Bit Set/Clear
The MCV has ten addressing modes available for use by the
programmer. They are explained and illustrated briefly in the
following paragraphs.
ADDRESSING MODES
Immediate
Direct
Extended
Relative
Implied
These instructions are used on any bit in the first 256 bytes
of the memory. One group either sets or clears. The other group
performs the bit test and branch operations. Refer to Table 5.
Control Instructions
Alphabetical Listing
179
HD8805V1--------------------------------------------------------EA
Memory
I
I
Stack Point
I
I
A6
Prog Count
1-------1
OSCO
F8
CC
I
I
I
I
lEA
Memory
I
I
I
I
I
I
I
I
I
FCB
32
LOA
CAT
Adder
'"
Joo
20
OO4B
I
L
0520
B6
052E
4B
I
Stack Point
I
Prog Count
052 F
CC
~
I
I
I
I
180
20
Index Reg
PROG
004B
CAT
I
I
--------------------------------------------------------HD6806V1
Memory
I
I
~
I
PROG
LOA
CAT
-~J
O4OA
06
040B
E5
64
40
Index Reg
Stack Point
I
I
FCB
CAT
0000
Prog Count
40
06E5
040C
CC
EA
Memory
04C1
i
I
Index Reg
Stack Point
PROG
BEQ
PROG2
04A 7
0000
27
t--------1
O4A8
18
04C1
181
HD6805V1---------------------------------------------------------
Memory
TABL
FCC / LI /00B8
4C
4C
49
Index Reg
B8
PROG
LOA
Stack Point
05F4~
Prog Count
05F5
CC
Figure 21
Memory
TABL
FCB
#BF
0089
BF
FCB
#86
OOBA
86
FCB
#OB
008B
DB
CF
FCB
#CF
008C
CF
Index Reg
03
Stack Point
PROG
LOA
TABL. X 0758
E6
075C
89
I
I
Prog Count
075E
CC
,I
182
---------------------------------------------------------HD6806V1
Memory
I
I
A
DB
Index Reg
PROG
lDA
TABl. X 0692
0693
02
~6
Stack Point
07
0694
~---~
7E
Prog Count
0695 ...
TABl
FCB
#BF
077E
FCB
#86
077F
FCB
#DB
0780
FCB
#CF
0781
CC
BF
86
I-__~D~B_ __t--------------~
CF
Memory
PORTB
EaU
BF
0001
A
0000
Index Reg
PROG BClR 6. PORT B
058F ' -_ _ _
1D
_ _--I
0590
Stack Point
01
Prog Count
0591
I
t@
I
I
I
I
CC
HD8806V1------------------------------------------------------
PORT C
EQU
FO
0002
Index Reg
0000
Stack Point
0574
05
Prog Count
1------1
0575
02
0576
10
0000
0594
CC
L -______________________________________
Memory
I
I
I
I
A
E5
Index Reg
PROG
TAX
E5
O~AR
Prog Count
0588
CC
184
---------------------------------------------------------HD6806V1
Table 2 Register/Memory Instructions
Addressing Modes
Function
Mnemonic
Immediate
Indexed
(No Offset)
Extended
Direct
Op
Op
Op
#
#
#
#
Code Bytes Cycles Code Bytes Cycles Code
Op
#
#
Bytes Cycles Code
Indexed
(8-Bit Offset)
Op
#
#
Bytes Cycles Code
Indexed
(16-BitOffset)
Op
#
#
Bytes Cycles Code
Bytes Cycles
LOA
A6
B6
C6
F6
E6
06
Load X from
LOX
AE
BE
CE
FE
EE
DE
Store A in Memory
STA
B7
C7
F7
E7
07
Store X in Memory
STX
BF
CF
FF
EF
OF
Add Memory to A
ADD
AB
BB
CB
FB
EB
DB
AOC
A9
B9
C9
F9
E9
09
Subtract Memory
SUB
AO
BO
CO
FO
EO
DO
sac
A2
B2
C2
F2
E2
02
6
6
Memory
AND Memory to A
AND
A4
B4
C4
F4
E4
04
OR Memory with A
ORA
AA
BA
CA
FA
EA
DA
Exclusive OR Memory
with A
EOR
AS
B8
C8
F8
E8
08
Arithmetic Compare A
with Memory
CMP
A1
B1
C1
Fl
El
01
Arithmetic C:ompare X
with Memory
CPX
A3
B3
C3
F3
E3
03
BIT
A5
B5
C5
F5
E5
05
Jump Unconditional
JMP
CC
FC
EC
DC
JSR
BC
Jump to Subroutine
BO
CD
FO
ED
DO
Implied (X)
Implied (A)
Mnemonic
Op
Code
Op
#
#
Bytes Cycles Code
Indexed
(No Offset)
Direct
Op
#
#
Bytes Cycles Code
Op
#
#
Bytes Cycles Code
Indexed
(8-Bit Offset)
Op
#
#
Bytes Cycles Code
Bytes Cycles
Increment
INC
4C
5C
3C
7C
6C
Decrement
DEC
4A
5A
3A
7A
6A
Clear
CLR
4F
5F
3F
7F
6F
Complement
COM
43
53
33
73
63
Negate
(2's Complement)
NEG
40
50
30
70
60
ROL
49
59
39
79
69
ROR
46
56
36
76
66
LSL
48
58
38
78
68
LSR
44
54
34
74
64
ASR
47
57
37
77
67
ASL
48
58
38
78
68
TST
40
50
3D
70
60
7-
185
Mnemonic
Op
Code
Bytes
Cycles
4
Branch Always
BRA
20
Branch Never
BRN
21
Branch IF Higher
BHI
22
BlS
23
BCC
24
(BHS)
24
BCS
26
(Branch IF lower)
(BlO)
26
BNE
26
4
4
Branch I F Equal
BEQ
27
BHCC
28
BHCS
29
Branch I F Plus
BPl
2A
Branch I F Minus
BMI
2B
BMC
2C
BMS
20
Bil
2E
BIH
2F
Branch to Subroutine
BSR
AD
Mnemonic
Bit Set/Clear
Op
Code
Bytes
Cycles
Op
Code
Bytes
Cycles
2-n
10
01+2-n
10
Set Bit n
10+2-n
Clear bit n
11+2-n
Mnemonic
Op
Code
Bytes
Cycles
Tiansfer A to X
TAX
97
Transfer X to A
TXA
9F
2
2
SEC
99
ClC
98
SEI
9B
CLI
9A
Software Interrupt
SWI
83
11
RTS
81
RTI
80
RSP
9C
No-Operation
NOP
90
186
-----------------------------------------------------------HD6805V1
Table 7 Instruction Set
Addressing Modes
Mnemonic
Implied
Immediate
Direct
Extended
Relative
ADC
ADD
AND
ASL
ASij
Condition Code
Indexed
Indexed Indexed
(No
(8 Bits) (16 Bits)
Offset)
x
x
x
Bit
Set/
Clear
x
x
BHCC
BHCS
BHI
BHS
BIH
x
x
BIL
x
BIT
x
x
BLS
BMC
x
x
BMI
BMS
BNE
BPL
BRA
BRN
COM
x
x
CMP
DEC
JMP
x
x
x
LOA
x
x
LOX
JSR
1\
1\
1\
1\
1\ 1\
INC
x
x
EOR
x
x
CPX
1\
1\
CLR
1\
1\
1\
1\
1\
1\
BSET
x
x
CLI
1\
BRSET
CLC
BRCLR
BSR
BLO
1\
BCS
BCLR
BEQ
BCC
Bit
Test &
Branch
-.
0
1\
1\
1\
1\
1\
1\
1\
1\
1\
1\
/\
1\
1\
1\
1\
1\
1
1\
1\
1\ 1\
/\ 1\
(to be continued)
C
1\
Carry Borrow
Test and Set if True, Cleared Otherwise
Not Affected
Z_E!ro
187
Implied
Immediate
x
x
x
x
Direct
Extended
Relative
x
x
x
x
x
x
x
x
x
x
x
Condition Code
Indexed
Indexed Indexed
(No
(8 Bits) (16 Bits)
Offset)
x
x
x
x
x
x
x
x
x
x
x
x
Bit
Setl
Clear
Bit
Test & H
Branch
x
x
\
x
x
x
x
x
x
x
x
x
x
x
x
x
1\
x
x
x
x
x
Carry/Borrow
Test and Set if True, Cleared Otherwise
Not Affected
Load CC Register From Stack
188
1\
0
1\
1\
1\
1\
1\
1\
1\
1\ 1\
1\
1\
1\
1\
1\
1\
?
?
7
1\
1\
1\
1
1\ 1\
1\ 1\
1\
1\
1\
1\ 1\
1
---------------------------------------------------------HD8806V1
Table 8
Bit Manipulation
Test &
Branch
Clear
0
0 BRSETO
Setl
Opcode Map
,X1
,XO
IMP
IMP
IMM
Rei
DIR
BSETO
BRA
NEG
RTI
A
4
X
5
BRClRO
BClRO
BRN
BRSET1
BSET1
BHI
RTS
2
3
BRClR1
BClR1
BlS
COM
SWI
BRSET2
BSET2
BCC
lSR
BRClR2
BClR2
BCS
DIR
EXT
BRSET3
BSET3
BNE
ROR
BRClR3
BClR3
BEQ
ASR
TAX
8 BRSET4
9 BRClR4
BSET4
BHCC
lSl/ASl
BClR4
BHCS
ROl
BRSET5
BSET5
BPl
DEC
B BRClR5
BClR5
BMI
C BRSET6
BSET6
BMC
INC
D BRClR6
BClR6
BMS
TST
3 l
4
5 W
lDA
STA(+1)
EOR
RSP
NOP
JMPH)
BSRI
JSR(-3)
TXA
1/
1/2
2/2
2/4
I 3/5
lDX
STX(+1)
I 3/6
2/5
189
AND
BIT
I 1/6
SBC
CPX
ADD
HIGH
0
1
SEI
ClR
I 2/7
+-
Bil
I 1/4
ADC
BIH
I 1/4
,XO
ORA
BSET7
2/6
CLI
BClR7
2/4
SEC
F BRClR7
2/7
8
9
ClC
E BRSET7
3/10
D
CMP
(NOTE)
I X2 I Xli
I
SUB
RegisterIMemory
Control
Read/ModifyJWrite
Branch
I 1/4
HD6805WO------------MCU
(Microcomputer Unit)
-PRELIMINARY -
HD6805WOP
(DP-40)
PIN ARRANGEMENT
A,
Vss
A6
RAME/RES
INT,
Vee
XTAl
EXTAl
NUM
TIMER
Co
C,
SOFTWARE FEATURES
Similar to HD6800
Byte Efficient Instruction Set
Easy to Program
True Bit Manipulation
Bit Test and Branch Instructions
Versatile Interrupt Handing
Powerful Indexed Addressing for Tables
Full Set of Conditional Branches
Memory Usable as Registers/Flags
Single Instruction Memory Examine/Change
10 Powerful Addressing Modes
All Addressing Modes Apply to ROM, RAM and I/O
Compatible with MC6805P2, HD6805S1 and HD6805V1
As
A.
A,
A~
A,
Ao
B,
B6
Bs
B.
B,
B2
B.
Bo
AVee
AVss
VRH/O s
Vee Standby
C~
C3
C.
IC/C s
DC/C 6
10 0
INT~
ANo/O,
AN, 10~
AN~/03
AN3/0.
(Top View)
190
---------------------------------------------------------HD6805WO
BLOCK DIAGRAM
TIMER
Port B
I/O Lines
TIMER-2
c:
Accumulator
A
7 Prescaler 2
Prescaler Control
8 Register 2
Timer Data
8 Register 2
CPU Control
Timer
8 Status Register 2
'0
o~
al
co~
10~
Condition Code
Register
CC
5
'
.~ ~
Index Register
oa:
Q)
a:
...
0..
CPU
Port C
I/O Lines
Stack Point
Output Compare
(OC)
8 Register
Input Capture
(IC)
8 Register
Port A
I/O Lines
Ao
AI
A2
A3
A.
As
A6
A,
SP
c:
Program Counter
"High"
4
PCH
Timer Control
8 Register 2
"Low"
';:;
u
Q)
AlU
'0
PCl
Q)
a:
c5!
()
oa:
0..
~.~
Program Counter
----...--....
~
'0
Q)
a:
1::
0
0..
Bo
BI
B2
B3
B.
B5
B6
B,
c:
Co
CI
C2
C3
C.
Cs II C)
C6 (OC)
,2
Port 0
Input Lines
.: "o~
f!os,
Do IINT 2 )
0 1 (AND)
O2 (ANd
03 (AN 2 )
D. (AN 3 )
05 (VRH)
Ia Q)
oa:
ADC Lines
, - - - - - - - - AVee
, - - - - - - AVSS
_~--~--~~----(VRH)
(ANo)
(ANI)
(AN 2 )
(AN 3 )
A/D Control
Status Register
8
AID Result
Register
8
(NOTE)
191
Item
Supply Voltage
Value
Vee
V in
-0.3 -+7.0
V
V
c
c
Operating Temperature
T oDr
-0.3 - +15.0
o -+70
Storage Temperature
Tstg
-55 - +150
(NOTE)
Unit
-0.3 - +7.0
This device has an input protection circuit for high quiescent voltage and field, however, be careful not
to impress a high input voltage than the insulation maximum value to the high input impedance circuit.
To insure normal operation, the following are recommended for Vln and V out :
Vss ~ (Vln or Vout ) ~ Vee
ELECTRICAL CHARACTERISTICS
typ
max
Unit
RES
4.0
Vee
INT
3.0
Vee
4.75
4.0
20
50
JJ.A
-1200
JJ.A
Symbol
Item
Input "High" Voltage
Test Condition
V IH
All Others
2.0
Timer Mode
2.0
Self-Check Mode
9.0
RES
-0.3
INT
-0.3
All Others
(except XTAL)
V IL
-0.3
Power Dissipation
Po
LVR
LVI
TIMER
Input Leak Current
-20
INT
IlL
V ln =O4V-V ee
XTAL(Crystal Mode)
Standby Voltage
Standby Current
-50
Vee
Vee
15.0
0.8
0.8
0.8
850
mW
JJ.A
Nonoperation Time
V SBB
4.0
5.75
Operation Time
V SB
4.75
5.75
Nonope~ation
ISBB
min
typ
max
Unit
0.4
4.0
MHz
1.0
10
4.0
JJ.s
MHz
ns
Time
VSBB=4.0V
V
mA
AC CHARACTERISTICS (Vee = 5.25V O.5V, Vss = GND, Ta = 0 -+70C, unless otherwise noted.)
Item
Symbol
Clock Frequency
Test Condition
fel
Cycle Time
tcyc
fexT
tlwL
t cvc+
250
tRwL
t cvc +
250
ns
tTWL
c+
tc"5
2 0
ns
tose
CL =22pF20%
Rs=600 max.
100
ms
tRHL
100
ms
25
30
pF
10
pF
I nput Capacitance
I
J
EXTAL
All Others
Cln
192
Rep =15.0kO1%
Vin=OV
2.7
--------------------------------------------------------HD6806VVO
PORT ELECTRICAL CHARACTERISTICS (Vee
Item
Symbol
Port A
Test Condition
min
typ
max
Unit
IOH =-10~A
3.5
1.5
2.4
IOL = 1.6 mA
0.4
= 3.2 mA
0.4
1.0
V IH
2.0
V IL
-0.3
Vee
0.8
-500
~A
V OH
Port B
IOH
= -100 ~A
2.4
IOH
= -200~A
2.4
IOH = -1 mA
Port C
IOH
Ports A and C
IOL
VOL
Port B
= -100 ~A
IOL = 10 mA
Ports A, B, C
and 0
Port A
V in = 0.8V
Vin = 2V
V in = O.4V-V ee
IlL
Ports B, C and 0
-300
-20
V
V
V
V
V
~A
20
JlA
typ
max
Unit
AVec
4.75
5.0
5.25
AV in
VRH
5.0
Reference Voltage
AVec +0.25
Reference Voltage
AVss
-0.1
7.5
pF
2.5
12.5
kfl
8
76
4
Bit
Channel
Item
Analog Power Supply
Voltage
Symbol
Test Condition
=OV,
Resolution Power
Conversion Time
at 4MHz
I nput Channels
~s
Non-Linearity Error
1/2
LSB
Offset Error
1/4
3/8
LSB
Full-scale Error
1/4
3/8
LSB
Quantum Error
1/2
LSB
Absolute Accuracy
1.0
LSB
10
100
nA
-100
-10
nA
193
Vee
Ii = 3.2 mA
40pF
(NOTE)
Ii = 1.6 mA
Test Point
Test Point
30 pF
12 k!l
2.4k!l
24 k!l
1. Load capacitance includes the floating capaci,tance of the probe and the jig etc.
2. All diodes are 1S2074(8) or equivalent.
SIGNAL DESCRIPTION
The input and output signals for the MCU shown in PIN
ARRANGEMENT are described in the following paragraphs.
Vee andVss
Vee Standby
Vee Stoodby
P",." U ..
RES
This pin allows resetting of the MCU at times other than the
automatic resetting capability already in the MCU. Refer to
RESETS for additional information.
NUM
This pin is not for user application and should be connected
to ground.
I/O Lines (Ao ~ A 7 , 8 0 ~ 8 7 , Co'" C6 )
There 23 lines are arranged as three ports (A, B and C). All
lines are programmable as I/O under software control of the
data direction registers. Refer to the section on INPUTS/
OUTPUTS for details.
Input Lines (Do '" Os)
Since the input for these 6 lines is TTL compatible, $003
address is read and they become Port D function.
194
RAME
This pin, like RES, is for the external control of standby
RAM.
After power up, RAME is set to "0" and Vee is set off.
Since RAM is disabled, the RAM contents are maintained. The
same type of function as this can be realized by software by
setting the RAM control register ($OIF) RAME (bit 6) to "0".
----------------------------------------------------------HD6805VVO
AVec
This pin is used for the power supply of the AID converter.
When high accuracy is requested, a different power source than
Vcc is impressed as
AVec =5.25 O.5V
Connect to Vee for all other cases.
ANo - AN3
000
$000
1/0 Ports
positive edge when bit 1 is "1" and for the negative edge when
bit 1 is set to "0". In this case, the DDR of port C5 is set to
"0".
Output Compare (OC)
When the output compare register ($OID) and .timer data
register 2 ($01C) contents are the same, this pin is used for data
output.
Data desired for output is specified by bit 0 of timer control
register 2 ($018). When bit 0 is "1", DC pin output is "1" and
when bit 0 is "0", DC pin output is "0". In this case, DDR of
port C6 is set to "1".
MEMORY
The MCV memory is configured as shown in Figure 3. During
the interrupt processing, the contents of the MCV registers are
pushed onto the stack in the order shown in Figure 4. Since
the stack pointer decrements during pushes, the low order byte
(PCL) of the program counter is stacked first; then the high
order three bits (PCH) are stacked. This ensures that the program counter is loaded correctly as the stack pointer increments
when it pulls data from the stack. A subroutine call will cause
only the program counter (pCH, PCL) contents to be pushed
onto the stack.
Port A
SOOO
Port B
$001
Port C
$002
Timer
$OlF
$020
031
032
RAM
196 BI
127
128
$07F
$080
Port 0
S003' ,
Port A DDR
$004'
Port BOOR
S005'
Port C ODR
S006'
$008
$007
ROM
13834 BI
$009
Miscellaneous Reg.
SooA
SooB
SOOC
SooO
SooE
SooF"
SOlO
SO 11
S012
S013
$014
SOlS
S016
S017
S018
3961
$F78
3962
SF79
S019
SOlA"
SOlB
SOlC
SOlD
SOlE"
SOlF
$020
S
S027
4081
SFFl
4082
SFF2
-----------------RAM 196 BI
Interrupt Vectors
sr
S028
S07F
WriteReg.
4095
-Read Reg
$FFF
195
HD6806VVO-------------------------------------------------------6
n-4
5
1
Condition
11 Code Register
Accumulator
n+2
n-2
Index Register
n+3
11
PCH*
PCl*
n+4
n+5
Push
* For subroutine calls, only PCH and PCl are stacked
n+1
n-3
n-1
Pull
REGISTERS
11
I
I
I
11
6 5
1010101010111
Index Register
Negative (N)
The negative bit is used to indicate that the result of the last
arithmetic, logical or data manipulation was negative (bit 7 in
a result equal to a logical one).
Program Counter
0
SP
Interrupt (I)
0
PC
Accumulator
Stack Pointer
Zero
Zero (Z)
Negative
Interrupt Mask
Half Carry
Accumulator (A)
196
TIMER 1
The MCV timer circuitry is shown in Figure 6. The 8-bit
------------------------------------------------------------HD6805VVO
timer interrupt has occurred and not disturb the counting process.
At power up or reset, the prescaler and counter are initialized
with all logical ones; the timer I interrupt request bit (bit 7) is
(Internal Clock)
4>2---1--1
Multiplexer
Timer Data Register 1 (TDR1: $008)
Time Out
Write
Read
Bit 4
0
1
k}s++sol
~
.
Clock
Inpu~
Source
P'''QI" F"quo."
Comparator
Bit 2
0
0
0
197
0
1
1
1
1
TCR1
Bit 1
0
0
1
1
0
0
1
1
Bit 0
0
1
0
1
0
1
0
1
HD6805WO--------------------------------------------------------- TIMER 2
The HD680SWO contains an on-chip programmable timer
(timer 2) which may be used to perform measurements on an
input waveform while independently generating an output
waveform. Pulse widths for both input and output signals may
vary from a few microseconds to many seconds. The timer 2
hardware consists of
~-----..... Read/Write
Reed
ICI
OCI TOI
198
--------------------------------------------------------HD6805VVO
order to gate in the external input signal to the edge detect
unit in the timer. In all cases, it is necessary to make the input
pulse width at least 2 enable cycles in order to mantain the
input capture.
With port C bit 5 confIgUred as an output and set to "I ", the external
input will still be seen by the edge detect unit.
L--_ _ _ _ _ _ _
5432
Bit4
0
0
Bit 2
0
0
0
0
1
1
1
1
PCR2
Bit 1
BitO
0
0
1
1
0
0
1
0
1
0
1
0
1
0
SELF CHECK
RESETS
INT
RES
A, 40
A. 39
7fT
As 38
A. 37
2.2}JF
5 XTAL
A3 36
A2 35
6 EXTAL
A, 34
Ao 33
+9V
TIMER
HD6805WO *
(Register option)
B7 32
7 NUM
B. 31
Vee
Bs 30
B. 29
B3 28
Co
10 C,
8 2 27
11 C 2
B, 26
12 C 3
Bo 25
Vee = Pin 3
Vss = Pin 1
Vee
RES
Pin
--------------~
Part of
HD6805WO
MCU
Internal
Reset
200
----------------------------------------------------------HD6805VVO
6 EXTAL
6 EXTAL
4 MHz c:::::J
max
HD6805WO
MCU
5 XTAL
5 XTAL
HD6805WO
MCU
22P F20%=ifi=
6 EXTAL
6 EXTAL
External
Clock
Input
5 XTAL
HD6805WO
MCU
XTAL
External Clock
CRYSTAL OPTIONS
RESISTOR OPTIONS
Figure 11
XTAL~~EXTAL
~~
I I
C,
HD6805WO
MCU
No
Connection
4
I
~
~
Vee = 5.25V
Ta = 25C
-
I\.
c:
Q>
:l
u..
~~
10
15
20
25
30
Resistance (kUl
35
~
40
'){\1
45
50
HD6805VVO-------------------------------------------------------
INTERRUPTS
Priority
Vector Address
RES
$FFE,$FFF
SWI
$FFC,$FFD
INTi
$FFA, $FFB
Timer/INT 1
$FFS, $FF9
ICI
$FFS, $FF7
OCI
OFI
S
7
$FF4, $FF5
Interrupt
$FF2, $FF3
INT.
INT2
Clear
y TIMER 1
1~1
ICI
OCI
7F~SP
O~DDR's
CLR
TNT Logic
Fetch Instruction
FF~TDR1
OO~TDR2
7F ~Prescaler 1
7F ~Prescaler 2
50~TCR1
1C~TCR2
10~PCR2
OO~TSR2
FF~OCR
OO~ICR
Load PC From
SWI: FFC, FFD
INT. : FFA, FFB
TIMER 1: FF8, FF9
INT2 : FF8, FF9
ICI: FF6, FF7
OCI: FF4, FF5
OFI: FF2, FF3
202
----------------------------------------------------------HD6805VVO
Miscellaneous Register (MR: SOOA)
As shown in Table 5, the interrupt vector address of external
interrupt vector INT 2 is the same as Timer 1 interrupt vector
address. For that reason, the control register for INT 2 is the
miscellaneous register (MR: $OOA).
Miscellaneous Register (MR: SOOA)
6
IRF
1M
VVVlZ121/1
INPUT/OUTPUT
OutPut
Data Bit
1/0 Pin
Data
Direction
Register
Bit
Output
Data Bit
Output
State
Input to
3State
Pin
MCU
203
HD6805WO--------------------------------------------------------
Ao
Port A
Port B
B,
A,
(b)
+V
+V
A
Bo
Port B
Port C
10 mA max
B,
CMOS Inverter
C3
(c)
AID
INPUT
CONVERTER
$003 Aead
Internal Bus
OIA
1-....._ _ _ _ _ Port 0
Do to 0,
AVss - - - - - - - '
ANo
AN,
AN,
Select MUX
AN.
Figllre 17 Port D
AVec 0 0 - - - - _
5V
204
--------------------------------------------------------HD6805VVO
Analog Input (AN o through AN 3)
Analog pins AN o through AN3 accept analog voltages of OV
through 5V. The resolution power is 8 bit (256 divisions) with
a conversion time of 76 #J.S at 1 MHz. Analog conversion is
selected by bits 0 through of control status register (ADCSR)
analog input. Since the CPU is unnecessary for conversion,
other user programs can be executed.
ADCSR
Bit 1
0
0
1
1
Bit 0
0
1
0
1
ANo
AN.
AN2
AN3
STANDBY RAM
The 8 bit RAMs S020 through $027 are used for standby
RAM. When used as standby RAM, Vee standby is impressed
after Vee OFF. Consequently, power supply is connected only
to standby RAM and other parts are not connected with power
supply. Accordingly, there is a small savings in power supply
but the standby RAM data is maintained.
Standby RAM control is performed by RAM control register
or RAME signal.
RAME
IIIIIII
X
Vee
RAM CTRL
~===~-5jj.L..L....L.~
7
STBY
PWR
Reg. ($01FI
/
I
RA--M-E------~\
jv------
:\""----------'f:
I
RAM
(96BI
I
Standby RAM Enable I
.1
1
1--_ _ _-t$07F
205
HD6805VVO-------------------------------------------------------
BIT MANIPULATION
The MeU has the ability to set or clear any single RAM or
input/output port (except the data direction registers) with a
single instruction (BSET and BCLR). Any bit in the page zero
read only memory can be tested by using the BRSET and
BRCLR instructions, and the program branches as a result of
its state. This capability to work with any bit in RAM, ROM or
I/O allows the user to have individual flags in RAM or to handle
single I/O bits as control lines. The example in Figure 21 shows
the usefulness of the bit manipulation and test instructions.
Assume that bit 0 of port A is connected to a zero crossing
detector circuit and that bit 1 of port A is connected to the
trigger of a TRIAC which powers the controlled hardware.
This program, which uses only seven bytes of ROM provides tum-on of the TRIAC within 14 microseconds of the zero
crossing. The timer is also incorporated to provide tum-on at
some later time which permits pulse-width modulation of the
controlled power.
SELF 1
Figure 21
Relative
Refer to Figure 27. The EA is calculated by adding the contents of the byte following the opcode to the contents of the
index register. In this mode, 511 low memory locations are
accessable. These instructions occupy two bytes.
Bit Set/Clear
The MCU has ten addressing modes available for use by the
programmer. These modes are explained and illustrated briefly
in the following paragraphs.
ADDRESSING MODES
Immediate
Extended
206
Implied
--------------------------------------------------------HD6805VVO
Memory
I
I
I
~
I
F8
Index
ea
Stack Point
A6
Prog Count
t-------I
OSCO
F8
CC
I
I
I,
lEA
Memory
I
I
I
I
I
I
I
I
I
I
CAT
FCB
32
004B
Adder
ooto
20
004B
I
I
20
Index Reg
I
I
PROG
LOA
CAT
0520
B6
052E
4B
Stack Point
I
Prog Count
052F
CC
~
I
I
I
I
I
1
207
I
I
I
HD6806VVO--------------------------------------------------------
Memory
i
i
I
8
I
PROG
LDA
CAT
06
040B
E5
64
06E5
40
Index Reg
Stack Point
FCB
~O9~
040A
CAT
0000
Prog Count
40
040C
CC
EA
04C1
Memory
i
Index Reg
Stack Point
PROG
BEQ
PROG2
04A7
27
04A8
18
0000
~
,
208
--------------------------------------------------------HD6805VVO
EA
00B8
Memory
TABL
FCC
t Lit 00B8
4C
~C
49
Index Reg
88
PROG
LOA
Stack Point
05F4~
Prog Count
05F5
CC
Figure 26
lEA
MeJory
I
TA8L
,I
I
FCB
#BF
0089
BF
FCB
# 86
008A
B6
FCB
"" DB
0088
DB
FCB
#CF
008C
CF
008C
/'
Adder
I
I
CF
Index Reg
03
Stack Point
PROG
LOA
TAB L. X 075B
E6
075C
89
075E
CC
Prog Count
Figure 27
209
HD6805WO--------------------------------------------------------
Memory
i
I
I
~
I
PROG
LOA
DB
Index Reg
02
TABLX069'~
0693
07
0694
7E
Stack Point
Prog Count
0695 ...
TABL
CC
BF
FCB
#BF
077E
FCB
#86
077F
86
FCB
#DB
0780
DB
FCB
#CF
0781
CF
Memory
PORT B
EQU
0001
BF
A
0000
Index Reg
10
0590
Stack Point
01
Prog Count
0591
,
CC
@
,,
I
210
----------------------------------------------------------HD6805VVO
PORT C
EQU
0002
FO
Index Reg
0000
Stack Point
0574
05
Prog Count
t--------4
0575
0576
0000
02
0594
I------i
10
CC
EA
Memory
i
I
I
I
A
E5
Index Reg
PROG
TAX
05BA
8
@
E5
I
I
Prog Count
05BB
CC
Figure 31
211
HD6805VYO---------------------------------------------------------
INSTRUCTION SET
The MeU has a set of 59 basic instructions. These instructions can be divided into five different types; register/memory,
read/modify/write, branch, bit manipulation and control. Each
instruction is breifly explained below. All of the instructions
within a given type are presented in individual tables.
Register/Memory Instructions
Control Instructions
The control instructions control the MeV operations during
program execution. Refer to Table 11.
Alphabetical Listing
Read/ModifylWrite Instructions
These instructions are used on any bit in the first 256 bytes
of the memory. One group either sets or clears. The other
group performs the bit test and branch operations. Refer to
Table 10.
Branch Instructions
Opcode Map
212
Addressing Modes
Function
Mnemonic
Indexed
(No Offset)
Extended
Direct
Immediate
Op
Op
Op
#
#
#
#
Code Bytes Cycles Code Bytes Cycles Code
# ' Op
#
Bytes Cycles Code
Indexed
(8-Bit Offset)
Op
#
#
Bytes Cycles Code
Indexed
06-Bit Offset)
Op
#
#
Bytes Cycles Code
Bytes Cycles
LDA
A6
B6
C6
F6
E6
D6
LDX
AE
BE
CE
FE
EE
DE
Store A in Memory
STA
B7
C7
F7
E7
D7
Store X in Memory
STX
BF
CF
FF
EF
DF
Add Memory to A
ADD
AB
BB
CB
FB
EB
DB
ADC
A9
B9
C9
F9
E9
D9
Subtract Memory
SUB
AO
BO
CO
FO
EO
DO
"""'"
SBC
A2
B2
C2
F2
E2
D2
AND Memory to A
AND
A4
B4
C4
F4
E4
D4
FA
EA
DA
(,.)
OR Memory with A
ORA
AA
BA
CA
Exclusive OR Memory
with A
EOR
A8
B8
C8
F8
E8
D8
Arithmetic Compare A
with Memory
CMP
Al
B1
C1
F1
E1
D1
Arithmetic Compare X
with Memory
CPX
A3
B3
C3
F3
E3
D3
BIT
A5
B5
C5
F5
E5
D5
Jump Unconditional
JMP
BC
CC
FC
EC
DC
Jump to Subroutine
JSR
BD
CD
FD
ED
DD
Symbols:
Op: Operation Abbreviation
# : Instruction Statement
-I..-
::J:
G)
CO
01
:eo
G)
00
oCJI
~
o
Table 8
Read/Modify/Write Instructions
Addressing Modes
Function
Implied (A)
Mnemonic
Op
Code
......
~
Op
#
#
Bytes Cycles Code
Indexed
(No Offset)
Direct
Implied (X)
Op
#
#
Bytes Cycles Code
Op
#
#
Bytes Cycles Code
Indexed
(8-Bit Offset)
Op
#
#
Bytes Cycles Code
Bytes Cycles
Increment
INC
4C
5C
3C
7C
6C
Decrement
DEC
4A
5A
3A
7A
6A
Clear
CLR
4F
5F
3F
7F
6F
Complement
COM
43
53
33
73
63
Negate
(2's Complement)
NEG
40-
50
30
70
60
ROL
49
59
39
79
69
76
66
ROR
46
56
LSL
48
58
38
78
68
LSR
44
54
34
74
64
ASR
47
57
37
77
67
ASL
48
58
38
78
68
TST
40
50
3D
70
60
-----~---.-
Symbols:
Op: Operation Abbreviation
# : Instruction Statement
36
-----------------------------------------------------------HD6806VVO
Table 9 Branch Instructions
Relative Addressing Mode
Function
Mnemonic
Op
Code
Bytes
Cycles
4
Branch Always
BRA
20
Branch Never
BRN
21
Branch IF Higher
BHI
22
BlS
23
BCC
24
(BHS)
24
BCS
25
(Branch I Flower)
(BlO)
25
BNE
26
4
4
Branch I F Equal
BEQ
27
BHCC
28
BHCS
29
Branch I F Plus
BPl
2A
Branch I F Minus
BMI
2B
BMC
2C
BMS
20
Bil
2E
BIH
2F
BSR
AO
Branch to Subroutine
Symbols; Op; Operation Abbreviation
#; Instruction Statement
Function
Bit Set/Clear
Op
Code
Bytes
Cycles
Op
Code
Bytes
Cycles
2n
10
01+2n
10
Set Bit n
10+2n
Clear bit n
11+2n
#; Instruction Statement
Table 11
Control Instructions
Implied
Function
Mnemonic
Op
Code
Bytes
Cycles
2
Transfer A to X
TAX
97
Transfer X to A
TXA
9F
SEC
99
ClC
98
SEI
9B
CLI
9A
Software Interrupt
SWI
83
11
RTS
81
RTI
80
RSP
9C
No-Operation
NOP
90
#; Instruction Statement
Mnemonic
ADC
ADD
AND
ASl
ASR
BCC
BClR
BCS
BEQ
BHCC
BHCS
BHI
BHS
BIH
Bil
BIT
BlO
BlS
BMC
BMI
BMS
BNE
BPl
BRA
BRN
BRClR
BRSET
BSET
BSR
ClC
Cli
ClR
CMP
COM
CPX
DEC
EOR
INC
JMP
JSR
lOA
lOX
Implied Immediate
x
x
x
x
x
ExDirect tended
x
x
x
x
x
Relative
x
x
Addressing Modes
Indexed Indexed Indexed
(No
(8 Bits) (16 Bits)
Offset)
x
x
x
x
x
x
x
x
x
x
x
x
Condition Code
Bit
Set/
Clear
Bit
Test &
Branch
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
C
1\
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
Carry Borrow
Test and Set if True, Cleared Otherwise
Not Affected
216
1\
1\
1\
1\
/\
1\
1\
1\
1\
1\
1\
1\
1\
1\
1\
1\
1\
1\
1\
1\
1\
1\
1\
1\
1\
1\
1\
1\
/\ /\
1\ /\
/\ /\
1\
1\
/\
1\
(to be continued)
----------------------------------------------------------HD6805VVO
Table 12
Instruction Set
Addressing Modes
Implied
Mnemonic
Immediate
Direct
Condition Code
Indexed
Indexed
(No
(8 Bits)
Offset)
Relative
Extended
LSL
LSR
NEQ
NOP
x
x
ROR
RSP
ORA
ROL
Bit
Set/
Clear
Indexed
(16 Bits)
Bit
Test &
Branch
/\ /\ /\
0 /\ /\
/\ /\ /\
/\ /\
/\ /\ /\
/\ /\ /\
RTI
RTS
/\ /\ /\
1
1
/\ /\
/\ /\
SBC
SEC
SEI
STA
x
x
STX
x
x
SUB
TAX
x
x
TST
TXA
C
/\
/\ /\ /\
1
/\ /\
x
x
SWI
Carry/Borrow
Test and Set if True, Cleared Otherwise
Not Affected
Load CC Register From Stack
Setl
Test &
Branch
Clear
0
0
Brnch
Control
Aead/Modify/Write
Ael
DIA
BASETO
BSETO
BAA
BAClAO
BClAO
BAN
BASET1
BSETl
BHI
A
4
,Xl
6
,XC
IMP
IMP
IMM
9
-
NEQ
ATI'
ATS'
I DIA
Aegister IMemory
EXT
C
l 1,x l,xo
,X2
SUB
-H IGH
CMP
SBC
BAClAl
BClAl
BlS
COM
CPx
BASET2
BSET2
BCC
lSA
AND
BAClA2
BClA2
BCS
BIT
5 W
TAX
SWI'
BASET3
BSET3
BNE
AOA
BAClA3
BClA3
BEQ
ASA
8 BASET4
9 BAClA4
BSET4
BHCC
lSL/ASl
BClA4
BHCS
AOl
LOA
STA(+ll
ClC
EOA
SEC
AOC
8
9
A
BASET5
BSET5
BPl
DEC
CLI
OAA
B BACLA5
~ClA5
BMI
SEI
ADD
C BASET6
BSET6
BMC
INC
JMP(-l)
D BAClA6
BClA6
BMS
TST
JSA(-3)
E BASET7
BSET7
Bil
LOX
F BAClA7
BClA7
BIH
ClA
TXA
1/"
1/2
212
3/10
[NOTE]
2/7
2/4
2/6
1/4
1/4
I 2/7
1/6
ASP
NOP
I
BSA'I
STX(+l)
2/4
I 3/5
I 3/6
I 2/5
217
F
I 1/4
HD6805XQ-------------MCU
(Microcomputer Unit)
-ADVANCE INFORMATION-
HD6805XOP
HARDWARE FEATURES
8-Bit Architecture
96 Bytes of RAM
Memory Mapped I/O
4096 Bytes of ROM
Internal 8-Bit Timer with 7-Bit Prescaler
Vectored Interrupts - 2 External, Timer, Soft and Serial I/O
56 I/O Lines (16 Lines LEO Compatible)
On-Chip Serial I/O (Usable as Timer)
On-Chip Clock Circuit
Self-Check Mode
Master Reset
Low Voltage Inhibit
Complete OevelopmentSystem Support by Evaluation Kit
5 Vdc Single Supply
(OP-64)
PIN ARRANGEMENT
Go (DATAo )
G, (DATA,)
G, (DATA.)
G 3 (DATA 3 )
G.(DATA.)
Gs(DATAs)
G 6 (DATA,)
G7(DATA 7 )
F, (E)
F6 (AtW)
Fs (ADR 13 )
SOFTWARE FEATURES
INT,
Similar to H06800
Byte Efficient Instruction Set
Easy to Program
True Bit Manipulation
Bit Test and Branch Instruction
Versatile I nterrupt Handing
Powerful I ndexed Addressing for Tables
Full Set of Conditional Branches
Memory Usable as Registers/Flags
Single Instruction Memory Examine/Change
10 Powerful Addressing Mode
All Addressing Modes Apply to ROM, RAM and I/O
Compatible with MC6805P2
Compatible with H06805V1, H06805U1
vee
XTAL
EXTAL
NUM
TIMEA
A,
HD6805XO
Ao
B.
B3
B2
B,
Bo
C,/Rx
C6 /Tx
CsICK 2
0,
D 6 /1NT,
Os
C.
D.
C.
O.
C2
C,
0,
0,
Co
00
(Top View)
218
F. (ADA'2)
F 3 (ADR II )
F2 (ADR,o)
F, (ADA.)
Fo (ADR.)
E, (ADR,)
47 E6 (ADR,)
Es (ADRs)
E. (ADR.)
E.(ADR.)
E2 (ADR,)
E, (ADR,)
Eo (ADRo)
------------------------------------------------------HD6805XO
BLOCK DIAGRAM
XTAL
Eo
E.
E2
Port
E,
E
Output E4
Lines Es
E6
E,
EXTAL
Timer/
Counter
TIMER
NUM
Accumulator
8
Port
E
Reg
CPU
Control
Index Register
Port
A
Reg
Data
oir
Reg
Ao
A.
A2
A, Port
A
A4 I/O
As Lines
A6
A,
Condition
Code Register CC
CPU
Stack Pointer
Fo
F.
Port F2
F,
F
Output F
4
Lines
Fs
F6
F,
Go
G.
Port G2
G G,
I/O
Lines G.
Gs
G6
G,
Port
F
Reg
Port
G
Reg
SP
Program Counter
"High"
6
PCH
ALU
Program Counter
"Low"
Data
oir
Reg
Port
8
Reg
80
8.
8 2 Port
8, 8
8. I/O
8 Lines
5
86
8,
Data
Dir
Reg
Data
Dir
Reg
Port
C
Reg
Co Port
C. C
C2 I/O
C, Lines
C.
C s (CK)
C 6 (Tx)
c, (Rx)
Serial I/O
Reg
Do
D. Port
2 Input
0, Lines
D.
05
06 (JNT 2 )
0,
219
HD6301VO, HD63A01VO,-HD63B01VO
CMOS MCU (Microcomputer Unit)
-PRELIMINARY The HD6301 VO is an 8-bit CMOS single-chip microcomputer unit, Object Code compatible with the H06801. 4kB
ROM, 128 bytes RAM, Serial Communication Interface (SCI),
parallel I/O terminals as well as three functions of timer on
chip are incorporated in the H06301VO. It is bus compatible
with HMCS6800, provided with some additional functions
such as an improved execution time of key instruction plus
several new instructions of operation to increase system
throughput. The HD6301 VO can be expanded up to 65k
words. Like the HMCS6800 family, I/O level is TTL compatible with +5.0V single power supply. By using the H~tachi's
3~m CMOS process, low power consumption is realized. And
as lower power dissipation mode, H06301 VO has Sleep Mode
and Stand-By Mode. So flexible low power consumption application is possible.
FEATURES
Object Code Upward Compatible with H06801 Family
Abundant On-Chip Functions Compatible with HD6801VO;
4kB ROM, 128 Bytes RAM,29 Parallel I/O Lines, 2 Lines of
Data Strobe, l6-bit Timer, Serial Communication Interface
Low Power Consumption Mode: Sleep Mode, Standby Mode
Minimum Instruction Cycle Time
lJ.Ls (f=lMHz), O.67J.Ls (f=1.5MHz), O.5J.Ls (f=2MHz)
BLOCK DIAGRAM
(DP-40)
PIN ARRANGEMENT
________....- vee
(Top View)
t-----PIO
......- - - P l l
TYPE OF PRODUCTS
Type No.
......- - - P , 2
t - - - - - - P I3
t - - - - _ P ..
t-----P'5
t------P,.
t------- P I7
220
Bus Timing
H06301VO
1 MHz
HD63A01VO
1.5 MHz
H063B01VO
2 MHz
-------------------------------------HD6301VO, HD63A01VO,HD63B01VO
Symbol
Value
Unit
Supply Voltage
Vee
-0.3 - +7.0
Input Voltage
Vin
-0.3 -
Operating Temperature
Topr
V
DC
Storage Temperature
T stg
(NOTE)
Vee+0.3
0- +70
DC
-55 - +150
This product has protection circuits in input terminal from high static electricity voltage and high electric field.
But be careful not to apply overvoltage more than maximum ratings to these high input impedance protection
'circuits. To assure the normal operation, we recommend V in , V out : VSS ~ (Vin or V out ) ~ Vee.
ELECTRICAL CHARACTERISTICS
Symbol
Test Condition
RES, STBY
Input "High" Voltage
EXTAL
V 1H
Other Inputs
min
typ
Vee-0.5
Vee xO .7
2.0
max
Unit
Vee
+0.3
All Inputs
V 1L
-0.3
0.8
lI in I
V in = 0.4-5.1 V
1.0
J.J,A
IITS11
V in = 0.4-5.1 V
1.0
IJ.A
All Outputs
V OH
All Outputs
VOL
IOL = 1.6mA
Vin=OV, f=l.OMHz,
D
Ta = 25 C
Sleeping (f=lMHz**)
1.0
2.0
Input Capacitance
All Inputs
Cin
Standby Current
Non Operation
lee
Cu rrent Dissipation *
lee
V RAM
IOH = -2001J. A
2.4
IOH = -lOJ.J,A
Vee- 0.7
0.55
12.5
pF
2.0
15.0
IJ.A
6.0
10.0
2.0
221
mA
V
HD6301VO, HD63A01VO,HD63B01VO------------------------------------
AC CHARACTERISTICS (Vee
Symbol
Test
Con
dition
HD6301VO
HD63A01VO
HD63B01VO
typ
typ
max min
typ
10 0.5
min
Cycle Time
tcyC
PW ASH
tASr
tASf
tAso
40
tEr
tEf
PW EH
450
max min
200
135
120
35
35
35
35
TBD
ns
10 0.666 -
35
35
PW EL
450
t ASEO
60
t A0 1
t A02
Fig. 1
tAOL
Fig. 2
Write
350
230
Read
tOSR
80
Read
tHR
Write
tHW
20
tASL
60
tAHL
20
tAH
20
tASM
Peripheral Read
Access Time
tosw
Non-Multiplexed
(tACCN)
Bus
250
!
35
35
TBD
TBD
220
TBD
TBD
0
20
TBD
200
(635)
(635)
20 TBD TBD
ns
ns
ns
35
ns
35
ns
ns
ns
TBD
TBD
ns
ns
TBD
35
35
ns
ps
TBD
10
TBD
TBD
140
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
TBD
TBD
TBD -
20
TBD
20
ms
250
250
ns
tRC
Fig_ 10
20
tpcs
Fig. 11
250
Symbol
Test
Condition
HD6301VO
HD63A01VO
min
typ
typ
TBD
250
TBD
Unit
max
ns
Fig. 3
200
Peripheral Data
Hoid Time
Port 1,2,3,4
tpDH
Fig. 3
200
tOS01
Fig. 5
tos02
Fig. 5
2* 3 4 t pwo
' ,
Fig. 4
I
I Port 3
Port 3
max min
HD63B01VO
max min
typ
max
Unit
200
200
ns
200
200
ns
300
300 -
300
ns
300
300
300
ns
300
300
300
ns
200
ns
150
ns
tPWIS
Fig. 6
200
200
tlH
Fig. 6
150
Fig. 6
150
tiS
* Except P21
222
ns
------------------------------------HD6301VO, HD63A01VO,HD63B01VO
TIMER, SCI TIMING
Item
Symbol
Test
Condition
HD63A01VO
HD6301VO
tpWT
TBD
400
TBD
/lS
0.6
0.4
--
0.6
tCYC
2.5
400
TBD
0.6
0.4
tToo
tscyC
2.0
tpWSCK
0.4
Test
Symbol Condition
min
3
150
Fig. 7
max
Unit
typ
typ
HD63B01VO
max min
min
TBD
400
tCYC
ns
MODE PROGRAMMING
Item
RES "low" Pulse Width
PW RSTL
tMPs
tHMP
Fig. 8
.
2.4V
typ
max min
2
150
O.8V
'J
2
150
- -
0 \ ;
\
~r
-- V'
-tASf
ASED
-if-
pW EL
PW EH
.....
J
-+
R/W ,As--Ar,
(SC1l (Port4)
}~2.4V
\'06V
)
)
t05W-
f.--tASM
2.4V
Address
Valid
O.6V
~l
I+tAHL
I{
}'f-2.4V
Data Valid
O.6V
r-
\.
(tACCM)
Data Valid
O.8V
223
I+-- t t-fN
.. ~
I-
-'OOR~J
}~2.0V
-,1
-tAH
.oJ
\.
Address Valid
2.4V
~rAddress I\.
Valid
O.6V
-tAOl-
-tEf
tASLI
\.
-tEr
-tAO-
MPU Read
0.-0" A.-A,
(Port 3)
max
-tASr
tASO
MPU Write
Do-D"A.-A,
(Port 3)
typ
-'k-
I-
-PWASH-
Enable
lEI
max min
tcyc
Address Strobe
(AS)
2.4 v)
typ
HD63B01VO
HD63A01VO
HD6301VO
I+-tHR
..... ~
,{
Unit
tcyC
tcyc
ns
HD6301VO, HD63A01VO,HD63B01VO-----------------------------------I,
tcyc
2.4V
-'k-
fPWEL
O.8V
PWEH
/'
Enable
(EI
1\-,
-
~f-eo
-tet
-tEr
...--tAD1-+
A.-A, (Port 41
R/W (Se2)
~
(SCt)
2.4V,"'""
-II\.
Address Valid
,'{.
O.6V'r-tosw-
MPUWrit e
2.4V J"'""
0.-0,
(Port3)
O.6V\-
Data Valid
(tACcNI
~tt-MI
~~
.:J'fi--toSR-
-.....
2.0V ~
MPU Read
0.-0,
(Port 3)
I--tAH
I--tHR
~K.
Data Valod
tAD2
O.8V'r-
i"- tAH
A.-A, (Port
1)
-'"
2.4V
'~O.6V
A,-A" (Port 4 I
Address Valid
-Jl
rMPURead
MPUWrite
O.8V\----J!
PIO -
Pl7
P 20
P"
I-tpwo
p - P"
Inputs
p,. -
All Data
Port Outputs
P)7
_ _ _ _ _ _ _..1
~:~~
Data Valid
Inputs-
r-
Address
Bus
p,. -
P"
Inputs
053-----.....;.,
224
--------------------------------------HD6301VO, HD63A01VO,HD63B01VO
RES
Timer
Counter _ _ _ _- - I ' - - - - ;_ _ _- - ' ' - -_ __
I~~~~,I~~~:: 1-------<.1
1'------""'1
P"
Output
Test Point
RL =2.2kn
14.0kn for EI
152074
or EQuiv
Internal
Address Bus _ _J'--+......~~~,~"....."'-~~"-~-"~...,..."-~~.......",."...,,-"'..,,..,.....,.....,="".-"~......,,~_-J~_,,':-:--~"-_-"....
NMI.IRQ,
Internal
DataBus _ _-"'_......n-_-"~_"-_--I'-
__-',___"-__
-J"-_-',_~,~_-''--_J~~~~~J~~~''-~~~
Internal
Read
- -_____~I
Internal
Write
\\\\\\\\\\\~~~~
J
/~
~
tPCS(
~.I
s-----Ji
O~F-.-----------~>
Vee
RES
IPCS
j \
~~~~~:~ BUS\S\\\SSS\\~
~,ernal
IRC
VCC- o.sv
tsS\\S\\\S\\S\Ssd
FFFF
FFFF New PC
\\S\\\S\\SQ
~\S\\\\\S\\\S\S\\
~,ernal ss\S\\\\~
}SSSS\SSS\\\SSS\
:$
S\S\SS\S\\\: ~\\SSS\S\ssS\\\y 1\
~~~~n:~s \S\SSSSSSs!-\ '%MSS\SS\\\Q
f
R
'~
FFFF
~
FFFF FFFF FFFF
tt=x=x=:lJt=x=x=:l-
........J1......-""""''"''""'''"'''=-''"~.-J'="....n"....,..-''(
Instruction
Figure 11
Reset Timing
225
FFFF
FFFF
FFFF
HD6301VO, HD63A01VO,HD63B01VO------------------------------------
Enable (E)
Vee, Vss
These two pins are used for power supply and GND.
Recommended power supply voltage is SV 10% (HD6301VO,
HD63AOIVO), SV S% (HD63B01VO) or 3 to 6V other than
for high speed operation (SOOkHz).
XTAL, EXTAL
These two pins are connected with parallel resonant fundamental crystal, AT cut. For instance, in order to obtain the
system clock 1MHz, a 4MHz resonant fundamental crystal is
useful because the devide by 4 circuitry is included. EXTAL
accepts an external clock input of duty SO% (1 0%) to drive,
then internal clock is a quarter the frequency of an external
clock. External driving frequency will be less than 4 times as
maximum internal clock. For external driving, no XTAL should
be connected. An example of connection circuit is shown in Fig.
12.
Co = 7 pF max
Rs = 60.n max
XTAL 1 - - -....- - - - ,
CJ
e L1
= C L2 -10-22pF 20%
(3.2-BMHz)
EXT A L 1 - - -__......,
STSY
Reset (RES)
This input is used to reset the MCU and start it from a power
off condition. RES must be held "Low'; for at least 20ms when
power is on. To reset the MCU during system operation, it must
be held "Low" at least 3 system clock cycles. From the third
cycle on, all address buses become "High" with RES at "Low"
level. Detecting "High" level, MPU does the following.
(1) I/O Port 2 bits 2,1,0 are latched into bits PC2, PC1, PCO of
program control register.
(2) The contents of the two Start Addresses, $FFFE, $FFFF
are brought to the program counter, from which program
starts (see Table 1).
(3) The interrupt mask bit is set. In order to have the MPU
recognize the maskable int~rrupts IRQI and IRQ2, clear it
beforehand.
226
lowest
Priority
Interrupt
MSB
LSB
FFFE
FFFF
1m
FFEE
FFEF
TRAP
FFFC
FFFO
NMI
FFFA
FFFB
FFFB
FFF9
FFF6
FFF7
FFF4
FFF5
FFF2
FFF3
FFFO
FFF1
C~tu'el
--------------------------------------HD6301VO, HD63A01VO,HD63B01VO
PonAddr...
I/0Pon 1
1I0Pon2
1I0Pon3
1I0Pon"
$0002
s0003
$0006
$0007
I/O Port 3
This is an 8-bit port which can be configured as I/O lines, a
data bus, or an address bus multiplexed with data bus. Its
function depends on hardware operation mode programmed by
the user using 3 bits of Port 2 during Reset. Port 3 as a data bus
is bi-directional. For an input from peripherals, regular TTL
level must be supplied, that is greater than 2.0V for a logic" 1"
and less than 0.8V for a logic "0". This TTL compatible
three-state buffer can drive one TTL load and 90pF. In the
expanded Modes, data direction register will be inhibited after
Reset and data flow will be dependent on the state of the R/W
line. Port 3 in each mode assumes the following characteristics.
Single Chip Mode" (Mode 7): Parallel Inputs/Outputs as
programmed by its corresponding Data Direction Register.
There are two control lines associated with this port in this
mode, an input strobe (IS3) and an output strobe (OS3), both
being used for handshaking. They are controlled by I/O Port 3
Control/Status Register. Additional 3 characteristics of Port 3
are summarized as follows:
(1) Port 3 input data can be latched using IS3 (SCd as a
control signal.
(2) OS3 can be generated by MPU read or write to Port 3's
data register.
(3) IRQI interrupt can be generated by an IS3 negative
edge.
Port 3 strobe and latch timing is shown in Figs. 5 and 6,
respectively.
Oat. Direction
Register Add ....
SOOOO
$0001
$0004
$0005
1/0 Port 1
This is an 8-bit port, each bit being defined individually as
input or outputs by associated Data Direction Register. The
8-bit output buffers have three-state capability, maintaining in
high impedance state when they are used for input. In order to
227
$00031 PC21
0 )
In the Single Chip Mode, all ports will become I/O. This is
shown in figure 15. In this mode, SCI, SC2 pins are configured
for control lines of Port 3 and can be used as input strobe (IS3)
and output strobe (OS3) for handshaking data .
MODE SELECTION
PC1
1/0 Port 4
228
-------------------------------------HD6301VO, HD63A01VO,HD63B01VO
Vee
~
>
~ > ~
R, R, R,
I I I
A B
RES
HD6301VO
X.
f--.-
Y.
z.
P,.
x,
P"
Y,
P"
Z,
???
~
Mode
Control
Sw'tch
8
9
10
Inh
P,. (PCO)
P" (PC,).
P" (PC2)
HD14053B
Note
1) Figure of Mode 7
2) RC""Reset Constant
J;
3) RI =10kn
Truth Table
Control Input
Inh
Inhibit
A
B
C
Xo
XI
Yo
Yla
Zo
ZI
X
Y
1 0
1 0
0
0
C B A HD14053B
On Switch
Select
,,
, ,
,,
,,
Zo Yo X.
Z. Yo X,
Zo Y, Xo
Z. Y, X,
Z, Yo X.
Z, Y, X.
Z, Yo X,
Z, Y, X,
X X X
Vee
Enable
Port'
81/0 lines
Port 3
81/0 Lines
Port 4
8110 Lines
Port 2
5110 Lines
8 Lines
Multiplexed
Data/Address
Port 1
81/0 Lines
Port 2
51/0 Lines
SCI
Timer
SCI
Timer
Vss
Port 4
To 8 Address
Lines or TO
7 I/O Lines
(Inputs Onlv)
229
HD6301VO. HD63A01VO.HD63B01VO------------------------------------Vee
Vee
Port 1
8 Parailel 1/0
Port 2
5 Parallel 1/0
SCI
Timer
Port 3
8 Data Lines
Port 1
To 8 Address Lines
Port 3
8 Data Lines
Port 4
To 8 Address
Lines or To
7110 Lines
(Inputs Onlyl
Port 2
5 Parailel I/O
SCI
Timer
Port 4
To 8 Addresl
Lines
Vss
(a) Mode 5
(b) Mode 1
Figure 17
GND
AS
G OC
0,
Port 3
Address/Data
0,
0,
Function Table
) A"'~A,-A,
74LS373
Output
Control
L
L
H
H
H
L
L
H
L
X
X
X
0,
Enable
Output
0
H
L
O.
Z
0 ... 0,-0,
PORT 2
Five Lines
PORT
3
Eight lines
PORT 4
Eight lines
SCI
SC2
SINGLE CHIP
I/O
I/O
I/O
I/O
IS3 (I)
OS3(0)
EXPANDED MUX
I/O
I/O
ADDRESS BUS
(Ao-A7)
DATA BUS
(Do-D7)
ADDRESS BUS
(A8-AIs)
AS(O)
R/W(O)
MODE
EXPANDED
Mode 5
I/O
I/O
DATA BUS
(Do-D7)
ADDRESS BUS
(Ao-A7)
10S(0)
R/W(O)
NON-MUX
Mode 1
ADDRESS BUS
(Ao-A7)
I/O
DATA BUS
(Do-D7)
ADDRESS BUS
(A8-AIs)
Not Used
R/WiO)
*These lines can be substituted for 1/0 (Input Only) starting with the MSB (except Mode 0, 4l.
I
o
R/Vii
Input
Output
ReadlWrite
IS3
OS3
lOS
Input Strobe
Output Strobe
1/0 Select
SC
AS
230
= Strobe Control
= Address Strobe
--------------------------------------HD6301VO, HD63A01VO,HD63B01VO
Table 4 Mode Selection Summary
Mode
7
6
5
4
3
2
1
0
Pu
(PC2)
P 21
(PClI
P 20
(PCO)
ROM
RAM
H
H
H
H
H
I
I
I
MUX(4)
NMUX(4)
E(2)
MUX
L
L
L
H
L
L
E(2)
I
Interrupt
Vectors
I
1(1)
1(3)
Bus
Mode
NMUX
MUX
(NOTES)
1) Internal RAM is addressed at $0080.
2) Internal ROM is disabled.
3) Reset vector is external for 3 or 4 cycles after
RES goes "high".
4) Idle lines of Port 4 address outputs can
be assigned to I nput Port.
LEGEND:
I - Internal
E - External
MUX
- Multiplexed
NMUX
- Non-Multiplexed
L - Logic "0"
H - Logic "1"
MemoryMap
Table 5
Port
Port
Port
Port
Register
1 Data Direction Register
2 Data Direction Register
1 Data Register
2 Data Register
Port 3
Port 4
Port 3
Port 4
Data
Data
Data
Data
Direction Register
Direction Register
Register
Register
Address
00'
01
02'
03
04"
05'"
06"
07'"
08
09
OA
OB
00
OE
OF"
10
11
12
13
oc
14
1S-1F
231
Operating
Mode
Single Chip
Multiplexed/Partial Decode
Non-Multiplexed/Partial Decode
Multiplexed/RAM
Not Used
Not Used
Non-Multiplexed
Multiplexed Test
HD6301VO, HD63A01VO,HD63B01VO-------------------------------------
HD6301VOO
Mode
HD6301VO
Mode
Non-Multiplexed/Partial Decode
$0000
Internal Registers
Internal Registers
$001F
$001F
$0080
Internal RAM
Internal RAM
$OOFF
$OOFF
$FOOO
Internal ROM
$FFFF(2)
[NOTES)
1) Excludes the following addresses which may be
used externally: $04, $05, $06, $07 and $OF.
2) Addresses $FFFE and $FFFF are considered
external if accessed within 3 or 4 cycles after a
positive edge of RES and internal at all other times.
3) After 3 or 4 MPU cycles, there must be no overlapping
of internal and external memory spaces to avoid
driving the data bus with more than one device.
4) This mode is the only mode which is used for
testing.
$FFFF ....._ _ _ _ J
[NOTE)
Excludes the following addresses which may be
used externally; $00, $02, $04, $05, $06, $07
and $OF.
(to be continued)
232
-------------------------------------HD6301VO, HD63A01VO,HD63B01VO
HD6301V04
Mode
Multiplexed/RAM
NonMultiplexed/Partial Decode
$0000
$OOlF
$0080
HD6301V5
Mode
Internal Registers
Internal RAM
$0000
}
_ _ Internal Registers
$OOlF ""~~"'+"~~
Unusable
$0080
} Internal RAM
$OOFF
$0100
Internal ROM
$FFFF _ _ _ _ _ ,
$FFFF
[NOTE)
[NOTE)
(to be continued)
HD6301VO, HD63A01VO,HD63B01VO--------------------------------------
HD6301V06
Mode
HD6301V07
Mode
Single Chip
Multiplexed/Partial Decode
$0000
Internal Registers
$OOOO~}
$001F '""~'f""~'"
Unusable
$0080
$001F
$0080
Internal RAM
Internal Registers
} Internal RAM
$OOFF
$OOFF
$FOOO
$FFFF
$FOOO
Internal ROM
Internal ROM
Int~rnal
$FFFF
[NOTE]
Excludes the following address which may be
used externally: $04, $06, $OF.
234
Interrupt Vectors
-------------------------------------HD6301VO, HD63A01VO,HD63B01VO
PROGRAMMABLE TIMER
The HD6301 VO contains 16-bit programmable timer and used
to make measurement of input waveform. In addition independently it can generate an output waveform by itself. For both
input and output waveform, the pulse width may vary from a
few microseconds to many seconds.
The timer hardware consists of
an 8-bit control and status register
a 16-bit free running counter
a 16-bit output compare register, and
a 16-bit input capture register
A block diagram of the timr is shown in Figure 20.
HD6301 VO Internal Bus
Bit 1
Port 2
DOR
I
_____ :
For the data writing on Compare Register, 2-byte transfer instruction such as STX is available.
Output Input
Ltel
EdtII
B~ 1
B., 0
"",2 ...... 2
Figure 21
235
OLVLI
sooos
HD6301VO, HD63A01VO,HD63B01VO------------------------------------Bit 1 IEDG (Input Edge); This bit control which transition
of an input of Port 2 bit 0 will trigger the data
transfer from the counter to the input capture
register. The DDR corresponding to Port 2 bit 0
must be clear in advance of using this function.
When IEDG = 0, trigger takes place on a negative
edge ("High" -to-"Low" transition). When IEDG =
1, trigger takes place on a leading edge ("Low" -to"High" transition).
Bit 2 ETOI (Enable Timer Overflow Interrupt); When set,
this bit enables TOF interrupt to generate the
interrupt request (lRQ2) but when clear, the
interrupt is inhibited.
Bit 3 EOCI (Enable Output Compare Interrupt); When set,
this bit enables OCF interrupt to generate the
interrupt request (IRQ2), when clear, the interrupt
is inhibited.
Bit 4 EICI (Enable Input Capture Interrupt); When set, this
bit enables ICF interrupt to generate the interrupt
request (IRQ2) but when clear, the interrupt is
inhibited.
Bit 5 TOF (Timer Over Flow Flag); This read-only bit is set
when the counter value is $0000. It is cleared by
MPU read of TCSR (with TOF set) following an
MPU read of the counter ($0009).
Bit 6 OCF (Output Compare Flag); This read-only bit is set
when a match is found in the value between the
output compare register and the counter. It is
cleared by a read of TCSR (with OCF set)
following an MCU write to the output compare
register ($OOOB or $OOOC).
Bit 7 ICF (Input Capture Flag); The read-only bit is set by
a proper transition on the input, and is cleared by
a read of TCSR (with ICF set) followed by an
MPU read of Input Capture Register ($OOOD).
Reset will clear each bit of Timer Control and Status
Register.
SERIAL COMMUNICATION INTERFACE
The HD6301 VO contains a full-duplex asynchronous Serial
Communication Interface (SCI). SCI may select the several
kinds of the data rate and comprises a transmitter and a receiver
which operate independently on each other but with the same
data format at the same data rate. Both of transmitter and
receiver communicate with the MPU via the data bus and with
the outside world, through Port 2 bit 2, 3 and 4. Description of
hardware, software, register is as follows.
Wake-Up Feature
In typical multiprocessor applications the software protocol
will usually have the designated address at the initial byte of the
message. The purpose of Wake-Up feature is to have the
non-selected MPU neglect the remainder of the message. Thus
the non-selected MPU can inhibit the all further interrupt
process until the next message begins.
Wake-Up feature is triggered by a ten consecutive "I "s which
indicates an idle transmit line. Therefore software protocol
needs an idle period between the messages.
With this hardware feature, the non-selected MPU be
re-enabled (or "wakes-up") for the appearing next message.
Programmable Option
The HD6301 VO has the following optional features provided
for its Serial I{O. They are all programmable.
236
210
-------------------------------------HD6301VO, HD63A01VO,HD63B01VO
framing error occurs (receive only), it is set by
hardware. Over Run Error occurs if the attempt is
made to transfer the new byte to the receive data
register with the RDRF set. Framing Error occurs
when the bit counters are not synchronized with
the boundary of the byte in the bit stream. The bit
is cleared by reading the status register and
B.t 7
RES.
Bit 7 RDRF (Receive Data Register Full); It is set by hardware
B.t 0
CCllccoISS1ISS0\510
I TIE
RE
I TE I
wu 1511
512
POrt
(Not
Addressable)
Clock
B.t
2
10
12
513
CC1
cco
sso
SS1
ADDR : $0010
SSl
SSO
XTAl
2.4576 MHz
4.0 MHz
614.4 kHz
1.0 MHz
4.9152MHz
1.2288MHz
13
.u s/16.800Baud
E+ 16
26 115/38,400 Baud
16
E+ 128
2081ls/4,800 Baud
E + 1024
1.67ms/600 Baud
1.024ms/976.6 Baud
833.3.u 51 1.200B8ud
E+4096
6.67ms/150 Baud
4.096ms/244.1 Baud
3.333ms/
115/62,500 Baud
104.2.us/ 9.600Baud
300Baud
Format
Clock Source
Port 2 Bit 2
Port 2 Bit 3
Port 2Bit 4
......
......
00
01
NRZ
Internal
Not Used
10
NRZ
Internal
Output
11
NRZ
External
Input
237
They control the data format and the clock select logic.
Table 7 defines the bit field.
238
Receive Operation
The receive operation is enabled by the RE bit, gating the
serial input through Port 2 bit 3. The receive section operation
is conditioned by the contents of the TRCS and RMC register.
In the normal non-biphase mode, the received bit stream is
synchronized by the first "0" (space). During 10-bit time, the
approximate center is strobed. If the tenth bit is not "1" (stop
bit), the system assumes a framing error and the ORFE is set.
If the tenth bit is "1", the data is transferred to the. receive
data register, with the interrupt flag set. If the tenth bit of the
next data is received, however, still RDRF is preserved set, then
ORFE is set indicating that an overrun error has occurred.
After the MCU read of the status register as a response to
RDRF flag or ORFE flag, following the MCU read of the receive
data register, RDRF or ORFE will be cleared.
RAM CONTROL REGISTER
The register assigned to the address $0014 gives a status
information about standby RAM.
RAM Control Register
-------------------------------------HD6301VO, HD63A01VO,HD63B01VO
MCV programming model (See Fig. 23)
Addressing modes
Accumulator and memory manipulation instructions (See
Table 8)
New instructions
Index register and stack manipulation instructions (See
Table 9)
Jump and branch instructions (See Table 10)
Condition code register manipulation instructions (See
Table 11)
Op-code map (See Table 12)
The programming model for the HD630 1VO is shown in Figure 23. The double accumulator is physically the same as the
accumulator A concatenated with the accumulator B, so that
the contents of A and B is changed with executing operation of
an accumulator D.
t.
,; -
A
-
7
-
8
-
Indl'JtRegistt'f IX)
1,5
1,5
SP
1'5
PC
~
H
N Z
V C
Overflow
Zero
Ne9f tlYe
Interrupt
H.lf <Any (From alt 31
239
Mnemonic
IMMED
OP -
DIRECT
#
OP
OP -
Register
EXTEND
INDEX
#
OP
Boolean/
Arithmetic Operation
IMPLIED
OP
BB
9B
AB 4
2 BB
A + M-+ A
ADDB
CB
DB 3
EB
FB
B+M-+B
Add Doable
ADDD
C3
3 3 03 4
E3
F3
Add Accumulators
ABA
AOCA
B9
2 99
A9
B9
4 3
A+M+C-+A
AOCB
C9
09
E9
F9
B+M+C-+B
AND
ANOA
B4
2 94
A4
84
A'M-+A
ANDB
C4
04
E4
F4
8M -+ B
Bit Test
BITA
85
2 95
A5
B5
AM
BIT B
C5
05
E5
F5
4 3
6F
7F
5 3
Clear
Compare
A:B+M:M+l-+A:B
lB
CLR
B'M
00-+ M
CLRA
4F
1 00 -+ A
CLRB
5F
1 00 -+ B
CMPA
81
91
Al
2 Bl
A-M
CMPB
Cl
01
3 ,2
El
2 Fl
B-M
63
73
Compere
Accumulators
CeA
Complement, l's
COM
11
43
COMB
53
70
1 A-B
M-+M
COMA
60
1
1
1 A -+A
1 B -+ B
OO-M-+M
Complement,2's
NEG
(Negate)
NEGA
NEGB
40
1 OO-A-+A
50
1 OO-B-+B
Decimal Adjust, A
DAA
19
1 1
Decrement
DEC
Exclusive OR
Increment
Load
Accumulator
A-l-+A
OECA
4A
OECB
5A
1 B-l-+B
EORA
88
2 98
AS 4 2 B8 4 3
A@M-+A
EORB
C8
E8
F8
B @ M-+ B
6C
7C
INC
M+l-+M
A+l-+A
INCA
4C
INCB
5C
1 1 B + 1- B
LOAA
86
96
A6
2 B6
M-+A
LOAB
C6
06 3
E6
F6
M-+B
Load Double
Accumulator
LOO
CC
DC 4
EC 5
FC
M + 1 -+ B, M -+ A
Multiply Unsigned
MUL
OR, Inclusive
ORAA
8A
ORAB
CA 2
3D
2
AA 4
BA 4
OA 3
EA 4
FA 4
2 9A
2
AKB-+A:B
A+M-+A
B + M-+ B
PSHA
36
1 A -+ MsP, SP - 1 -+ SP
PSHB
37
1 B -+ MsP, SP - 1 -+ SP
Pull Data
PULA
32
33
49
PULB
Rotate Left
ROL
69
79
ROLB
Rotat. Right
ROR
59
66
76
AOlA
1 1
RORA
46
1 1
RORB
56
240
:} C9=1! ! ! ! ! !
B
b7
:}~)
I
I
I
I
I
I
I
I
I
1 0
I
I
I
I
I
I
I
I
:
:
I
I
I
I
I
I
I
I
t t
t
R
R
R
R
R S R R
R S R R
R S R R
I
I
I
I
I
I
I
I
I
I
R S
R S
I
t
I
I
I
I
t @
R S
<D~
(j) (V
CD
: @
t t
I
I
I
t R
t @
@.
: :
:
: :
:
:
Push Olta
,
,
,
,
ItJ
,,
, ,,
6A 6 2 7A 6 3
08
A+B-+A
I N Z V C
I
I
ADDA
Add
iiO
I I I II !~
bO
I
I
I
@ I
<I> I
<1>,'
<I> ,
@ ,
(to be continued)
Addressing Modes
Operations
Mnemonic
IMMED
OP
Shift Left
Arithmetic
Double Shift
Left, Arithmetic
Shift Right
Arithmetic
DIRECT
#
OP
INDEX
ASL
EXTEND
#
op
IMPLIED
OP -
OP
68
7B
Double Shift
Right Logical
M}
__
9"111111111-0
48
58
ASLB
ASLD
05
1 1 ~
47
57
1 1
1 1
44
1 1
AS LA
67
ASR
77
64
LSR
74
A
8
b7
A7
A~e!l. ~ee I
---
AO 87
AO-olIIIIIIII"'"9
8
b7
bO
LSRB
54
LSRD
04
1 o-oj
A7
--
ACCAOAJ 8~CC 8
STAA
97
A7
B7
4 3
A .... M
STAB
07
E7
F7
B .... M
Store Double
Accumulator
STD
DO 4
FO 5
A .... M
B .... M+ 1
Subtract
SUBA
80
SUBB
CO
83
2 2
3 3
Double Subtract
SUBO
Subtract
Accumulators
SBA
Subtract
With Carry
ED 5
AO 4
BO
A-M .... A
DO
EO
FO
4 3
B -M .... B
93
4 2 A3 5 2 B3
5 3
2 90
1 1
A - B .... A
82
92
A2
B2
A-M-C .... A
SBCB
C2
2 2
02
E2
F2
B-M-C .... B
TAB
TBA
Test Zero or
Minus
TST
16
17
60
1 1
1 1
A .... B
B .... A
M -00
4 2 70 4 3
TSTA
40
TSTB
50
1 B - 00
And Immediate
AIM
OR Immediate
DIM
EDR Immediate
ElM
Test Immediate
TIM
61 7 3
3 62 7 3
75 6 3 65 7 3
7B 4 3 68 5 3
71
72
A -00
MIMM-M
80~
SBCA
Transfer
Accumul;ltors
1-0
80
111111J.g
M)
LSRA
=J
C?Ib7
8
Store
Accumulator
bO
ASRA
ASRB
Shift Right
Logical -
Booleanl
Arithmetic Operation
M+IMM-M
MIMM-M
MIMM
I N Z V
1 0
C
t t @t
t t @H
t t KIDt
t t ~t
t t & t
t t 6 t
t t 6 t
R t 6 t
R t @t
R t @t
R
t @t
t t
t t
t t
t t t t
t t t t
t t t t
t t t t
t
t
t
t
t
t
t
t
t t t
t t t
t R
t R
t R R
t R R
t R R
t
t
t t
t t
R
R
New Instructions
In addition to the HD680l Instruction Set, the HD630l VO
has the following new instructions:
AIM----(M) (IMM) -+ (M)
Evaluates the AND of the immediate data and the
memory, places the result in the memory.
OIM---- (M) + (IMM) -+ (M)
Evaluates the OR of the immediate data and the
memory, places the result in the memory.
EIM- - - -(M) () (IMM) -+ (M)
Evaluates the EOR of the immediate data and the
contents of memory, places the result in memory.
TIM----(M) (IMM)
Evaluates the AND of the immediate data and the
memory, changes the flag of associated condition code
register
Each instruction has three bytes; the fIrst is op-code, the
second is immediate data, the third is address modifier.
XGDX--(ACCD) # (IX)
Exchanges the contents of accumulator and the index
register.
SLP- - - -The MPU is brought to the sleep mode. For sleep
mode, see the "sleep mode" section.
241
Addressing Modes
Pointer Operations
Mnemonic
CPX
DEX
1---.
IMMED
DIRECT
OP
OP
8C
3 3
9C
INOEX
EXTEND
IMPLIED
OP
OP
OP
AC
5 2 BC 5 3
1----
DES
Decrement Stack Pntr
- - - - - - - - - - _.. _--_ .. _---INX
Increment Index Reg
- - - - - - - - - t---..
Increment Stack Pntr
INS
lOX
--
CE
--t8E
-.
-Load
- -Stack
- -Pntr
- - - - t -LOS
~-
f--- r-
1 1
34
1 1 SP - 1 - SP
X-I-X
31
1 sP + 1 - SP
EE
FE
M-XH,(M+ll-XL
AE
BE
M- SP H , (M+lI-SP L
3
1
X H - M, XL - (M + 11
SPH - M, SP L - (M+ 1)
X-l-SP
OF
EF
FF
STS
9F
AF
BF
5 3
TXS
~X
- - - - - - - - - - - - ' - f---
ABX
Add
----- .
------------
35
30
SP+l-X
3A
XL - Mop, SP - 1 - SP
XH- M IP , SP -1- SP
SP + 1 - SP, MIP ... X H
Push Data
PSHX
3C
Pull Data
PUlX
38
Exchange
XGDX
18
+X~
t l
X+l-X
08
OE
STX
I N Z
09
9E
"X-M:M+l
3 3
3
5 4 3 2 1 0
H
--------.-
Boolean/
Arithmetic Operation
CZ) l
l
l
(j)
l
(j)
(j)
R
R
ACCD-IX
Addressing Modes
Operations
Mnemonic
RELATIVE
OP
Branch Alwavs
BRA
20
DIRECT
OP
INDEX
OP
EXTEND
IMPLIED
OP
OP
Branch Test
None
None
Branch Never
BRN
21
Bee
24
C=O
BCS
25
Branch If = Zero
BEQ
27
C- 1
Z -I
Branch If .. Zero
BGE
2e
N0
> Zero
BGT
2E
Z + (N 0 VI - 0
Branch If
v-o
Branch If Higher
BHI
22
C+Z=O
Branch If .. Zero
BlE
2F
Z+ (N 0
Branch If lower Or
Same
BlS
23
C+Z-l
Branch If
< Zero
VI - 1
BlT
20
N0 V-I
Branch If Minus
BMI
2B
N -I
BNE
26
Z-O
Branch If Overflow
Clear
BVe
28
v-o
BVS
29
V-I
Branch If Plus
BPl
2A
3 2
N-O
80
5 2
Branch To Subroutine
BSR
Jump
JMP
Jump To Subroutine
JSR
No Operation
NaP
01
RTI
3B 10 1
Return From
Subroutine
RTS
39
5 1
Software Interrupt
SWI
3F
12 1
WAI
3E
SLP
lA
6E
90
AD 5
7E
2 BO 6 3
1
3 2
N Z
--
ev
--@
Note) *WAI puts R/W high; Address Bus goes to FFFF; Data Bus goes to the three state level.
Condition Register will be explained in Note of Table 11.
242
5
H
Operltions
Mnemonic
Clear Carry
Cleer Interrupt Misk
Cleer Overflow
Set Carry
Set Interrupt Milk
SetO\lllrflow
Accumulltor A - CCR
CCR - Accumulltor A
[NOTE]
IMPLIED
#
OP
1
1
OC
OE
1
1
1
OA
1
1
00
1
1
OF
1
1
OB
1
1
06
1
1
1
07
ClC
Cli
ClV
SEC
SEI
SEV
TAP
TPA
1
V
0
C
R
O-C
0-1
o-v
1- C
1-1
1-V
A- CCR
CCR-A
---
---
Condition Code
CD (Bit V)
@
(Bit C)
@
(Bit C)
@
(Bit V)
@
(Bit V)
@
(Bit N)
CD (Bit N)
@
(All)
(Bit I)
~
lO
0000
0
1000
0001
o~
1 NOP
0010
0011
0100
2
4
0101
0110
0111
1000
1001
1010
lOll
0001
I
SBA
CBA
./ ~
,,/' ~
lSRD
ASlD
0010
2
BRA
BRN
BHI
BlS
BCC
~ BCS
0011
3
TSX
INS
DES
TXS
TAB
TBA
BNE
BEQ
9
A
INX
DEX
ClV
BVC
BVS
BPL
SEV
XGDX
DAA
SlP
ABA
PSHB
PUlX
RTS
ABX
BMI
RTI
1100 C
1101 0
ClC
BGE
PSHX
1110 E
1111 F
SEC
Cli
SEI
0
~ BLT
~ BGT
~ BlE
I
0100
4
0101
0110
IND
------
PSHA
MUl
WAI
ACC
-------
PULA
PUlB
TAP
TPA
ACC
A
---
DIR
0111
7
ACCA or SP
ACCB or X
IMM
8
IMM
1100
J
J
SUB
NEG
AIM
DIR liND
1101
0
-Tex:r-
I 1110 I
1E I
1111
F
CMP
OIM
SUBD
--
ADDD
AND
BIT
ElM
ROR
ASR
4
6
~I
STA
STA
EOR
ASL
ROl
DEC
9
A
QRA
ADD
TIM
CPX
BSR
~i
ClR
LDD
~I
JSR
LOS
JMP
6
- - - c--
8
- - I--
ADC
INC
TST
STS
9
3
5
LOA
~l
0
I
2
,-'---
SBC
COM
lSR
~~
SWI
STD
0
E
LOX
STX
I o I
UNDEFINED OP CODE ~
Only each instructions of AIM, OIM, ElM, TIM
SleepMode
243
HD8301VO, HD83A01VO, HD83B01VO-----------------------------------sleep ~tarts to execute. However, in such a case that the timer
interrupt is inhibited on the timer side, the sleep mode cannot
be released due to the absence of the interrupt request to the
MPU.
This sleep mode is available to reduce an average power
consumption in the applications of the H06301 VO which may
not always drive.
Standby Mode
Vee
il NMl1
I
I
NMI
<D
I
HD6301VO
STBY
RES
I
I
I
I
LI_ _ _ _ _ _
r:-
I
~,~
~
Oscil.lator I
starting
time
~
restart
o Stack
o RAM control
register set
ERROR PROCESSING
Op-Code Error
$0000
$0000
$0000
$0000
$ocioo
$0000
$0100
$EFFF
$EFFF
Address Error
244
-------------------------------------HD6301VO, HD63A01VO,HD63B01VO
Vee
Vee
Enable
Enable
IRQ,
iRQ,
Port 3
8 Transfer
Lines
Port 1
Port 1
81/0
81/0 Lines
Lines
Port 2
5110 Lines
Port 4
8110 Lines
SCI
16 Bit Timer
Vss
Port 4
81/0 Lines
Port 2
5110 Lines
SCI
Vss
245
HD6301VO
MCU
Address
Bus
Data
Bus
Address Bus
Data Bus
HD6301VO MCU
16
Address Bus
Figure 29
Data Bus
246
HD6303P
HD63A03P
HD63B03P
FEATURES
Object Code Upward Compatible with the HD6800, HD6802,
HD6801
Multiplexed Bus (Do-D,/Ao-A,)
Abundant On-Chip Functions Compatible with the
HD6301 VO; 128 Bytes RAM, 13 Parallel 1/0 Lines (includ-
ing Timer, SCI I/O Terminals), 16-bit Timer, Serial Communication I nterface (SCI)
Low Power Consumption Mode; Sleep Mode, Stand-By Mode
Minimum Instruction Cycle Time
11lS (f=1MHzl. O.671lS (f=1.5MHz), O.5J.Ls (f=2.0MHz)
Bit Manipulation, Bit Test Instruction
Error Detecting Function; Address Trap, Op Code Trap
BLOCK DIAGRAM
(DP-40)
PIN ARRANGEMENT
AS
R/Vii
D,/A,
D,/A,
D,/A,
D,/A,
m
xx
~~
n",
~~
D,/A,
HD6303
nV'l rrm
D,/A,
A.
i-r--P'o
t4-r---P2I
A"
t4-~-P22
t4-!--+-'''---P23
p"
All
(Top View)
As
A.
~:~
~:~
Au --
A,s.
-P,o
I---~P,'
Address
Buffers
r=====:~:~
1------- PI'
1------- P, ~
1 - - -____
1------- P"
P,.
247
TYPE OF PRODUCTS
Type No.
Bus Timing
HD6303
1.0 MHz
HD63A03
1.5 MHz
HD63B03
2.0 MHz
HD6303, HD63A03,
HD63B03----------------------------------------~
MEMORY MAP
Internal RAM
~~~~~~~~~~~LL~~~
~~~~~~~~~~~~~~~
~~~~LL~~~~~~~~~~
$FFFF~
________________________
248
HD63L05--------------CMOS MCU
(Microcomputer Unit)
- PRELIMINARY-
The HD63LOS is a CMOS single-chip microcomputer suitable for low-voltage and low-current operation. Having CPU
functions similar to those of the HMCS6800 family, the
HD63LOS is equipped with a 4k bytes ROM, 96 bytes RAM,
I/O, timer, 8 bits A/D, and LCD (6 x 7 segments) drivers, all
on one chip.
HARDWARE FEATURES
3V Power Supply
8-Bit Architecture
Built-in 4k Bytes ROM (Mask ROM)
Built-in 96 Bytes RAM
20 Parallel I/O Ports
Built-in 6 x 7 Segments LCD Driver Capability
Built-in 8-Bit Timer
Built-in 8-Bit A/D Converter
Program Halt Function for Low Power Dissipation
Stand-by Input Terminal for Data Holding
SOFTWARE FEATURES
An Instruction Set Similar to That of The HMCS6800
Family (Compatible with The HD6805S)
HMCS6800 Family Software Development System Is Applicable
HD63L05
(FP-60A)
PIN ARRANGEMENT
~i~t5tE<E
~
...... - oOOOwww
muuuuuuu",,,,,,,
SEG.
SEG IO
SEG II
SEG"
SEG"/CH.
SEG,,/CH,
SEG,,/CH.
HD63L05
VCM
i rJ. r3 IS
> > u u
(Top View)
249
Common
Driver
Output
COMI
COM 2
COM 3
Data
Latch
LCD1
SEG I
SEG2
LCD2
SEG 3
SEG4
8
8
....::::J
S::::J
LCD3
7
XIN
XOUT
'':
LCD4
SEG s
SEG 6
SEG,
SEG s
SEG,
SEGlo
II)
CI
LCD5
II)
(/)
7
LCD6
SEG 13
SEG I4
SEG 15
7 LCD7
7 LCD8
SEG I6
SEG 17
RES
NUM
TIMER
7
Prescaler
SEG II '
SEG I2
c:
.....
';; co
GIl\!
~c
Accumulator
()
II)
t:
~
c:
0
()
Index
Register
Ao
AI
A2
A3
A4
As
A6
A,
c:
System
Cont. Reg.
~'i
Q.([
.~!
o'~
!!!([
ce
:;(g
Condition
Code Reg.
5
I\!
:;(
()
CCR
CPU
--CHI
CH2
CH3
CH4
CHs
CH6
(CH,)
(CH s )
Stack
Pointer
SP
Program
Counter
"High" PCH
Program
Counter
"Low" PCL
c:
';::; ....
UGI
ALU
!1;;
o'~
!!!([
10$
t: .!!!
J'.I
I\!
Bo
BI
B2
B3
B4
Bs
B6
B,
c:
.g . .
~!
()$
!!!([
Q.~
0'61
GI
I\!
250
~ 's,
Co
CI
C2
C3
----------------------------------------------------------HD63L05
Symbol
Supply Voltage
Input Voltage
Output Voltage
Operating Temperature
V out
Topr
Storage Temperature
Tstg
(NOTE)
Value
Vee
Vin
Unit
-0.3 - +5.5
V
c
-55-+125
If LSI's are used at rating exceeding the absolute maximum rating, they can be permanently destroyed.
ELECTRICAL CHARACTERISTICS
DC CHARACTERISTICS (Vee = 3.0V O.SV, Vss =OV, Ta= -20-+75C, typ means typical value at 3V unless otherwise noted.)
Item
Symbol
min
typ
max
Unit
RES
2.4
INT
2.4
2.2
2.2
1.5
0.6
0.6
100
f.J.A
At Halt
40
f.J.A
f.J.A
300
f.J.A
0.1
f.J.A
0.1
f.J.A
Others
Test Condition
V IH
Timer Mode
Self-check Mode
RES
Input "Low" Voltage
INT
V IL
Others
Current Dissipation
lee
At Stand-By
During AID Operation
TIMER
IlL
INT
V in = OV -Vee
0.8
AC CHARACTERISTICS (Vee = 3.0V O.SV, Vss =OV, Ta= -20-+75C, typ means typical value at 3V unless otherwise noted.)
min
typ
max
Unit
fel
400
kHz
Cycle Time
teye
10
f.J.s
tlWL
teyc
+1
f.J.s
f.J.s
Item
Symbol
Test Conditions
tRWL
teyc
+1
tTWL
teyc
+1
f.J.s
toscf
C L = 10 pF 20%
100
ms
toscl
CG = 10 pF 20%'
1.0
tRHL
400
ms
Oscillation Frequency
(Resistor Option)
f EXT
400
kHz
10
pF
10
pF
R = 90 kQ 1%
EXTAL
I nput Capacitance
XOUT
Cin
Others
251
pF
HD63L05--------------------------------------------~------------
Symbol
Test Condition
=-100 J.LA
IOL = 100 J,LA
Port A, B, C
V OH
Port A, B, C
VOL
Port A, B, C
V IH
Port A, B, C
V IL
Port A, B, C
IIH
V in = 3.0V
Port A, B, C
IlL
V in = OV
Port A, B, C
liLA
V in = OV
(NOTE)
Segment
Common
Common
min
typ
max
Unit
2.7
0.3
V
V
0.8
0.1
J.LA
0.1
J.LA
20
J.LA
2.2
min
typ
max
Unit
V OH1
IOH = -1 J.LA
2.8
V OH2
IOH = -1 J.LA
1.8
V OH3
IOH = -1 J.LA
0.8
V OL1
IOL = 1 J.LA
2.2
V OL2
IOL = 1 J.LA
IOL = 1 J.LA
1.2
V OL3
0.2
V OH1
IOH = -SJ.LA
2.8
V OH2
IOH = -SJ.LA
1.8
V OH3
IOH =-SJ.LA
0.8
V OL1
IOL=SJ.LA
2.2
V OL2
IOL =SJ.LA
1.2
V OL3
IOL =SJ.LA
0.2
Symbol
Segment
IOH
VOH 1 and VOL3 characteristics apply to the .output obtained when segment terminals are used as output ports
(lOH = -JOlLA, IOL = JOlLA).
______; -________________~VOH1
__________~------~~~~VOH2
________________~~~--~VOH3
AID CONVERTER CHARACTERISTICS (Vee = 3.0V, Vss =OV, Ta = -20C-+75C, C = 300 pF, typ means typical value at
3V unless otherwise noted.)
Item
Accuracy
Reference Voltage
min
typ
max
Resolution
Symbol
Test Condition
Unit
Bit
Non-Linear Error
1.5
LSB
"High" Side
V AH
2.2
"Low" Side
VAL
t!. V AEF
0.2
2.0
VAL
2
V AH
ms
V AH - VAL
Input Voltage Range
V IN
Conversion Time
tCNV
252
----------------------------------------------------------HD63L06
SIGNALS
The input and output signals of the MCV are described in
the following:
Vcc, Vss
Power is applied to the MCV at these two terminals. Vee
is a positive power input port and Vss is grounded.
INT
This terminal is used to envoke an external interruption to
the MCV. For details, see the information given under the title,
"Interruptions" .
XTAL, EXTAL
These are control input ports to the built-in clock circuit.
A crystal or resistor is connected to each of them depending
on the degree of stability of the internal oscillation. For the
method of using the input terminals, see the information,
"Internal Oscillator Option".
XIN, XOUT
Connected to these terminals are crystals for the oscillator
on the time base. A clock operation is possible by using a
32.768kHz crystal. For details, see "Internal Oscillator Option".
TIMER
An external input terminal at which the internal timer is
counted down. For details, see the information, ''Timer''.
E
System Clock Output (Cycle clock).
VI, V2
These are terminals for LCD driver. Capacitors are connected
between VI, V2 and Vee
MEMORY
The memory map of the MCV is shown in Figure 1. During
processing of an interruption, the contents of the MCV registers
are saved into the stack in the order shown in Figure 2. During
saving, the stack pointer is decremented and the lower byte
(PCL) of the program counter is the first to be stacked. Then
the upper 4 bits (PCH) are stacked. For pulling, the saved
contents are pulled in order while the stack pointer is being
incremented. In the case of a subroutine call, the contents
of only the program counters (PCH, PCL) are saved into the
stack.
0
Port A
SOOO
$001
Port B
RES
Vsed to reset the MCV. For details, see "Reset".
STANDBY
An external input terminal used halt all MCV operations
and hold data. For details, see "Internal Oscillator Option".
AID Input Terminals (CH I
'"
Port C
$002
Not Used
$003
Port A ODR'
$004
Port B DOR'
$005
Not Used
CHs)
Input terminals for analog voltages needed for A/D conversion. These may also be used as level check inputs under program control. For details, see the information, "AID Converter".
I Port C DOR'
Not Used
$006
$007
$OOB
$009
SOOA
Not Used
$000
SOOE
$OOF
SOlO
Not Used
VRH,VRL
Reference voltages for A/D conversion are applied to these
two terminals. For details, see "A/D Converter".
S013
Main ROM
13632 Bytes)
CC I , CC 2
Connected to CC I and CC 2 are A/D converter offset compensating capacitors. For details, see "A/D Converter".
NUM
This is not intended for user applications. Connect it to Vee.
1--------....
SF30
D8te Reg,'
S014
Oat. Reg.-
S015
LC03
Data Aeg,-
LC04
OataReg.-
S016
S017
LC05
Dati Reg.-
SOlS
LC06
O..a Reg,'
S019
LC07
OataRlg,'
LCOB
OltlReg,-
SOlA
SOlS
Self Check
ROM
1196 Bytes)
SF2F
LCOl
LC02
S01C
SOlO
Not Used
S01F
S020
RAM 196 Sytes!
$FF3
1--------.... $FF4
------------STACK
S060
S07F
Interrupt
Vectors
ROM
112 Bytes)
253
HD63L05-----------------------------------------------------------o
1 1 11
n-4
Condition
Code Reg.
Pull
n+1
n-3
Accumulator
n+2
n-2
Index Register
n+3
1 1 1 1
n-1
PCH*
PCl*
n+4
n+5
Push
Figure 2
REGISTER
The CPU has five registers that can be operated by the programmer. They are shown in Figure 3.
Index Register
Program Counter
Negative (N)
I Accumulator
11
0
PC
11
5 4
10 I 0
10 10 1 0 11 11 1
0
SP
Stack Pointer
Used to indicate that the result of the most recent arithmetic operation, logical operation or data processing is negative
(i.e .. bit 7 being at logical" I ").
Zero (Z)
Half Carry
Accumulator (A)
)1
Reset
Stores an' interruption request flag from the time base which
is selected by the TB select bit. If the TB mask or I (Interrupt
Mask Bit in the CCR) is set, the Interruption Request Flag is
not acknowledged.
Time Base Interruption Mask (TB MASK)
If this bit is set, any interrupt request from the time base
is not acknowledged.
254
----------------------------------------------------------HD63L06
Halt (HALT)
Used to halt the CPU, when this bit is set, the registers are
saved into the stack in the same sequence as in interruption
processing. After all registers have been saved, the CPU halts
and is wait-for-interrupt state.
If the bit is reset by an external interruption or time base
interruption, the CPU restarts operating. A combined use of
the Halt and Time Base Interruption functions permits the
CPU to operate intermittently.
EXT
The LCD drive signal is based on 1/3 bias - 1/3 duty. However, there are switching circuits built in for expanded LCD
capabilities and output only ports. For details, see the infor-
TIMER
Timer
Input Terminal
~
_ _ _ _ _ _ _ _ _ _ _ Timer Output
r----'
I
1 - - - - (Timer I nterrup
tion Request)
I
I
I.... ____ JI
Program
Control
Write
Read
~ Indicates Frequency
Bit Count
Interruption
Request at "1"
Mask at "1" - - - - - - - - '
~----------Timer
at "1"
Counter at "0"
'----------------tP2
at"1" (100kHz)
255
HD63L06---------------------------------------------------------
RESET
VCCT:~":,----n/
GND-----',
-t
V1
An T"m''''
"
Built-in Reset
~VIL
1_
V1H
'
HD63L05
MCU
-----
~--------~I~
The MeV incorporates two oscillators: oscillator 1 for system clock supply and oscillator 2 for time base interruption,
LCD driving and clock supply.
EXTAL
XTAL
Vee
HD63L05
MCU
HD63L05
MCU
6
Crystal Oscillator
Vee
Ext. Clock
Input
Vee
EXTAL
XTAL
RC Oscillator
.....-'''''~----4
EXTA,L
Ext. Clock
Input
MCU
HD63L05
MCU
Ext. Clock
Ext. Clock
Crystal Option
Resistor Option
256
------------------------------------------------------------HD63L05
Oscillator 2 (XIN, XOUT)
Clocks for time base interruption and LCD driving can be
supplied by connecting a 32.768kHz crystal. In Halt status,
oscillator 2 operates and this permits low power dissipation,
XOUT
CJ
HD63L05
MCU
XIN
CPU Clock
Veer
HALT---~
Crystal Oscillator
,--______. . . .1I _
STANDBY
Freq. Divider
Time base
Interrupt
XOUT
Vee
XIN
Vee
HD63L05
MCU
Figure 11
Not Used
When OSC 1 is RC
OSC2
Not Available
OSC1
OSC2
Available
OSC2
Available
OSC2
Not Available
CPU Peripheral
During System
Operation
At Halt
At Standby
0
X
X
X
0
X
0
X
X
X
0
X
0
X
X
X
0
X
X
X
X
X
0
X
(NOTE)
0 ..... run
x ..... stop
Figure 12 Oscillator 2 Mask Option and System Operation
When OSC2 is not available, the clocks for the AID converter and
LCD drivers are provided by the OSCI through the frequency divider.
When OSCI is crystal, OSCI is not allowend to stop at HALT. Because
the response of the oscillator is not so fast. The accuracy of the time
base is kept when OSC2 is 32.768 kHz crystal oscillator.
INTERRUPTION
There are six different interruptions to the MCV: external
interruption (INT), interruption envoked via an input terminal,
internal timer interruption, interruption by termination of
AID conversion, time base interruption (2 types), and interruption by an instruction (SWI).
257
Vector Address
RES
SWI
INT
$FFFE,$FFFF
$FFFC,$FFFD
$FFFA,$FFFB
TIMER
$FfiF8, $FFF9
AID
TIME BASE
5
6
$FFF6,$FFF7
Interruption
$FFF4,$FFF5
Standby
Operation
Sequence
258
---------------------------------------------------------HD83L06
INPUT/OUTPUT
Output
Data Bit
1/0 Pin
Bits of
Data
Direction
Register
Configuration of Port
Output
State
Input to
MCU
3-State
Pin
1
0
rVss~
,.--,
I
,--
..
I
:
---' __ L..... __
VSS
Vss
Vss
259
r1
r-l- -,
CC1
CC I
CHI
Multiplexer
I
I
~~:
} MASK OPTION
CH.
'--_ _.....I.----(CH. )
Multiplexer
L __ ~.ontr:2!J
MPX
_ _ _---'''-_ _ _ _ _ _ _ _.x...._ _ _ _ _
Data Bus
Channel
000
CHI
001
CH 1
010
CH 3
011
CH 4
100
CH.
101
CH 6
110
(CH 7 )
111
(CH.)
~_~
_ _- L_ _
~~_~_~
_______
AID CTRL
Register
This voltage comparison system achieves high input impedance. Offset are compensated for by external capacitors.
Figure 17 shows the configuration of the AID control register.
COMP OUT
AID INT
Used to request an interruption after completion of AID
conversion (Request at "1").
MPX
AID MASK
Used to mask interruptions after completion of AID conversion (Masking at "I").
CNV
To start AID conversion, set this bit to "I". During conversion, "1" is held. Tlie bit is automatically reset to "0" when
260
----------------------------------------------------------HD63L05
SEG.
SEG,
SEG,
SEG.
SEG.
SEG.
SEG,
SEG.
SEG.
SEG
SEG ..
SEG ..
SEG ..
SEG
SEG ..
SEG ..
Pin Location
Block
SEG .. -SEG"
Mask Option
System
Cont.
Duty
Contents of
SEG 1 -SEG 17
00
OUTPUT PORT
01
---
SEG"
10
---
11
1/3 Bias
1/3 Duty LCD
Data Reg.
COM.
COM,
COM,
4>.4>,4>,
Duty
COMMON 1
COMMON 2
COMMON 3
SEGMENT
(1.2.3)
COM, SEGMENT
COMoSEGMENT
COM,SEGMENT
Vee
Fb:
"1"
GND
Output level.
"0" matching Data in
Regilte,
261
HD63L05-------------------------------------------------------
BIT PROCESSING
This MCV can use one instruction (BSET, BCLR) to set
or clear one bit of the RAM or I/O port (except for the data
direction register). All bits of I/O or memory on page 0 are
tested by the BRSET and BRCLR instructions. Depending
on the result of the test, the program can be branched. Since
the bits within the RAM, ROM or I/O can be processed by the
MCV, the user can easily use a bit in the RAM as a flag or
utilize a single I/O bit as an independent control terminal.
ADDRESSING MODE
There are 10 addressing modes available to the MCV for
programming. Familiarize yourself with these modes by reading
the information and referring to the diagrams that follow.
Immediate
See Figure 20. In immediate addressing mode, constants
that will not change during execution of a program are accessed.
The instruction used for that purpose has a length of 2 bytes.
The effective address (EA) is PC. The operand is fetched from
the byte that follows the OP code.
Direct
See Figure 21. In direct addressing mode, the address of the
operand is contained in the second byte of the instruction.
The user can gain direct access to the LSB 256 of memory. All
RAM bytes, I/O registers, and 128 bytes of ROM are located
on page 0 in order to utilize this useful addressing mode.
Extended
See Figure 22. The extended addressing mode is used for
referencing to all addresses of memory. The EA consists of
the contents of the two bytes that follow the OP code. The
instruction used for extended addressing has a length of 3
bytes.
Relative
See Figure 23. Only Branch instructions are used in relative
addressing mode. When a branching takes place, the contents
of the byte next to the OP code are added to the program
counter. EA =(PC) + 2 + ReI., where ReI. indicates signed 8 bits
data at the address following the OP code. When no branching
takes place, ReI. = O. When a branching occurs, the program
jumps to any byte of +129 to -127 of the current instruction.
The length of the Branch instruction is 2 bytes.
Bit Set/Clear
See Figure 27. This addressing mode can be applied to any
instruction that permits any bit on page 0 to be set or cleared.
The byte following the OP code indicates an address within
page O.
Implied
See Figure 29. There is no EA for this mode. All information
needed for execution of instructions is contained in the OP
code. Operations that are carried out directly on the accumulator and index register are included in the implied addressing
mode. In addition, the SWI and RTI instructions are also included in the group of this operation. The instruction using
this addressing has a length of one byte.
262
--------------------------------------------------------HD83L06
Memory
,i
I
8
I
05BF
Fa
Ind,J,Q.:QD"'-_ _ _...
Steck Point
I
A6
1-------1
F8
Prog Count
06CO
CC
~
I
I
I,
Memory
lEA
,
,,
i
,
I
I
I
I
I
t
Adder
'"
~
0000
20
004B
-.
86
052E
48
Steck Point
I
I
I
I
,,
Figure 21
263
20
Index Reg.
I
Prog Count
062F
CC
I
I
I
HD63 L06-------------------------------------------------------
Memory
i
i
I
PROG
LOA CAT
0000
0409~6
06
040A
040B
E5
40
Index Reg
-------..
Stack Point
I
I
Prog Count
40
040C
1-------1
CC
Memory
ii
Index Reg
Stack Point
27
04A8
18
0000
I
i
i
264
------------------------------------------------------------HD63L05
Memory
4C
I-----~
49
4C
Index Reg
B8
PROG LOA X
Stack Point
05F4~
Prog Count
05F5
CC
lEA
I
Melory
008C
BF
Adder
FCB # 86 008A
86
FCB # DB 008B
DB
FCB # CF 008C
CF
I
I
E6
075C
89
I
I
I
I
TABL FCB # BF 0089
'"
r
~
CF
Index Reg
03
Stack Point
Prog Count
075E
CC
HD63L06----------------------------------------------------------
Memory
i
I
DB
Index Reg
02
~6
07
0694
7E
Stack Point
1-------'
Prog Count
0695
I
CC
BF
FCB # 86 077F
86
FCB # DB 0780
DB
FCB # CF 0781
CF
Memory
BF
0000
Index Reg
10
I-----~
01
L
I
Stack Point
I
Prog Count
0591
CC
266
--------------------------------------------------------HD63L06
FO
Index Reg
0000
Stack Point
02
~------1
0576
10
~------1
Prog Count
0000
0594
CC
Memory
I
I
I
I
E5
Index Reg
E5
I
I
Prog Count
OSSB
CC
HD63L06---------------------------------------------------------
INSTRUCTION SET
There are 59 instructions available to the MCV. They can
be divided into five groups: Register/Memory, Read/Modify/
Write, Branch, Bit Processing, and Control. All of these instructions are explained below according to the groups, and are
summarized in individual tables.
Register/Memory
Most of these instructions use two operands. One operand
is either the accumulator or index register, while the other is
acquired from memory using one of the addressing modes.
No operand of register is available in the unconditional Jump
(JMP) and Subroutine Jump (JSR) instructions. See Table 2.
Read/Modify/Write
These instructions read a memory address or register, modify
or test its contents, and writes a new value into the memory or
register. Negative or Zero instructions (TST) do not provide
writing, and are exceptions for the Read/Modify/Write. See
Table 3.
Branch
A Branch instruction will branch from the program sequence
in progress if the specific branch condition is satisfied. See
Table 4.
Bit Processing
This instruction can be used for any bit of the first 256
bytes of memory. One group is used for setting or clearing,
while the other is used for bit testing and branching. See Table 5.
Control
The Control instruction controls the operation of the MCV
for which a program is being executed. See Table 6.
A List of Instructions Arranged in Alphabetical Order
All instructio~s are listed in Table 7 in the alphabetical
order.
OP Code Map
Table 8 shows an OP code map of the instructions used
with the MCV.
268
----------------------------------------------------------HD63L05
Table 2
Register/Memory Instructions
Addressing Mode
Immediate
Operation
Mnemonic
Op
Code
Direct
#
Op
#
Bytes Cycles Code
Op
#
#
Bytes Cycles Code
Indexed
(8-BitOffset)
Indexed
(No Offset)
Extended
Op
#
#
Bytes Cycles Code
Op
#
#
Bytes Cycles Code
Indexed
(16-8it Offset)
Op
#
#
Bytes Cycles Code
---#
Bytes Cycles
LDA
A6
B6
C6
F6
E6
D6
LDX
AE
BE
CE
FE
EE
DE
Store A in Memory
STA
B7
C7
F7
E7
D7
Store X in Memory
STX
BF
CF
FF
EF
DF
Add Memory to A
ADD
AB
BB
CB
FB
EB
DB
ADC
A9
B9
C9
F9
E9
D9
Subtract Memory
SUB
AO
BO
CO
FO
EO
DO
SBC
A2
B2
C2
F2
E2
D2
AND Memory to A
AND
A4
B4
C4
F4
E4
D4
OR Memory with A
ORA
AA
BA
CA
FA
EA
OA
Exclusive OR Memory
with A
EOR
A8
B8
C8
F8
E8
D8
Arithmetic Compare A
with Memory
CMP
Al
Bl
Cl
Fl
El
Dl
Arithmetic Compare X
with Memory
B3
C3
F3
E3
D3
5
5
--
CPX
A3
BIT
A5
B5
C5
F5
E5
D5
Jump Unconditional
JMP
BC
CC
FC
EC
DC
Jump to Subroutine
JSR
BD
CD
FD
ED
DD
Symbols: Op = Operation
# = Instruction
---Implied (A)
Operation
Mnemonic
Implied (X)
Op
Code
Bytes
Cycles
Op
Code
Indexed
(No Offset)
Direct
I T ,Cycles
#
Bytes
Op
Code
Bytes
Cycles
Indexed
(8-Bit Offset)
Op
Code
Cycles
Op
Code
Bytes
Bytes
Cycles
5
Increment
INC
4C
5C
3C
7C
6C
Decrement
DEC
4A
5A
3A
7A
6A
Clear
CLR
4F
5F
3F
7F
6F
Complement
COM
43
Negate
(2's Complement)
NEG
40
- - r----
----
f--
53
33
73
63
50
30
70
60
5
5
ROL
49
59
39
79
69
ROR
46
56
36
76
66
LSL
48
58
38
78
68
LSR
44
54
34
74
64
ASR
47
57
37
77
67
ASL
48
78
68
TST
4D
5D
3D
7D
6D
Symbols: Op = Operation
# = Instruction
- - - - I - - - - f--------1
58
38
1
- ---
Op
Code
Bytes
Cycles
Branch Always
BRA
20
Branch Never
BRN
21
2 or 3 *
Branch IF Higher
BHI
22
2 or 3 *
BlS
23
2 or 3 *
24
2 or 3 *
BCC
(BHS)
24
2 or 3 *
BCS
25
2 or 3 *
(Branch IF lower)
(BlO)
25
2 or 3 *
BNE
26
2 or 3 *
Branch I F Equal
BEQ
27
2 or 3 *
BHCC
2B
2 or 3 *
BHCS
29
2 or 3 *
Branch I F Plus
BPl
2A
2 or 3 *
Branch IF Minus
BMI
2B
2 or 3 *
BMC
2C
2 or 3 *
BMS
20
2 or 3 *
Bil
2E
2 or 3 *
BIH
2F
Branch to Subroutine
BSR
AD
2 or 3 *
4
Operation
Symbol: Op - Operation
# Instruction
If branchad. each instruction will be a 3-cycle instruction.
Mnemonic
BRSET n (n = 0 ..... 7)
BRClR n (n = 0 ..... 7)
Op
Code
Bytes
Cycles
Op
Code
2-n
4 or 5 *
4 or 5 *
BSET n (n = 0 ..... 7)
10+ 2 - n
Clear Bit n
BClR n (n = 0 ... 7)
11+2-n
270
#
Cycles
01 + 2 - n
Set Bit n
#
Bytes
---------------------------------------------------------HD63L06
Table 6 Control Instructions
Implied
Operation
Mnemonic
Op
Code
Bytes Cycles
Transfer A to X
TAX
97
Transfer X to A
TXA
9F
SEC
99
ClC
98
SEI
9B
CLI
9A
Software Interrupt
SWI
83
RTS
81
RTI
80
RSP
9C
No-Operation
NOP
90
1
1
Symbol: Op = Operation
# = Instruction
Implied
Immediate
ADC
ADD
AND
ASl
ASR
Direct
x
x
x
x
x
Extended
Relative
x
x
BCC
BClR
BCS
x
x
x
x
x
x
x
x
x
x
x
Bit
Set/
Clear
BHCC
BHCS
BHI
BHS
BIH
Bil
BlO
x
x
x
x
x
x
BMI
BMS
BNE
BPl
BRA
Symbols for condition code:
H
Half Carry (From Bit 3)
I
Interrupt Mask
N
Negative (Sign Bit)
Z
Zero
BlS
1\
BMC
Bit
Test &
Branch
1\
BEQ
BIT
Condition Code
Indexed
Indexed Indexed
(No
(8 Bits) (16 Bits)
Offset)
x
x
x
x
x
x
1\ 1\
1\ 1\
1\ 1\
1\ 1\
1\ 1\
e
1\ 1\
1\
1\
1\
1\
(Continued)
C
1\
Carry/Borrow
Test and Set if True, Cleared Otherwise
Not Affected
271
~D63L06---------------------------------------------------------Table 7
Addressing Modes
Mnemonic
Implied
Immediate
Direct
Extended
Relative
Condition Code
Indexed
Indexed Indexed
(No
(8 Bits) (16 Bits)
Offset)
Bit
Setl
Clear
Bit
Test &
Branch
RSP
RTI
0
0
A
A
A
A
A
A
AA
A
0
A
A
A
A
RTS
A A
1
A A
A A
A A
1
A A
BRN
x
x
BRCLR
BRSET
BSET
BSR
CLC
CLI
CLR
1<
x
x
x
EOR
INC
CPX
DEC
CMP
COM
x
x
x
JMP
JSR
x
x
LOA
LOX
LSL
LSR
NEG
x
x
NOP
ROL
ROR
SBC
SEC
SEI
x
x
x
X
"x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
STA
STX
SUB
)(
SWI
TAX
TST
x
x
TXA
ORA
x
x
x
)(
x
x
x
x
x
x
x
x
x
x
Carry/Borrow
Test and Set if True, Cleared Otherwise
Not Affected
Load CC Register From Stack
272
A
A
A
A
A
A
A
A
A
1
A
A
A
A
A
A
A
A
A
A
A
A
1
----------------------------------------------------------HD63L06
Table 8 OP Code Map
Bit Manipulation
Control
Read/Modify /Write
Register /Memory
1 l J 1
Set/
Clear
Rei
DIR
BRSETO
BSETO
BRA
BACLRO
BCLRO
BRN
BRSET1
BSET1
BHI
3 BRCLR1
BCLR1
BLS
COM
CPX
BRSET2
BSET2
BCC
LSR
AND
5 W
I
I
A
4
5
NEG
,X1
J
I
,XO
IMP
IMP
ATI*
RTS*
-
SWI*
IMMj DIR
AI
EXT
,X1
,X2
,xo
SUB
+-
CMP
SBC
BRCLR2
BCLR2
BCS
BIT
BRSET3
BSET3
BNE
ROR
LOA
BRCLR3
BCLR3
BEQ
ASR
TAX
STA (+1)
8 BRSET4
9 BRCLR4
BSET4
BHCC
LSL/ASL
EOR
BHCS
ROL
CLC
BCLR4
SEC
AOC
8
9
CLI
SEI
ORA
BRSET5
BSET5
BPL
DEC
B BRCLR5
BCLR5
BMI
C BRSET6
BSET6
BMC
INC
0 BRCLR6
E BRSET7
BCLR6
BMS
BSET7
SIL
BRCLR7
BCLR7
3/4 or 5
2/4
f---
(NOTES)
NOP
TXA
1/*
1/1
CLR
BIH
2/20r 3
TST
2/4
1/1
1/1
I 2/5 ! 1/3
RSP
BSR*
JSR(+1)
ADD
JMP(-1)
JSR
IJSR(+1
LOX
- I
I
2/2
STX(+1)
2/3
3/4
3/5
0
E
F
2/4
273
HIGH
Branch
Test &
Branch
1/2
HD63L05--------------------------------------------------------
~
~. ~
~
LC01
LC02
Multiplexed
Timing
C
0
C
0
c
0
sis
~I~
1
2
E
G
E
G
E
G
E
G
E
G
E
G
8
E
G
E
G
10
E
G
11
E
G
E
G
E
G
12
13
14
15
16
17
1
2
3
4
5
6
7
0
1
2
3
4
7
1
2
3
4
5
LC05
1
2
3
4
5
6
0
1
2
3
4
5
6
LC06
LC07
LeOS
1
2
3
4
5
6
0
1
2
3
4
5
6
2
3
4
5
6
WAITE
(NOTE)
U
Mark a selected Multiplexed Timing and Segment Output Terminal with a circle (OJ.
In the case of Output or Static LCD driver, Multiplexed Timing is fixed at COM 1
4> WR ITE is a write clock for the external option (EXT = "'''J.
It is generated when LCD1 is rewritten by the CPU.
274
E
G
LC04
E
G
LC03
E
G
----------------------------------------------------------HD63L06
110 Option
Pin Name
Remarks
I/O
A
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
!LO
!LO
I/O
I/O
Ao
A1
A2
A3
A4
A5
As
A7
Bo
B1
B2
B3
B4
B5
Bs
B7
Co
C1
C2
C::I
/LO
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
INT
110 Option
Pin Name
SEG1
SEG2
SEG3
SE.G4
SEG5
SEGs
SEG7
SEGa
SEGs
SEG10
SEGll
SEG12
SEG13/CHs
SEG14/CH5
SEG15/CH4
SEG16/CH3
SEG 17/CH 2
V1/CH7
V2/CHa
(NOTE)
I/O
Remarks
F
J)
0,1
0,1
0,1
0,1
0,1
0,1
0,1
1\
II
I
.~
1
\ L
11
1 I
1 1
V
1\
/\
/ ~
/ \
/
\
1f
\I
\.
A
/
1\
I \
I \
I
I
II
I
I
l~
/"'-..
275
MCU
(Microcomputer Unit)
FEATURES
Expanded HMCS6800 Instruction Set
8 x 8 Multiply Instruction
Serial Communications Interface (SCI)
Upward Source and Object Code Compatible with HD6800
16-bit Threefunction Programmable Timer
Applicable to All Type of EPROM
2048 bytes; HN462716
4096 bytes; HN462732 or HN462532
8192 bytes; HN482764
128 Bytes of RAM (64 bytes Retainable on Powerdown)
29 Parallel I/O and Two Handshake Control Line
Internal Clock Generator with Divide-byFour Output
Full TTL Compatibility
Full Interrupt Capability
Single-Chip or Expandable to 65k Bytes Address Space
Bus compatible with HMCS6800 Family
TYPE OF PRODUCTS
-PRELIMINARY-
HD68P01S0
Vss 1
Vss 1
xrAL
EXTAl
NMi
o Vee
iiiO.
REi
vee
p ..
P"
Pu
Pu
1
11
ONe
OA,
OA,
OA,
OA,
o A.,
OA,
P14 t
OA,
P. l
P II 14 OA.
00.
PH 1
P., 1 00,
P,.'1 00,
OVss
l
Vee 0
Vee 0
Vee 0
A. 0
A. 0
Vee 0
VssO
AIO 0
CEO
0, 0
O. 0
0, 0
0, 0
0, 0
sc,
sc,
EXTAL
NMi
P"
iRCi.
ill
P"
vee
P"
p ..
p,.
P"
p ..
P"
Pn 1
PO'
p
p ..
P"
P.,
p..
p..
p ..
sc,
sc,
o Vee
ONe
OA,
OA.
OA,
OA,
OA,
OA,
OA,
OA.
00.
00,
00,
OVss
p ..
HD68P01V07
Sc,
Sc,
Bus Timing
HD68P01S0
1 MHz
HN462716
HD68P01V05
1 MHz
HN462532
HD68P01V07
1 MHz
HN462732
o Vee
ONe
OA,
OA.
OA,
P"
OA,
Pn 1
OA,
'u
"
OA,
Pu 1
OA,
P. l l
40A.
00.
PilI
00,
P., 1
,00,
p '
OVSS
Pit 1
'II'
PO'
276
P,.
P"
p ..
P"
P~
p ..
P.,
P.,
p ..
p ..
p..
vee Standby
PO'
Vss I
Type No.
P"
P"
p ..
P.,
vee StandbY
PO'
P,.
Vee 0
Vee 0
VccO
A. 0
A, 0
Vee 0
0"0
A,.O
All 0
0, 0
O. 0
0, 0
0, 0
0, 0
Vee '0
Vee 0
Vee 0
A. 0
A. 0
All 0
VssO
A,.O
C"E0
0,0
0.0
0,0
0,0
0,0
P"
P"
P"
p ..
P,.
P"
P,.
PO'
p ..
p ..
P.,
P.,
P"
p ..
P"
P.,
Vee Standby
~-~-+"'P20
I++-r-~>-t-+
I++-+-~~'"
1++-+-+--1~-+
P21
P22
P23
I++-+-+-tl-r+ P24
M----+PIO
M-----+Pu
.----+PI2
1+------+PI3
M-----+P 14
k-----+PIs
.-----+PI6
tt-----+PI7
On Package
r-- ------ -- - - - j
I
I
I
I
I
I
I
I
EPROM
HN462716]
[ HN462732
HN462532
Ao I
Al
A2
A3
A4
-As
A6
A7
As
A9
AIO
Address
Output
Au l
Ct:-___
AI21
00 I
01
02 I
03 I
O.
Data
Input
05 :
06 I
07 I
IL _ _ _ _ _ _ _ _ _ _ ...JI
')77
Item
Supply Voltage
Input Voltage
Vee
V in
Operating Temperature
Topr
Storage Temperature
T stg
*
*
Value
Unit
-0.3 -+7.0
-0.3 -+7.0
V
c
-+ 70
-55 - +150
ELECTRICAL CHARACTERISTICS
Item
Input "High" Voltage
Symbol
RES
V1H
Other Inputs*
Allinputs*
P40 - P47
SCl
EXTAL
Ilinl
Ilinl
PlO -P l7 ,P 30 -P 37
Pzo - PZ4
P30 - P37
P40 - P47 , E, SC l , SC z
Input Capacitance
Vee Standby
Standby Current
Frequency of Operation
max
Vee
0.5
Vin = 0 - 2.4V
V in = 0- Vee
Pl7
typ
-0.3
VIL
All Outputs
min
4.0
2.0
V in = 0 - 5.25V
V in = 0.5 - 2.4V
ilTSd
V OH
I LOAD = -2051J.A
ILOAD=- 145 IJ. A
2.4
2.4
2.4
VOL
-IOH
V out = 1.5V
1.0
V in = OV, Ta = 25C,
Other Outputs
Output "Low" Voltage
Test Condition
Po
-
P47 , SCl
Cin
f = 1.0 MHz
Vee
0.8
2.5
IJ.A
10
100
IJ.A
0.5
10.0
mA
1200
mW
12.5
10.0
V SBB
4.0
5.25
V SB
4.75
5.25
Powerdown
ISBB
8.0
Extarnal Clock
4fo
2.0
4.0
Crystal
fXTAL
3.579
278
V
mA
Operating
0.8
0.8
Powerdown
V SBB = 4.0V
Unit
4.0
pF
V
mA
MHz
Symbol
Cycle Time
Test Condition
typ
max
Unit
10
200
Ils
ns
50
ns
50
ns
min
tCYC
PWASH
tASr
tASf
tAS O
60
ns
tEr
50
ns
50
ns
tEf
PW EH
450
ns
PW EL
450
ns
tASEO
tAD
tAOL
tosw
tOSR
225
80
tHR
10
tHW
20
tAS L
tAHL
60
20
I Read
I Write
l Non-Multiplexed Bus
I Multiplexed Bus
20
tAH
(tAC CN )
(tACCM)
tRC
tpcs
60
Fig. 1
Fig. 2
Fig. 11
Fig. 12
100
200
ns
260
ns
270
ns
ns
ns
(610)
(600)
ns
ns
ns
ns
ns
ms
ns
PERIPHERAL PORT TIMING (Vee = S.OV S%, Vss = OV, Ta = 0"'" +70C, unless otherwise noted.)
Symbol
Test Condition
min
typ
max
Unit
Port 1,2,3,4
tposu
Fig. 3
200
ns
Port 1, 2,3,4
tpOH
Fig. 3
200
tOS01
Fig. 5
350
ns
toso2
Fig. 5
350
ns
Port 1, 2*,3,4
t pwo
Fig.4
400
ns
*
Port 2**, 4
tCMOS
Fig.4
2.0
Ils
tPWIS
Fig. 6
200
ns
tlH
Fig. 6
50
ns
tiS
Fig. 6
20
ns
Item
-K;rt3
Port 3
ns
Item
Symbol
tpWT
tToD
max
ns
--
--
600
ns
min
Fig. 7
tSCYC
tPWSCK
typ
2tcyc+ 2OO
Test Condition
--
tCYC
0.4
0.6
tScyc
Item
Mode Programming Input "Low" Voltage
V MPL
V MPH
Test Condition
min
typ
max
Unit
1.7
Fig.8
4.0
3.0
2.0
150
PW RSTL
tMPs
tMPH
teye
.Jl2.2V.,"-PWASH-
Address Strobe
(ASt
/
-- --
O.6V-t-
2.4 V~
Enable
(Et
--
~r
---- -,r.
/
-tASf
-tASr
tASD
ASEC
0'\
PW El
--
--
-tEr
-tEf
}~2.2V
Address Valid
)
)
l'-+1
j-tAHl
tosw-~2.2V
2.2V
-lr
Address \
Valid
I
O.6V
-tADL-
Data Valid
}'f- 2 .0V
)~ !;d;ess ~~
Valid
r- 0 .6V ,I{
\
... O.8V
Data Valid
ItACCMt
280
.... ~
-tt-NV
O.6V
-tOSR-
-tAH
.-
O.6V
tASl-J
MPU Read
0.-0" A.-A,
(Port 3t
\.
PW EH
MPU Write
Do-D,.A.-A,
(Port 3t
.... r-
-tAD-
R/W .Ar-A."
(SC~ (port4t
Unit
~tHR
.l\.
,{
--
-.
tcyc
tcyc
--
ns
.
27v'Jr-
-.'f-
Enable
IE)
PWEL
0.5V-~
Rjlil
iOS
(SC2)
(SCI)
:"~
PW EH
~{
--\
r-----tAO-
AO"""'AJ(Port4 )
tcyc
--
-tEr
_tEf
.. ~
2.2V r-
-tAH
Address Valid
,~
O.6V\..
r+--tosw--+
MPUWrite
2.2V r-
0.-0,
(Port 3)
O.6V\"
~~
Data Valid
..)l.
-tOSR-
(tACCN)
MPU Read
0.-0,
(Port 3)
-tt-fill
.......
-tHR
2.0V
Data Valid
--------------------------------------~
O.SV
r-
r-MPU Read
MPU Write
E
CMOS
t
P IO -P I7
P 20 - PH
p. O - p. 7
--+}
-tPWD_
All Data
Port Outputs
Inputs
P)7
Inputs"
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _J
"
----0.7VCC
2.2V
O.6V Data Valid
p)O -
(NOTE)
Figure 3
Figure 4
Address
Bus
OS3 - - - - - - - -......
Figure 5
Figure 6
281
Timer
Counter _ _ _ _- - I
1'---- ____
___
(;:~~~,I~;p:: )-----...;.;...'"<1
r------------J1
P2I
Output
Vee
Equ,v.
INTRODUCTION
an on-package EPROM. The HD68POI is pin and code compatible with the HD6801 and can be used to emulate the
HD6801, allowing easy software development using the onpackage EPROM. Software developed using the HD68POI can
then be masked into the HD6801 ROM.
~175- ~
- -
- -
_oUO ?- - - ~ - -
- ~oo
21
8Bit Accumulators
A and B
Or 16-Bit Double
Accumulator 0
115
01
115
SP
01
P5
PC
01
Figure 10
282
INTERRUPTS
set to inhibit maskable interrupts and a vector is fetched corresponding to the current highest priority interrupt. The vector
is transferred to the Program Counter and instruction execution
is resumed. Interrupt and RES timing is illustrated in Figure 11
and 12.
L." InstruCl,on
---I
LSB
Interrupt
FFFE
FFFF
RES
FFFC
FFFO
NMI
FFFA
FFFB
FFF8
FFF9
FFF6
FFF7
FFF4
FFF5
FFF2
FFF3
FFFO
FFF1
Cvcle
#7
#1
#, 0
I #" I
Internal
Add,ess Bus-"_......"""_....., ' -_ _ _ _ _ ' _ _ _ ' - - _ . . J " _ _ _, ' - _ - - - ' , ' -_ _ _ _ _ ' _ _ _
mMO'IAa:-----~\"_~
,~_.,.,'"
#12
______________________________________________________________
-II--'pcs
Inle'n.I_,.r---....---..,---,,.---"'---,..,---__"\.r----.....---""'\.,..----..J'-----..J'---,r-----....----..,----"\.r---~-
oal. Bus ~_ _ _. J '---oI"-O-P-C-od-e' ~O-P-Cod-", ~PC-O-_p-CoI7 "'p-CS---PC-"S ....X-O---X7-' ....X-S---X'-5' '-A-C-C-A...I '-A-C-C-B...I ....-C-C-A-' ' ....
1,-,e-Ie-nl...l "-v-ec-to-,' ....v-e-cl-o-,"F
....,-rs-tl-nsJt. "0-'-o.,a
MSS
LSB
Inlerrupl Routone
Inle,n.1 A!W
\~------------------------------~I
Figure 11
~~\\~\\\\~
--5.25V
Vc;c
4.75V
}\\\\\\\\\\\\\\\\\
Interrupt Sequence
LrLf4
\\\\\\\\\\\\\\\\\\\'{
nn.ns
I
.~~~~~~~~~~~~:.-~f-~~~~~~~~~~_'_AC-------_----~s ~1e-4
RES __
Inl.,nal RtW
~o;-IPCS
....;-,...,V.,..-tP-cs-----------_ _
XSS\\\\\\\\\\SSSSSS\\\\\\Ssy
~NOIV.lod
Figure 12
Reset Timing
283
pc:::x:::::x::
0')
co
-u
en
0
0')
CO
-u
<
UI
0')
CO
-U
0
...a
<
0
I\:)
(X)
~
............ ~n("l./
........... . /
Vector
NMI
SWI
IRQ!
ICF
OCF
TOF
SCI
Figure 13
Interrupt Flowchart
PC
FFOC:FFFO
FFFA:FFFB
FFF8:FFF9
FFF6:FFF7
FFF4:FFF5
FFF2:FFF3
FFFO:FFF1
Non-MaskablEl Interrupt
Software Interrupt
Maskable Interrupt Request 1
Input CapturE! Interrupt
Output Compare Interrupt
Timer Overfle.w Interrupt
SCI Interrupt (TORE + RORF + ORFEI
Figure 14
Pow,,, U",
Ix
RES
This input is used to reset the MCU's internal state and provide an orderly startup procedure. During powerup, RES must
be held below 0.8 volts: (1) at least tRe after Vee reaches 4.75
volts in order to provide sufficient time for the clock generator
to stabilize, and (2) until Vee Standby reaches 4.75 volts. RES
must be held low at least three E-cycles if asserted during powerup operation.
When a "High" level is detected, the MCV does the following:
1) All the higher order address lines will be forced "High".
2) I/O Port 2 bits, 2, I, and 0 are latched into programmed
control bits PC2, PCI and peo.
3) The last two ($FFFE, $FFFF) locations in memory will
be used to load the program addressed by the program
counter.
4) The interrupt mask bit is set; must be cleared before the
MPV can recognize maskable interrupts.
E (Enable)
patible clock to the MCU's internal clock generator. Divide-byfour circuitry is included which allows use of the inexpensive
3.58 MHz Color Burst TV crystals. A 22 pF capacitor is required from each crystal pin to ground to ensure reliable startup and
operation. Alternatively, EXTAL may be driven with an external TTL compatible clock of 4fo with a duty cycle of 50%
(1O%) with XTAL connected to ground.
The internal oscillator is designed to interface with an AT-cut
quartz crystal resonator or a ceramic resonator operated in parallel resonance mode in the frequency range specified for fXT AL.
The crystal should be mounted as close as possible to the input
pins to minimize output distortion and startup stabilization
time. The MCU is compatible with most commercially available
crystals and ceramic resonators and nominal crystal parameters
are shown in Figure 15.
Ix
This is an output clock used primarily for bus synchronization. It is TTL compatible and is the slightly skewed divide-byfour result of the MCV input frequency. It will drive one
Schottky TTL load and 90 pF, and all data given in cycles is referenced to this clock unless otherwise noted.
285
In Single Chip Modes, SCI and SC2 are configured as an input and output, respectively, and both function as Port 3 controllines. SCI functions as IS3 and can be used to indicate that
Port 3 input data is ready or output data has been accepted.
Three options associated with IS3 are controlled by Port 3's
Controi and Status Register and are discussed in Port 3's description. If unused, IS3 can remain unconnected.
SC 2 is configured as OS3 and can be used to strobe output
data or acknowledge input data. It is controlled by Output
Strobe Select (OSS) in Port 3's Control and Status Register. The
strobe is generated by a read (OSS= 0) or write (OSS = I) to
Port 3's Data Register. OS3 timing is shown in Figure S.
2------------~IDI~-------------3
r---4I......------,
Cll '" C l 2 '" 22pF
(3.2
20%
-4 MHz)
EXT A L t-----tl-...,
Co
Equivalent Circuit
Vcc
~~~--------_~,rJ~'-----------------------------4.75V
-----------------'
RES
------------------~------------~
....---tRC---'~
Oscillator
Stabilization
Time, tAC
Figure 15
Oscillator Characteristics
286
two lines, IS3 and OS3, which can be used to control Port 3
data transfers.
Three Port 3 options are controlled by the Port 3 Control
and Status Register and available only in Single-Chip Mode: (1)
Port 3 input data can be latched using IS3 as a control signal,
(2) OS3 can be generated by either an MPU read or write to
Port 3's Data Register, and (3) an IRQl interrupt can be enabled by an IS3 negative edge. Port 3 latch timing is shown in
Figure 6.
Port 3 Control and Status Register
Port 1
Port 2
Port 3
Port 4
Port Address
Data Direction
Register Address
$0002
$0003
$0006
$0007
$0000
$0001
$0004
$0005
$OOOF
Bit 0-2
Bit 3
P10-P17 (Port 1)
Port 1 is a mode independent 8-bit I/O port where each line
is an input or output as defined by its Data Direction Register.
The TTL compatible three-state output buffers can drive one
Schottky TTL load and 30 pF, Darlington transistors, or CMOS
devices using external pullup resistors. It is configured as a data
input port by RES. Unused lines can remain unconnected.
Bit 4
Bit 5
Bit 6
P20-P24 (Port 2)
Port 2 is a mode independent 5-bit I/O port where each line
is configured by its Data Direction Register. During RES, all
lines are configured as inputs. The TTL compatible three-state
output buffers can drive one Schottky TTL load and 30 pF or
CMOS devices using external pullup resistors. P20 , P21 and P22
must always be connected to provide the operating mode. If
lines P23 and P24 are unused, they can remain unconnected.
P20, P21, and P 22 provide the operating mode which is
latched into the Program Control Register on the positive edge
of RES. The mode may be read from Port 2 Data Register as
shown where PC2 is latched from pin 10.
Port 2 also provides an interface for the Serial Communications Interface and Timer. Bit 1, if configured as an output, is
dedicated to the timer's Output Compare function and cannot
be used to provide output from Port 2 Data Register.
Bit 7
PC21 PC1
543
P22
P21
P20
I I I I I I
PCO
P24
P23
Not used.
LATCH ENABLE. This bit controls the input latch for Port 3. If set, input data is
latched by an IS3 negative edge. The latch
is transparent after a read of Port 3's Data
Register. LATCH ENABLE is cleared by
RES.
ass (Output Strobe Select). This bit determines whether OS3 will be generated by a
read or write of Port 3's Data Register.
When clear, the strobe is generated by a
read; when set, it is generated by a write.
ass is cleared by RES.
Not used.
IS3 IRQl ENABLE. When set, an IRQl
interrupt will be enabled whenever IS3
FLAG is set; when clear, the interrupt is
inhibited. This bit is cleared by RES.
IS3 FLAG. This read-only status bit is set
by an IS3 negative edge. It is cleared by a
read of the Port 3 Control and Status
Register (with IS3 FLAG set) followed by
a read or write to Port 3's Data Register or
by RES.
$0003
P30-P37 (Port 3)
Port 3 can be configured as an I/O port, a bidirectional 8-bit
data bus, or a multiplexed address/data bus depending on the
operating mode. The TTL compatible three-state output buffers
can drive one Schottky TTL load and 90 pF. Unused lines can
remain unconnected.
P40-P47 (Port 4)
Port 4 is configured as an 8-bit I/O port, address outputs, or
data inputs depending on the operating mode. Port 4 can drive
one Schottky TTL load and 90 pF and is the only port with
internal pullup resistors. Unused lines can remain unconnected.
287
HD68P01S0, HD68P01V05, HD68P01V07------------------------------Internal pullup resistors allow the port to directly interface with
CMOS at 5 volt levels. External pullup resistors to more than 5
volts, however, cannot be used.
Port 4 in Expanded Non.Multi~ed Mode
OPERATING MODES
Fundamental Modes
288
addition, the internal and external data buses are connected and
there must be no memory map overlap to avoid potential bus
conflicts. Mode 0 is used primarily to verify the ROM pattern
Vee
Vee
Vee
XTAL
XTAL
c::::J
EXTAL
Port 1
Port 3
81/0 Lines
8110 Lines
NMI
IRQ,
IRQ,
Port 1
8 I/O
Lines
Port 1
81/0
Lines
Port 4
Port 2
8110 Lines
5110 Lines
Serial 1/0
16Bit Timer
Vss
Port 2
Port 4
5110 Lines
81/0
SCI
16Bit Timer
Lines
Vss
Figure 16
NMI
Vss
Lines
16Bit Timer
Vee
Vee
.... -- 100 -01)
- - IA o-A1)
. "--IO'S'
-_i-+-+--_ R/W
~-~~r+~--_.~~_r--_._r~r+---.E
Port 3
8 Data Lines
Port 1
81/0 Lines
Port 1
81/0
Port 2
Port 2
5110
5110
Lines
Serial 110
16Bit Timer
SCI
Timer
Vss
Vss
Figure 18
Vee
Vee
XTAL
R/iN
Port 3
Port 1
16
81/0 Lines
Port 2
Port 4
8 Lines
Address Bus
16Bit Timer
Port 2
5S~~ ~
Timer
'----,...----'
Vss
Vss
Figure 19
289
--_1-+---- JlIW
E
~o~;~ 4I 1t1
5110 Lines
Serial 1/0
---'-+---(A o
G OC
01
Port 3
Add",,/Dota ,
01
74LS373
(Typical)
_ T
T I
TI I
I
Function Table
Add.." ... - A,
Enable
-,
OR
DR
-
IIIIII
L
L
H
."
H
H
L
X
H
L
X
X
00
Z
) Do.., O. - 0,
Figure 20
, PC2 , PC1 ,
pco ,
P20
$0003
PH
(PC2)
(PC1)
P20
(PCO)
ROM
RAM
Interrupt
Vectors
MUXI5,6)
NMUX(5,6)
1(2)
111 )
E
E
E
MUX(4)
E
E
1(3)
P21
\egend:
I - Internal
~ - External
\JX - Multiplexed
'UX - NonMultiplexed
logic "0"
ogic "1"
Bus
Mode
Operating Mode
Single Chip
Multiplexed/Partial Decode
NonMultiplexed/Partial Decode
Single Chip Test
Multiplexed /No RAM or ROM
MUX(4)
Multiplexed /RAM
MUX(4)
MUX(4)
Multiplexed Test
NotlS:
(1) Internal RAM is addressed at $XX80
(2) Internal ROM is disabled
(3) RES vector is external for 2 cycles after RES goes high
(4) Addresses associated with Ports 3 and 4 are considered external in Modes 0, 1, 2, and 3
(5) Addresses associated with Port 3 are considered external in Modes 5 and 6
(6) Port 4 default is user data input; address output is optional by writing to Port 4 Data Direction Register
290
.>
RI RI RI
6
I BI IC
HD68P01
Xo
Yo
f - - - Zo
Xl
RES
9
10
P20 (PCO)
P21 (PC1)
P22 (PC2)
YI
ZI
(
C~
???
~
Mode
Control
Switch
Figure 21
Inh
HD14053B
[NOTES)
Jr
1) Mode 7 as shown
2) RC ~ Reset time constant
3) RI = 10kfl
Truth Table
Control Input
On Switch
Inh
A
B
C
Inhibit
Binary to 1-of-2
Decoder with
Inhibit
C B A
xocr-----------------4~~~~+-~
Xl o--------------------!c;:>!+-+++_---l
Yoo-------------------4<~++_--,
YIo---------------------~H-+_---l
Zoo-------------------K>H---,
Zlcr--------------~~~
Figure 22
Select
Zo
Yo
Xo
0 1
Zo
Yo
XI
1 0
Zo
YI
Xo
Zo
YI
Xl
0 0
ZI
Yo
Xo
0 1
ZI
Yo
XI
1 0
Zl
YI
Xo
ZI
YI
XI
X X X
HD14053B Multiplexers/Demultiplexers
291
HD14053B
MEMORY MAPS
The MCV can provide up to 6Sk byte address space depending on the operating mode. The HD68PO 1 provides 8k byte address space for EPROM, but the maps differ in EPROM types as
follows.
1) HN462716 (a 2k byte ROM)
In order to support the HD6801S0, EPROM of the
HD68P01S0 must be located at $F800-$FFFF.
2) HN462532, HN462732 (a 4k byte ROM)
In order to support the HD6801VO EPROM of the
HD68PO 1VOS and the HD68PO 1V07 must be located
at $FOOO-$FFFF.
3) HN482764 (a 8k byte ROM)
The HD68PO 1 can provide up to 8k byte address
space using HN482764 instead of HN462732. In this case,
EPROM of the HD68POI . is located at $EOOO-$FFFF.
A memory map for each operating mode is shown in Figure
23. The first 32 locations of each map are reserved for the
MCU's internal register area, as shown in Table S, with exceptions as indicated.
Register
Address
Port 1
Port 2
Port 1
Port 2
Data
Data
Data
Data
Direction Register* * *
Direction Register***
Register
Register
00
01
02
03
Port 3
Port 4
Port 3
Port 4
Data
Data
Data
Data
Direction Register***
0 irection R egister* * *
Register
Register
04*
05**
06*
07**
08
09
OA
OB
OC
00
OE
OF*
10
11
12
13
14
15-1F
292
HD68POl
Mode
HD68POl
Mode
$0000(1)
Internal Registers
I nternal Registers
$001F
$001F
External Memory Space
$0080
Internal RAM
Internal RAM
$OOFF
$OOFF
$EOOO
$EOOO
EPROM
$FFEF
EPROM
$FFFO
$FFFF(2)
(NOTES)
1) Excludes the following addresses which may
be used externally: $04, $05, $06, $07 and $OF.
2) Addresses $FFFE and $FFFF are considered
external if accessed within 2 cycles alter a
positive edge of RES and internal at all other
times.
3) After 2 MPU cycles, there must be no overlapping of internal and external memory
spaces to avoid driving the data bus with more
than one device.
4) This mode is the only mode which may be used
to examine the interrupt vectors in EPROM
using an external Reset vector.
Figure 23
[NOTES]
1) Excludes the following addresses which may
be used externally: $04, $05, $06, $07 and
$OF.
2) EPROM addresses $FFFO to $FFFF are
not usable.
293
HD68POl
Mode
HD68POl
Mode
Multiplexed/RAM
$0000(1)
$0000(1)
} Internal Registers
Internal Registers
$001F
$001F
External Memory Space
$0080
Internal RAM
$OOFF
----I,
$FFFO ....
$FFFO
1----11
$FFFF _ _ _ _.. }
[NOTE]
1) Excludes the following addresses which may
be used externally: $04, $05, $06, $07, and
$OF.
Figure 23
[NOTE]
1) Excludes the following addresses which may
be used externally: $04, $05, $06, $07 and
$OF.
294
- - - - - - - - - - - - - - - - H D 6 8 P 0 1 S Q , HD68P01V05, HD68P01V07
HD68POl
Mode
HD68POl
Mode
Non-Multiplexed/Partial Decode
$0000
} Internal Registers
$OOlF
$0080
} I nternal RAM
$OOFF
$0100
$01 FF ' - _......._
.....
$EOOO
EPROM
$XX80
$XXFF
Internal RAM
Internal Interrupt Vectors
[NOTES]
1) Excludes the following addresses which may
not be used externally: $04, $06, and $OF.
(No lOS)
2) This mode may be entered without going
through RESET by using Mode 4 and subsequently writing a "1" into the PCO bit of
Port 2 Data Register.
3) Address lines Ao -A, will not contain addresses until the Data Direction Register for Port 4
has been written with "l's" in the appropriate
bits. These address lines will assert "l's" until
made outputs by writing the Data Direction
Register.
[NOTES]
1) The internal ROM is disabled.
2) Mode 4 may be changed to Mode 5 without
having to assert RESET by writing a "1" into
the PCO bit of Port 2 Data Register.
3) Addresses As to AI s are treated as "don't
cares" to decode internal RAM.
4) Internal RAM will appear at $XX80 to $XXFF.
Figure 23
$FFFF
295
HD68P01
Mode
HD68P01
Mode
Single Chip
Multiplexed/Partial Decode
$0000(1)
Internal Registers
$OO'F
Internal Registers
$0080
Internal RAM
$OOFF
$OOFF
$EOOO
$FFFF
$EOOO
EPROM
EPROM
[NOTES)
,) Excludes the following address which may be
used externally: $04, $06, $OF.
2) Address lines As -A IS will not contain
addresses until the Data Direction Register for
Port 4 has been written with ""s" in the
appropriate bits. These address lines will
assert ""s" until made outputs by writing the
Data Direction Register.
296
24.
Counter ($09:0A)
The key timer element is a 16-bit free-running counter which
is incremented by E (Enable). It is cleared during RES and is
read-only with one exception: a write to the counter ($09) will
preset it to $FFF8. This feature, intended for testing, can disturb serial operations because the counter provides the SCI's
internal bit rate clock. TOF is set whenever the counter contains
alII's.
Timer b~7~~~~~~__T-~~~~
Control
And .,...........-&..,-........,........,........,...1..........-Status
Register
$08
Bit 1
Port 2
DDR
.---I
Figure 24
297
654
Bit 0 OLVL
Bit 1 IEDG
Bit 2 ETOI
Bit 3 EOCI
Bit 4 EICI
Bit 5 TOF
Bit 6 OFC
Bit 7 ICF
tOP 22
The Serial Communications Interface includes four addressable registers as depicted in Figure 25. It is controlled by the
Rate and Mode Control Register and the Transmit/Receive Control and Status Register. Data is transmitted and received utilizing a write-only Transmit Register and a read-only Receive
Register. The shift registers are not accessible to software.
Bit 7
I X
Bit 0
$12
Port 2
(Not Addressable)
Receive Shift Register
....- - - E
Tx
Bit
4
12
$13
Figure 25
SCI Registers
Wake-Up Feature
The Rate and Mode Control Register controls the SCI bit
rate, format, clock source, and under certain conditions, the
configuration of P22 . The ~ster consists of four write-only
bits which are cleared by RES. The two least significant bits
control the bit rate of the internal clock and the remaining two
bits control the format and clock source.
Rate and Mode Control Register (RMCR)
Programmable Options
6543210
298
I I I I I I I
X
CC1
cco SS1
sso
$0010
Bit 2 TIE
Bit 3 RE
Bit 4 RIE
Bit 5 TORE
(Note) The source of SCI internal bit rate clock is the timer's free running counter. An MPU write to the counter can disturb serial
operations.
Bit 6 ORFE
Bit 0 WU
Bit I TE
543
Bit 7 RDRF
: SSO
0
1
0
1
2.4576 MHz
614.4 kHz
26 ~s/38,400 Baud
20~s/4,800 Baud
1.67ms/600 Baud
-..- 6.67ms/150 Baud
4fo
E
E + 16
E + 128
E + 1024
E + 4096
4.0 MHz
1.0 MHz
16
~s/62,500
Baud
Baud
1.024ms/976.6 Baud
4.096ms/244.1 Baud
128~s/7812.5
Format
Clock Source
Port 2 Bit 2
NRZ
NRZ
NRZ
Internal
Internal
External
Not Used
Output*
Input
* * Bit 3 is used for serial input if R E = "1" in TRCS; bit 4 is used for serial output if TE = "1" in TRCS.
299
Port 2 Bit 3
**
**
**
**
Port 2 Bit 4
**
**
**
**
If the user wishes for the serial I/O to furnish a clock, the following requirements are applicable:
the values of RE and TE are immaterial.
CCl, ceo must be set to 10
the maximum clock rate will be E + 16.
the clock will be at 1X the bit rate and will have a rising
edge at mid-bit.
Then the 8 data bits (beginning with bit 0) followed by the stop
bit (1), are transmitted. When the Transmitter Data Register has
been emptied, the TORE flag bit is set.
If the MCU fails to respond to the flag within the proper time, (TORE is still set when the next normal transfer from
the parallel data register to the serial output register should
occur) then a 1 will be sent (instead of a 0) at "Start" bit time,
followed by more 1's until more data is supplied to the data
register. No O's will be sent while TORE remains a 1.
Serial Operations
The transmit operation is enabled by TE in the Transmit/Receive Control and Status Register. When TE is set, the output of
the transmit serial shift register is connected to P 24 and the
serial output by first transmitting to a ten-bit preamble of 1'so
Following the preamble, internal synchronization is established
and the transmitter section is ready for operation.
At this point one of two situation exist:
1) if the Transmit Data Register is empty (TORE = 1), a continuous string of ones will be sent indicating an idle line,
or,
2) if a byte has been written to the Transmit Data Register
(TORE = 0), it is transferred to the output serial shift register and transmission will begin.
During the transfer itself, the start bit (0) is first transmitted.
Receive Operations
INSTRUCTION SET
Description
ABX
ADDD
ASLD
BRN
LDD
LSRD
MUL
PSHX
PULX
STD
SUBD
300
Programming Model
A programming model for the HD68POI is shown in Figure
10. Accumulator A can be concatenated with accumulator B
and jointly referred to as accumulator D where A is the most
significant byte. Any operation which modifies the double
accumulator will also modify accumulator A and/or B. Other
registers are defmed as follows:
Program Counter
The program counter is a 16-bit register which always points
to the next instruction.
Immediate Addressing
The operand or "immediate byte(s)" is contained in the following byte(s) of the instruction where the number of bytes
matches the size of the register. These are two or three byte
instructions.
Stack Pointer
The stack pointer is a 16-bit register which contains the address of the next available location in a pushdown/pullup
(LIFO) queue. The stack resides in random access memory at a
location defmed by the programmer.
Direct Addressing
The least significant byte of the operand address is contained
in the second byte of the instruction and the most significant
byte is assumed to be $00. Direct addressing allows the user to
access $00 through $FF using two byte instructions and execution time is reduced by eliminating the additional memory access. In most applications, the 256-byte area is reserved for
frequently referenced data.
Index Register
The Index Register is a 16-bit register which can be used to
store data or provide an address for the indexed mode of
addressing.
Accumulators
The MCU contains two 8-bit accumulators, A and B, which
are used to store operands and results from the arithmetic logic
unit (ALU). They can also be concatenated and referred to as
the D (double) accumulator.
Extended Addressing
The second and third bytes of the instruction contain the absolute address of the operand. These are three byte instructions.
Table 9
Pointer Operations
Mnemonic
Immed
OP
Direct
Extend
Index
OP
OP
9C
AC 6
OP
Implied
OP
Boolean/
Arithmetic Operation
2 BC 6 3
CPX
DEX
09
DES
34
1 SP - 1 - SP
INX
08
X + 1 .... X
INS
31
SP + 1 ..... SP
LOX
CE
LOS
8E
STX
STS
8C
Indexed Addressing
The unsigned offset contained in the second byte of the instruction is added with carry to the Index Register and used to
reference memory without changing the Index Register. These
are two byte instructions.
DE 4
2 EE 5
2 AE 5
OF 4 2 EF 5
9F 4 2 AF 5
9E
2
2
2
2
X - M: M+ 1
X-1 ..... X
FE
BE
TXS
35
X H .... M. XL .... (M + 1)
SP H .... M, SP L -+ (M + 1)
X -1 ..... SP
TSX
30
SP + 1- X
Add
ABX
3A
B + X ..... X
Push Data
PSHX
3C
Pull Data
PULX
38
FF
BF
I N Z V
2 1 0
t t
t
t
t
t
t
t
t
t
t
t
t t
R
R
R
301
Mnemonic
Immed
OP -
Direct
# OP -
Add Acmltrs
ABA
AddBtoX
Add with Carry
ABX
ADCA
Add
ADCB
ADDA
Add Double
ADDB
ADDD
CB 2 2
C3 4 3
And
ANDA
84
2 2
DB 3
03 5
94 3
ANDB
C4
2 2
04 3
89
2 2
99
C9
2 2
8B
2 2
09 3
9B 3
ASL
ASLA
ASLB
ASLD
ASR
ASRA
ASRB
Bit Test
BITA
85
2 2
95
BITB
C5
2 2
05 3
Compare Acmltrs
CBA
Clear
CLR
CLRA
CLRB
Compare
1's Complement
CMPA
81
2 2
91
CMPB
C1
2 2
01
COM
COMA
Decimal Adj, A
COMB
DAA
Decrement
DEC
DECA
DECB
Exclusive OR
Increment
EORA
88
2 2
98
EORB
C8
2 2
08 3
INC
INCA
INCB
Load Acmltrs
LDAA
LDAB
C6 2
Load Double
LDD
CC 3
LSL
LSLA
LSLB
LSLD
LSR
LSRA
LSRB
LSRD
86
2 2
2
3
96
06 3
DC 4
Index
Extend
Implied
Boolean Expression
# OP - # OP - # OP - #
1B 2 1 A+B~A
3A 3 1 B+X ..... X
2 A9 4 2 B9 4 3
A+M+C ..... A
2 E9 4 2 F9 4 3
B+M+C ..... B
2 AB 4 2 BB 4 3
A+M ..... A
2 EB 4 2 FB 4 3
B+M ..... A
2 E3 6 2 F3 6 3
0+ M:M + 1 ..... 0
AM ..... A
2 A4 4 2 B4 4 3
2 E4 4 2 F4 4 3
BM ..... B
68 6 2 78 6 3
48 2 1
58 2 1
05 3 1
67 6 2 77 6 3
47 2 1
57 2 1
2 A5 4 2 B5 4 3
A'M
2 E5 4 2 F5 4 3
B'M
11 2 1 A-B
6F 6 2 7F 6 3
OO-+M
4F 2 1 OO-+A
5F 2 1 OO-+B
2 A1 4 2 B1 4 3
A-M
2 E1 4 2 F1 4 3
B -M
Jl ..... M
63 6 2 73 6 3
43 2 1 A"'" A
53 2 1 -e- ..... B
19 2 1 Adj binary sum to BCD
M -l ..... M
6A 6 2 7A 6 3
4A 2 1 A-1 ~A
5A 2 1 B -l ..... B
2 A8 4 2 B8 4 3
A()M ..... A
2 E8 4 2 F8 4 3
B()M ..... B
M+ l ..... M
6C 6 2 7C 6 3
4C 2 1 A+l ..... A
5C 2 1 B+ l ..... B
M ..... A
2 A6 4 2 B6 4 3
M ..... B
2 E6 4 2 F6 4 3
2 EC 5 2 FC 5 3
M:M + 1-+0
68 6 2 78 6 3
48 2 1
58 2 1
05 3 1
64 6 2 74 6 3
44 2 1
54 2 1
04 3 1
302
t t t t t
..
.
t~
~
~ ~ t
~ ~ ~
t t ~
~ ~ ~
t t ~
~ ~ R
~ ~ R
~ ~ ~
~ ~ ~
~ ~ ~
~ ~ ~
~ ~ ~
~ ~ ~
~ ~ ~
~ ~ R
~ ~ R
...
~ ... ~
t
~
~
~
~
~
~
~
~
~
R S R R
S R R
R
R S R R
~
t
~
~
~
~
~~
~
~
~ ~ ~
~ ~
~ R S
~ R S
~ R S
...
..
~ ~ ~
~ ~
~ ~
~ ~
~ R
~ ~ R
~ ~ ~
~
~
~
~
~
~
~
~
~
~ ~
~ R
~ R
~
~
~
~
~
~
R
~
R
~
R
~
~ ~
~ ~
~ ~
~ ~
~ ~
~ ~
~ ~
~ ~
R
(Continued)
Mnemonic
Multiply
MUL
2'5 Complement
(Negate)
NEG
Direct
Immed
OP
# OP
Extend
Index
# OP
60
# OP
Implied
# OP
3D 10 1
6 2
70
AXB-+D
OO-M-+M
NEGA
Boolean Expression
40
OO-A-+A
NEGB
50
OO-B-+B
No Operation
NOP
01
PC + 1 -+PC
Inclusive OR
ORAA
8A 2
9A 3
AA 4
BA 4
A+M-+A
ORAB
CA 2
DA 3
EA 4
FA 4
B +M-+B
Push Data
Pull Data
Rotate Left
PSHA
36
A -+Stack
PSHB
37
B -+Stack
PULA
32
Stack -+A
PULB
33
Stack -+B
49
59
ROL
69
6 2
79
ROLA
ROLB
Rotate Right
ROR
66
76
RORA
46
56
10
SBA
SBCA
82
SBCB
C2
02 3
92
A2 4
A-B-+A
B2
A-M-C-+A
B-M-C-+B
E2
F2
STAA
97
A7 4
B7
A-+M
STAB
07 3
E7
F7
B-+M
FD 5
STD
Subtract
RORB
Subtract Acmltr
Store Acmltrs
ED 5
AO 4
2 BO 4 3
A-M-+A
D-+M:M + 1
DO 3
EO
FO
B-M-+B
93
A3 6
B3
80
90
SUBS
CO
Subtract Double
SUBD
83
Transfer Acmltr
TAB
16
A-+B
TBA
17
B-+A
TSTA
40 2
A -00
TSTB
50 2
B -00
TST
60 6
The Condition Code Register notes are listed after Table 12.
303
70 6
0- M:M
M-OO
N Z V
t t ~
t t t
t t
t ~
DO 4
SUBA
Cond.Code Reg.
H
+ 1-+0
R
R
t t t
t t
~ ~
~ t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t R
t R
t R
t t t
t t t
t t t
t R
t R
t R R
t R R
t R R
Operations
Direct
Mnemonic
OP
Branch Always
BAA
Relative
Index
# OP
# OP
20
Extend
# OP
Implied
# OP
Branch Test
#
None
Branch Never
BRN
21
BCC
24
None
CeO
BCS
25
C=1
Branch If = Zero
BEQ
27
Z"1
Branch If
Zero
BGE
2C
N <'> VeO
Branch If
> Zero
BGT
2E
Z + (N <'> V)-O
Branch If Higher
BHI
22
C+Z=O
BHS
24
C=O
Branch If ~ Zero
BlE
2F
Z+ (N <'> V)-1
BlO
25
Co:1
BlS
23
2
2
C+Z"1
N(>V=1
< Zero
BLT
20 3
Branch If Minus
BMI
2B
BNE
26
BVC
28
VeO
BVS
29
Vc 1
Branch If Plus
BPl
2A 3
N =0
Branch To Subroutine
BSA
80 6
Jump
JMP
Jump To Subroutine
JSR
No Operation
NOP
01
RTI
3B 10 1
ATS
39
Software Interrupt
SWI
3F 12 1
WAI
3E
Branch If
N" 1
N=O
6E
90 5
7E
AD 6
BD 6
js.. '''';''
Figure 26
2
5
9
N Z V
"",,"';0"
1
1
1 0
Clear Carry
Mnemonic
OP
Figure 26
CLC
OC
O .... C
CLI
OE
0 .... 1
Clear Overflow
ClV
OA
0 .... V
1-C
Set Carry
SEC
00
SEI
OF
1 .... 1
Set Overflow
SEV
OB
TAP
06
1 .... V
A .... CCA
TPA
07
CCA .... A
Accumulator A - CCA
CCR - Accumulator A
--------
LEGEND
OP Operation Code (Hexadecimal)
- Number of MPU Cycles
MSp Contents of memory location pointed to by Stack Pointer
# Number of Program Bytes
+ Arithmetic Plus
- Arithmetic Minus
Boolean AND
X Arithmetic Multiply
+ Boolean Inclusive OA
<'> Boolean Exclusive OA
fin Complement of M
-+ Transfer Into
OBit = Zero
00 Byte = Zero
304
Boolean Operation
Implied
The Condition Code Register notes are listed after Table 12.
Operations
A
S
A
A
S
S
* * * * * *
Addressing Mode
~
:c
(II
ABA
ABX
ADC
ADD
ADDD
AND
ASl
ASlD
ASR
BCC
BCS
BEQ
BGE
BGT
BHI
BHS
BIT
BlE
BlO
BlS
BlT
BMI
BNE
BPl
BRA
BRN
BSR
BVC
BVS
CBA
ClC
CLI
ClR
ClV
CMP
COM
CPX
DAA
DEC
DES
DEX
EOR
INC
INS
...
(J
"0
(II
"0
"0
(II
c:
(II
>
.+:;
0.
I'CI
.!!:!
"0
.:
2
3
2
4
2
3
5
3
4
6
4
6
4
6
4
6
6
4
6
4
6
6
6
6
3
5
2
3
2
2
2
2
2
2
2
2
2
3
3
I'CI
:c
(II
"0
a::
INX
JMP
JSR
lOA
lDD
lDS
lOX
lSl
lSlD
lSR
lSRD
MUl
NEG
NOP
ORA
PSH
PSHX
PUl
PUlX
ROl
ROR
RTI
RTS
SBA
SBC
SEC
SEI
SEV
STA
STD
STS
STX
SUB
SUBD
SWI
TAB
TAP
TBA
TPA
TST
TSX
TXS
WAI
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
6
3
3
305
QI
"0
>
.+:;
"0
a::
.:
,3
4
4
4
6
4
3
3
3
2
4
3
4
4
4
3
5
5
5
5
6
(II
(II
5
5
5
6
5
5
5
4
6
4
6
4
5
5
(II
.!!:!
1:)
"0
1)
"
"$c:
(II
0.
2
3
2
3
10
2
2
3
4
4
5
2
2
10
5
2
2
2
2
12
2
2
2
2
2
3
3
9
I'CI
1)
Data Bus
Address Bus
IMMEDIATE
2
1
2
Op Code Address
Op Code Address + 1
1
1
Op Code
Operand Data
LDS
LDX
LDD
1
2
3
Op Code Address
Op Code Address + 1
Op Code Address + 2
1
1
1
Op Code
Operand Data (High Order Byte)
Operand Data (Low Order Byte)
CPX
SUBD
ADDD
1
2
3
4
Op Code Address
Op Code Address + 1
Op Code Address + 2
Address Bus F F F F
1
1
1
1
Op Code
Operand Data (High Order Byte)
Operand Data (Low Order Byte)
Low Byte of Restart Vector
1
2
3
Op Code Address
Op Code Address + 1
Address of Operand
1
1
1
Op Code
Address of Operand
Operand Data
STA
1
2
3
Op Code Address
Op Code Address + 1
Destination Address
1
1
0
Op Code
Destination Address
Data from Accumulator
LDS
LDX
LDD
1
2
3
4
Op Code Address
Op Code Address + 1
Address of Operand
Operand Address + 1
1
1
1
1
Op Code
Address of Operand
Operand Data (High Order Byte)
Operand Data (Low Order Byte)
STS
STX
1
2
3
4
Op Code Address
OP. Code Address + 1
Address of Operand
Address of Operand + 1
1
1
0
0
Op Code
Address of Operand
Register Data (High Order Byte)
Register Data (Low Order Byte)
CPX
SUBD
ADDD
1
2
3
4
5
Op Code Address
Op Code Address + 1
Operand Address
Operand Address + 1
Address Bus FFFF
1
1
1
1
1
Op Code
Address of Operand
Operand Data (High Order Byte)
Operand Data (Low Order Byte)
Low Byte of Restart Vector
JSR
1
2
3
4
5
Op Code Address
Op Code Address + 1
Subroutine Address
Stack Pointer
Stack Pointer + 1
1
1
1
0
0
Op Code
Irrelevant Data
First Subroutine Op Code
Return Address (Low Order Byte)
Return Address (High Order Byte)
ADC
ADD
AND
BIT
CMP
EOR
LOA
ORA
SBC
SUB
DIRECT
ADC
ADD
AND
BIT
CMP
EOR
LOA
ORA
SBC
SUB
STD
(Continued)
306
Address Bus
Data Bus
EXTENDED
JMP
1
2
3
ADC
ADD
AND
BIT
CMP
EOR
LDA
ORA
SBC
SUB
3
4
4
STA
1
2
1
2
3
4
LDS
LDX
LDD
STS
STX
STD
ASL
ASR
CLR
COM
DEC
INC
1
2
3
4
5
1
2
3
4
5
LSR
NEG
ROL
ROR
TST*
1
2
3
4
5
6
CPX
SUBD
ADDD
JSR
1
2
3
4
5
6
1
2
3
4
5
6
Op Code Address
Op Code Address + 1
Op Code Address + 2
1
1
1
Op Code
Jump Address (High Order Byte)
Jump Address (Low Order Byte)
Op Code Address
Op Code Address + 1
Op Code Address + 2
Address of Operand
1
1
1
1
Op Code
Address of Operand
Address of Operand (Low Order Byte)
Operand Data
Op Code Address
Op Code Address + 1
Op Code Address + 2
Operand Destination Address
1
1
1
0
Op Code
Destination Address (High Order Byte)
Destination Address (Low Order Byte)
Data from Accumulator
Op Code Address
Op Code Address + 1
Op Code Address + 2
Address of Operand
Address of Operand + 1
1
1
1
1
1
Op Code
Address of Operand
Address of Operand
Operand Data (High
Operand Data (Low
Op Code Address
Op Code Address + 1
Op Code Address + 2
Address of Operand
Address of Operand + 1
1
1
1
0
0
Op Code
Address of Operand
Address of Operand
Operand Data (High
Operand Data (Low
Op Code Address
Op Code Address + 1
Op Code Address + 2
Address of Operand
Address Bus F F F F
Address of Operand
1
1
1
1
1
0
Op Code
Address of Operand (High Order Byte)
Address of Operand (Low Order Byte)
Current Operand Data
Low Byte of Restart Vector
New Operand Data
Op Code Address
Op Code Address + 1
Op Code Address + 2
Operand Address
Operand Address + 1
Address Bus FFFF
1
1
1
1
1
1
Op Code
Operand Address (High Order Byte)
Operand Address (Low Order Byte)
Operand Data (High Order Byte)
Operand Data (Low Order Byte)
Low Byte of Restart Vector
Op Code Address
Op Code Address + 1
Op Code Address + 2
Subroutine Starting Address
Stack Pointer
Stack Pointer - 1
1
1
1
1
0
0
Op Code
Address of Subroutine (High Order Byte)
Address of Subroutine (Low Order Byte)
Op Code of Next Instruction
Return Address (Low Order Byte)
Return Address (High Order Byte)
In the TST instruction, the line condition of the sixth cycle does the following: R/W = "High", AB = FFFF, DB = Low Byte of Reset Vector.
(Continued)
307
Data Bus
Address Bus
INDEXED
JMP
1
2
3
ADC
ADD
AND
BIT
CMP
EOR
LDA
ORA
SBC
SUB
3
4
4
STA
1
2
1
2
3
4
LDS
LDX
LDD
1
2
3
4
5
STS
STX
STD
1
2
3
4
5
ASL
ASR
CLR
COM
DEC
INC
LSR
NEG
ROL
ROR
TST *
1
2
3
4
5
6
CPX
SUBD
ADDD
JSR
1
2
3
4
5
6
1
2
3
4
5
6
Op Code Address
Op Code Address + 1
Address Bus FFFF
1
1
1
Op Code
Offset
Low Byte of Restart Vector
Op Code Address
Op Code Address + 1
Address Bus FFFF
Index Register Plus Offset
1
1
1
1
Op Code
Offset
Low Byte of Restart Vector
Operand Data
Op Code Address
Op Code Address + 1
Address Bus F F F F
Index Register Plus Offset
1
1
1
Op Code
Offset
Low Byte of Restart Vector
Operand Data
Op Code Address
Op Code Address + 1
Address Bus F F F F
Index Register Plus Offset
Index Register Plus Offset + 1
1
1
1
1
1
Op Code
Offset
Low Byte of Restart Vector
Operand Data (High Order Byte)
Operand Data (Low Order Byte)
1
1
1
Op Code
Offset
Low Byte of Restart Vector
Operand Data (High Order Byte)
Operand Data (Low Order Byte)
0
0
Op Code Address
Op Code Address + 1
Address Bus FFFF
Index Register Plus Offset
Address Bus F F F F
Index Register Plus Offset
Op Code
Offset
Low Byte of Restart Vector
Current Operand Data
Low Byte of Restart Vector
New Operand Data
Op Code Address
Op Code Address + 1
Address Bus F F F F
Index Register + Offset
Index Register + Offset + 1
Address Bus F F F F
1
1
1
1
1
1
Op Code
Offset
Low Byte of Restart Vector
Operand Data (High Order Byte)
Operand Data (Low Order Byte)
Low Byte of Restart Vector
Op Code Address
Op Code Address + 1
Address Bus FFFF
Index Register + Offset
Stack Pointer
Stack Pointer - 1
1
1
1
1
Op Code
Offset
Low Byte of Restart Vector
First Subroutine Op Code
Return Address (Low Order Byte)
Return Address (High Order Byte)
1
1
1
1
1
0
0
* In the TST instruction, the line condition of the sixth cycle does the following: R/IN = "High", AS = FFFF, DB = Low Byte of Reset Vector.
(Continued)
308
Data Bus
Address Bus
IMPLIED
2
1
2
Op Code Address
Op Code Address + 1
1
1
Op Code
Op Code of Next Instruction
ABX
1
2
Op Code Address
Op Code Address + 1
Address Bus F F F F
1
1
1
Op Code
Irrelevant Data
low Byte of Restart Vector
ASlD
lSRD
Op Code Address
Op Code Address + 1
Address Bus FFFF
1
1
1
Op Code
Irrelevant Data
low Byte of Restart Vector
DES
INS
Op Code Address
Op Code Address + 1
Previous Register Contents
1
1
1
Op Code
Op Code of Next Instruction
Irrelevant Data
INX
DEX
Op Code Address
Op Code Address + 1
Address Bus F F F F
1
1
1
Op Code
Op Code of Next Instruction
low Byte of Restart Vector
PSHA
PSHB
Op Code Address
Op Code Address + 1
Stack Pointer
1
1
Op Code
Op Code of Next Instruction
Accumulator Data
TSX
Op Code Address
Op Code Address + 1
Stack Pointer
1
1
1
Op Code
Op Code of Next Instruction
Irrelevant Data
TXS
Op Code Address
Op Code Address + 1
Address Bus F F F F
1
1
1
Op Code
Op Code of Next Instruction
low Byte of Restart Vector
PULA
PUlB
Op Code Address
Op Code Address + 1
Stack Pointer
Stack Pointer + 1
1
1
1
1
Op Code
Op Code of Next Instruction
Irrelevant Data
Operand Data from Stack
Op Code Address
Op Code Address + 1
Stack Pointer
Stack Pointer + 1
1
1
0
0
Op Code
Irrelevant Data
Index Register (low Order Byte)
Index Register (High Order Byte)
4
5
1
2
3
4
Op Code Address
Op Code Address + 1
Stack Pointer
Stack Pointer + 1
Stack Pointer +2
Op Code Address
Op Code Add ress + 1
Stack Pointer
Stack Pointer + 1
1
1
1
1
1
1
1
1
1
ABA
ASl
ASR
CBA
ClC
Cli
ClR
ClV
COM
DAA
DEC
INC
lSR
NEG
NOP
ROl
ROR
SBA
SEC
SEI
SEV
TAB
TAP
TBA
TPA
TST
3
1
2
3
1
2
3
1
2
3
1
2
3
1
2
3
1
2
3
1
2
3
4
PSHX
1
2
3
4
PUlX
1
2
RTS
Op Code
Irrelevant Data
Irrelevant Data
Index Register (High Order Byte)
Index Register (low Order Byte)
Op Code
Irrelevant Data
Irrelevant Data
Address of Next Instruction
(H igh Order Byte)
Address of Next Instruction
(low Order Byte)
(Continued)
309
MUL
Cycles
10
Cycle
Address Bus
R/W
Line
1
2
3
4
Op Code Address
Op Code Address + 1
Stack Pointer
Stack Pointer - 1
1
1
0
0
5
6
7
8
9
Stack
Stack
Stack
Stack
Stack
0
0
0
0
0
Op Code
Op Code of Next Instruction
Return Address (Low Order Byte)
Return Address
(High Order Byte)
Index Register (Low Order Byte)
Index Register (High Order Byte)
Contents of Accumulator A
Contents of Accumulator B
Contents of Condo Code Register
1
2
3
4
5
6
7
10
Op Code Address
Op Code Address + 1
Address Bus FFFF
Address Bus F F F F
Address Bus F F F F
Address Bus FFFF
Address Bus FFFF
Address Bus FFFF
Address Bus FFFF
Address Bus FFFF
1
1
1
1
1
1
1
1
1
1
Op Code
Irrelevant
Low Byte
Low Byte
Low Byte
Low Byte
Low Byte
Low Byte
Low Byte
Low Byte
1
2
3
4
Op Code Address
Op Code Address + 1
Stack Pointer
Stack Pointer + 1
1
1
1
1
Stack Pointer + 2
Stack Pointer + 3
Stack Pointer + 4
Stack Pointer + 5
Stack Pointer + 6
10
Stack Pointer + 7
Op Code
Irrelevant Data
Irrelevant Data
Contents of Condo Code Reg.
from Stack
Contents of Accumulator B
from Stack
Contents of Accumulator A
from Stack
Index Register from Stack
(High Order Byte)
Index Register from Stack
(Low Order Byte)
Next Instruction Address from
Stack (High Order Byte)
Next Instruction Address from
Stack (Low Order Byte)
1
2
3
4
Op Code Address
Op Code Address + 1
Stack Pointer
Stack Pointer - 1
1
1
0
0
10
11
Stack Pointer Stack Pointer Stack Pointer Stack Pointer Stack Pointer Stack Pointer Vector Address
2
3
4
5
6
7
FFFA (Hex)
0
0
0
0
0
1
1
12
8
9
RTI
SWI
10
12
6
7
8
9
Pointer
Pointer
Pointer
Pointer
Pointer
2
3
4
5
6
Data Bus
Data
of Restart
of Restart
of Restart
of Restart
of Restart
of Restart
of Restart
of Restart
Vector
Vector
Vector
Vector
Vector
Vector
Vector
Vector
Op Code
Irrelevant Data
Return Address (Low Order Byte)
Return Address
(High Order Byte)
Index Register (Low Order Byte)
Index Register (High Order Byte)
Contents of Accumulator A
Contents of Accumulator B
Contents of Condo Code Register
Irrelevant Data
Address of Subroutine
(High Order Byte)
Address of Subroutine
(Low Order Byte)
** While the MCU is in the "Wait" state, its bus state will appear as a series of the MCU reads of an address which is seven locations
less than the original contents of the Stack Pointet'o Contrary to the HD6800, none of the ports are driven to the high impedance
state by a WAI instruction.
(Continued)
310
Data Bus
Address Bus
RELATIVE
1
2
1
2
3
4
5
6
Op Code Address
Op Code Address + 1
Address Bus FFFF
1
1
1
Op Code
Branch Offset
Low Byte of Restart Vector
Op Code Address
Op Code Address + 1
Address Bus FFFF
Subroutine Starting Address
Stack Pointer
Stack Pointer - 1
1
1
1
1
Op Code
Branch Offset
Low Byte of Restart Vector
Op Code of Next Instruction
Retu rn Address (Low Order Byte)
Return Address (High Order Byte)
0
0
When the op codes (4E, SE) are used to execute, the MPU
continues to increase the program counter and it will not stop
until the Reset signal enters. These op codes are used to test the
LSI.
ACC
B
IND
EXT
0011
0100
0101
0110
0111
OP
CODE
~
LO
0000
0001
0010
0011
0100
0000
0001 0010
------
SBA
BRA
TSX
CBA
BRN
INS
/
/
NOP
------ /
------
LSRD (+1)
BCC
------6
I DIR
liND
ACCB or X
I EXT
IMM
SUBD (+2)
LSR
TXS
BIT
PSHA
ROR
LOA
0111
TPA
TBA
BEQ
PSHB
1000
INX (+1)
1001
DEX (+1)
DAA
BVS
RTS (+2)
1010
CLV
BPL
ABX
BMI
RTI (+7)
1101
SEC
1110
CLI
1111
SEI
BYTE/CYCLE
1/2
//
/
1/2
BLT
MUL (+7)
BGT
WAI (+6)
BLE
SWI (+9)
2/3
1/3
STA
STA
ASL
EOR
AOC
DEC
ORA
TST
**---
JMP (-3)
CLR
112
ROL
INC
ADDD (+2)
BCS
~1
BNE
ASR
TAB
ABA
AND
TAP
SEV
ASLD (+1)
CLC
SBC
CMP
0110
1011
I EXT
SUB
0101
1100
liND
11001110111110J1111
I DIR
NEG
COM
DES
ACCA or SP
IMM
1/2
3/6
CPX (+2)
LDD (+1)
(+1>1
STD (+1)
LOX (+1)
)'1
STX (+1)
BSR
(+4)
JSR (+2)
LOS (+1)
STS (+1)
* (+1
.: (+1)
2/6
ADD
2/2
2/2
1 2/3
1 2/4
1 3/4
Direct
$90" JSR
K
RTN
INDXD
~
Stack
--SP-2 , . . . - - - - - - - . . . . ,
$AD "JSR
K" Offset
RTN
SP -1
~
EXTND
$BD =JSR
SH .. Subr. Addr.
SL .. Subr. Addr.
RTN
Main Program
PC
$80 = BSR
K" Offset
RTN
$39'" RTS
I
~NI
$3F" SWI
I
r=>
r=>
r=>
--SP-2
SP-1
~NI
$3E "WAI
I
t--------i
RTNH
SP '--_ _R_T_N..::L'--_-'
SP
Stack
SP
SP+ 1
--SP+2
Stack
--+SP-7
Stack
r=>
SP -6
Condition Code
SP - 5
SP -4
Acmltr A
SP -3
SP - 2
Acmltr B
SP-1
RTNH
SP
RTNL
Stack
ec
$3B" RTI
I
SP
SP+ 1
Condition Code
SP+2
SP+3
Acmltr A
SP+4
SP+5
SP+6
--+SP+7
JMP, Jump
Main Program
~
INDXD
$6E
PC
= JMP
Acmltr B
RTNH
RTNL
Main Program
$7E =JMP
K = Offset
Exteooed
KH .. Next Address
K L " Next Address
312
HD68P05V05,
HD68P05V07
Me U (Microcomputer Unit)
The HD68POSV is the 8-bit Microcomputer Unit (MCV)
which contains a CPU, on-chip clock, RAM, I/O and timer. It is
designed for the user who needs an economical microcomputer
with the proven capabilities of the HD6800-based instruction
set. Setting EPROM on the package, this MCU has the equivalent function as the HD680SU and HD680SV. HD68POSVOS
uses HN462S32 as EPROM. HD68POSV07 uses HN462732 as
EPROM. The following are some of the hardware and software
highlights of the MCU.
HARDWARE FEATURES
8-Bit Architecture
96 Bytes of RAM
Memory Mapped I/O
Internal 8-Bit Timer with 7-Bit Prescaler
Vectored Interrupts - External, Timer and Software
24 I/O Ports + 8 Input Port
(8 Lines LED Compatible; 7 Voltage Comparator Inputs)
On-Chip Clock Circuit
Master Reset
Complete Development System Support by Evaluation Kit
5 Vdc Single Supply
SOFTWARE FEATURES
Similar to HD6800
Byte Efficient Instruction Set
Easy to Program
True Bit Manipulation
Bit Test and Branch Instructions
Versatile Interrupt Handing
Powerful Indexed Addressing for Tables
Full Set of Conditional Branches
Memory Usable as Registers/Flags
Single Instruction Memory Examine/Change
10 Powerful Addressing Modes
-PRELIMINARY -
HD68P05V05
HD68P05V07
OADR,
() ADRs
() ADR.
OADR,
() ADR,
o ADR,
() ADR.
c_
Cs
A.
As
A_
A,
A,
A,
Ao
B,
B.
Bs
B_
AD~.(l
ADR,on
ADRIIO
B,
HD68P05V07
Vee
XTAL
EXTAL
NUM
TIMER
Co
Vee
OADR. ,
o ADR,
o ADR6
OADRs
o ADR.
o ADA,
o ADA,
o ADA,
o ADR.
00
00.
00 ,
o ~ss
D.
313
A,
A.
As
A.
A,
~
A,
An
B,
B,
Bs
B.
B,
Bo
Do
D,
D,
D,
RES
NUM INT
TIMER
Port B
I/O Lines
Accumulator
Port A
I/O Lines
Port A
Reg
Data
Dir
Reg
Data
Input Lines
0.0.
Condition
Code
Register
CPU Control
cc
Data
Dir
Reg
Program
Counter
"Low" PCl
Port B
Reg
CPU
Port C
I/O Lines
Stack
Pointer
0.
0,
Index
Register
SP
Program
Counter
"High" PCH
20.
ALU
Data
Dir
Reg
Port C
Reg
Data
Input r-----~----------------;_--~--------~--------.
Port 0
Input Lines
0,
0,
Address
Output Lines
ADR.
ADR,
ADR2
ADR.
AD!'\.
ADR.
ADR,
ADR,
Port 0
Reg
Address
Output~--~----------------~
Buffer
Address
Output Lines
ADR.
ADR,
ADR
ADR"
ADRu
Address
Output
Buffer
CE
LJ
314
-------------------------------------------HD68P05V05, HD68P05V07
ABSOLUTE MAXIMUM RATINGS
Item
-0.3-+7.0
-0.3- +12.0
Operating Temperature
Topr
o -+70
V
c
Storage Temperature
T stg
- 55 - +150
With respect to
(NOTE)
V in
Unit
-0.3- +7.0
Vee *
Value
Symbol
Supply Voltage
Permanent LSI damage may occur if maximum ratings are exceeded. Normal operation should be under
recommended operating conditions. If these conditions are exceeded, it could affect reliability of LSI.
ELECTRICAL CHARACTERISTICS
DC CHARACTERISTICS (Vcc=5.25V 0.5V, VSS=GND, Ta=0-+70C, unless otherwise noted.)
Item
Symbol
Test Condition
RES
Input "High" Voltage
INT
V ,H
Unit
Vee
0.6
-0.3
0.8
400
700
mW
-0.3
Po
LVR
I'L
V in =0.4 V-Vee
4.75
-50
-1200
Unit
-20
-0.3
-0.3
V ,L
Vee
0.8
0.8
RES
XTAL (Crystal Mode)
Vee
INT
Power Dissipation
max
2.0
All Other
typ
3.0
All Other
min
4.0
20
p,A
50
p,A
p,A
typ
max
Clock Frequency
fel
0.4
4.0
MHz
Cycle Time
tcyc
1.0
10
p,s
t'WL
teye +
250
ns
tRWL
teye +
250
ns
t TWL
t e2'G +
50
ns
tose
CL =22pF20%,
Rs=60n max.
100
ms
tRHL
100
ms
Vin=OV
25
35
pF
10
pF
Item
Input Capacitance
l
I
EXTAL
All Other
Symbol
Cin
Test Condition
315
Symbol
Port B
VOH
Port C
Port A and C
Output "Low" Voltage
Input "High" Voltage
Input "Low" Voltage
Port B
Port A, B, C,
and 0*
VOL
min
typ
max
= -10~A
IOH = -100~A
IOH = -200~A
IOH = -1 mA
IOH = -100~A
IOL = 1.6 mA
IOL = 3.2 mA
IOL = 10mA
3.S
2.4
2.4
1.S
2.4
0.4
0.4
1.0
Vee
Vin
= 0.8V
= 2V
-300
Vin
= 0.4V"'" Vee
VIH
2.0
VIL
-0.3
Vin
Port A
Test Condition
IOH
IlL
Port B, C,
and 0
-SOO
20
Unit
0.8
~A
~A
20
~A
Port 0**
(Do"'" 0 6 )
V IH
VTH+0.2
Port 0**
(Do"'" 0 6 )
VIL
VTH-0.2
Threshold Voltage
Port 0**(0 7 )
VTH
0. 8xV ee
..
Vee
2.4k!l
Ij=3.2mA
Ii = 1.6mA
Test Point
Test Point
Vi
40pF
(NOTE)
30 pF
12 k!l
24 k!l
1. Load capacitance includes the floating capacitance of the probe and the jig etc.
2. All diodes are 152074 @or equivalent.
SIGNAL DESCRIPTION
The input and output signals for the MCV shown in PIN
ARRANGEMENT are described in the following paragraphs.
INT
TIMER
RES
NUM
316
-------------------------------------------HD68P05V06, HD68P06V07
REGISTERS
The MCU has five registers available to the programmer.
They are shown in Figure 2 and are explained in the following
paragraphs.
Accumulator
L -_ _ _ _ _ _.....llndex Register
"
L-_ _ _ _ _ _
pc_ _ _ _ _
"
5 4
LI0....lI_o.....I_0..J..I_o.....l_o,.LI_,..J..I_,..J..I_ _ _
sP_---'1
~
l
l
N.
Stack Pomt
-~~
Carry/Borrow
Zero
--~~- Negat,ve
~~~-
Interrupt Mask
Accumulator (A)
The accumulator is a general purpose 8-bit register used to
hold operands and results of arithmetic calculations or data
manipulations.
Index Register (X)
The index register is an 8-bit register used for the indexed
addressing mode. It contains an 8-hit address that may be added
to an offset value to create an effective address. The index
register can also be used for limited calculations and data
manipulations when using read/modify/write instructions. When
not required by a code sequence being executed, the index
register can be used as a temporary storage area.
Program Counter (PC)
The program counter is a 13-bit register that wntains the
address of the next instruction to be executed.
TIMER
The MeU timer circuitry is shown in Figure 3. The is-bit
counter is loaded under program control and counts down toward zero as soon as the clock input is applied. When the timer
reaches I.ero the timer interrupt request hit (bit 7) in the timer
control register is set. The MCli re~ponds to this interrupt hy
saving the present Mel) state in the stack. fetching the timer
interrupt vector from locations $OFF8 and $OFF9 and executing the interrupt routine. The timer interrupt can be masked by
setting the timer interrupt mask hit (bit 6) in the time control
Prescaler
} Address Bits
Clock Input
8-bit Counter
Figure 3
317
HD88P05V05, HD88P05V07-----------------------------------------register. The interrupt bit (I bit) in the condition code register
will also prevent a timer interrupt from being processed.
The clock input to the timer can be from an external source
applied to the TIMER input pin or it can be the internal tP2
signal. Note that when the tP2 signal is used as the source it can
be gated by an input applied to the TIMER input pin allowing
the user to easily perform pulse-width measurements. A
prescaler option can be applied to the clock input that extends
the timing interval up to a maximum of 128 counts before being
applied to the counter. The timer continues to count past zero
and its present count can be monitored at any time by monitoring the timer data register. This allows a program to determine
the length of time since a timer interrupt has occured and not
disturb the counting process.
The timer data register is 8-bit read/write register with address $008 on memory-map. This timer data register and the
prescaler are initialize with all logical ones at reset time.
The timer interrupt request bit (bit 7 of timer control register) is set to one by hardware when timer count reaches zero,
and is cleared by program or by hardware reset. The bit 6 of
timer control register is writable by program. Both of those bits
can be read by MPU.
The bit 5 and bit 4 of the timer control register is a clock
input source. The combinations are shown in Table 1. The bit 3
is not used. The bit 2, bit 1 and bit 0 are used to select a dividing ratio of the prescaler. The options of the dividing ratio are
shown in Table 2. An internal clock is selected as a clock input
source and the dividing ratio of a prescaler is set at "Bypass
Prescaler" at reset time.
RES Pin
---------1"
~:::~al _ _ _ _ _ _ _ _ _---1
Part of
HD68P05V
MCU
INTERNAL OSCILLATOR
tP2
(Internal Clock)
TIMER Input Pin
6 EXTAl
Timer Control
Register (TCR)
:a~Z
c:::J
5 XTAl
HD68P05V
MCU
b,
0
0
0
0
b1
bo
0
0
Bypass Prescaler
Prescaler + 2
Prescaler .;. 4
Prescaler + 8
1
1
0
0
Prescaler + 16
1
1
1
1
Prescaler + 32
Prescaler + 64
Prescaler .;. 128
6 EXTAl
External
Clock
5 XTAl
H068P05V
MCU
Input
RESETS
External Clock
Figure 6
318
Internal Oscillator
-------------------------------------------HD68P05V05, HD68P05V07
the program counter (PCH, PCL) contents to be pushed onto
the stack. This interrupt bit (I) in the condition code register is
set, the address of the interrupt routine is obtained from the appropriate interrupt vector address, and the interrupt routine is
executed. The interrupt service routines normally end with a
return from interrupt (RTI) instruction which allows the MCV
to resume processing of the program prior to the interrupt.
Table 3 provides a listing of the interrupts, their priority, and
the vector address that contain the starting address of the
appropriate interrupt routine.
A flowchart of the interrupt processing sequence is given
in Fig. 9.
XTAl~~EXTAl
5
~~
Pull
INTERRUPTS
11
Condition
Code Register
n+1
n-3
Accumu lator
n+2
n-2
Index Register
n+3
n+4
n-1
'1
PCH*
PCl*
n+5
Push
* For subroutine calls, only PCH and PCl are stacked.
1-1
7F -sP
O-OOR's
319
Interrupt
Priority
RES
SWI
INT
TIMER
2
3
4
Vector Address
$OFFE and $OFFF
$OFFC and $OFFD
$OFFA and $OFFB
$OFF8 and $OFF9
HD68P05V05, HD68P05V07-----------------------------------------
INPUT/OUTPUT
Data
Direction
Register
Bit
Output
Data Bit
Output
State
Input to
MCU
0
1
0
1
3-State
0
1
Pin
1
1
0
Ao
Port A
Port B
A,
B,
+V
Port B
Port C
10mA max
CMOS Inverter
C,
B,
INPUT
BIT MANIPULATION
The MCU has the ability to set or clear any single random
access memory or input/output bit (except the data direction
registers) with a single instruction (BSET, BCLR). Any bit in
the page zero read only memory can be tested, using the BRSET
and BRCLR instructions, and the program branches as a result
of its state. This capability to work with any bit in RAM, ROM
or I/O allows the user to have individual flags in RAM or to
handle single I/O bits as control lines. The example in Figure 13
illustrates the usefulness of the bit manipulation and test
instructions. Assume that bit 0 of port A is connected to a zero
crossing detector circuit and that bit 1 of port A is connected to
the trigger of a TRIAC which power the controlled hardware.
This program, which uses only seven ROM locations, provides turn-on of the TRIAC within 14 microseconds of the zero
crossing. The timer could also be incorporated to provide turnon at some later time which would permit pulse-width modulation of the controlled power.
320
--------------------------------------------HD68P05V05, HD68P05V07
$003 Read
Internal Bus
(BitO - Bit6)
$003 Read
Internal Bus
(Bit 7)
(a) The logic configuration of Port 0
Port
C
r----...._0,
Referance Level
0,
Port
Analog Input 6
0'
0
0,
0,
Port
I---"----Analog Input 6
Do
1 - - - - Analog Input 0
Analog Input 0
0,
VTH (= 3.5V)
0,
Port
3 Levels Input 6
Do
Input
Voltage
($003)
($007)
OV-O.8V
2.0V - 3.3V
1
1
3.7V -Vee
3 Levels Input 0
321
HD88P06V06, HD88P06V07-----------------------------------------
SELF 1
The MCU has ten addressing modes available for use by the
programmer. They are explained and illustrated briefly in the
following paragraphs.
Immediate
Refer to Figure 14. The immediate addressing mode accesses
constants which do not change during program execution. Such
instructions are two bytes long. The effective address (EA) is
the PC and the operand is fetched from the byte following the
opcode.
Direct
Refer to Figure 15. In direct addressing, the address of the
operand is contained in the second byte of the instruction.
Direct addressing allows the user to directly address the lowest
256 bytes in memory. All RAM space, I/O registers and 128
bytes of ROM are located in page zero to take advantage of this
efficient memory addressing mode.
Extended
Refer to Figure 16. Extended addressing is used to reference
any location in memory space. The EA is the contents of the
two bytes following the opcode. Extended addressing instructions are three bytes long.
Relative
Refer to Figure 17. The relative addressing mode applies only
to the branch instructions. In this mode the contents of the
byte following the opcode is added to the program counter
when the branch is taken. EA={pC}+2+Rel. ReI is the contents
of the location following the instruction opcode with bit 7
being the sign bit. If the branch is not taken Rel=O, when a
branch takes place, the program goes to somewhere within the
range of +129 bytes to -127 of the present instruction. These
instructions are two bytes long.
Indexed (No Offset)
Refer to Figure 18. This mode of addressing accesses the
lowest 256 bytes of memory. These instructions are one byte
long and'their EA is the contents of the index register.
indexed (8-bit Offset;
Refer to Figure 19. The EA is calculated by adding the
contents of the byte following the opcode to the contents of
the index register. In this mode, 511 low memory locations are
accessable. These instructions occupy two bytes.
Indexed (16-bit Offset)
Refer to Figure 20. This addressing mode calculates the EA
by adding the contents of the two bytes following the opcode
to the index register. Thus, the entire memory space may be
accessed. Instructions which use this addressing mode are three
bytes long.
Bit Set/Clear
322
------------------------------------------HD68P05V05, HD68P05V07
EA
Memory
I
I
Stack Point
A6
Prog Count
Fa
05CO
t-------t
CC
,
,,
I
I
I
I
I
I
I
I
CAT
FCB
32
LOA
CAT
0048
Adder
""
ol
20
0048
,
PROG
lEA
Memory
A
I
0520
86
052E
48
Stack Point
I
052F
CC
I
I
I
I
I
Prog Count
20
Index Reg
'
'
:
,
Figure 15 Direct Addressing Example
323
HD68P05V05, HD68P05V07-------------------------------------------
Memory
i
I
I
I
PROG
LOA
040A
06
040B
E5
64
40
Index Reg
Stack Point
FCB
~oo~J
CAT
Prog Count
CAT
0000
040C
40
06E5
CC
EA
Memory
04C1
:
I
I
Index Reg
Stack Point
PROG
BEQ
PROG2
04A7
27
04A8
18
0000
324
------------------------------------------HD68P06V06, HD68P06V07
EA
OOB8
Memory
TABL
4C
4C
49
Index Reg
B8
PROG
LOA
Stack Point
~F4~
Prog Count
05F5
CC
.~
008C
/'
Adder
TABL
lEA
Memory
I
FCB
#BF
0089
BF
FCB
#86
OOSA
86
FCB
#OB
008B
DB
FCB
#CF
008C
CF
J
I
I
I
'"
A
f
CF
Index Reg
03
Stack Point
PROG
LOA
TABL. X 0758
E6
075C
89
I
I
Prog Count
I,
325
075E
CC
HD88P06V06, HD88P06V07-----------------------------------------
Me ory'
i
I
PROG
lOA
TABl. X 0692
0693
DB
I'ndex Reg
02
~6
Stack Point
07
0694
_ _ _--J
7E
Prog Count
0695
I
TABl
CC
FCB
#BF
077E
FCB
#86
077F
BF
86
FCB
#OB
0780
DB
FCB
#CF
0781
CF
Memory
PORTB EQU
0001
BF
A
0000
Index Reg
058F
0590
10
Stack POint
t-------1
01
Prog Count
0591
I
CC
t@
I
Figure 21
326
------------------------------------------HD68P06V06, HD68P06V07
PORT C
EQU
FO
0002
Index Reg
0000
Stack Point
0574
0575
05
1-------4
02
0576
r----:1;;D;--;.~----,
Prog Count
0000
0594
CC
C
~
Figure 22 Bit Test and Branch Addressing Example
Memory
~
I
PROG
TAX
E5
Index Reg
E5
O~A8
Prog Count
0588
cc
327
Mnemonic
Op
Op
#
#
Code Bytes Cycles Code
Op
#
#
Bytes Cycles Code
Op
#
#
Bytes Cycles Code
Indexed
(l6Bit Offset)
Op
#
#
Bytes Cycles Code
Bytes Cycles
LOA
A6
B6
C6
F6
E6
06
LOX
AE
BE
CE
FE
EE
DE
Store A in Memory
STA
B7
C7
F7
E7
07
Store X in Memory
STX
BF
CF
FF
EF
OF
Add Memory'to A
ADD
AB
BB
CB
FB
EB
DB
AOC
A9
B9
C9
F9
E9
09
FO
EO
DO
6
6
BO
CO
B2
C2
F2
E2
02
B4
C4
F4
E4
04
AA
BA
CA
FA
EA
OA
EOR
A8
B8
C8
F8
E8
08
CMP
A1
B1
C1
F1
E1
01
CPX
A3
B3
C3
F3
E3
03
BIT
A5
B5
C5
F5
E5
05
Jump Unconditional
JMP
BC
CC
FC
EC
DC
Jump to Subroutine
JSR
BO
CD
FO
ED
DO
AO
SBC
A2
AND
A4
ORA
Exclusive OR Memory
with A
Arithmetic Compare A
with Memory
Arithmetic Compare X
with Memory
Bit Test Memory with A
(Logical Compare)
Subtract Memory
Op
#
#
Bytes Cycles Code
Indexed
(8Bit Offset)
Indexed
(No Offset)
Extended
Direct
Immediate
SUB
Table 5
Read/ModifylWrite Instructions
Addressing Modes
Function
Implied (A)
Mnemonic
Op
Code
Implied (X)
Op
#
#
Bytes Cycles Code
Indexed
(No Offset)
Direct
Op
#
#
Bytes Cycles Code
Op
#
#
Bytes Cycles Code
Indexed
(8-Bit Offset)
Op
#
#
Bytes Cycles Code
Bytes Cycles
Increment
INC
4C
5C
3C
7C
6C
Decrement
DEC
4A
5A
3A
7A
6A
Clear
eLR
4F
5F
3F
7F
6F
Complement
COM
43
53
33
73
63
Negate
(2's Complement)
NEG
40
50
30
70
60
ROL
49
59
39
79
69
ROR
46
56
36
76
66
LSL
48
58
38
78
68
7
7
LSR
44
54
34
74
64
ASR
47
57
37
77
67
ASL
48
58
38
78
68
TST
40
50
3D
70
60
328
-------------------------------------------HD68P05V05, HD68P06V07
Table 6 Branch Instructions
Relative Addressing Mode
Mnemonic
Function
Op
Code
Bytes
Cycles
Branch Always
BRA
20
Branch Never
BRN
21
Branch IF Higher
BHI
22
BlS
23
BCC
24
(BHS)
24
BCS
25
(Branch IF lower)
(BlO)
25
BNE
26
Branch I F Equal
BEQ
27
BHCC
28
BHCS
29
Branch I F Plus
BPl
2A
Branch IF Minus
BMI
2B
BMC
2C
BMS
20
Bil
2E
BIH
2F
Branch to Subroutine
BSR
AO
Mnemonic
Bit Set/Clear
Op
Code
Bytes
Cycles
Op
Code
Bytes
Cycles
2 n
10
01+2 n
10
Set Bit n
10+2 n
Clear bit n
11+2 n
Mnemonic
Op
Code
Bytes
Cycles
Transfer A to X
TAX
97
Transfer X to A
TXA
9F
SEC
99
ClC
98
SEI
9B
CLI
9A
Software Interrupt
SWI
83
11
RTS
81
RTI
80
RSP
9C
No-Operation
NOP
90
329
Addressi n9 Modes
Mnemonic
Implied
Immediate
Direct
Extended
Relative
Indexed
Indexed Indexed
(No
(8 Bits) (16 Bits)
Offset)
x
x
x
ADC
ADD
AND
ASl
ASR
Bit
Set/
Clear
Bit
Test &
Branch
BCS
BEQ
BHCC
BHCS
BHI
BHS
BIH
Bil
x
x
BIT
BlO
BlS
BMC
BMI
BMS
BNE
BPl
BRA
BRN
BRClA
BRSET
x
x
BSET
x
BSR
x
ClC
CLI
ClR
COM
x
x
CMP
x
DEC
x
x
EOR
x
x
CPX
x
x
JMP
JSR
INC
lOA
lOX
A
A
A
A
A
A
A
A
A
A
A
A
A
A
BClR
BCC
0
0
A
A
A
A
A
A
A
A
A
A
A
A
0
1
A
A
A
A
A
1\
A
1
A
A
(to be continued)
C
Carry Borrow
Test and Set if True, Cleared Otherwise
Not Affected
Zero
330
------------------------------------------HD68P05V05, HD68P05V07
Table 9 Instruction Set
Addressing Modes
Mnemonic
LSL
LSR
NEG
NOP
ORA
ROL
ROR
RSP
RTI
RTS
SBC
SEC
SEJ
STA
STX
SUB
SWI
TAX
TST
TXA
Implied
Immediate
Direct
Extended
Relative
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
Condition Code
Indexed
Indexed Indexed
(No
(8 Bits) (16 Bits)
Offset)
x
x
x
x
x
x
x
x
x
x
x
x
Bit
Setl
Clear
Bit
Test &
Branch
1\
0
1\
1\
1\
1\
1\
1\
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
1\
Carry!Borrow
Test and Set if True. Cleared Otherwise
Not Affected
Load CC Register From Stack
331
1\
1\ 1\
1\
1\
1\
1\
1\
1\
1\
? ?
1\ 1\
1
1\ 1\
1\ 1\
1\ 1\ /\
1\ 1\
HD88P06V05, HD88P06V07-----------------------------------------Table 10
Bit Manipulation
Set/
Clear
Rei
OIR
0
BRSETO
BSETO
BRA
I
I
A
4
I
I
Control
Ragister /Memory
IMM
OIR
1 I
)(2
)(1
,XO
,X1
,XO
IMP
IMP
NEG
RTI*
RTS*
CMP
SBC
X
5
I
I
BClRO
BRN
BRSET1
BSET1
BHI
1 BRClRO
EXT
SUB
+-
CPX
AND
BIT
6 W
6
BRClR1
BClR1
BlS
COM
SWI*
BRSET2
BSET2
BCC
lSR
SEC
AOC
Cli
ORA
BRClR2
BClR2
BCS
BRSET3
BSET3
BNE
ROR
BRClR3
BClR3
BEQ
ASR
BSET4
BHCC
lSl/ASl
BClR4
BHCS
ROl
A BRSET5
BSET5
BPl
DEC
B BRClR5
BClR5
BSET6
BMI
SEI
C BRSET6
BMC
INC
RSP
TXA
1/
1/2
2/2
BRClR6
BClR6
BMS
TST
E BRSET7
BSET7
Bil
F BRClR7
BClR7
BIH
ClR
, 1/4
3/10
(NOTE)
2/7
2/4
2/6
, 1/4
, 2/7
, 1/6
TAX
lOA
8 BRSET4
9 BRClR4
ClC
NOP
STA(+lI
EOR
ADD
JMP(-1)
BSR*,
JSR(-3)
lOX
I,
2/4
3/5
HIGH
Read/Modify!Write
Branch
Test &
Branch
Opcode Map
STX(+lI
, 3/6 , 2/5
, 1/4
register in the program just after reset and selects the dividing
ratio of the prescaler and the clock input source. Fig. 24 shows
an example of the program which selects the external clock as
an input source at 128 dividing.
If the program specified by the HD68P05V is masked as
HD6805U/V, the command to operate this bit is ignored because HD6805U/V doesn't have the bit 0 to 5 of the timer control register.
lOA #$77
STA TCR ($009)
332
------------------------------------------HD68P05V05, HD68P05V07
7
000
127
128
76543210
$000
I/O Ports
Timer
RAM
(96 Bytes)
ROM
Port A
$000
Port B
$001
$07F
Port C
$002
,\80
Port D (digital)
$003**
Port A DDR
$004*
$OFF
$100
Port B DDR
$005*
Port C DDR
$006*
Port D (analog)
$007**
$008
$009
(128 Bytes)
255
256
Not Used
$7FF
$800
2047
2048
10
31
32
ROM
(1920 Bytes)
Not Used
$OOA
(22 Bytes)
$01F
$020
S~Ck
1J
3967
3968
4087
4088
4095
Self-Test
Interrupt Vectors
$07F
$F7F
$F80
$FF7
$FF8
$FFF
7
000
127
128
76543210
$000
I/O Ports
Timer
RAM
(96 Bytes)
$07F
$080
Port A
$000
Port B
$001
$002
Port C
Port D (digital)
$003**
Port A DDR
$004*
Port B DDR
$005*
Port C DDR
$006*
Port D (analog)
$007**
ROM
$008
(3840 Bytes)
10
Not Used
(22 Bytes)
31
32
1~
3967
3968
4087
4088
4095
Self-Test
Interrupt Vectors
Sta~ck
$009
$OOA
$01F
$020
$07F
7F
F80
FF7
FF8
$FFF
333
334
8-BIT MICROCOMPUTER
HMCS6800 MULTI-CHIP
SERIES
335
336
M PU
FEATURES
Versatile 72 Instruction - Variable Length (1~3 Byte)
Seven Addressing Modes - Direct, Relative, Immediate,
Indexed, Extended, Implied and Accumulator
Variable Length Stack
Vectored Restart
Maskable Interrupt
Separate Non-Maskable Interrupt - Internal Registers Saved
in Stack
Six Internal Registers - Two Accumulators, Index Register,
Program Counter, Stack Pointer and Condition Code Register
Direct Memory Accessing (DMA) and Multiple Processor
Capability
Clock Rates as High as 2.0 MHz
(HD6800 ... 1 MHz,
HD68AOO ... 1.5 MHz, HD68BOO ... 2.0 MHz)
Halt and Single Instruction Execution Capability
Compatible with MC6800, MC68AOO and MC68BOO
BLOCK DIAGRAM
(DC-40)
HD6800P, HD68AOOP, HD68BOOP
(DP-40)
PIN ARRANGEMENT
vss
A is
25
AI..
24
All
23
Au
22
All
20
A lo
19
At
18
A,
17
A,
16
A.
15
A,
14
A.
13
A,
12
A.
11
A,
10
A,
9
HALf
<PI
NC
<P2
VMA
DBE
NMI
NC
Rffl
,
Do
, 37
RES
40
A,
A,
NMI
HALT
iRQ
HD6S00
0,
A,
A.
TSC 39
As
DBE 36
A,
BA
VMA
A,
Rlii
34
A,
0,
A"
A ..
A"
(Top View)
26
0,
27
O.
2B
Os
29
0..
30
0,
31
01
32
0.
33
0"
337
..
Item
Symbol
Supply Voltage
Value
Vee
V in
Input Voltage
Operating Temperature
Topr
T stg
Storage Temperature
Unit
-0.3- +7.0
-0.3- +7.0
-20-+75
V
c
- 55- +150
min
typ
max
Unit
Supply Voltage
4.75
5.0
5.25
O.B
Vee
75
V
c
Input Voltage
Operating Temperature
...
Vee
V IL
-0.3
V IH
2.0
-20
25
Topr
ELECTRICAL CHARACTERISTICS
DC CHARACTERISTICS (Vee = 5V 5%, Vss = OV, Ta = -20-+75C, unless otherwise noted.)
Item
min
typ
max
Unit
Logic
V IH
2.0
Vee
Logic
V IL
- 0.3
O.B
1, 2
V IHe
V ee - 0.6
Vee + 0.3
1, 2
VILe
-0.3
0.4
Symbol
0 0 -0,
Output "High" Voltage
A o-A 15 R/W
VMA
V OH
BA
Output"Low" Voltage
Logic*-*
Input Leakage Current
ThreeState (Off-state)
Input Current
Ao""A15. R/W
IOH = -205pA
2.4
IOH = -145pA
2.4
IOH = -100pA
2.4
0.4
VOL
IOL = 1.6mA
lin
Yin = 0-5.25V.
All other pins are connected
to GNO
1.2
0 0 ""0,
Test Condition
ITSI
Po
Power Oissipation
Logic*
Input Capacitance
0 0 ""0,
1
Output Capacitance
**.*.
2
A o'..... A 15 , R,W
VMA BA
Cin
-2.5
2.5
pA
-100
100
pA
-10
10
pA
-100
100
pA
0.5
1.0
6.5
10
pF
10
12.5
pF
25
35
pF
45
70
pF
12
pF
Cout
V in = OV, Ta = 25 C.
f = 1 MHz
Ta 2soe. Vee:o 5V
All inputs except 1/1 1 and 1/1 2
All inputs except 1/11 .1/12 and Do -0 7
:0
338
AC CHARACTERISTICS
(Vee
1.0
1.000
Fig. 10
400
4,500
t r , tf
Fig. 10
tel
Fig. 10
4,500
tUT
Fig. 10
900
tCYC
I tPl, tP2
I tPl, tP2
PWCH1. PWCH 2
HD68AOO
HD6800
Fig. 10
typ
0.1
Frequency of Operation
Cycle Time
tP2
and
min
Symbol
Item
tPl
Test
Condition
max
typ
min
230
100
4,500
0.1
10 0.666
100
HD68BOO
max
0
600
1.5
typ
min
0.1
10 0.500
4,500
Unit
--
2.0
10
I-/S
4,500
ns
--
180
max
MHz
100
ns
0
440
4,500
ns
ns
2 READIWRITE CHARACTERISTICS
Symbol
Item
Address Delay
Time
Test
Condition
typ
HD68BOO
HD68AOO
HD6800
min
max
min
typ
max
min
typ
max
Unit
C=90pF
tAo1
Fig. 11,
Fig. 12
270
180
150
ns
C=30pF
t A02
Fig. 11,
Fig. 12
250
135
ns
Fig. 11
100
60
165
tOSR
40
ns
530
360
250
ns
10
20
20
10
ns
10
ns
280
220
ns
tacc
Fig. 11
tH
Fig. 11
10
tH
Fig. 12
20
tAH
Fig. 11,
Fig. 12
10
tEH
Fig. 12
450
toow
Fig. 12
t5BE
Fig. 12
150
225
tOBEO
Fig. 12
300
tOBEr
tOBEf
Fig. 12
10
200
160
ns
120
75
ns
250
180
ns
25
25
25
ns
140
110
ns
100
100
100
ns
165
135
ns
270
220
ns
tpcs
200
Processor Control
Aise and Fall Times
tpcr
tpCf
tBA
250
tTSO
270
5.0V
ns
C = 130pF for Do -0 7
= 90pF for Ao -A,s' R/W. and VMA
= 30pF for BA
R = 11 kn for Do -0 7
= 16kn for Ao -A, s. R/W and VMA
= 24kn for BA
C includes Stray Capacitance.
All diodes are 152074
or equivalent.
.....
339
BA
Figure 2 Timing of HALT and SA
Halt Cycle
I nstruction Cycle
-I'
O.4V
BA
Figure 3 Timing of HALT and SA
-I-
MP,U Reset
---1
____r
\'-------J/
~_-...J/
2 \ ' - -_ _ _
RES
2.4V
VMA
340
-I-
\'--_ _----J/
Interrupt Sequence
\___---"r
Vec - O.6V
I
-.
.
I
The last execution cycle of
WAI instruction (#9)
WAIT Cycle
\----s::=:vL
_tpcr
SA
tPl
TSC
R/W
VMA
SA
__~~~~~V~-------4--~~--_
v
~ Indeterminate period
341
MPU REGISTERS
The MPU provides several registers in Fig. 8, which is available for use by the programmer.
Each register is described below.
Increment., IH)
Ptogrem Count., IH)
Inc,ement... III
I
I
ACCA
15
IX
PC
SP
I
I
I
0
ACCB
Accumulator B
Index Register
I
I
Program Counter
15
Accumulator A
Clock (2, 2 )
15
Stack Pointer
.............,.....,r-'-T""'"r-...,......,..
Condition Codes
Register
cfi
Overflow
cfi 2
Zero
vov
VILC
--------1
Negative
Interrupt Mask
' - - - - - - Half Carry
(From Bit 3)
The condition code register indicates the results of an Arithmetic Logic Unit operation: Negative (N), Zero (Z), Overflow
(V) , Carry from bit 7 (C), and half carry from bit 3(H). These
bits of the Condition Code Register are used as testable conditions for the conditional branch instructions. Bit 4 is the
interrupt mask bit (I). The unused bits of the Condition Code
Register (b6 and b7) are" 1". The detail block diagram of the
microprossingunit is shown in Fig. 9.
Sixteen pins are used for the address bus. The outputs are
three-state bus drivers capable of driving one standard TTL load
and 90pF. When the output is turned off, it is essentially an
open circuit. This permits the MPU to be used in DMA applications. Putting TSC in its high state forces the Address bus to go
into the three-state mode.
342
~----------------------tcvc----------------------~
cp,
.....-
--~---------tacc---------
Data From
Memory or
Peripherals
2.0V --:=-,J-~==~_
---------------------------------=~~
O.8V -=--t-;;;;;;;;;=====::;;po1'E'~'0Ilndeterminate period
Figure 11 Read from Memory or Peripherals
Address
FromMPU~~!-~~~~-~~~--------+---------------------------~~
~-----------tEHI------------~
Data
From MPU
Data Valid
~~
Indeterminate period
343
This input is the three-state control signal for the MPU data
bus and will enable the bus drivers when in the "High" state; will
make the bus driver off when in the "Low" state. This input is
TTL compatible; however in normal operation, it would be
driven by 4>2 clock. During an MPU read cycle, the data bus
drivers will be disabled internally. When it is desired that another device control the data bus such as in Direct Memory
Access (DMA) applications, DBE should be held "Low."
If additional data setup or hold time is required on an MPU
write, the DBE down time can be decreased as shown in Fig. 13
(DBE ~ 4>2). The minimum down time for DBE is tOBE as
shown and must occur within 4>1 up time. As for the characteristical values in Fig. 12, refer to the table of electrical characteristics.
ReadlWrite (R/W)
Reset (RES)
The RES input is used to reset and start the MPU from a
power down condition resulting from a power failure or initial
start-up of the processor. This input can also be used to reinitialize the machine at any time after start-up.
If a "High" level is detected in this input, this will signal the
MPU to begin the reset sequence. During the reset sequence, the
contents of the last two locations (FFFE, FFFF) in memory
will be loaded into the Program Counter to point to the beginning of the reset routine. During the reset routine, the interrupt
mask bit is set and must be cleared under program control
before the MPU can be interrupted by IRQ. While RES is
"Low" (assuming a minimum of 8 clock cycles have occured)
the MPU output signals will be in the following states; VMA =
"Low", BA = "Low", Data Bus = high impedance, R/W="High"
(read state), and the Address Bus will contain the reset address
FFFE. Fig. 13 illustrates a power up sequence using the Reset
control line. After the power supply reaches 4.7SV, a minimum
of eight clock cycles are required for the processor to stabilize
in preparation for restarting. During these eight cycles, VMA will
be in an indeterminate state so any devices that are enabled by
VMA which could accept a false write during this time (such as
a battery-backed RAM) must be disabled until VMA is forced
"Low" after eight cycles. RES can go "High" asynchronously
with the system clock any time after the eighth cycle.
uu-u-uu-L
Ij
:~~~~~~l~~~~~~~~~~~~~~~~il
~~~;~
;::::::=---
Restart Routine
Address Bits 8-15
~A
= Indeterminate period
344
Restart Routine
Restart Routine
Address 8its 0-7
Instruction of
Restart Routine
mo
Cycle
#1
Cycle
#2
Cycle
#3
Cycle
#4
Cycle
#5
Cycle
#6
Cycle
#7
Cycle
#8
Cycle
#9
Cycle
#10
ICycle
ICycle
ICycle
I Cycle
I Cycle
I
#11
#12
#13
#14
#15
C/>,
Address
Bus
iROor
NMT
1M
Data
Bus
Inst (x)
R/Vii
PCO-PC7 PCB-
\~
ACCA
IXO-IX7 IX8-
ACCB
CCR
PC15
IX15
__________________________________
__JI
VMA
I Wa'
VLn..slSU""Ul.J
</>,
'1>2
A~~sess
I #n
t Cy
Cycle
I
#1 I
.ruL1L1l-fLfL.f
(NOTE)
n
Cycle
n+4 #n+5
n+3
In+1 n+2
.x
FFF8-FFF9- New PC
Address
VMA
IM~~~~~5~f~
mnor
~ta
Bus
Wait
Inst
Jl
Jl
Jl
Jl
Jl
..
345
-X-'
First Inst.
ot Interrupt
Routine
HD8800, HD88AOO, HD88BOO----------------------------------------the PC, IX, ACCX, and the CCR is already done.
While the MPU is waiting for the interrupt, Bus Available will
go "High" indicating the following states of the control lines:
VMA is "Low", and the Address Bus, R!W and Data Bus are all
in the high impedance state. After the interrupt occurs, it is
serviced as previously described.
Description
LS
FFFF
FFFD
FFFB
FFF9
Restart
Non-maskable Interrupt
Software Interrupt
Interrupt Request
Cycle
#1
#2
#3
#4
#5
#6
System
III.
MPUIII.
Address
Bus
Rfiii
VMA
Data
Bus
1112 DBE
TSC
346
"">--...;.Y_+ IRQ
Ignored
<Cycle>
#1- 2
#3- 9
(FFFC) Fetch
IM=1
Reset
#10
(FFFS) Fetch
#11
IM=1
Reset
(~~~
#12
#13
347
(~R~~
#11
HD8800,HD88AOO, HD68BOO------------------------------------------
,Instruction Instruction
Fetch
Execution,
</I,
~
tpCf
:::::::::~~~~~A~_--~JJ~----~~~~r
~(N~O~T~E~l~)-----------J
VMA
R/W
Address
Bus
Data
Bus
'"
pc
BA
I
~
~~_(~N~O~TE~2~)~n------------~
Execute
~!r?~--------4'JJ~----------~
~~~~~~~------4J----------~
WA>
W4>
~
(NOTE)
Table 2 Operation States of MPU and Signal Outputs (Except the Execution of Instruction)
Halt and
Signals
Reset state
Halt state
WAI state
Reset state
ilL"
"l"
BA
"H"
"H"
ilL"
VMA
"L"
"L"
"L"
R/W
"H"
''T''
"H"
''T''
"T"
(FFFE)16
(FFFEh6
"T"
Ao -- A 1s
"T"
"T"
"T"
''T''
Do -- 0 7
TSC state
"l"
"L"
"T"
"T"
...
The fetch of the OP code by the MPU is the first cycle of the
instruction. If HALT had not been "Low" at Point A but went
"Low" during!P2 of the cycle, the MPU would have halted after
completion of the following instruciton. BA will go "High" by
time tBA (bus available delay time) after the last instruction
cycle. At this point in time, VMA is "Low" and R/W, Address
Bus, and the Data Bus are in the high impedance state.
To debug programs it is advantageous to step through programs instruction by instruction. To do this, HALT must be
brought "High" for one MPU cycle and then returned "Low" as
shown at point B of Fig. i8. Again, the transitions of HALT
must occur tpcs before the trailing edge of !P1' BA will go
"Low" at t BA after the leading edge of the next !P1 , indicating
that the Address Bus, Data Bus, VMA and R/W lines are back
on the bus. A single byte, 2 cycle instruction such as LSR is
used for this example also. During the first cycle, the instruction
Y is fetched from address M+ 1. BA returns "High" at tBA on
the last cycle of the instruction indicating the MPU is off the
bus, if instruction Y had been three cycles, the width of the BA
"Low" time would have been increased by one cycle.
Table 2 shows the relation between the state of MPU and
signal outputs.
348
NOP
(IMP)
SBA
(A,B)
CBA
(A, B)
BRA
(REL)
TSX
(IMP)
NEG
(A)
NEG
(B)
NEG
(lNO)
NEG
(EXT)
SUB (A)
(EXT)
~~:T)(B)
INS
(IMP)
.
.
TAP
(IMP)
TPA
(IMP)
TAB
(IMP)
TBA
(IMP)
8
INX
(IMP)
DAA
(IMP)
A
CLV
(IMP)
BLS
(REL)
BCC
(REL)
BCS
(REL)
BNE
(REL)
BEO
(REL)
PUL
(A)
PUL
(B)
DES
(IMP)
TXS
(IMP)
PSH
(A)
PSH
(B)
COM
(A)
LSR
(A)
ROR
(A)
ASR
(A)
ASL
(A)
ROL
(A)
DEC
(A)
COM
(B)
LSR
(B)
ROR
(B)
ASR
(B)
ASL
(B)
ROL
(B)
DEC
(B)
COM
(lND)
LSR
(lNO)
ROR
(lNO)
ASR
(lNO)
ASL
(lNO)
ROL
(lND)
DEC
(lNO)
COM
(EXT)
LSR
(EXT)
ROR
(EXT)
ASR
(EXT)
ASL
(EXT)
ROL
(EXT)
DEC
(EXT)
~:~T)(B)
~~R)(A)
LOA (A)
(OIR)
BVC
(REL)
9
DEX
(IMP)
BHI
(REL)
f~:T)(A) ~:~T)(A)
fEM:T)(B)
BVS
(REL)
RTS
(IMP)
BPL
(REL)
BMI
(REL)
ADD (A)
(lMM)
INC
(A)
INC
BLT
(REL)
TST
(A)
E
CLI
(IMP)
F
SEI
(IMP)
BGT
(REL)
BLE
(REL)
WAI
(IMP)
SWI
(IMP)
CLR
(A)
(8)
TST
(B)
INC
(IND)
TST
(lNO)
JMP
(lND)
CLR
(lNO)
INC
(EXT)
TST
(EXT)
JMP
(EXT)
CLR
(EXT)
~~XM)(A)
BSR
(REL)
LOS
(lMM)
STS
(OIR)
CLR
(B)
LOS
(OIR)
JSR
(lNO)
LOS
(lNO)
STS
(lNO)
JSR
f::T)(A) (EXT)
LOS
(EXT)
STS
(EXT)
STA (A)
(lND)
D
SEC
(IMP)
(A)
~~)(A) f;I~)(A)
~~~)(A) ~~:)(A) ~~~)(A) ORA
(OIR)
BGE
(REL)
RTI
(IMP)
(A)
~EN~)(A) ~~~T)(A) ~~:rlA) ~;;n(A) ~~:T)(A) ~EOX;')(A) ORA
~i'~)(A)
(EXT)
CLC
(IMP)
ABA
(IMP)
~~~)(B)
8
SEV
(IMP)
349
LOX
(lMM)
~~~)(Bl ~~I~)(BI
LOX
(lNO)
STX
(lND)
LOX
(EXT)
STX
(EXT)
Complement, 2',
INegatel
Decimal Adjust, A
Decrement
Exclusive OR
Increment
Load Acmltr
Or, Inclusive
Push Data
Pull Data
Rotate Left
Rotate Right
Store Acmltr
Subtract
Subtract Acmltrs
Subtr with Carrv
Transfer Acmltrs
Test Zero or Minus
Mnemonic
ADDA
ADDB
ABA
ADCA
ADCB
ANDA
ANDB
BITA
BITB
CLR
CLRA
CLRB
CMPA
CMPB
CBA
COM
COMA
COMB
NEG
NEGA
NEGB
DAA
DEC
DECA
DECB
EORA
EORB
INC
INCA
INCB
LDAA
LDAB
ORAA
ORAB
PSHA
PSHB
PULA
PULB
ROL
ROLA
ROLB
ROR
RORA
RORB
ASL
AS LA
ASLB
ASR
ASRA
ASRB
LSR
LSRA
LSRB
STAA
STAB
SUBA
SUBB
SBA
SBCA
SBCB
TA8
TBA
TST
TSTA
iSiS
LEGEND:
OP Operation Code IHexadecimall
Number of MPU Cvcles
#
Number of Program Bvtes
+
Arithmetic Plus
Arithmetic Minus
800lean AND
Msp Contents of memory location
pointad to be Stack Pointer
IMMED
DIRECT
INDEX
EXTND
IMPLIED
OP- #
OP-#
OP- #
OP-#
OP- #
8B
CB
2 2 9B 3 2
2 2 DB 3 2
B9
2 2 99
3 2 A9
5 2
B9
4 3
C9 2 2 D9 3 2 E9 5 2 F9 4 3
B4 2 2 94 3 2 A4 5 2 B4 4 3
C4
85
C6
2 2 04
2 2 95
2 2 05
3 2 E4
3 2 A5
3 2 E5
6F
5 2 F4
5 2 B5
5 2 F5
7 2 7F
81
Cl
2 2 91
2 2 01
3 2 Al
3 2 El
5 2
5 2
63
60
6A
88
C8
2 2 98
2 2 08
3 2
3 2
7 2
Bl
Fl
73
7 2 70
2 7A
A8 5 2 B8
E8 5 2 F8
6C 7 2 7C
4
4
4
6
3
3
3
3
4F
5F
2
2
1
1
11
43
53
2
2
40
60
19
2
2
2
4A
5A
2
2
4 3
4 3
6
6
4
4
6
4
4
4
4
49
2
2
1
1
3
3
3
2
2
86 2 2 96 3 2 A6 5 2 B6 4 3
C6 2 2 06 3 2 E6 5 2 F6 4 3
89
BA 4 3
FA 4 3
7 2 79
59
66
7 2 76
68
7 2
46
56
78
68
2
2
1
1
47
57
2
2
1
1
44
2
2
1
1
48
67
2 77
64
7 2 74
2 1
2 1
:}
:}
:}
:}
:J
LO-C[[[I]J:Il:J
C b7
+-
bO
LO(J .. 1JiiiiII):J
C b7 00-
bO
mmm-o
bO
b7
~-o
b7
..
I
3 2
1 0
N Z V C
t
l
l
l
l
l
l
l
l
l
l
l
l
l
l
l
l
l
l
l
l
l
l
l
l
l
l
l l l
l l l
l l l
l R S
l R S
l R S
l <D
l "1
l l
l l
l l
l l
R
R
R
R
R S R R
R S R R
R S R R
36
37
32
33
*
** * *
**
*
** **
*** ** ***
** *
** ***
* * *
* **
*
l
l
l
l
l
1 JI:--A
1 IJ--B
oo-M--M
1 oo-A--A
1 oo-B--B
1 Convert, Binarv Add of BCD
Characters into BCD Format
M-l--M
1 A-l--A
1 B-l--B
A(!)M--A
B(!)M--B
M+l--M
1 A+l--A
1 B+l--B
M--A
M--B
A+M--A
B+M--B
1 A-- Msp,SP -l--SP
1 B -- Msp, SP - 1 -- SP
1 SP + 1 -- SP, Msp -- A
1 SP + 1 -- SP, Msp -> B
4C
5C
8A 2 2 9A 3 2 AA 5 2
CA 2 2 DA 3 2 EA 5 2
A '+ M-- A
B+M--B
A+B--A
A+M+C--A
B+M+C--B
AM--A
B oM __ B
AoM
BoM
oo ... M
OO--A
00-- B
A-M
B-M
A-B
~--M
5
H
A8 5 2 BS 4 3
EB 5 2 FB 4 3
lB
Booleanl
Arithmetic Operation
bO C
O.a::rihro-o
bOC
b7
<D
l <D
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
@
@
@
@
R
R
R
R
R
R
t t t
t
l t t
t
t t ~
t t t
t
t t
t t t
R
R
@
R
A-- M
t R
B--M
R
t
80 2
A-M->A
t
CO 2
B-M--B
t t t
10 2 1 A-B--A
t t t
82 2 2 92 3 2 A2 5 2 B2 4 3
A-M-C--A
t
t
C2 2 2 02 3 2 E2 5 2 F2 4 3
8-M-C--8
t t t
16 2 1 A--B
t t R
17 2 1 B--A
t t R
M -00
60 7 2 70 6 3
t t R
40 2 1 A-oo
t t R
50 2 1 B -00
t t R
CONDITION CODE SVMBOLS:
Boolean Inclusive OR
H Half-carrv from bit 3
R Reset Alwavs
Boolean Exclusive OR
I Interrupt mask
S Set Alwavs
Complement of M
N Negative Isign bitl
t Test and set if true. clearad otherwise
Transfer Into
Z Zero Ibvtel
Not Affectad
o Bit - Zero
V Overflow. 2's complement
00 Bvte Zero
C CarrV from bit 7
54
97 4 2 A7
07 4 2 E7
2 90 3 2 AO
2 DO 3 2 EO
6
6
5
5
2 B7
2 F7
2 BO
2 FO
5 3
5 3
4 3
4 3
INotel Accumulator addressing mode instructions are includad in the column for IMPLI ED addressing.
CONDITION CODE REGISTER NOTES:
IBit set if test is true and clearad otherwise)
<D IBit VI Test: Result = lOOOOOOO?
IBit CI Test: Result" OOOOOOOO?
@ IBit CI Test: Decimal value of most significant BCD Character greater than nine?
INot cleared if previouslV set.1
@ IBit VI Test: Operand a 10000000 prior to execution?
@ IBit VI Te.t: Operand - 01111111 prior to execution?
@ IBit VI Test: Set equal to result of N<!)C after shift has occurred.
350
t
t
t
t
t
R
R
R
Program Control operation can be subdivided into two categories: (I) Index Register/Stack Pointer instructions: (2) Jump
and Branch operations_
Mnemonic
CPX
DEX
DES
INX
INS'
LOX
LOS
STX
STS
TXS
TSX
CD
IMMED
DIRECT
INDEX
EXTND
OP
# OP
OP
OP
8C
9C
AC
6 2
BC
3
3
3
3
DE
9E
OF
9F
4
4
5
5
2
2
2
2
EE
AE
EF
AF
6 2
6 2
7 2
7 2
FE
BE
FF
BF
5
5
6
6
OP
09
34
08
31
CE
8E
IMPLIED
4
4
4
4
3
3
3
3
35
30
4
4
= 1)
351
2 1 0
N Z V
CD t
t
= 1?
Boolean!
Arithmetic Operation
@@ t RR
t
@@ t RR
t
MPU
ACCA
[ill
ACCA
m-2
m-2
..
m-1
SP-m-1
:::J
SP
In
~;O""V
m+1
....
{
Stacked
Data
7F
m+2
63
m+3
FD
New Data
!!!
III
Previously
Stacked
Data
F3
m+1
7F
m+2
63
m+3
FD
ACCA
ACCA
m-2
m-2
m-1
m-1
SP-m
Previously
Stacked
Data
m+1
SP-m+1
1A
m+2
m+2
3C
Previously
Stacked
Data
{
m+3
m+3
PC-------<...
05
EC_ _- -
PULA
PC-
(a)
Next Instr.
(b)
Before PU LA
352
After PULA
m-2
SP-m-2
m-1
m-1
(n+2)H
SP---m
(n+2)L
m+1
7E
PC-------n
7E
m+1
7A
r----
BSR
n+1
K*
BSR
= Offset
n+2
n+1
K* = Offset
n+2
~
*K
= Signed
7Bit Value
PC--(n+2) K
m-2
----
m-3
SP--m-2
m-1
m-1
sP-m
(n+3)H
(n+3)L
m+1
7E
m+1
7E
m+2
7A
m+2
7A
-pc--- n
70
JSR = BO
n+1
SH = Subr. Addr.
n+1
SH
= Subr.
n+2
SL
Addr.
n+2
SL
= Subr. Addr.
n+3
n+3
= Subr.
JSR
Addr.
PC---S
(5 formed from
SH and SL)
(b) After Execution
353
m-2
SP--m-2
m-1
m-1
(n+2)H
(n+2)L
SP-m
m+1
7E
m+1
7E
7A
7A
Pc-n
JSR = AD
n+1
K*
n+2
= Offset
n+1
n+2
PC-X** + K
SP-m-2
m-2
m-1
(n+3)H
m-1
(n+3)L
SP----m
m+1
7E
m+1
--
7A
JSR
---
(n+3)H
(n+3)L
--7E
7A
= BD
JSR = BD
n+1
SH
= Subr. Addr.
n+1
SH = Subr. Addr.
n+2
SL = Subr. Addr.
n+2
SL
= Subr.
Addr.
RTS
354
Software Interrupt
Main Program
Hardware Interrupt or
Non-Maskable Interrupt (NMI)
Main Program
n+1
Yes
Stack
SP--- m-7
c:::::>
m-6
Condition Code
m-5
Acmltr. B
m-4
Acmltr.A
m-3
Index Register (X H )
Index Register (XL)
m-2
SWI
m-1
PC(n+1 )H
PC(n+llL
WAI
HDWR
INT
No
FFF8
FFF9
Hardware Int.
MS
FFF9
FFFA
Hardware Int.
Software
MS
FFFB
Software
LS
FFFC
FFFE
NonMaskable Int. MS
NonMaskable Int. LS
Restart
MS
FFFF
Restart
FFFD
(NOTE)
LS
c:::::>
First Instr.
Addr. Formed
By Fetching
2-Bytes From
Per. Mem.
Assign.
LS
355
NMI
SP-m-7
m-7
m-6
CCR
m-6
CCR
m-5
ACCB
m-5
ACCB
m-4
ACCA
m-4
ACCA
m-3
XH (Index Reg)
m-3
XH
m-2
XL (Index Reg)
m-2
XL
m-1
PC(n+1 )H
m-1
PCH
PC(n+1)L
SP---m
PCL
..2.:.----- n+1
PC-n+1
Pc---Sn
RTI
356
Addressing Modes
Operation
Branch Always
Branch If Carry Clear
Branch If Carry Set
Branch If = Zero
Branch If ~ Zero
Branch If> Zero
Branch If Higher
Branch If ~ Zero
Branch I f lower Or Same
Branch If < Zero
Branch If Minus
Branch If Not Equal Zero
Branch If Overflow Clear
Branch If Overflow Set
Branch If Plus
Branch To Subroutine
Jump
Jump To Subroutine
No Operation
Return From Interrupt
Return From Subroutine
Software Interrupt
Wait for Interrupt
BAA
BCC
BCS
BEQ
BGE
BGT
BHI
BlE
BlS
BlT
BMI
BNE
BVC
BVS
BPl
BSR
JMP
JSR
NOP
RTI
RTS
SWI
WAI
CD (Alii
(Bit I)
OP
20
24
25
27
2C
2E
22
2F
23
2D
2B
26
28
29
2A
8D
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
8
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
OP
IMPLIED
EXTND
OP
OP
Branch Test
2
2
7E 3
BD 9
3
3
01 2 1
3B 10 1
39 5 1
3F 12 1
3E 9 1
None
C=O
C=1
Z=1
N()V=O
Z + (N@ V) = 0
C+Z=O
Z + (N @ V) = 1
C+Z=1
N <>V=1
N=1
z=o
v=o
V =1
N=O
6E 4
AD 8
- I- S
~r
I-- I-
PC
PC
Main Program
6E = JMP
{"
K = Offset
n+1
INDXD
INDEX
RELATIVE
Mnemonic
EXTND
Next Instruction
X+K
{"
Main Program
n+1
KH = Next Address
n+2
K L = Next Address
Main Program
7E = JMP
20= BRA
n+1
(n+2) K
K* = Offset
I Next Instruction
INext Instruction
*K = Signed 7-bit value
(b) 8ranch
(a) Jump
BMI
BPl
N= 1;
N = 0;
BEQ
BNE
Z=1;
Z=O;
BVC
BVS
V=O;
V= 1 ;
BCC
BCS
C= 0;
C= 1 ;
BHI
BlS
C+Z=O;
C+Z= 1;
BlT
BGE
N~ V= 1;
N + V=O;
BlE
BGT
:
:
Z + (N C> V) = 1 ;
Z + (N C> V) = 0 ;
357
HD8800, HD88AOO, HD68BOO-----------------------------------------3. Branch On Overflow Clear (BVC) and Branch On Overflow
Set (BVS) tests the state of the V bit to determine if the
previous operation caused an arithmetic overflow.
4. Branch On Carry Clear (BCC) and Branch On Carry Set
(BCS) tests the state of the C bit to determine if the previous
operation caused a carry to occur. BCC and BCS are useful
for testing relative magnitude when the values being tested
are regarded as unsigned binary numbers, that is, the values
are in the range "00" (lowest) of "FF" (highest). BCC
following a comparison (CMP) will cause a branch if the
(unsigned) value in the accumulator is higher than or the
same as the value of the operand. Conversely, BCS will cause
a branch if the accumulator value is lower than the operand.
The Fifth complementary pair, Branch On Higher (BHI)
and Branch On Lower or Same (BLS) are in a sense complements to BCe and BCS. BHI tests for both C and Z = "0", if
used following a CMP, it will cause a branch if the value in the
accumulator is higher than the operand. Conversely, BLS will
cause a branch if the unsigned binary value in the accumulator
is lower than or the same as the operand.
The remaining two pairs are useful in testing results of operations in which the values are regarded as signed two's complement numbers. This differs from the unsigned binary case in the
following sense: In unsigned, the orientation is higher or lower;
in signed two's complement, the comparison is between larger
or smaller where the range of values is between -128 and +127 .
Branch On Less Than Zero (BLT) and Branch On Greater
Than Or Equal Zero (BGE) test the status bits for NEf)V = "I"
and N E> V = "0", respectively. BLT will always cause a branch
following an opeiation in which two negative numbers were
added. In addition, it will cause a branch following a CMP in
which the value in the accumulator was negative and the operand was positive. BLT will never cause a branch following a
CMP in which the accumulator value was positive and the
operand negative. BGE, the complement to BLT, will cause a
branch following operations in which two positive values
were added or in which the result was "0".
The last pair, Branch On Less Than Or Equal Zero (BLE) and
Branch On Greater Than Zero (BGT) test the status bits for
Z Ef) (N + V) = "1" and Z E> (N + V) = "0", respectively,
The action of BLE is identical to that for BLT except that a
branch will also occur if the result of the previous result was
"0". Conversely, BGT is similar to BGE except that no branch
will occur following a "0" result.
b4
b3
b2
bl
bO
=
=
V
C
Carry; set if there was a carry from the most significant bit
(b7) of the result; cleared otherwise.
= "0"; cleared
otherwise.
ADDRESSING MODES
Operations
Clear Carry
Clear Interrupt Mask
Clear Overflow
Set Carry
Set Interrupt Mask
Set Overflow
Acmltr A -+ CCR
CCR -+ Acmltr A
Mnemonic
CLC
CLI
CLV
SEC
SEI
SEV
TAP
TPA
Add ressmg
Mode
IMPLIED
OP
OC
OE
OA
00
OF
OB
06
07
2
2
2
2
2
2
2
2
0-+ C
0-+ I
0-+ V
1 -+ C
1-+ I
1 ~ V
A ~CCR
CCR-+ A
II
Boolean Operation
#
1
1
1
1
1
1
1
1
R = Reset
S = Set
= Not affected
CD (ALL) Set according to the contents of Accumulator A.
358
CD
III
DO Instruction
Direct:
Example: SUBB Z
Addr. Range = 0~255
&
n+1
Z = Operand Address
n+2
(K = TwoByte Operand)
Instruction
Immediate:
Example: LDAA #K
(K = OneByte Operand)
Next Instr.
(K = One-Byte Operand)
n+1
K = Operand
n+2
Next Inst.
OR
(K = TwoByte Operand)
(CPX, LDX and LDS)
Instruction
n
n+1
KH = Operand
K = Operand
n+2
KL = Operand
OR
n+3
Next Instr.
KH = Operand
Z+1
KL = Operand
Instruction
Relative:
Example: BNE K
n+1
n+2
K = Branch Offset
Next Instr.&
Addr. Range:
-125 to +129
Relative to n.
Extended:
n+1
ZH = Operand Address
Addr. Range:
n+2
ZL = Operand Address
n+3
Next Instr.
(K = One-Byte Operand)
FO Instruction
Example: CMPA Z
& 256~65535
K = Operand
(n+2)K
&
&.
Next Instr.ffi
Instruction
Example: ADD A Z, X
n+1
Z = Offset
Addr. Range:
0~255 Relative to
Index Register, X
n+2
Next Instr.
Indexed:
OR
(K = Two-Byte Operand)
KH = Operand
Z+1
KL = Operand
X+Z
K_=_o_p_e_r_an_d_ _......I
L . 1_ _
AceB
~
Operand
MPU
MPU
RAM
RAM
Comment
MEM12
MEM12
The example used earlier for the test instruction, TST, also
applies to the accumulators and uses the "accumulator addressing mode" to designate which of the two accumulators is being
tested:
Example
General Flow
Comment
TEST CONTENTS OF ACCB
TEST CONTENTS OF ACCA
MPU
Operand
LDAA
#25
Comment
LOAD 25 INTO ACCA
INDEX
199......20
RAM
PC
PC = 5000 1--";"";"--1"
General Flow
PC
RAM
RAM
Program
Memory
Program
Memory
I--~~-t/
General Flow
Example
PC
= 5002 I--'~~~/
Example
360
CLI
CLR
CLV
COM
DAA
DEC
INC
LSR
NEG
NOP
ROL
ROR
SBA
Cycle
Cycle
SEC
SEI
SEV
TAB
TAP
TBA
TPA
TST
- _ . _ - - - - - - - _ ..
VMA
Line
R/W
Address Bus
Data Bus
Line
Op Code Address
II
Op Code Address + 1
Op Code
Op Code of Next Instruction
I
I
I
-+-_...- .. _.... __ ._- ---_._._-----_.-
_-
DES
~NESX
__I_N_X
____.~. _________ ~---+i
PSH
__4__
PUL
1
1
1
Op Code Address
Op Code Address + 1
Stack Pointer
Stack Pointer - 1
TSX
3
4
----r- --1-
1
2
3
4
RTS
1
2
-...-......
WAI
Op Code
Op Code of Next Instruction
Irrelevant Data (NOTE 1)
Operand Data from Stack
1
1
0
0
Op Code Address
Op Code Address + 1
Stack Pointer
New Index Register
1
1
1
1
Op Code
Op Code of Next Instruction
Irrelevant Data (NOTE 1)
Irrelevant Data (NOTE 1)
6
7
8
--_.
RTI
II
.-
.----- -
Code
Code of Next Instruction
Irrelevant Data
Irrelevant Data
1
1
0
1
1
Code Address
Code Address + 1
Stack Pointer
Stack Pointer + 1
Stack Pointer + 2
1
1
1
1
1
Op Code
Irrelevant Data (NOTE 2)
Irrelevant Data (NOTE 1)
Address of Next Instruction (High Order Byte)
Address of Next Instruction (Low Order Byte)
1
1
0
0
0
Op Code
Op Code of Next Instruction
Return Address (Low Order Byte)
Return Address (High Order Byte)
Index Register (Low Order Byte)
Index Register (High Order Byte)
Contents of Accumulator A
Contents of Accumulator B
Contents of Condo Code Register
1~
1
1
1
- I
. -. - .. --.-..... --
Op Code Address
Op Code Address + 1
Stack Pointer
Stack Pointer - 1
Stack Pointer - 2
Stack Pointer - 3
Stack Pointer - 4
Stack Pointer - 5
Stack Pointer - 6 (NOTE 3)
o~
------+.----+------.--------------------~
o
1
1
1
1
1
1
5
6
7
8
9
Stack Pointer + 7
10
3
4
5
6
7
8
9
10
11
12
1
1
1
1
1
1
1
1
1
Op Code Address
Op Code Address + 1
Stack Pointer
Stack Pointer + 1
Stack Pointer + 2
Stack Pointer + 3
Stack Pointer + 4
Stack Pointer + 5
Stack Pointer + 6
--1--1~---O~-c~d;-Addre;s-----
12
-.-----_._.. _ - - - -
1
1
1
1
3
4
SWI
--.-..-
Op Code Address
Op Code Address + 1
Index Register
New Stack Pointer
9
2
10
.- ...-
1
1
0
0
1
1
1
1
1
3
4
5
Data (NOTE 1)
Op Code
Op Code of Next Instruction
Accumulator Data
. -.... -
1
2
Op Code
Op Code of Next Instruction
Irrelevant Data (NOTE 1)
1
1
1
1
1
1
TXS
Op Code Address
Op Code Address + 1
Stack Pointer
Stack Pointer + 1
1
1
-- --t- ---------------------t
1
1
1
2
3
...
Op Code Address
Op Code Address + 1
Previous Register Contents
Op Code Address + 1
1
1
1
1
1
1
1
0
1
1
Stack Pointer
Stack Pointer Stack Pointer Stack Pointer Stack Pointer Stack Pointer Stack Pointer Stack Pointer Vector Address
Vector Address
----t 1
1
2
3
4
5
6
7
FFFA (Hex)
FFFB (Hex)
NOTE 1.
o
o
o
o
o
o
o
Op Code
Irrelevant Data (NOTE 2)
Irrelevant Data (NOTE 1)
Contents of Condo Code Register from Stack
Contents of Accumulator B from Stack
Contents of Accumulator A from Stack
Index Register from Stack (High Order Byte)
Index Register from Stack (Low Order Byte)
Next Instruction Address from Stack
(High Order Byte)
Next Instruction Address from Stack
(Low Order Byte)
Op Code
Irrelevant Data (NOTE 1)
Return Address (Low Order Byte)
Return Address (High Order Byte)
Index Register (Low Order Byte)
Index Register (High Order Byte)
Contents of Accumulator A
Contents of Accumulator B
Contents of Condo Code Register
Irrelevant Data (NOTE 1)
Address of Subroutine (High Order Byte)
Address of Subroutine (Low Order Byte)
If deVice which IS addressed dUring thiS cycle uses VMA, then the Data Bus Will go to the high Impedance three-state condition.
Depending on bus capacitance, data from the previous cycle may be retained on the Data Bus.
NOTE 2. Data is ignored by the MPU.
NOTE 3. While ~e MPU is waiting for the interrupt, Bus Available will go "High" indicating the following states of the control lines: VMA is "Low"; Address
Bus,R/W, and Data Bus are all in the high impedance state'.
361
EOR
LOA
ORA
SBC
SUB
CPX
LOS
LOX
Cycle
Cycle
#"
VMA
Line
Address Bus
R/W
Line
Data Bus
1
2
1
1
Op Code Address
Op Code Address + 1
1
1
Op Code
Operand Data
1
2
3
1
1
1
Op Code Address
Op Code Address + 1
Op Code Address + 2
1
1
1
Op Code
Operand Data (High Order Byte)
Operand Data (Low Order Byte)
EOR
LOA
ORA
SBC
SUB
Cycle
Cycle
#
VMA
Line
1
2
3
1
1
1
Op Code Address
Op Code Address + 1
Address of Operand
1
1
1
Op Code
Address of Operand
Operand Data
1
2
3
4
1
1
1
1
Op Code Address
Op Code Address + 1
Address of Operand
Operand Address + 1
1
1
1
1
Op Code
Address of Operand
Operand Data (High Order Byte)
Operand Data (Low Order Byte)
1
2
3
4
1
1
0
1
Op Code Address
Op Code Address + 1
Destination Address
Destination Address
1
1
1
0
OpCode
Destination Address
Irrelevant Data (NOTE 1)
Data from Accumulator
1
1
0
1
1
Op Code Address
Op Code Address + 1
Address of Operand
Address of Operand
Address of Operand + 1
1
2
3
4
5
1
1
0
0
Op Code
Address of Operand
Irrelevant Data (NOTE 1)
Register Data (High Order Byte)
Register Data (Low Order Byte)
STA
STS
STX
Address Bus
RIW
Line
Data Bus
NOTE 1. If device which is address during this cycle uses VMA, then the Data Bus will go to the high impedance three-state condition.
Depending on bus capacitance, data from the previous cycle may be retained on the Data Bus.
362
Cycle
Cycle
VMA
Line
1
2
3
4
5
6
1
1
1
0
1
1
Op Code Address
Op Code Address + 1
Op Code Address + 2
Address of Operand
Address of Operand
Address of Operand + 1
1
2
3
4
5
6
7
1
1
1
Op Code Address
Op Code Address + 1
Op Code Address + 2
Subroutine Starting Address
Stack Pointer
Stack Pointer - 1
Stack Pointer - 2
Op Code Address + 2
Op Code Address + 2
STS
STX
JSR
8
9
JMP
3
ADC EOR
ADD LOA
AND ORA
BIT SBC
CMP SUB
STAA
STA B
5
ASL
ASR
CLR
COM
DEC
INC
NOTE 1.
NOTE
LSR
NEG
ROL
ROR
TST
1
1
1
0
0
1
1
1
1
0
0
1
1
1
Op Code
Address of Operand (High Order Byte)
Address of Operand (Low Order Byte)
Irrelevant Data (NOTE 1)
Operand Data (High Order Byte)
Operand Data (Low Order Byte)
Op Code
Address of Subroutine (High Order Byte)
Address of Subroutine (Low Order Byte)
Op Code of Next Instruction
Return Address (Low Order Byte)
Return Address (High Order Byte)
I rrelevant Data (NOTE 1)
Irrelevant Data (NOTE 1)
Address of Subroutine (Low Order Byte)
Op Code Address
Op Code Address + 1
Op Code Address + 2
Op Code
Jump Address (High Order Byte)
Jump Address (Low Order Byte)
1
1
1
1
Op Code Address
Op Code Address + 1
Op Code Address + 2
Address of Operand
1
1
1
1
Op Code
Address of Operand (High Order Byte)
Address of Operand (Low Order Byte)
Operand Data
1
2
3
4
5
1
1
1
1
Op Code Address
Op Code Address + 1
Op Code Address + 2
Address of Operand
Address of Operand + 1
Op Code
Address of Operand
Address of Operand
Operand Data (High
Operand Data (Low
1
2
3
4
5
CPX
LOS
LOX
1
1
0
0
1
Data Bus
Line
1
1
1
2
3
1
R/W
Address Bus
3
4
1
2
3
4
5
6
1
1
1
0
1
1
1
1
1
0
1/0
(NOTE
2)
Op Code
Op Code
Op Code
Operand
Operand
1
1
1
1
1
1
Address
Address + 1
Address + 2
Destination Address
Destination Address
1
1
1
1
0
Op Code Address
Op Code Address + 1
Op Code Address + 2
Address of Operand
Address of Operand
Address of Operand
1
1
1
1
0
Op Code
Destination Address (High Order Byte)
Destination Address (Low Order Byte)
Irrelevant Data (NOTE 1)
Data from Accumulator
Op Code
Address of Operand (High Order Byte)
Address of Operand (Low Order Byte)
Current Operand Data
Irrelevant Data (NOTE 1)
New Operand Data (NOTE 2)
If device which is addressed during this cycle uses VMA, then the Data Bus will go to the high impedance three-state condition.
Depending on bus capacitance, data from the previous cycle may be retained on the Data Bus.
MPU
MPU
MPU
RAM
RAM
ADDR = 100
ADDR
ADDR
Program
Memory
Program
Memory
Program
Memory
PC
PC = 5004
5005
PC
PC-1
ADDR = 0 ~255
General Flow
= 3001--""':";:;_-1,,\
= 5006
I------i
5007
50081-_ _ _1
5009
ADDR ~ 256
General Flow
Example
Example
363
In both the Direct and Extended modes, the address obtained by the MPU is an absolute numerical address. The Relative addressing mode, implemented for the MPU's branch
instructions, specifies a memory location relative to the Program
Counter's current location. Branch instructions generate two
bytes of machine code, one for the instruction opcode and one
for the "relative" address (see Fig. 36). Since it is desirable to be
able to branch in either direction, the 8-bit address byte is interpreted as a signed 7-bit value; the 8th bit of the operand is
treated as a sign bit, "0" =plus and "I" =minus. The remaining
seven bits represent the numerical value. This result in a relative
addressing range of 127 with respect to the location of the
branch instruction itself. However, the branch range is computed with respect to the next instruction that would be executed if the branch conditions are not satisfied. Since two
byte are generated, the next instruction is located at PC+2.
If, D is defined as the address of the branch destination, the
range is then;
or
MPU
MPU
RAM
RAM
Program
Memory
Program
Memory
PC
1---"';"''';''''--11''
PC 5008
(PC+2)
Next Instr.
PC 5010
(PC+2) + (Offset)
.-.------f
Next Instr.
1-------1
PC 5025
364
BHI
BlE
BlS
BlT
BMI
Cycle
BNE
BPl
BRA
BVC
BVS
Cycle
#
1
BSR
1
1
2
3
4
1
VMA
line
2
3
4
5
6
7
8
R/W
line
Address Bus
0
0
Op Code Address
Op Code Address
Op Code Address
Branch Address
1
1
0
1
1
0
0
0
Op Code Address
Op Code Address + 1
Return Address of Main Program
Stack Pointer
Stack Pointer - 1
Stack Pointer - 2
Return Address of Main Program
Subroutine Address
+1
+2
Data Bus
1
1
1
1
Op Code
Branch Offset
Irrelevant Data (NOTE 1)
Irrelevant Data (NOTE 1)
1
1
1
0
0
1
1
1
Op Code
Branch Offset
Irrelevant Data (NOTE 1)
Return Address (Low Order Byte)
Return Address (High Order Byte)
Irrelevant Data (NOTE 1)
Irrelevant Data (NOTE 1)
Irrelevant Data (NOTE 1)
NOTE 1. If device which IS addressed dUring thiS cycle uses VMA, then the Data Bus will go to the high Impedance three-state condition .
Depending on bus capacitance, data from the previous cycle may be retained on the Data Bus.
The operand field can also contain a numerical value that will
be automatically added to X during execution. This format is
illustrated in Fig. 37.
When the MPU encounters the LDAB (Indexed) opcode in
location 5006, it looks in the next memory location for the
value to be added to X (5 in the example) and calculates the
required address by adding 5 to the present Index Register value
of 400. In the operand format, the offset may be represented
by a label or a numerical value in the range 0 '" 255 as in the
example. In the earlier example, STAA X, the operand is
equivalent to 0, X , that is, the "0" may be omitted when the
desired address is equal to X. Table 13 shows the cycle-by-cycle
operation for the Indexed Mode of Addressing_
Operand
Comment
STAA
MPU
RAM
RAM
ADDR = INDXt--::-:~:---V
+ OFFSET
Program
Memory
PC
t -.....- - - I /
Program
Memory
PC
= 5006
OFFSET ; 255
General Flow
1-=;"';';;;"--1/
Example
365
Cycle
JMP
4
Cycle
#
VMA
Line
Address Bus
R/W
Line
1
2
3
1
1
0
0
Op Code Address
Op Code Address + 1
Index Register
Index Register Plus Offset (w/o Carry)
1
1
1
Op Code
Offset
Irrelevant Data (NOTE 1)
Irrelevant Data (NOTE 1)
1
1
0
0
1
Op Code Address
Op Code Address + 1
Index Register
Index Register Plus Offset (w/o Carry)
Index Register Plus Offset
1
1
1
1
1
Op Code
Offset
Irrelevant Data (NOTE 1)
Irrelevant Data (NOTE 1)
Operand Data
1
1
0
0
1
1
Op Code Address
Op Code Address + 1
Index Register
Index Register Plus Offset (w/o Carry)
Index Register Plus Offset
Index Register Plus Offset + 1
1
1
1
1
1
1
Op Code
Offset
Irrelevant Data (NOTE 1)
Irrelevant Data (NOTE 1)
Operand Data (High Order Byte)
Operand Data (Low Order Byte)
1
1
0
0
0
1
Op Code Address
Op Code Address + 1
Index Register
Index Register Plus Offset (w/o Carry)
Index Register Plus Offset
Index Register Plus Offset
1
1
1
1
1
0
Op Code
Offset
Irrelevant Data (NOTE 1)
Irrelevant Data (NOTE 1)
Irrelevant Data (NOTE 1)
Operand Data
1
1
0
0
1
0
Op Code Address
Op Code Address + 1
Index Register
Index Register Plus Offset (w/o Carry)
Index Register Plus Offset
Index Register Plus Offset
Index Register Plus Offset
1
1
1
1
1
1
0
Op Code
Offset
Irrelevant Data (NOTE 1)
Irrelevant Data (NOTE 1)
Current Operand Data
Irrelevant Data (NOTE 1)
New Operand Data (NOTE 2)
1
1
0
0
0
1
1
Op Code Address
Op Code Address + 1
Index Register
Index Register Plus Offset (w/o Carry)
Index Register Plus Offset
Index Register Plus Offset
Index Register Plus Offset + 1
1
1
1
1
1
0
0
Op Code
Offset
Irrelevant Data (NOTE 1)
Irrelevant Data (NOTE 1)
Irrelevant Data (NOTE 1)
Operand Data (High Order Byte)
Operand Data (Low Oder Byte)
1
1
0
1
1
0
0
0
Op Code Address
Op Code Address + 1
Index Register
Stack Pointer
Stack Pointer - 1
Stack Pointer - 2
Index Register
Index Register Plus Offset (w/o Carry)
1
1
1
0
0
1
1
1
Op Code
Offset
Irrelevant Data (NOTE 1)
Return Address (Low Order Byte)
Return Address (High Order Byte)
Irrelevant Data (NOTE 1)
Irrelevant Data (NOTE 1)
Irrelevant Data (NOTE 1)
ADC
ADD
AND
BIT
CMP
EOR
LOA
ORA
sac
SUB
CPX
LOS
LOX
1
2
3
1
2
3
4
5
6
STA
ASL
ASR
CLR
COM
DEC
INC
LSR
NEG
ROL
ROR
TST
1
2
3
4
5
6
1
2
3
7
5
6
7
1/0
Data Bus
(NOTE
2)
STS
STX
1
2
3
7
5
6
7
JSR
1
2
3
NOTE 1.
NOTE 2.
5
6
7
8
..
If Device which IS addressed during this cycle uses VMA, then the Data Bus will go to the high Impedance three-state condition.
Depending on bus capacitance, data from the previous cycle may be retained on the Data Bus.
For TST, VMA = 0 and Operand data does not change.
366
IMMEDIATE
VMA
10
12
11
13
----l---~---J---
--"1
~~I----_4I----~I----~----~----~-__~--~----~----~----~----+_----1
RIW --,
I
I
:
-'
I
I
I
[
DataBus=
LOA
Data
Next
Inst.
DIRECT
I
VMA
Rffl --'j
-'
I
I
I
I
[I . \
~-L-b
I
r"J
'--;-'
[
Data B u s = : : : : : : : : : : x : : : : : : x _ _ _ _ _
LOA Address Data
ST A Address
ACCA
Next
Data
Inst.
INDEXED
RIW'J:!
VMA
Data Bus
I:
--+---t
t-/'---+-----.--t"
t-j---j.I-.J..--~_).~_.........
_.
-).~"""'---+-----+-Ji.
I
I
Offset
Data
STA
EXTENDED
Offset
:
Data
RfflJ
[ Data Bus
L_L..17
I
LOA
Address Address
Data
STA
IMPLIED
Address Address
ACCA
Data
::J--+--.....I...-~....J..--+t.LJ7---+-~-----r---+I
R/W:t~--~:~--~:-----T:----~l~~~-----+----~----~----~
I
Data Bus
::x:::::::x::::_____x:=:x=:::x_____
ABA
RELATIVE
PSH
I
Data
Next
Inst.
I
tS:t.....---'---!-Iti--....L.....--.--t--"1'---"~
VMA
D,..R:'J
::-:;;c::::~::::)~::::);:::1::~::::)(::::~:::::~::::;(:
Branch
Inst.
PC
Offset
Next
Inst.
367
Next
Inst.
I
I
VMA~-i-----T-----T-l.LJ7
L.Ll7
I
-=x:::::::x::::_______x::::::x::=:::x___________x::::x=:
LOA
VMA
I
:
HD6802---------------M PU
The HD6802 is a monolithic 8-bit microprocessor that contains all the registers and accumulators of the present HD6800
plus an internal clock oscillator and driver on the, same chip.
In addition, the HD6802 has 128 bytes of RAM on the chip
located at hex addresses 0000 to 007F. The first- 32 bytes of
RAM, at hex addresses 0000 to OOIF, may be retained in a low
power mode by utilizing V cc standby, thus facilitating memory
retention during a power-down situation.
The HD6802 is completely software compatible with the
HD6800 as well as the entire HMCS6800 family of parts.
Hence, the HD6802 is expandable to 65k words.
FEATURES
On-Chip Clock Circuit
128 x 8 Bit On-Chip RAM
32 Bytes of RAM are Retainable
Software-Compatible with the HD6800
Expandable to 65k words
Standard TTL-Compatible Inputs and Outputs
BLOCK DIAGRAM
(DC-40)
PIN ARRANGEMENT
Vee
Vee
Vec
Standby
Vss
Vee
Vee
RES
HALT
EXTAL
XTAL
MR
Counter/ {
Timer I/O
es o
'J!tn
Parallel
I/O
'iRci
VMA
Clock
R/W
TIm
MR
VMA
RES
0,
0,
Rfii
Ao-A,s
RiW
D.
RE
A,
0,
BA
D.
XTAL
D.
0,
CJ
Control {
VeeStandbv
BA
HD6802
0 0 -0,
RE
NMI
Vee
MPU
VMA
EXTAL
C
Crystal
0,
_Ie>
';J; ;t;
A"
A..
A"
A"
--,. _ _ _ _ _ _- - J -
(Top View)
368
Vss
------------------------------------------------------------HD6802
ABSOLUTE MAXIMUM RATINGS
Item
Supply Voltage
Input Voltage
Symbol
Value
Unit
Vee *
Vee StandbY*
Vin *
Operating Temperature
Topr
Storage Temperature
Tstg
c
c
Symbol
Vee *
Vee Standby*
VIL *
Supply Voltage
Input Voltage
VIH *
typ
max
Unit
4.75
5.0
5.25
V
V
-0.3
0.8
Except RES
2.D
Vee
RES
4.25
-20
25
Vee
75
Operation Temperature
min
Topr
Except RES
RES
Except RES
RES
V1H
VOH
BA
Output "Low" Voltage
Three State (Off State) Input Current
OO-o?
Output Capacitance
VOL
ITS1
lin
0 0 ..... 0 7
Except 0 0 ..... 0 7
A o -A 15 , R/W , BA,
VMA,E
0.4
-10
10
J.lA
-2.5
2.5
J.lA
0.6
1.2
10
12.5
6.5
10
12
2.4
Caut
Vin=OV, Ta =25C,
f=1.0MHz
369
0.8
IOH = -100J.lA
~n
2.4
Vin=OV, Ta =25C,
f=1.0MHz
Vee
0.8
Unit
2.4
IOL = 1.6mA
Vee
-0.3
IOH = -145J.lA
Vin = 0.4-2.4 V
Vin = Q-5.25V
-0.3
IOH = -205J.lA
Po *
Power Dissipation
Input Capacitance
4.25
***
V1L
00-0 7 , E
Output "High" Voltage
2.0
av.
pF
pF
HD6802---------------------------------------------------------- AC CHARACTERISTICS (Vee=5.0V5%, Vee Standby=5.0V5%, Vss=OV, Ta=-20~+75C, unless otherwise noted.)
1. CLOCK TIMING CHARACTERISTICS
Item
Frequency of Operation
Symbol
min
typ
max
0.1
1.0
I Crystal
fXTAL
1.0
4.0
1.0
10
450
4500
ns
25
ns
Frequency
Cycle Time
I "High" Level
I "Low" Level
Test Condition
fcyc
Fig. 2, Fig. 3
PW4JH
PW4JL
tcp
0.8V
2.4V(Fig.2,Fig.3)
Unit
MHz
J,J.s
2. READIWRITE TIMING
typ*
Test Condition
min
Address Delay
tAD
tacc
Fig. 2
tOSR
Fig. 2
100
tH
Fig. 2
10
tH
Fig. 3
20
tAH
Fig. 2, Fig. 3
10
toow
tSA
Processor Controls
Processor Control Setup Time
Processor Control Rise and Fall Time
(Measured at 0.8V and 2.0V)
tpcs
Fig.
tpcr
tpCf
Item
Symbol
Fig. 3
Fig. 4, Fig. 5, Fig. 7, Fig. 8
4~Fig.
7, Fig. 12
max
Unit
270
ns
530
ns
ns
ns
ns
165
225
ns
250
ns
200
ns
100
ns
ns
3. POWER DOWN SEQUENCE TIMING, POWER UP RESET TIMING AND MEMORY READY TIMING
min
typ
max
tRE1
Fig. 13
150
tRE2
Fig. 13
E-3 cycles
tLRES
Fig. 12
20*
tRE3
Fig. 12
tSMR
Fig. 16
300
ns
tHMR
Fig. 16
200
ns
Item
Symbol
Test Condition
370
Unit
ns
ms
ns
----------------------------------------------------------------HD6802
5.0V
R L = 2Akn
C = 130pF for Do ~D7' E
= 90pF for Ao ~Als, R/W, and VMA
= 30pF for BA
R = 11 kn for Do ~D7' E
= 16kn for Ao ~A1S ,R/W, and VMA
= 24kn for BA
C includes stray Capacitance.
All diodes are 152074 (ft or equivalent.
~-----------------------tcyc----------------------~
2AV
RM
Address
From MPU
VMA
Data
From Memory
or Peripherals
2.0V --:::;:o;oo,,..,..1-....,,,===~
--------------------------------~~
0.8V--="4----~==F
~ Data Not Valid
~----------------------tcyc----------------------~
PWcI>H
E
OAV
Address
From MPU
VMA
tDDW
2.4V
Data
From MPU
OAV
371
HD6802-----------------------------------------------------------
I-
HALT Cycle
2.4V
O.4V
2.0V
O.BV
2.4V
SA
I nstruction Cycle
-I-
--
--'r
'-O.4V
.... 2.0V
HALT
-, 1/ O.BV
tPcr
tpcs
tBA
BA
~O.4V
MPU Reset
RES
VMA _ _
Figure 6
-----'~24V
372
----------------------------------------------------------HD6802
WAIT Cycle or
The Last Instruction Cycle
Interrupt Sequence
2.4V
IRQ. NMI
--'\
BA
O.4V
Figure 7
I-
WAIT Cycle
2.4V
2.4V
BA
Figure 8
MPU REGISTERS
373
HD6802--------------------------------------------------------A"/
At.
A~
A4
A ..
16
15
14
13
12
A,
1i
AI
10
MR 3
E 37
40
NMI 6
HAIT 2
11m 4
EXTAl39
XTAl38
BA 7
VMA 5
RM 34
Rn"
26
0,
27
0,
28
0,
29 30
0, 0,
31
0,
32 33
0, 0"
I
I
I
I
ACCA
Accumulator A
15
I
I
I
Accumulator B
ACCB
IX
15
0
PC
15
I'
ndex Register
Program Counter
SP
Stack Pointer
Interrupt mask
I
I
:....---1
m- 9
m- 8
m-7
m-6
SP
CC
ACCB
ACCA
IXH
IXl
PCH
PCl
Stack Pointer
m- 2
m-l
---r
SP
CC
m- 5
ACCB
m-4
ACCA
m -3
IXH
m- 2
m-l
PCH
IXl
PCl
m +1
m
m+ 1
m+2
+2
Before
After
374
"'
-----------------------------------------------------------HD6802
HD6802
Sixteen pins are used for the address bus. The outputs are
capable of driving one standard TTL load and 90pF.
Data Bus (Do "" 0 7 )
Eight pins are used for the data bus. It is bidirectional,
transferring data to and from the memory and peripheral
devices. It also has three-state output buffers capable of driving
one standard TTL load and 130pF.
Data Bus will be in the output mode when the internal RAM
is accessed. This prohibits external data entering the MPU. It
should be noted that the internal RAM is fully decoded from
$0000 to $OO7F. External RAM at $0000 to $007F must be
disabled when internal RAM is accessed.
HALT
ReadlWrite (R/W)
Reset (RES)
A low-going edge on this input requests that a non-maskbe generated within the processor. As with
the IRQ signal, the processor will complete the current
instruction that is being executed before it recognizes the NMI
signal. The interrupt mask bit in the Condition Code Register
has no effect on NMI.
The Index Register, Program Counter, Accumulators, and
Condition Code Register are stored away on the stack. At the
end of the cycle, a 16-bit address will be loaded that points to a
vectoring address which is located in memory locations FFFC
and FFFD. An address loaded at these locations causes the
MPU to branch to a non-maskable interrupt routine in memory.
A 3kn external resistor to Vee should be used for wire-OR
and optimum control of interrupts.
Inputs IRQ and NMI are hardware interrupt lines that are
sampled when E is "High" and will start the interrupt routine
on a "Low" E following the completion of an instruction. IRQ
and NMI should be tied "High" if not used. This is good engineering design practice in general and necessary to insure
proper operation of the part. Fig. 14 is a flowchart describing the
major decision paths and interrupt vectors of the microprocessor. Table 1 gives the memory map for interrupt vectors.
inter~sequence
375
HD6802-------------------------------------------------------------
VCC
E
!--tpcs
>4.25V
Option 1
(See Note below)
RES --------~I
Option 2
it
______________O~.8~~
RE
VMA
O.8V
tPCr
____--J/
(NOTE)
fI~-----------------,,~___________________
VCC
l-t
RE
AE1
tPCf3f1
2.0V
tAE2
O.8V
-----------
376
----------------------------------------------------------HD6802
Conditions for Crystal (4 MHz)
AT Cut Parallel resonant
Co =7 pF max.
Rl = 80n max.
Description
MS
LS
FFFE
FFFF
Restart
FFFC
FFFD
FFFA
FFFB
Software Interrupt
(SWI)
FFFB
FFF9
Interrupt Request
(IRQ)
(RES)
Co
LJ------.......----,
HD6802
38 pin
C,
= C2 = 22pF
20%
When using the crystal, see the note for Board Design of the
Oscillation Circuit in HD6802.
~----------------------------------------~J~-------------------------_
\.-0.4V /
~tSMR
tPCr
MR
377
HD6802------------------------------------------------------------
Enable (E)
This pin supplies the clock for the MPU and the rest of the
system. This is a single phase, TTL compatible clock. This clock
may be conditioned by a Memory Ready Signal. This is
equivalent to <1>2 on the HD6800.
Vee Standby
_____
Crystal oscillator and load capacity CL must be placed near
______
the LSI as much as possible.
~
t-'-~.........- - - f ,
TIn
~;';";';:;=-4----f~
HD6802
i~ i~ / ' \\
-+----;---;------
38
Signal C
HD6802
Figure 17
378
-----------------------------------------------------------HD6802
HD6802
Figure 18
379
HD6802W
MPU
H06802W is the enhanced version of HD6802 which contains MPU, clock and 256 bytes RAM. Internal RAM has been
extended from 128 to 256 bytes to increase the capacity of
system read/write memory for handling temporary data and
manipulating the stack.
The internal RAM is located at hex addresses 0000 to OOFF.
The first 32 bytes of RAM, at hex addresses 0000 to 001 F, may
be retained in a low power mode by utilizing Vee standby,
thus facilitating memory retention during a power-down situation.
The HD6802W is completely software compatible with the
H06800 as well as the entire HMCS6800 family of parts. Hence,
the H06802W is expandable to 65k words.
FEATURES
On-Chip Clock Circuit
256 x 8 Bit On-Chip RAM
32 Bytes.of RAM are Retainable
Software-Compatible with the HD6800. HD6802
Expandable to 65k words
Standard TTL-Compatible Inputs and Outputs
HD6802WP
(DP-40)
PIN ARRANGEMENT
BLOCK DIAGRAM
RES
Vss
HALf
Vee
Vee
Vee
Standby
EXTAL
XTAL
VMA
RE
Vee
Vee
vee
RM
D.
0,
A,
Counterl {
Timer 1/0
11m
MR
HD6802W
RES
0,
2 0,
0,
RE
1/0
0,
D.
1m
Parallel
0,
if
R/W
HD6802W NMI
IMPUI
BA
0.-0 7
A"
A,.
A"
XTAL
CJ
Control {
A.-A"
AI>
Crystal
Vss
EXTAL
C';r; *C'
380
(Top View)
Standby
---------------------------------------------------------HD6802VV
A expanded block diagram of the HD6802W is shown in Fig.
1. As shown, the number and configuration of the registers are
the same as the HD6802 except that the internal RAM has been
extended to 256 bytes.
MR 3
E 37
RES 40
NMI 6
HALT 2
Tm:i 4
EXTAL 39
XTAL 38
SA 7
VMA 5
Rm 34
26
Vee = Pins
8,35
Vss = Pins 1,21
27
28
0, 0, Os
29
D.
30
OJ
31
O2
32
0,
33
Do
: : _____________ } retention by
Vee Standby
0020
381
HD6802W----------------------~---------------------------------
Symbol
Value
Unit
Vee *
Vee Stand by *
-0.3- +7.0
Input Voltage
Yin *
-0.3 - +7.0
Operating Temperature
Topr
Tstg
-20- +75
-55 - +150
Storage Temperature
Symbol
Supply Voltage
min
Vee*
4.75
Vee Standby *
V ,L *
4.0
I nput Voltage
V ,H
Operation Temperature
I RES
max
Unit
5.0
5.25
V
V
-0.3
0.8
2.0
Vee
Vee -0.75
-20
25
Vee
75
I Except RES
typ
Topr
V
c
ELECTRICAL CHARACTERISTICS
DC CHARACTERISTICS (Vee=5.0V5%, Vee Standby=5.0V5%, Vss=OV, Ta=-2o-+75C, unless otherwise noted.)
Item
Input "High" Voltage
Input "Low" Voltage
min
typ*
max
V,H
2.0
Vcc-O.75
Vee
**
V,L
-0.3
Vee
0.8
-0.3
0.8
IOH = -205J,LA
2.4
IOH = -145J,LA
2.4
IOH = -100J,LA
2.4
Symbol
Except RES
RES
Except RES
RES
Do-0 7 , E
VOH
BA
Output "Low" Voltage
Three State (Off State) Input Current
0 0 ""07'
Except Do -0 7
Output Capacitance
* T a =25 C,
0 0 ""0 7
Except 0 0 ""0 7
Ao""A 1s , R/W, BA,
VMA
Unit
V
V
0.4
Yin = 0.4""2.4 V
-10
10
J,LA
Yin = Q-5.25V
-2.5
2.5
J,LA
0.7
1.2
10
12.5
c'n
Vin=OV, Ta=25C,
f=1.0MHz
6.5
10
Caut
Vin=OV, Ta=25C,
f=1.0MHz
12
VOL
ITS1
lin ***
IOL = 1.6mA
Po ****
~\I\Ier Dissipation
Input Capacitance
Test Condition
va.; =5V
** As RES input has histeresis character, applied voltage up to 2.4V is regarded as "Low" level when it goes up from OV.
*** Does not include EXTAL and XTAL, which are crystal inputs.
**** In power-down mode, maximum power dissipation is less than 42mW.
382
pF
pF
--------------------------------------------------------HD6802W
AC CHARACTERISTICS (Vee=5.0V5%, Vee Standby=5.0V5%, Vss=OV, Ta=-20~+75C, unless otherwise noted.)
1. CLOCK TIMING CHARACTERISTICS
Frequency of Operation
Cycle Time
I "High" Level
I "Low" Level
min
typ
max
0.1
1.0
fXTAL
1.0
4.0
1.0
450
4500
ns
25
ns
Symbol
Item
Test Condition
fcye
Fig. 4, Fig. 5
PWc/>H
at 2.4V(Fig. 4, Fig. 5)
PWc/>L
t,p
10
Unit
MHz
Ils
2. READ/WRITE TIMING
Item
Symbol
Test Condition
min
typ*
max
Unit
270
ns
Fig.4
tOSR
Fig.4
100
Address Delay
tAD
tace
tH
Fig.4
10
tH
Fig.5
20
tAH
Fig. 4, Fig. 5
10
toow
Fig. 5
165
225
ns
tSA
250
ns
tpcs
200
ns
tpcr,
tpCf
100
ns
max
Unit
Processor Controls
Processor Control Setup Time
Processor Control Rise and Fall Time
(Measured at O.SV and 2.0V)
530
ns
ns
ns
ns
ns
3. POWER DOWN SEQUENCE TIMING, POWER UP RESET TIMING AND MEMORY READY TIMING
min
typ
tRE1
Fig. 12
150
tRE2
Fig. 12
E-3 cycles
Item
Symbol
Test Condition
tLRES
Fig. 11
20
tRE3
Fig. 11
tSMR
Fig. 14
300
tHMR
Fig. 14
383
ms
200
ns
ns
ns
ns
HD6802W--------------------------------------------------------
S.OV
Test Point
0-_--_--..--.. .
C
R L = 2.4kn
C = 130pF for 0 0 -0" E
= 90pF for Ao -A 1S , R/W, and VMA
= 30pF for BA
R = 11 kn for Do -0" E _
= 16kn for Ao -A IS , R/W, and VMA
= 24kn for SA
C includes stray Capacitance.
All diodes are 1S2074@or equivalent.
~-----------------------tCyC--------------------~
.4V
R/W
Address
From MPU
VMA
Data
From Memory
or Peripherals
2.0V -::::=-~.-.!==~"'---
--------------------------------------~~
O.8V---=-'f-===~
~
Figure 4
~---------------------tcyc----------------------~
PWtPH
E
O.4V
R/W
Address
From MPU
VMA
Data
2.4V
From MPU
O.4V
--:::~~=~~=::::~~
---'''''''''4-=======~r
384
---------------------------------------------------------HD6802VV
I_
HALT Cycle
2.4V
O.4V
BA
2.4V
.~ ~
Instruction Cycle
_ _ _ _ _ _ _...,-- O.4V
2.0V
HALT
O.8V
tpc. - * " I
tpcs
....:..:....-.j
BA
O.4V
2.4V
VMA
385
HD6802VV---------------------------------------------------------
WAIT Cycle or
The Last Instruction Cycle
Interrupt Sequence
2.4V
IRQ, NMI
- --- - - ---- - - -- - - - - - - - -- - - -- - - - - - -
'\
BA
O.4V
WAIT Cycle
2.4V
2.4V
BA
386
--------------------------------------------------------HD6802W
Sixteen 'pins are used for the address bus. The outputs are
capable of driving one standard TTL load and 90pF.
Reset (RES)
A low-going edge on this input requests that a non-maskbe generated within the processor. As with
the IRQ signal, the processor will complete the current
instruction that is being executed before it recognizes the NMI
signal. The interrupt mask bit in the Condition Code Register
has no effect on NMI.
The Index Register, Program Counter, Accumulators, and
Condition Code Register are stored away on the stack. At the
end of the cycle, a 16-bit address will be loaded that points to a
vectoring address which is located in memory locations FFFC
and FFFD. An address loaded at these locations causes the
MPU to branch to a non-maskable interrupt routine in memory.
A 3kO external resistor to Vee should be used for wire-OR
and optimum control of interrupts.
Inputs IRQ and "WI are hardware interrupt lines that are
sampled when E is "High" and will start the interrupt routine
on a "Low" E following the completion of an instruction. IRQ
and NMI should be tied "High" if not used. This is good engineering design practice in general and necessary to insure
proper operation of the part. Fig. 13 is a flowchart describing
the major decision paths and interrupt vectors of the microprocessor. Table 1 gives the memory map for interrupt vectors.
inter~sequence
387
HD6802W--------------------------------------------------------
Vcc
E
!--tpcs
>VCC-O.75V
__--------------~~--------~+------------l---Option 1
(See Note below)
Option 2
See Figure 12 for
Power Down condition
iC
RE
DV
O.8V
O.8V
tpcr
(I
VMA
(NOTE)
Figure 11
Vcc
tPCf=:j
RE
2.0V
rl-t
RE1
'1\ l.-tRE2--l
O.8V~
388
---------------------------------------------------------HD6802W
Conditions for Crystal (4 MHz)
AT Cut Parallel resonant
Co =7 pF max.
Rl = 80n max.
Description
MS
LS
FFFE
FFFF
Restart
FFFC
FFFD
FFFA
FFFB
Software Interrupt
(SWI)
FFF8
FFF9
Interrupt Request
(IRQ)
(RES)
Co
Q------..,..--....,
HD6802W
38 pin
n------.......,
2.4V
C,
= C,
= 22pF .20%
When using the crystal, see the note for Board Design of the
Oscillation Circuit in HD6802W.
~--------------~r~----------~\
:t.. O.4V
I==tSMA
tPCr
tpCf
MR
389
HD6802W--------------------------------------------------------
Enable (E)
This pin supplies the clock for the MPU and the rest of the
system. This is a single phase, TTL compatible clock. This clock
may be conditioned by a Memory Ready Signal. This is
equivalent to 2 on the HD6800.
Vee Standby
This pin supplies the dc voltage to the first 32 bytes of RAM
as well as the RAM Enable (RE) control logic. Thus retention of
data in this portion of the RAM on a power-up, power-down, or
standby condition is guaranteed at the range of 4.0 V to 5.25 V.
Maximum current drain at S.2SV is 8mA.
_____
Crystal oscillator and load capacity CL must be placed near
_______
the LSI as much as possible.
~
1--'-'--........----1.
38
7h
~;';"":";:=-+-----1 ~
HD6802W
-------
37
~~
/'\
~ ~
\
-+--~-+------ Signal C
38
HD6802W
390
--------------------------------------------------------HD6802W
HD6802W
391
M PU
HD6809,HD68A09,HD68B09
HD6800 COMPATIBLE
Hardware - Interfaces with All HMCS6800 Peripherals
Software - Upward Source Code Compatible Instruction Set and Addressing Modes
ARCHITECTURAL FEATURES
Two 16-bit Index Registers
Two 16-bit Indexable Stack Pointers
Two 8-bit Accumulators can be Concatenated to Form
One 16-Bit Accumulator
HARDWARE FEATURES
On Chip Oscillator
DMA/BREQ Allows DMA Operation or Memory Refresh
Fast Interrupt Request Input Stacks Only Condition
Code Register and Program Counter
(DP-40)
PIN ARRANGEMENT
HALi'
XTAL
EXTAL
IRO
m-s
FIRO
BS
MROY
DMA7BREo
Riw
0,
0,
A,.
(Top View)
SOFTWARE FEATURES
10 Addressing Modes
HMCS6800 Upward Compatible Addressing Modes
Direct Addressing Anywhere in Memory Map
Long Relative Branches
Program Counter Relative
True Indirect Addressing
Expanded Indexed Addressing:
392
-----------------------------------------HD6809~
HD68A09, HD68B09
Auto-Increment/Decrement by 1 or 2
Improved Stack Manipulation
1464 Instructions with Unique Addressing Modes
8 x 8 Unsigned Multiply
16-bit Arithmetic
Transfer/Exchange All Registers
Push/Pull Any Registers or Any Set of Registers
Load Effective Address
BLOCK DIAGRAM
~Vcc
+--vss
, . . . - - - - RES
NMI
_ - - - DMA/BREQ
R/iii
HALT
BA
BS
, - - - - - XTAL
EXTAL
MRDY
'----. E
~--""Q
393
Symbol
Value
Unit
Vee *
Vin *
-0.3 -+7.0
-0.3-+7.0
-20 - +75
-55 - +150
Supply Voltage
Input Voltage
Operating Temperature
Topr
Tstg
Storage Temperature
c
c
Permanent lSI damage may occur if maximum ratings are exceeded. Normal operation should be under
recommended operating conditions. If these conditions are exceeded, it could affect reliability of lSI.
Symbol
min
typ
Vee *
V'L *
4.75
-0.3
2.2
4.0
5.0
-
-20
Supply Voltage
Input Voltage
V'H *
~-
Operating Temperature
----- -
I Logic
-_ _____ L~
..
Topr
max
Unit
V
5.25
0.8
V
- -- - - - Vce *
Vce *
25
75
ELECTRICAL CHARACTERISTICS
Symbo'
Except RES
RES
V ,H
V'L
Except EXTAl,
XTAl
0 0 -0,
lin
ITS'
Ao-A,s' RIW,
a, E
'VOH
BA, BS
Output Capacitance
Vin""0-5.25V,
Vee""max
Vin""0.4-2.4V,
Vee""max
I LOAO""-205#,A,
Vee""min
I LOAO""-145",A,
Vee""min
I LOAO=-100",A,
Vee""min
Test Condition
VOL
Po
Do-D,
Except Do -D,
Cin
Ao-A,s' RIW,
BA,BS
Cout
I LOAO""2mA
Vin""OV,
Ta""25C,
f""1MHz
i'
394
min
2.2
4.0
-0.3
-2.5
HD6809
typ* max
Vee
Vee
0.8
HD68A09
min tvP* max
2.2
- Vee
4.0
- Vee
-0.3
- 0.8
H068809
min tvP* max
2.2
Vee
4.0
Vee
-0.3
0.8
2.5
-2.5
2.5
",A
-10
10
100 -100
10
100
-10
-100
10
100
",A
2.4
2.4
2.4
2.4
2.4
2.4
2.4
2.4
10
0.5
1.0
15
10
12
2.4
-2.5
2.5
-100
-10
Unit
10
7
0.5
1.0
15
10
12
0.5
1.0
15
10
12
10
V
W
pF
pF
1. CLOCK TIMING
HD6809
Item
Symbol
HD68A09
HD68B09
Test Condition
Unit
min
typ
Frequency of Operation
(Crystal or External Input)
fXTAL
0.4
Cycle Time
tcyc
1000
Total Up Time
tUT
975
tPWEH
450
tpwEL
450
tEr, tEf
Fig. 2, Fig. 3
max
min
typ
0.4
10000 667
640
280
25
295
max
min
typ
0.4
10000 500
10000
max
MHz
ns
480
220
210
25
220
25
20
ns
100
ns
min
typ
max
110
tAVS
250
Q Clock "High"
tpWOH
450
280
tor,tof
25
QLow to E Falling
tOE
200
133
min
typ
max
165
ns
ns
ns
20
ns
125
ns
ns
2. BUS TIMING
Item
Address Delay
Address Valid to QHigh
Peripheral Read Access Time
(tUT-tAO-tOSR=tACC)
Data Set Up Time (Read)
Input Data Hold Time
Address Hold Time
Ao-A ls , RtW
Symbol
tAO
tAO
tACC
Fig. 2, Fig. 3
tDDW
tOHW
Fig. 2, Fig. 3
Ta=0-+75C
Fig. 2, Fig. 3
Ta=-20-0C
Fig. 3
Fig.3
Ta-0-+75C
Fig.3
Ta=-20-0C
HD68A09
HD68B09
min
typ
max
200
140
25
15
440
330
60
10
40
10
20
20
10
10
20
10
225
30
30
20
20
50
tOSR
tOHR
tAH
HD6809
Test Condition
695
80
10
Unit
ns
ns
ns
ns
ns
ns
ns
145
30
ns
20
ns
typ
max
tyD
min
125
110
110
110
125
100
100
ns
30
30
ms
180
ns
Symbol
Test Condition
tpCSM
tpr.!':
tpr.!':101
tpCSR
tpCSO
tPCr,
tpCf
tRC
Fig. 6-Fig. 10
Fig. 14, Fig. 15
395
HD6809
HD68A09
min
125
200
200
200
125
typ
max
min
125
140
140
140
125
100
50
HD68B09
max
Unit
ns
ns
ns
ns
ns
Test Point
o------4I~---4I~-_M~_4
-r
RiW _ _ _
~NotV.lid
*Hold time for SA, SS not specified.
~NotV.lid
*Hold time for SA,
as not specified.
PROGRAMMING MODEL
As shown in Figure 4, the HD6809 adds three registers to the
set available in the HD6800. The added registers include a
Direct Page Register, the User Stack pointer and a second Index
Register.
Accumulators (A, B, D)
The A and B registers are general purpose accumulators
which are used for arithmetic calculations and manipulation of
data.
Certain instructions concatenate the A and B registers to
form a single 16-bit accumulator. This is referred to as the D
396
15
x-
Index Register
Y - Index Register
Po;",,,
R.g;~."
A
\
Program Counter
Accumulators
./
0
D_P_ _ _ ~
L . I_ _ _ _ _
I E IF I H I I I N I
I V I C
cc -
Bit 0 (C)
Bit 0 is the carry flag, and is usually the carry from the
binary ALU. C is also used to represent a 'borrow' from subtract
like instructions (CMP, NEG, SUB, SBC) and is the complement
of the carry from the binary ALU.
Bit 1 (V)
Bit 1 is the overflow flag, and is set to a one by an operation
which causes a signed two's complement arithmetic overflow.
This overflow is detected in an operation in which the carry
from the MSB in the ALU does not match the carry from the
MSB-1.
Bit 2 (Z)
Bit 2 is the zero flag, and is set to a one if the resul t of the
previous operation was identically zero.
Bit 3 (N)
Bit 3 is the negative flag, which contains exactly the value of
the MSB of the result of the preceding operation. Thus, a
negative two's-complement result will leave N set to a one.
Carry
Overflow
L - - - - Zero
L -_ _ _ _ Negative
L -_ _ _ _ _ IRQ Mask
L -_ _ _ _ _ _ _ Half Carry
L-_ _ _ _ _ _ _ _ FIRQ Mask
' - - - - - - - - - - - Entire Flag
Bit 4 (I)
Bit 4 is the IRQ mask bit. The processor will not recognize
interrupts from the ~ line if this bit is set to a one. NMI,
FIRQ, IRQ, RES, and SWI all are set I to a one; SWI2 and SWI3
do not affect I.
Bit 5 (H)
397
Bit 6 (F)
Bit 6 is the FIRQ mask bit. The processor will not recognize
interrupts from the FIRQ line if this bit is a one. NMI, FIRQ,
SWI, and RES all set F to a one. iRO; SWI2 and SWI3 do not
affectF.
Bit 7 (E)
Bit 7 is the entire flag, and when set to a one indicates that
the com{>lete machine state (all the registers) was stacked, as
opposed to the subset state (pC and CC). The E bit of the
stacked CC is used on a return from interrupt (RT!) to
determine the extent of the unstacking. Therefore, the current
E left in the Condition Code Register represents past action.
SIGNAL DESCRIPTION
Power (Vss, Ved
Two pins are used to supply power to the part: VSS is
ground or 0 volts, while VCC is +5.0V 5%.
MS
LS
FFFE
FFFC
FFFA
FFF8
FFF6
FFF4
FFF2
FFFO
FFFF
FFFD
FFFB
FFF9
FFF7
FFF5
FFF3
FFF1
Interrupt Vector
Description
RES
NMI
SWI
IRQ
FIRQ
SWI2
SWI3
Reserved
HALT
A "Low" level on this input pin will cause the MPU to stop
running at the end of the present instruction and remain halted
indefinitely without loss of data. When halted, the BA output is
driven "High" indicating the buses are high impedance. as is
also "High" which indicates the processor is in the Halt or Bus
Grant state. While halted, the MPU will not respond to external
real-time requests (FIRQ, IRQ) although DMA/BREQ will
always be accepted, and NMI or RES will be latched for later
response. During the Halt state Q an~ continue to run
normally. If the MPU is not running (RES, DMA/BREQ). a
halted state (BA BS=I) can be achieved by pulling HALT
"Low" while ~ is still "Low". IfDAM/BREQ and HALT are
both pulled "Low", the processor will reach the last cycle of the
instruction (by reverse cycle stealing) where the machine will
then become halted. See Figs. 8 and 16.
Read/Write (R/W)
This signal indicates the direction of data transfer on the data
bus. A "Low" indicates that the MPU is writing data onto the
data bus. R/W is made high impedance when BA is "High". R/W
is valid on the rising edge of Q. Refer to Figs. 2 and 3.
Reset (RES)
A "Low" level on this Schmitt-trigger input for greater than
one bus cycle will reset the MPU, as shown in Fig. 6. The Reset
vectors are fetched from locations FFFE16 and FFFF16 (Table
1) when Interrupt Acknowledge is true, (BA BS=I). During
initial power-on, the Reset line should be held "Low" until the
clock oscillator is fully operational. See Fig. 7.
Because the HD6809 Reset pin has a Schmitt-trigger input
with a threshold voltage higher than that of standard peripherals,
a simple R/C network may be used to reset the entire system.
This higher threshold voltage ensures that all peripherals are out
of the reset state before the Processor.
BA
BS
0
0
1
1
0
1
0
1
MPU State
Normai (Running)
Interrupt or RESET Acknowledge
SYNC Acknowledge
HALT or Bus Gfant
398
Vee
lIB"
--+---:
W r'
Ad::" \\\\\\\
ANi
.\\S\\\S\ssf~
~~ N\\\\\\\~
SA
\\\\\\\\s{~
\\'L\\mss:~
rs
VMA
\lUX
rl
\ _ _ _ __
<0
<0
4.75V
Vcc
E
:::t
C
RES
CO
tAC
HD6809
YI
8 MHz
6 MHz
4 MHz
Figu~
Cin
Cout
18pF20% 18 pF 20%
22pF20% 22 pF 20%
22pF2091: 22 pF 20%
381
VI
39
YnJ;
J;
Cout
:r:
c
m
CO
:a:o
CD
:::t
CO
m
o
CD
Fig. 9.
~--~J~---------------c::x::)~-----
Address
Bus
Fetch
Execute
r---~~--~~------~r~-------------------------------JI
\,____________
,-______1
BA _ _ _ _ _ _ _ _ _ _ _ _- - i
BS ______________--ir-----~If'------------------~,
Data
Bus
I'----~----
c::x::)------
Instruction
Opcode
A~,"s~--~,~~J_--~--~--~~~~--v_--~--_v--~r_-v_--~--~--~r_~,_--v_--~--~--~r_~~--~--~
Bus
FFFF
5P-1
5P-t 5P-3 5P-4 5P-5 5P-6 5P-7 8P-8 5P-9 5P-10 5P-11 5P-12 FFFF ~~~~~: ~~~~~li: FFFF NewPC PC+'
RIW
MY
BA
::ss\\SS\
BS
\'SSSSSS\
PCl
PCH
USl
USH
IYl
IYH
IXl
IXH
DP
ACCB
ACCA
ceR
\~---------------------------------------------=--~I
I
Figure 9
fRO
400
A~r_~~~~~--~,---~,--~,,---~~--~,---~,--~r---~,--~,~--~~--~.~--~,~--
Bus
RlWmssw
V'MA
PCl
PCH
VMA
CCR
VMA
ht Inst.
Of Interrupt
Service Routine
,'-____----J/
BA~
BS~
\\..-------
r-~~~~__~ICO~
ch
HD6809
XTAL, EXTAL
These inputs are used to connect the on-chip oscillator to an
external parallel-resonant crystal. Alternately, the pin EXTAL
may be used as a TTL level input for external timing by
grounding XTAL. The crystal or external frequency is four
times the bus frequency. See Fig. 7. Proper RF layout
techniques should be observed in the layout of printed circuit
boards.
401
m
iiii
e.
iii iii
E,Q
Must be avoided.
1\
MRDY
This input control signal allows stretching of E and Q to
extend data-access time. E and Q operate normally while MRDY
is "High". When MRDY is "Low", E and Q may be stretched in
integral multiples of quarter (1/4) bus cycles, thus allowing
interface to slow memories, as shown in Fig. 14. A maximum
...--..:...;.........
: -----Signal C
Cout
t-~~-----fcih
HD6809
Start
OJ Cycle
I
~ O.SV
E X-_O_os_V_ _ _ _ _-J
l--- 1~~----~
~~
I
I
tAVS
~---~I------
Address Valid
f~
\-----1
!'------\-----11
\\.----r-1--if~S----'I
2.4V"\
I
I
a
MRDY
tPCfj ~
\\\\\~
402
ll;t
fr-l102~~V
pc r
DMA/BREQ
MPU
DEAD
DEAD
DMA
MPU
DMA/BAEQ
BA,BS
DMAVMA*
ADDA
(MPU)
ADDA
(DMAC)
C
(
*DMAVMA is a signal which is developed externally, but is a system requirement for DMA.
Figure 15 Typical DMA Timing 14 Cycles)
403
>
ani
DMA/BREQ
~~I~~
____________________________________________~I__~__~~-----------
--Y
I
DMAVMA*
BA,BS
~
I
~~----------------------------------------------~~------------
*DMAVMA is a signal which is developed externally, but is a system requirement for DMA.
Immediate Addressing
In Immediate Addressing, the effective address of the data is
the location immediately following the opcode (i.e., the data to
be used in the instruction immediately follows the opcode of
the instruction). The HD6809 uses both 8 and 16-bit immediate
values depending on the size of argument specified by the
opcode. Examples of instructions with Immediate Addressing
are:
LDA #$20
LDX #$FOOO
LDY #CAT
(NOTE) # Signifies Immediate addressing, $ signifies hexadecimal value.
Extended Addressing
In Extended Addressing, the contents of the two bytes
immediately following the opcode fully specify the 16-bit
effective address used by the instruction. Note that the address
generated by an extended instruction defines an absolute
address and is not position independent. Examples of Extended
Addressing include:
CAT
LDA
STX
MOUSE
LDD
$2000
Extended Indirect
As a special case of indexed addressing (discussed below),
"1" level of indirection may be added to Exten.ded Addressing.
In Extended Indirect, the two bytes following the postbyte of
an Indexed instruction contain the address of the data.
[CAT]
LDA
LDX
[$FFFE]
STU
[DOG]
Direct Addressing
Direct addressing is similar to extended addressing except
that only one byte of address follows the opcode. This byte
specifies the lower 8-bit of the address to be used. The upper
8-bit of the address are supplied by the direct page register. Since
only one byte of address is required in direct addreSSing, this
mode requires less memory and executes faster than extended
addressing. Of course, only 256 locations (one page) can be
404
f'il!m.~
I>->DPR
l-+F, f
l-+RJW
Clr TiIJM
Logic
U1
l:
C
CD
00
o
U)
Sync
Halt/Bus Grant
(NOTE)
I BA
Running
Asserting RES will result in entering the reset sequence from any point in the flow chart.
Figure 17 Flowchart for HD6809 Instruction
BS
CD
00
l>
U)
l:
C
CD
00
.:D
oU)
Indexed
Addressing
Mode
dressing.
Register Addressing
Some opcodes are followed by a byte that defmes a register
or set of registers to be used by the instruction. This is called a
postbyte. Some examples of register addressing are:
X, Y
Transfers X into Y
TFR
EXG
A, B
Exchanges A with B
PSHS
A, B, X, Y
Push Y, X, B and A onto S
X, Y, D
Pull D, X, and Y from U
PULU
0
0/1
,R +
,R ++
EA
= ,R + 5 Bit Offset
,-R
0/1
,-- R
0/1
0/1
0/1
0/1
0/1
0/1
x
x
011
0/1
= ,R + 0 Offset
= ,R + ACCB Offset
EA = ,R + ACCA Offset
EA = , R + 8 Bit Offset
EA = ,R + 16 Bit Offset
EA = ,R + D Offset
EA =,PC + 8 Bit Offset
EA = ,PC + 16 Bit Offset
EA = [,Addressl
-------
EA
EA
Indirect Field
(Sigh bit when b7 = 0)
Non Indirect
{o........
1 ........ Indirect
' - - - - - - - - - - - Register Field: RR
00 = X
01 = y
10= U
11 = S
x = Don't Care
Indexed Addressing
In all indexed addressing, one of the pointer registers (X, Y,
U, S, and sometimes PC) is used in a calculation of the effective
address of the operand to be used by the instruction. Five basic
types of indexing are available and are discussed below. The
postbyte of an indexed instruction specifies the basic type and
variation of the addressing mode as well as the pointer register
to be used. Fig. 18 lists the legal formats for the postbyte. Table
3 gives the assembler form and the number of cycles and bytes
Forms
Auto Increment/Decrement R
Assembler
Form
Indirect
+ +
Postbyte
OP Code
-#
No Offset
,R
1 RR00100
0 0
5 Bit Offset
n, R
ORRnnnnn
1 0
Assembler
Form
[,R)
+ +
Postbyte
OP Code
-#
1 RR10100
3 0
defaults to a-bit
4 1
a Bit Offset
n, R
1 RR01000
1 1
[n, Rl
1RR11000
16 Bit Offset
n, R
1 RR01001
4 2
[n, Rl
1RR11001
7 2
A Register Offset
A,R
1RR00110
1 0
lA, Rl
1 RR10110
4 0
B Register Offset
B,R
1 RR00101
1 0
[B, Rl
1 RR10101
4 0
o Register Offset
D,R
1RR01011
4 0
[0, Rl
1RR11011
7 0
Increment By 1
,R +
1 RROOOOO
2 0
Increment By 2
,R ++
1 RROOO01
3 0
,- R
1 RROOO10
2 0
Decrement By 1 .
not allowed
LR ++l
1 RR10001
6 0
not allowed
Decrement By 2
,- - R
1 RROO011
3 0
L - - Rl
1RR10011
6 0
a Bit Offset
n, PCR
1xx01100
1 1
[n,PCRl
1xx11100
4 1
16 Bit Offset
n, PCR
1xx01101
1xx11101
a 2
16 Bit Address
5 2
- -
[n, PCRl
Extended Indirect
[nl
10011111
5 2
R = X, Y, U orS
x = Don't Care
~ and
RR:
00= X
01 = Y
10= U
11 = S
:# indicate the number of additional cycles and bytes for the particular variation.
406
$FOIO
$FOll
$FI
$50
$F150 $AA
After Execution
A = $AA Actual Data Loaded
X= $FOOO
All modes of indexed indirect are included except those
which are meaningless (e.g., auto increment/decrement by I
indirect). Some examples of indexed indirect are:
LDA
[,X]
LDD
[10,S]
LDA
[B,Y]
LDD
[,X++]
Relative Addressing
The byte(s) following the branch opcode is (are) treated as a
signed offset which may be added to the program counter. If
the branch condition is true then the calculated address (pC +
signed offset) is loaded into the program counter. Program
execution continues at the new location as indicated by the PC;
short (I byte offset) and long (2 bytes offset) relative addressing
modes are available. All of memory can be reached in long
relative addressing as an effective address is interpreted modulo
216 Some examples of relative addressing are:
CAT
DOG
RAT
RABBIT
BEQ
BGT
LBEQ
LBGT
NOP
CAT
DOG
RAT
RABBIT
(short)
(short)
(long)
(long)
NOP
407
0000 - D
0001 - X
001O-Y
0011 - U
0100 - S
CAT,PCR
TABLE, PCR
0101
1000
1001
1010
1011
PC
A
B
CC
DP
[CAT, PCR]
[DOG,PeR]
~ou~C~ IDE~TI~AT!ONI
LEAX/LEA Y /LEAU/LEAS
The LEA (Load Effective Address) works by calculating the
effective address used in an indexed instruction and stores that
address value, rather than the data at that address, in a pointer
register. This makes all the features of the internal addressing
hardware available to the programmer. Some of the implications
of this instruction are illustrated in Table 4.
The LEA instruction also allows the user to access data in a
position independent manner. For example:
MSG I, PCR
LEAX
LBSR
PDATA (print message routine)
MSGI FCC
PULU/PULS
The pull instructions have the same capability of the push
instruction, in reverse order. The byte immediately following
the push or pull opcode determines which register or registers
are to be pushed or pulled. The actual PUSH/pULL sequence is
fIXed; each bit defines a unique register to push or pull, as
shown in below.
'MESSAGE'
This sample program prints: 'MESSAGE'. By writing MSGI,
PCR, the assembler computes the distance between the present
address and MSG I. This result is placed as a constant into the
LEAX instruction which will be indexed from the PC value at
the time of execution. No matter where the code is located,
when it is executed, the computed offset from the PC will put
the absolute address of MSG 1 into the X pointer register. This
code is totally position independent.
Table 4 LEA Examples
Instruction
LEAX
LEAX
LEAY
LEAY
LEAU
LEAS
LEAS
LEAX
CC
A
'----- B
' - - - - - - DP
'-------x
'--------y
, - - - - - - - - Stu
' - - - - - - - - - - PC
+- Pull
Order
Push Order -+
PC
U
Y
X
DP B
A
CC
FFFF ... +- increasing memory address ..... 0000
PC
DP
CC
.TFR/EXG
Within the HD6809, any register may be transferred to or
exchanged with another of like-size; i.e., 8-bit to 8-bit or 16-bit
to 16-bit. Bits 4-7 of postbyte define the source register, while
bits 0-3 represent the destination register. Three are denoted as
follows:
10, X
500, X
A, Y
D, Y
-10, U
-10, S
10, S
5, S
Operation
Comment
X + 10 -+ X
X + 500 -+ X
Y+A -+Y
Y+D -+Y
U-l0-+U
S-10-+S
S + 10 -+ S
S+5 -+X
MUL
Multiplies the unsigned binary numbers in the A and B
accumulator and places the unsigned result into the 16-bit D
accumulator. This unsigned multiply also allows multipleprecision multiplications.
408
SYNC
After encountering a Sync instruction, the MPU enters a
Sync state, stops processing instructions and waits for an
interrupt. If the pending interrupt is non-maskable (NMI) or
maskable (FIRQ, IRQ) with its mask bit (F or I) clear, the
processor will clear the Syne state and perform the normal
interrupt stacking and service routine. Since FIRQ and IRQ are
not edge-triggered, a "Low" level with a minimum duration of
three bus cycles is required to assure that the inte~t will be
taken. If the pending interrupt is maskable (FIRQ, IRQ) with its
mask bit (F or I) set, the processor will clear the Sync state and
continue processing by executing the next inline instruction.
Fig. 19 depicts Sync timing.
Software Interrupts
A Software Interrupt is an instruction which will cause an
interrupt, and its associated vector fetch. These Software Interrupts are useful in operating system calls, software debugging, trace operations, memory mapping, and software development systems. Three levels of SWI are available on this
HD6809, and are prioritized in the following order: SWI, SWI2,
SWI3.
16-Bit Operation
The HD6809 has the capability of processing 16-bit data.
These instructions include loads, stores, compares, adds, subtracts, transfers, exchanges, pushes and pUlls .
CYCLE-BY-CYCLE OPERATION
The address bus cycle-by-cycle performance chart illustrates
the memory-access sequence corresponding to each possible
instruction and addressing mode in the HD6809. Each instruc~ion begins with an opcode fetch. While that opcode is being
mternally decoded, the next program byte is always fetched.
(Mo~t instructions will use the next byte, so this technique
considerably speeds thrOUghput.) Next, the operation of each
opcode will follow the flow chart. VMA is an indication of
FFFF16 on the address bus, R/W="High" and BS="Low".
The following examples illustrate the use of the chart; see Fig.
20.
LBSR
(Branch taken)
Cycle # 1
2
3
4
5
6
7
8
9
opcode Fetch
opcode +
opcode +
VMA
VMA
ADDR
VMA
STACK (write)
STACK (write)
DEC
(Extended)
Cycle # 1
2
3
4
5
6
7
opcode Fetch
opcode +
opcode +
VMA
ADDR (read)
VMA
ADDR (write)
409
Sync
Opcode
Inst.
Fetch
I..
..I .
I. . ..I .
Execute
Dead
Cycle
.I
SYNC Acknowledge
M+1
Address
Fetch
Data
A/W
BA
BS
:{
(NOTE)
:=:x=A'--________1
~~-----------------~r------~-------------------------------See Note 2
tpcs
1. If the associated mask bit is set when the interrupt is requested, thi.!Slcle will continue the instruction fetched from the previous cycle.
However, if the interrupt is accepted (NM1 or an unmasked FIRQ or IRQ) the opcode address (placed on the bus from cycle M + 1) remains
on the bus and interrupt~cessin8..2!!tinues with this cycle as (M. + 2) on Figs. 9 and 10 (Interrupt Timing),
2. If mask bits are clear, IRQ and FIRQ must be held low for three cycles to guarantee interrupt to be taken, although only one cycle is
necessary to bring the processor out of SYNC.
Opcode (Fetch)
Short
Branch
Indexed
Immediate
&
Inherent
Opcode +
Opcode +
ACCAOffset
ACCBOflset
R + 5 Bit
R + 8 Bit
PC + 8 Bit
wh
Auto
Auto R + 16Bit
Inc/Dec InclDec
By 1
By 2
VMA
VM
wk;
wk;
whwk.-vk
vkwkvk
VMA
Stack (Write)
Stack (Write)
410
PC + Ex tendltd No Offset
16-8it Indirect
VMA
-L.
VMA
ADDR
I
(NOTE)
R+D
i7MA
~~,~----~--~--~--~----+---~------------~---+----ff---ASLA
ASLB
ASRA
ASR6
CLRA
CLRB
COMA
COMB
DAA
DECA
DECB
INCA
INCB
LSLA
LSLB
LSRA
LSRB
NEGA
NEGB
NOP
ROLA
ROLB
RORA
RORB
SEX
TSTA
TSTB
ABX
RTS
EXG
TFR
MUL
SWI
PULU
PULS
PSHU
PSHS
RTI
CWAI
SWI2
SWI3
STACK
ADDR
12XSTACK
(wrr)
STACK 112
( IWrite) ~
STACK
STACK
wkI
VMA
V A
V"fA
STACK'
(Dumnjv Read)
VMA
VMA
ImA
VMA
VMA
12XSTACK
(Wre)
(VMA
II
1
VECTOR VECTOR
VECTOR, VECTOR
VMA
VJ;fA
I
I
nr~
STACK
(Write)
(NOTE) STACK':
STACK":
12
I~
Non-Implied
ADCA
ADCB
AOOA
AOOB
ANOA
ANDB
BITA
BITB
CMPA
CMPB
EORA
EORB
LOA
LOB
ORA
ORB
SBCA
SBCB
STA
STB
SUBA
SUBB
LDD
LOS
LOU
LOX
LOY
ANOCC
ORCC
ASL
ASR
CLR
COM
DEC
INC
LSL
LSR
NEG
ROL
ROR
TST
ADDD
CMPO
CMPS
CMPU
CMPX
CMPY
SUBD
JSR
STD
STS
STU
STX
STY
VMA
STACK
VM'A
VM'A
ADDR +
i~~b~
ADDR +
TAO'"rl~rr'
411
Operation
ADCA, ADCB
ADDA, ADDB
ANDA,ANDB
BITA,BITB
CMPA, CMPB
DAA
EORA, EORB
EXG Rl, R2
LOA, LOB
MUL
~emory
Negate accumulator or
ORA, ORB
SBCA,SBCB
STA, STB
SUBA, SUBB
TFR Rl, R2
(NOTE) A, 8, CC or DP may be pushed to (pulled from) either stack with PSHS, PSHU
(PULS, PULU) instructions.
Operation
ADDD
CMPD
EXG 0, R
Exchange 0 with X, Y, S, U or PC
LDD
SEX
STD
SUBD
TFR 0, R
Transfer 0 to X, Y, S, U or PC
TFR R,D
Transfer X, Y , S, U or PC to 0
(NOTE) 0 may be pushed (pulled) to either stack with PSHS, PSHU (PULS, PULU)
instructions.
412
Operation
CMPS, CMPU
CMPX, CMPY
EXG Rl, R2
Exchange 0, X, Y, S, U or PC with 0, X, Y, S, U or PC
LEAS, LEAU
LEAX, LEAY
LOS, LOU
LOX, LOY
PSHS
PSHU
PULS
PULU
STS, STU
STX, STY
TFR Rl, R2
Transfer 0, X, Y, S, U or PC to 0, X, Y, S, U or PC
ABX
Operation
BEQ, LBEQ
Branch if equal
SIMPLE BRANCHES
BNE, LBNE
BMI, LBMI
Branch if minus
BPL,LBPL
Branch if plus
BCS,LBCS
BCC,LBCC
BVS, LBVS
BVC, LBVC
BGT, LBGT
SIGNED BRANCHES
BGE, LBGE
BEQ, LBEQ
Branch if equal
BLE, LBLE
Branch if less than or equal (signed)
-----B-L-T-,-L-B-L-T-----4---B-ra-nch if less than (signed)
UNSIGNED BRANCHES
BHI, LBHI
BHS,LBHS
BEQ, LBEQ
Branch if equal
BLS, LBLS
BLO,LBLO
BSR,LBSR
Branch to subroutine
BRA, LBRA
Branch always
BRN, LBRN
Branch never
OTHER BRANCHES
413
Operation
ANDCC
CWAI
NOP
No operation
OReC
JMP
Jump
JSR
Jump to subroutine
RTI
RTS
SYNC
414
INSTRUCTION/
FORMS
IMPLIED
3A 3
OP
ABX
DIRECT
OP
EXTENDED
IMMEDIATE
OP
OP
INDEXEO<D
OP
RELATIVE
OP
1 0
V C
t
t
t
t
UN~G~ED)
ADCA
ADCB
99
D9
4
4
2
2
B9
F9
5
5
3
3
89
C9
2
2
2
2
A9 4+
E9 4+
2+
2+
A +
+ ---> A
B+M+C--->B
ADD
ADDA
ADDB
ADDD
9B
DB
D3
4
4
6
2
2
2
BB
FB
F3
5
5
7
3
3
3
8B
CB
C3
2
2
4
2
2
3
AB 4+
EB 4+
E3 6+
2+
2+
2+
A+M---> A
B + M---> B
D + M:M + 1---> D
AND
ANDA
ANDB
ANDCC
94
D4
4
4
2
2
B4
F4
5
5
3
3
84
C4
1C
2
2
3
2
2
2
A4 4+
E4 4+
2+
2+
ASL
AS LA
ASLB
ASL
48
58
2
2
1
1
ASRA
ASRB
ASR
47
57
2
2
1
1
t
t
t
t
t
t
t
t
AAM--->A
B AM ---> B
eCA IMM---> CC
t
t
t
t
t
t
t
t t
tt 00
t
t
t
t
t
t
t
t t
t t
08
78
68
6+
2+
07
77
67
6+
2+
~}~
@ t
@ t
@ t
BCC
BCC
lBCC
24
10
24
3
2
5(6) 4
Branch C=O
Long Branch
C=O
BCS
BCS
LBCS
25
10
25
2
3
5(6) 4
Branch C=1
Long Branch
C=1
BEQ
BEQ
LBEQ
BGE
BGE
LBGE
BGT
BGT
lBGT
2E
10
2E
2
3
5(6) 4
Branch ZV(N<lV)=O
Long Branch
ZV(N (BV)=O
BHI
BHI
lBHI
22
10
22
2
3
5(6) 4
Branch CVZ=O
Long Branch
CVZ=O
BHS
BHS
24
LBHS
10
24
BIT
BITA
BITB
BlE
BlE
lBlE
~ + X---> X
ADC
ASR
H N Z
DESCRIPTION
- #
3
2
\27
10 5(6) 4
27
2C
3
2
10 5(6) 4
2C
95
D5
4
4
2
2
B5
F5
5
5
3
3
85
C5
2
2
2
2
A5 4+
E5 4+
5(6) 4
2+
2+
2F
10
2F
3
2
5(6) 4
25
10
25
2
3
5(6) 4
Branch Z =1
Long Branch
Z==1
Branch N (BV=O
Long Branch
N(B V=O
Branch
C=O
Long Branch
C=Q
BitTestA(MAA)
Bit Test B (M AB)
B,,~h
ZVIN(j)VI-'
Long Branch
ZVIN (BV)=1
Branch C=1
Long Branch
C=1
Branch
CVZ=1
Long Branch
CVZ=1
I'
:.
BlO
BLO
LBLO
BLS
BLS
23
LBLS
10
23
5(6) 4
BLT
BLT
lBlT
2D
10
2D
2
3
5(6) 4
Branch N (BV=1
Long Branch
N (BV=1
BMI
BMI
lBMI
2B
10
2B
3
2
5(6) 4
Branch N=1
Long Branch
N=1
BNE
BNE
lBNE
26
'0
26
15161
2
4
BPL
BPl
lBPl
2
2A 3
10 5(6) 4
2A
BRA
BRA
lBRA
20
16
3
5
2
3
BRN
BRN
LBRN
21
10
21
3
5
2
4
Branch N = 0
long Branch
N=O
Branch Always
Long Branch/
Always
Branch Never
t
t
t
t
t
t
t t
0
0
t
t
t
(to be continued)
415
OP BSR
OP
OP -
OP
OP -
OP
-@
Branch V = 0
Long Branch
V=O
3
2
5(6) 4
Branch V = 1
Long Branch
V= 1
0-+ A
0- B
0-+ M
BVC
BVC
LBVC
28
10
28
BVS
BVS
LBVS
29
10
29
CLR
CLRA
CLRB
CLR
CMP
CMPA
CMPB
CMPD
CMPS
CMPU
CMPX
CMPY
COM
COMA
COMB
COM
CWAI
43
53
3C
DAA
2
2
20
19
4A
5A
2
2
OF
7F
91
D1
10
93
11
9C
11
93
9C
4
4
7
2
3
B1
F1
10
B3
11
BC
11
B3
BC
10
9C
03
5
8
10
BC
73
81
C1
10
83
11
8C
11
83
8C
10
8C
2
5
2
2
4
6F
6+
2+
A1
E1
10
A3
11
AC
11
A3
AC
4+
4+
7+
2+
2+
3+
7+
3+
7+
3+
6+
2+
10 7+
AC
3+
63
2+
1
1
Compare M from
Compare M from
Compare M: M +
from D
Compare M: M +
from S
Compare M: M +
from U
Compare M: M +
from X
Compare M: M +
from Y
0
0
0
1 0
1 0
1 0
0
0
0
A @ t
B @ t
1 t
t t
t t
t t
A-+ A
B
;.n-+M
B -+
6+
1 0
3
2
5(6) 4
17
8D
LBSR
H N Z V C
Branch to
Subroutine
Long Branch to
Subroutine
BSR
4F
5F
DESCRIPTION
CC 1\ IMM -+ CC
(except 1-+E)
Wait for Interrupt
Decimal Adjust A
t t
t t t
t t t
t 0
t 0
t 0
(-I-<I,Ho-
t
t
t
t
t
t
t
1
1
1
)
@ t
DEC
DECA
DECB
DEC
EOR
EORA
EORB
EXG
R1, R2
1E
R1 .... R2@
H-@)~
INC
INCA
INCB
INC
4C
5C
1
1
A+1-+A
B+1-+B
M+1-+M
EAQ, -+ PC
OA
7A
98
D8
4
4
2
2
B8
F8
5
5
3
3
3
88
C8
2
2
6A 6+
2+
A-1-+A
B-1-+B
M-1-M
A8 4+
E8 4+
2+
2+
AEf)M-+A
BEf)M-+B
t t
t
t
t
t t
t to.
t to.
t
t t t
t t t
OC
7C
6C
6+
2+
JMP
OE
7E
3+
2+
9D
7
4
4
5
BD
AD 7+
2+
Jump to Subroutine.
B6
F6
FC
10
FE
FE
BE
10
BE
3
3
3
6E
JSR
4
8
5
5
6
7
4+
4+
5+
6+
2+
2+
2+
3+
M-A
M-+B
M: M + 1 -+ D
M: M + 1 -+ S
6
6
A6
E6
EC
10
EE
EE
AE
10
AE
5+
5+
6+
2+
2+
3+
M: M + 1 -+ U
M: M + 1 -+ X
M: M + 1 -+ Y
32
33
30
31
4+
4+
4+
4+
2+
2+
2+
2+
EA@ ..... S
EA@- U
EA@-+ X
EA@-Y
A}
LD
LDA
LDB
LDD
LDS
96
D6
DC
10
DE
DE
9E
10
9E
LDU
LDX
LDY
2
3
5
5
6
2
2
3
3
4
86
C6
CC
10
CE
CE
8E
10
8E
2
2
3
4
3
3
4
2
3
4
3
3
4
LEA
LEAS
LEAU
LEAX
LEAY
LSL
LSLA
LSLB
LSL
48
58
LSRA
LSRB
LSR
44
54
2
2
1
1
3D
11
AxB-+D
(Unsigned)
40
50
2
2
1
1
A+1-+A
B+1-+B
LSR
MUL
NEG
NOP
NEGA
NEGB
NEG
2
08
78
68
6+
2+
04
74
64
6+
2+
00
12
70
60
6+
2+
t to.
t to.
t to.
t to.
t to.
t to.
t to.
0-.--'
t t t t
t t t t
~+1-+M
. t ~
t t t t
t t t t
Ii@.B'tttt
No Operation
(11)
(to be continued)
416
~-------.--------~--------._--------._------~.-------_4
IMPLIED
OP OR
PSH
ORA
ORB
ORCC
DIRECT
OP
9A
DA
4
4
EXTENDED
OP -
2
2
BA
FA
5
5
IMMEDIATE
OP
3
3
8A
CA
1A
2
2
3
INDEXEDCD
OP -
2
2
2
AA 4+
EA 4+
2+
2+
PSHS
ROR
ROLA
ROLB
ROL
49
59
RORA
RORB
ROR
46
2
2
1
1
56
RTI
3B 6/15
RTS
39
SBC
ST
SWI
SYNC
79
69
6+
2+
06
76
66
6+
2+
H N Z V C
AVM-A
BVM-B
CCV IMM - CC
t to.
) ) 0
(--CV
I-
~}q}M:
~19JiIDID.JY :
Return From
Interrupt
4
4
2
2
B2
F2
5
5
3
3
82
C2
2
2
2
2
A2 4+
E2 4+
2+
2+
STA
STB
STD
STS
SWI3@
92
02
10
SUBA
SUBB
SUBD
SWI
SWI2@
97
D7
DO
10
OF
OF
9F
10
9F
STU
STX
STY
SUB
09
SBCA
SBCB
SEX
PULS
PULU
ROL
DESCRIPTION
_ #
Push Registers on
S Stack
Push Registers on
U Stack
PSHU
PUL
RELATIVE
OP
90
DO
93
4
5
6
5
5
6
4
4
6
2
2
2
3
2
2
3
B7
F7
FD
10
FF
FF
BF
10
SF
5
5
6
7
6
6
3
3
BO
FO
B3
5
5
7
3
3
3
Return From
Subroutine
A-M-C-A
B-M-C-B
@ t
@ t
t
t
t
t
Sign Extend B
into A
2+
2+
2+
3+
A- M
B- M
0- M: M+ 1
5 -+ M: M + 1
t to.
t to.
t
t
5+
5+
6+
2+
2+
3+
U- M: M + 1
X- M: M + 1
Y- M: M + 1
t
t
t
AO 4+
EO 4+
A3 6+
2+
2+
2+
(ill t
(ij) t
to.
to.
to.
to.
to.
19
20
1
2
A-M-A
B-M-B
D - M: M + 1 - D
Software I nterrupt1
Software Interrupt2
t
t
t
20
Software I nterrupt3
13
~2
3F
10
3F
11
3F
2
2
2
80
CO
83
2
2
2
2
3
t
t
4+
4+
5+
6+
A7
E7
ED
10
EF
EF
AF
10
AF
3
3
3
! Ii
If:
Synchronize to
Interrupt
t
t
t
TFR
R1,R2
1F
R1 ~ R2'ID
(-r-- @)- )
TST
TSTA
TSTB
TST
40
50
2
2
1
1
Test A
Test B
Test M
00
70
6D 6+
2+
t
t
t
to.
to.
to.
(NOTES)
<D
This column gives a base cycle and byte count. To obtain total count, and the values obtained from the INDEXED ADDRESSING MODES table.
R1 and R2 may be any pair of 8 bit or any pair of 16 bit registers.
Tt!e 8 bit registers are: A, B, CC, DP
The 16 bit registers are: X, Y, U, S, 0, PC
@ EA is the effective address.
@ The PSH and PUL instructions require 5 cycle plus 1 cycle for each byte pushed or pulled.
@ 5(6) means: 5 cycles if branch not taken, 6 cycles if taken.
@ SWI sets 1 and F bits. SWI2 and SWI3 do not affect I and F.
(j) Conditions Codes set as a direct result of the instruction.
@ Value of half-carry flag is undefined.
Special Case - Carry set if b7 is SET.
@> Condition Codes set as a direct result of the instruction if CC is specified, and not affected otherwise.
LEGEND:
OP
Operation Code (Hexadecimal)
Z
Zero (byte)
Number of MPU Cycles
V
Overflow, 2's complement
C
Carry from bit 7
#
Number of Program Bytes
+
Arithmetic Plus
t
Test and set if true, cleared otherwise
Arithmetic Minus
Not Affected
X
Multiply
CC
Condition Code Register
~
Complement of M
Concatenation
V
Logical or
Transfer Into
H
Half-carry (from bit 3)
1\
Logical and
N
Negative (sign bit)
<>
Logical Exclusive or
@
417
Mnem
Mode
00
01
02
03
NEG
Direct
04
05
06
07
08
09
OA
OB
OC
00
OE
OF
COM
LSA
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
10
1E
1F
} See
Next Page
NOP
SYNC
20
21
22
23
24
25
26
27
28
29
2A
2B
2C
20
2E
2F
OP
Mnem
Mode
2
2
LEAX
LEAY
LEAS
LEAU
PSHS
PULS
PSHU
PULU
Indexed
30
31
32
33
34
35
36
37
38
39
3A
3B
3C
3D
3E
3F
AOA
ASA
ASL, LSL
AOL
DEC
INC
TST
JMP
CLA
#
6
Direct
Implied
Implied
LBAA
LBSA
Aelative
Aelative
DAA
OACC
Implied
Immed
ANDCC
SEX
EXG
TFA
Immed
Implied
;
Implied
BAA
BAN
BHI
BLS
BHS, BCC
BLO, BCS
BNE
BEQ
BVC
BVS
BPL
BMI
BGE
BLT
BGT
BLE
Aelative
Aelative
2
2
6
6
6
2
2
2
6
6
2
2
2
2
5
9
3
3
1
2
8
6
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
40
41
42
43
44
45
46
47
48
49
4A
4B
4C
40
4E
4F
50
51
52
53
2
2
54
55
2
2
56
57
58
59
5A
5B
5C
50
5E
5F
2
2
2
2
2
2
2
2
2
2
2
Indexed
Implied
4+
4+
4+
4+
5+
5+
5+
5+
OP
Mnem
Mode
60
61
62
63
64
65
66
67
68
69
6A
6B
6C
60
6E
6F
NEG
Indexed
5
3
ATS
ABX
ATI
CWAI
MUL
6,15
20
11
SWI
Implied
19
NEGA
Implied
COMA
LSAA
AOAA
ASAA
ASLA, LSLA
AOLA
DECA
2
2
2
2
2
2
2
CLAA
Implied
NEGB
Implied
COMB
LSAB
2
2
AOAB
ASAA
ASLB,LSLB
AOLB
DECB
2
2
2
2
2
INCB
TSTB
2
2
Implied
LEGEND:
~ Number of MPU cycles (less possible push pull or indexed-mode cycles)
# Number of program bytes
* Denotes unused opcode
418
70
71
72
73
INCA
TSTA
CLAB
#
2+
2+
2+
2+
2
2
2
2
75
76
77
78
79
7A
7B
7C
70
7E
7F
80
81
82
83
84
85
86
87
88
89
8A
88
8C
80
8E
8F
#
6+
2+
COM
LSA
6+
6+
2+
2+
AOA
ASA
ASL, LSL
AOL
DEC
6+
6+
6+
6+
6+
2+
2+
2+
2+
2+
INC
TST
JMP
CLA
Indexed
6+
6+
3+
6+
2+
2+
2+
2+
NEG
Extended
COM
LSA
7
7
3
3
AOA
ASA
ASL, LSL
AOL
DEC
7
7
7
7
7
3
3
3
3
3
INC
TST
JMP
CLA
7
7
4
7
3
3
3
3
2
2
2
4
2
2
2
2
2
2
SUBA
CMPA
SBCA
SUBD
ANDA
BITA
LOA
EOAA
ADCA
OAA
ADDA
CMPX
BSA
LOX
Extended
Immed
Immed
Aelative
Immed
2
2
2
2
4
7
3
3
2
2
2
2
2
2
2
3
2
(to be continued)
Mnem
Mode
90
91
92
93
94
95
96
97
98
99
9A
9B
9C
90
9E
9F
SUBA
CMPA
SBCA
SUBD
ANOA
BITA
LOA
STA
EORA
AOCA
ORA
ADOA
CMPX
JSR
LOX
STX
Direct
AO
Al
A2
A3
A4
AS
A6
A7
A8
A9
AA
AB
AC
AD
AE
AF
SUBA
CMPA
SBCA
SUBD
ANOA
BITA
LOA
STA
EORA
ADCA
ORA
ADOA
CMPX
JSR
LOX
STX
Indexed
BO
Bl
B2
B3
B4
B5
B6
B7
B8
B9
BA
BB
BC
BO
BE
BF
SUBA
CMPA
SBCA
SUBD
ANOA
BITA
LOA
STA
EORA
AOCA
ORA
ADOA
CMPX
JSR
LOX
STX
Extended
CO
Cl
C2
C3
C4
C5
SUBB
CMPB
SBCB
AOOD
ANOB
BITB
4
4
4
6
4
Direct
Indexed
OP
Mnem
Mode
2
2
CS
C7
C8
C9
CA
CB
CC
CO
CE
CF
LOB
Immed
2
2
2
4
4
4
4
4
4
4
6
7
2
2
2
2
2
2
2
5
5
2
2
4+
4+
4+
6+
4+
4+
4+
4+
4+
4+
4+
4+
6+
7+
5+
5+
2+
2+
2+
2+
2+
2+
2+
2+
2+
2+
2+
2+
2+
2+
2+
2+
5
5
5
7
5
5
5
5
5
5
5
5
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
8
Extended
6
6
'T~
2
2
2
4
Immed
2
2
2
2
2
2
2
3
2
2
EORB
ADCB
ORB
AOOB
LCD
I
I
LOU
Immed
00
01
02
03
04
05
06
07
08
09
OA
DB
DC
00
DE
OF
SUBB
CMPB
SBCB
AOOO
ANOB
BITB
LOB
STB
EORB
AOCB
ORB
AOOB
LOO
STO
LOU
STU
Direct
EO
El
E2
E3
E4
E5
E6
E7
E8
E9
EA
EB
EC
ED
EE
EF
SUBB
CMPB
SBCB
AOOO
ANOB
BITB
LOB
STB
EORB
AOCB
ORB
AOOB
LOO
STD
LOU
STU
Indexed
FO
Fl
F2
F3
F4
F5
F6
F7
F8
F9
FA
FB
SUBB
CMPB
SBCB
ADDD
ANDB
BITB
LOB
STB
EORB
ADCB
ORB
ADDB
Extended
j
Direct
Indexed
Extended
419
OP
Mnem
Mode
2
2
2
2
LOD
STD
LOU
STU
Extended
2
2
FC
FD
FE
FF
2
2
4
4
6
4
4
4
4
4
4
4
4
2
2
2
2
2
2
2
2
2
5
5
2
2
5
5
4+
4+
4+
6+
4+
4+
4+
4+
4+
4+
4+
4+
5+
5+
5+
5+
2+
2+
2+
2+
2+
2+
2+
2+
2+
2+
2+
2+
2+
2+
2+
2+
5
5
5
7
5
5
5
5
5
5
5
5
3
3
3
3
3
3
3
3
3
3
3
3
Extended
6
6
6
6
3
3
3
3
5
5(6)
5(6)
5(6)
5(6)
5(6)
5(6)
5(6)
5(6)
5(6)
5(S)
5(6)
5(6)
5(6)
5(6)
20
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
2
4
7
4
3
7
6
6
3
3
3
7+
7+
6+
6+
3+
3+
3+
3+
8
8
7
4
4
4
2 Bytes Opcode
1021
1022
1023
1024
1025
1026
1027
1028
1029
102A
102B
102C
1020
102E
102F
103F
1083
108C
108E
1093
109C
109E
109F
10A3
10AC
10AE
lOAF
10B3
10BC
lOBE
10BF
10CE
lODE
10DF
10EE
10EF
10FE
10FF
113F
1183
118C
1193
119C
11 A3
11 AC
11 B3
11 BC
~:~~
Relartive
LBLS
LBHS,LBCC
LBCS,LBLO
LBNE
LBEQ
LBVC
LBVS
LBPL
LBMI
LBGE
LBLT
LBGT
Relative
LBLE
Implied
SWI2
Immed
CMPD
CMPY
LOY
Immed
Direct
CMPD
CMPY
LOY
STY
Direct
CMPD
CMPY
LOY
Indexed
STY
CMPD
od
CMPY
LOY
STY
Extended
LOS
Immed
LOS
Direct
STS
Direct
LOS
Indexed
STS
Indexed
LOS
Extended
STS
Extended
SWI3
Implied
CMPU
Immed
CMPS
Immed
CMPU
Direct
CMPS
Direct
CMPU
Indexed
CMPS
Indexed
CMPU
Extended
CMPS
Extended
'"di~
E"r
4
6
6
6+
6+
7
7
20
5
5
7
7
7+
7+
8
8
3
3
3+
3+
4
4
2
4
4
3
3
3+
3+
4
4
(#1)
MPU
cycle
I cycle
Dead I
DMAcycle
MPU cycle
Dead
cycle
I I
Dead
cycle
DMA cycle
Assertion of
BAdelays
one clock
cVcle
3 cycles
6-13 cycles
I ~
1 or 2 cycles "High"
(This inactive level is ignored.)
DMA/BRE~~I__________~r____l~:----------------r----T----r----r-----------I
MPU
14 DMA cycles
DMA
BA.Bs---1j
I
I
~I ~__~__~rr--~-----------
LJj
I
I
I
I
Self Refresh
counter
I
I'
I
I
I
I
I
effective
420
----.I
\~
BA, BS
__
_____..JI
HD6809
(MPU)
BA
DMA transfer
request
DRQH
C f - - - E clock
'---7474
HD6844
(DMAC)
DGRNT
DMA acknowledge
(b) Restriction
"The number of transfer Byte per one DMA Burst
transfer must be less than or equal to 14."
(d)
421
t - - - - - - - - 1 4 cycles ----------1
H 06809 reverse
cycle steal
DMAfBAEQ
BA
HD6809r---~~~~~~----------------------------~~7T~--~~~--------------
cycle
DMA cycles
DMA cycles
MPU cycle is
excuted right
after DMA,
Bus confliction
occurs.
DGRNT
(BA)
----+-----{
HD6844
DMA cycles
DMA cycles
cycles
@)
(
422
(DC-40)
HD6809EP, HD68A09EP, HD68B09EP
PIN ARRANGEMENT
HALT
Vss 1
NMI
TSC
IRO
L1C
FIRO
BS
R"ES
AVMA
BA
Vee
Ao
BUSY
Al
A2
A3
R/W
HD6809E
01
A.
O2
03
As
o.
A7
05
06
A.
A,
AI.
07
Al5
Au
All
(Top View)
423
Symbol
Value
Unit
Supply Voltage
Vcc*
-0.3-+7.0
Input Voltage
Vin*
-0.3-+7.0
Topr
-20 - +75
Tstg
-55 - +150
c
c
Symbol
min
typ
Vcc*
4.75
5.0
5.25
Logic, Q, RES
VIL *
-0.3
0.8
VILC*
-0.3
0.4
2.0
Vcc*
4.0
Vcc*
Vcc* -0.75
Vcc* +0.3
Supply Voltage
Input Voltage
Logic
VIH*
RES
E
VIHC*
Topr
Operating Temperature
-20
max
unit
75
25
ELECTRICAL CHARACTERISTICS
DC CHARACTERISTICS (Vee = 5.0V 5%, Vss = OV, Ta
Item
Symbol
=-20 -
Test Condition
min
min
Unit
Logic, a
VIH
2.0
Vee
2.0
Vee
2.0
Vee
VIHR
4.0
Vee
4.0
Vee
4.0
Vee
VIHC
Vee
-0.75
Vee
+0.3
Vee
-0.75 -
Vee
+0.3
Vee
-0.75
Vee
+0.3
VIL
-0.3
0.8
-0.3
0.8
-0.3
0.8
VILC
-0.3
0.4
-0.3
0.4
-0.3
-2.5
2.5
-2.5
2.5
-2.5
-100
100
-100
100
-100
Logic. a. RES
Logic. a. RES
Input Leakage Current
lin
0 0 -0 7
Ao-Au. R/W
VOH
VOL
Vin = 0 - 5.25V.
Vee = max
Do - 07. Logic
Input, a. RES
Cin
/JA
100
/JA
2.4
ILoad = -145/JA.
Vee = min
2.4
2.4
2.4
!Load = -100iJA.
Vee = min
2.4
2.4
2.4
ILoad = 2mA.
Vee = min
0.5
1.0
Vin = OV.
Ta = 25C,
f= lMHz
Vin = OV.
Ta = 25C.
f= lMHz
10
30
10
0.5
0.5
15
50
30
15
10
1.0
15
15
pF
50
30
50
pF
15
10
15
pF-
2.0
MHz
10
/JA
100
/JA
E,a
0.1
1.0
0.1
1.5
0.1
00- 0 7
-10
10
-10
10
-10
100
-100
100
-100
Ta = 25C. VCC = 5V
424
-100
10
1.0
10
Frequency of Operation
ITSI
2.5
2.4
Output Capacitance
Ao-Au.R/W
0.4
2.4
Ao-Au, R/W,
BA. BS. LlC,
AVMA.BUSY
Cout
I Load = -205/JA.
Vee = min
Po
Power Dissipation
Input Capacitance
H068B09E
typ. max
min
RES
HD68A09E
typ. max
Symbol
Test
Condition
HD68A09E
HD6809E
min
typ
max
min
typ
max
HD68B09E
min
Cycle Time
tcyc
1000
tACC
695
440
330
60
140
140
10000 667
tDSR
80
tDHR
10
tDHW
30
tAH
20
20
Address Delay
tAD
tDDW
E Clock "Low"
tPWEL
450
200
9500
295
tpWEH
450
9500
280
tEr, tEf
25
o Clock "High"
o Rise and Fall Time
tpWOH
9500
tOr, tOf
25
E "Low" to 0 Rising
tEOl
200
tE02
200
130
o "High" to E Rising
130
E "High" to 0 Falling
tE03
200
130
o "Low" to E Falling
tE04
200
tpcs
200
tTSA
tTSR
tTSD
120
Fig. 1,2,
7-11,
13,14 and
17
450
200
10
30
280
10000 500
typ
max
10000
Unit
ns
ns
40
ns
10
ns
ns
ns
110
ns
110
ns
9500
210
9500
ns
9500
220
9500
ns
20
ns
ns
25
30
20
220
9500
25
20
ns
100
ns
100
ns
100
ns
9500
130
100
ns
140
110
ns
150
85
210
250
100
200
tCD
300
tPCr. tpCf
100
140
120
ns
110
ns
80
ns
200
ns
100
ns
R/IN
Addr
BA,BS* ____________
~~
Data
~------tCD----~~
BUSY,
Lie,
AVMA
~NotValid
* Hold time for BA, BS not specified
(NOTE)
Waveform measurements for all inputs and outputs are specified at logic "High" = V I Hmin and logic "Low" = V I Lmax unless otherwise specified.
~-------tpWOH------~
tOf
Q
R/W
Addr
BA,BS* __________~~
Data
Data Valid
BUSY,
Lie,
AVMA
~NotValid
* Hold time for BA, BS not specified
(NOTE)
Waveform measurements for all inputs and outputs are specified at logic "High"=VIHmln and logic "Low" = VILmax unless otherwise specified.
426
r-----
RES
NMI
FIRQ
IRQ
I-..--:lrr==~.... Lie
...---.AVMA
R/W
TSC
HALT
BA
L-_ _
BS
BUSY
'----- E
'-----Q
Figure 3 HD6809E Expanded Block Diagram
5.0 V
RL
Test Point
2.2 kn
()-.....-_---wl-~
PROGRAMMING MODEL
As shown in Figure 5, the HD6809E adds three registers to
the set available in the HD6800. The added registers include a
Direct Page Register, the User Stack pointer and a second
Index Register.
Accumulators (A, B, D)
The A and B registers are general purpose accumulators
which are used for arithmetic calculations and manipulation
of data.
Certain instructions concatenate the A and B registers to
form a single 16-bit accumulator. This is referred to as the D
Register, and is formed with the A Register as the most
significant byte.
427
15
x-
Index Register
V - Index Register
} Po;n'" R..;,,,,,,
Program Counter
J.,
Accumulators
I
IElF I H II I N I z I
0
V IC
Carry
Overflow
L......---Zero
~---- Negative
~----- IRO Mask
L......_ _ _ _ _ _ Half Carry
L......--------FIROMask
' - - - - - - - - - - - Entire Flag
Bit 0 is the carry flag, and is usually the carry from the
binary ALU. C is also used to represent a 'borrow' from
subtract like instructions (CMP, NEG, SUB, SBC) and is the
complement of the carry from the binary ALU.
Bit 1 (V)
Bit 2 is the zero flag, and is set to a one if the result of the
previous operation was identically zero.
Bit 3 (N)
428
Bit 4 (I)
Bit 4 is the IRQ mask bit. The processor will not recognize
interrupts from the IRQ line if this bit is set to a one. NMI,
FIRQ, IRQ, RES and SWI all set I to a one; SWl2 and SWI3
do not affect I.
Bit 5 (H)
Bit 6 (F)
Bit 6 is the FIRQ mask bit. The processor will not recognize
interrupts from the FIRQ line if this bit is a one. NMI, FIRQ,
SWI, and RES all set F to a one. IRQ, SWI2 and SWI3 do not
affect F.
FFFD
NMI
FFFA
FFFB
SWI
FFF8
FFF9
IRQ
FFF6
FFF7
FIRQ
FFF4
FFF5
SWI2
FFF2
FFF3
SWI3
FFFO
FFFl
Reserved
HALT
ReadlWrite (R!W)
RES
FFFC
A "Low" level on this input pin will cause the MPU to stop
running at the end of the present instruction and remain halted
indefmitely without loss of data. When halted, the BA output
is driven "High" indicating the buses are high impedance. BS
is also "High" which indicates the processor is in the Halt state.
While halted, the MPU will not ~nd ~ternal real-time
requests (FIRQ, IRQ) although NMI or RES will be latched
for later response. During the Halt state Q and E should
continue to run normally. A halted state (BA BS = 1) can be
achieved by pulling HALT "Low" while RES is still "Low". See
Figure 8.
LS
FFFF
MS
FFFE
Bit 7 (E)
Bit 7 is the entire flag, and when set to a one indicates that
the complete machine state (all the registers) was stacked, as
opposed to the subset state (pC and CC). The E bit of the
stacked CC is used on a return from interrupt (RTI) to determine the extent of the unstacking. Therefore, the current E
left in the Condition Code Register represents past action.
Interrupt Vector
Description
RES
BA
BS
o
o
Normal (Running)
SYNC Acknowledge
429
:z:
G)
CO
o
CD
!"
:z:
G)
CO
l>
CD
!"
G)
CO
OJ
R3
CD
Address
Data
New PCH New PCL
R/W
~
~
BA
BS
mmm
mm\\\\
..
AVMA
\, ____
BUSY
LIC
(NOTE)
Waveform measurements for all inputs and outputs are specified at logic "High" = VIHmin and logic "Low" = VILmax unless otherwise specified.
Figure 7
RES Timing
Halted
Halted
a
E
HALT
Address
Bus
Fetch
~
Execute
R/W
-I.
BA
_ _ _ _ _~/
BS _ _ _ _ _
~/
I
_~r----J:
Data
Bus
~---
----
AVMA
Lie
____~~
--------~/
Instruction
Opcode
CJ)
CO
CD
\~
__
!"
J:
C
CS)
CO
o
CD
(NOTE)
Waveform measurements for all inputs and outputs are specified at logic "High" = V IHmin and logic "Low" = V I Lmax unless otherwise specified.
!"
J:
0)
CO
OJ
CD
HD6809E, HD68A09E, HD68B09E-------------------------------------A negative transition on this input requests that a nonmaskable interrupt sequence be generated. A non-maskable
interrupt cannot be inhibited by the program, and also has a
higher priority than FIRQ, IRQ or software interrupts. During
recognition of an NMI, the entire machine state is saved on
the hardware stack. After reset, an NMI will not be recognized
until the first program load of the Hardware Stack Pointer (S).
The pulse width of NMI low must be at least one E cycle .. If
the NMI input does not meet the minimum set up with respect
to Q, the interrupt will not be recognized until the next cycle.
See Figure 9.
AVMA
NMI, FIRQ, and IRQ requests are sampled on the falling edge of Q.
One cycle is required for synchronization before these interrupts are
recognized. The pending interrupt(s) will not be serviced until
completion of the current instruction unless a ~YNC or CWAI
condition is present. If IRQ and FIRQ do not remain "Low" until
completion of the current instruction they may not be recognized.
However, ~ is latched and need only remain "Low" for one cycle.
Clock Inputs E, a
BUSY
Busy will be "High" for the read and modify cycles of a readmodify-write instruction and during the access of the first byte
TSC
TSC (Three-State Control) will cause MOS address, data,
and R/W buffers to assume a high-impedance state. The control
signals (BA, BS, BUSY, AVMA and LIC) will not go to the
high-impedance state. TSC is intended to allow a single bus to
be shared with other bus masters (processors or DMA controllers).
While E is "Low", TSC controls the address buffers and R/W
directly. The data bus buffers during a write operation are in a
high-impedance state until Q rises at which time, if TSC is
true, they will remain in a high-impedance state. If TSC is held
beyond the rising edge of E, then it wUl be internally latched,
keeping the bus drivers in a high-impedance state for the
remainder of the bus cycle. See Figure 14.
MPU Operation
432
last Cycle
of Current
Instruction
Instruction
Fetch
m-2 , m-1,
"
-I- -I
.I
n I n+1 I
-I..'
.,
".
-I
. -I'
"I'
E
Q
Data
==:)C:==:X::==)[:::J(:==:)~~~~~~;;;:~~:>C;~?<~~)[~~~~~~UiJ(IDP-~~:.t~cc~~CA~~~~~~~~~~~(\____#~
VMA
PCl
PCH
USl
USH
IYl
IYH
IXl
IXH
DP
ACCB ACCA
CCR
VMA
cw
cw
R/W~
New
PCH
New
PCl
VMA
_ __ _
B A J C : J C : )_____________________________________________________________________________________________
BS
.:x:::>e:::).
1\
BUSY :::).
AVMA
LlC
\'-_____________
c=
,'-_ _ __
0)
CO
CD
!"
%
C
CJ)
(NOTE)
Waveform measurements for all inputs and outputs are specified at logic "High" = VIHmin and logic "low" = VILmax unless otherwise specified.
E clock shown for refer.ence only.
CO
o
CD
!"
%
C
0)
CO
aJ
CD
l:
G)
last Cycle
of Current
Instruction
l" m -- 11 1_
Instruction
Fetch
!------4-
l. m - 2
00
m+1
l" m + 3
l,m+2
m+4
m+s
m+6.,
ll
U)
_I
m+8.
m+9
I.
!1'1
n+1./
l:
G)
00
U)
!1'1
l:
PC
PC
FFFF
SP-l
SP-2
SP-3
$FFFF
$FFF6
$FFF7
$FFFF
G)
00
OJ
U)
FIRQ
Data
\7MA
.J:o..
VJ
.J:o..
R/W
BA
BS
PCl
PCH
CCR
VMA
New PCH
New PCl
VMA
~~--------------------------
\~--------
AVMA
BUSY
llC
:=A
----~I
1."--_
\~_____
,(NOTE)
Waveform measurements for a" inputs and outputs are specified at logic "High" = V'Hmin and logic "low" = V'Lmax unless otherwise specified_
E clock shown for referenNl onlv_
..-....- - - - - - - - - , 74LS73
o
(AI
(BI
0..-....-+--4
Start of
Cycle
E~______~~_______/
End of
Cycle
% Cycle
% Cycle
% Cycle
O~_ _--JJ
,-----
~--------------Figure 11
Memory
Location
PC~
Memory
Contents
--
Contents Description
$0200
$68
$0201
$9F
$0202
$63
$0203
$00
$0204
--...
$6300~
$6301~
$E3D6~
T"got 0 ...
435
%
C
Last Cycle of
Current Instr.
m-1
G)
m+1
m+2
m+3
m+4
m+5
m+6
m+7
m+ 8
m+9
m+10
-I
CD
o
U)
,!TI
:J:
G)
Address
CD
oU)
Data
$00
VMA
$06
$E3
VMA
$5C
VMA
BUSY
LIC
I
\~
AVMA
Waveform measurements for all inputs and outputs are specified at logic "High" = VIHmin and logic "Low" = VILmax unless otherwise specified.
t;
en
R/W Addr
(NOTES) Data will be asserted by the MPU only during the interval while R/W is "Low" and E or is "High".
Waveform measurements for all inputs and outputs are specified at logic "High" = V IHmin and logic "Low" = V I Lmax unless otherwise specified.
____
-----------------------------------------------------------------------------,
(NOTE)
,!TI
$B8
,-----
G)
CD
o
U)
m
'fiIm.1!
J:o.
c..>
'"
%
C
G)
00
o
C&)
!"
%
C
G)
Bus State
Running
Interrupt or Reset Acknowledge
Sync Acknowledge
Halt Acknowledge
(NOTES) 1. Asserting RES will result in entering the reset
sequence from any point in the flow chart.
2. BUSY is "High" during first vector fetch cycle.
BA
0
0
BS
0
,1
00
o
C&)
!"
%
C
G)
00
m
o
C&)
Figure 15 Flowchart for HD6809E Instruction
Direct Addressing
Register Addressing
Immediate Addressing
Indexed Addressing
Indexed
Addressing
Mode
Extended Addressing
In Extended Addressing, the contents of the two bytes immediately following the opcode fully specify the 16-bit effective
address used by the instruction. Note that the address generated
by an extended instruction defines an absolute address and is
not position independent. Examples of Extended Addressing
include:
LDA CAT
STX MOUSE
LDD $2000
R
R
0
i
0
0
0
0
0
0
1
1
0
i
Extended Indirect
0
0
0
0
0
0
1
1
1
0
0
0
1
1
0
0
EA
= ,R + 0 Offset
EA = ,R + ACCB Offset
EA
= ,R + ACCA Offset
=, R + B Bit Offset
= ,R + 16 Bit Offset
EA
0
1
EA
0
0
EA = ,R + 0 Offset
EA
L-
EA
L---_ _ _ _ _
:~~~e~:t ~~~n
b7 = 0)
438
Forms
Auto Increment/Decrement R
R = X, Y, U or S
x
No Offset
,R
5 Bit Offset
a Bit Offset
n, R
n,R
16 Bit Offset
A Register Offset
B Register Offset
n,R
A,R
D Register Offset
D,R
,R +
B,R
Increment By 1
Increment By 2
Decrement By 1
Decrement By 2
8 Bit Offset
,- - R
n, PCR
16 Bit Offset
n, PCR
16 Bit Address
Extended Indirect
Assembler
Form
,R ++
, -R
+ +
Postbyte
OP Code
-#
lRR00100
ORRnnnnn
a a
1 a
1 RR01000
1 RR0100l
1 RROOll0
1 RR00101
1 1
4 2
1 a
1 a
lRR010ll
1 RROOOOO
1 RROOOOl
1 RROOOl 0
1 RROO011
lxxOl100
lxxOl101
-
a
a
a
a
a
3
2
3
1 1
5 2
- -
Assembler
Form
Indirect
Postbyte
OP Code
LR]
defaults
[n, RJ
[n, RJ
[A, R]
+ +
1 RR10l00
-a
to a-bit
1 RRll000
4 1
[B, RJ
1 RRll00l
1 RR10ll0
1 RR10101
[0, RJ
lRRll011
a
a
a
not allowed
LR + +]
lRR10001
not allowed
1 RR100l1
L - - R]
[n,PCR]
lxxl1100
[n, peR]
lxxl1101
[n]
10011111
7 2
4
4 1
a 2
5 2
RR:
= Don't Care
OO=X
01 = Y
10= U
11 = S
~ and #- indicate the number of additional cycles and bytes for the particular variation.
Zero-Offset Indexed
In this mode, the selected pointer register contains the
effective address of the data to be used by the instruction.
This is the fastest indexing mode.
Examples are:
LOO
O,X
LOA
S
Constant Offset Indexed
In this mode, a two's-complement offset and the contents
of one of the pointer registers are added to form the effective
address of the operand. The pointer register's initial content is
unchanged by the addition.
Three sizes of offsets are available:
5-bit (-16 to +15)
8-bit (-128 to +127)
16-bit (-32768 to +32767)
The two's complement 5-bit offset is included in the postbyte and, therefore, is most efficient in use of bytes and cycles.
The two's complement 8-bit offset is contained in a single byte
following the postbyte. The two's complement 16-bit offset is
in the two bytes following the postbyte. In most cases the
programmer need not be concerned with the size of this offset
since the assembler will select the optimal size automatically.
Examples of constant-offset indexing are:
23,X
LOA
LOX
-2,S
LOY
LOU
300,X
CAT, Y
Accumulator-Offset Indexed
This mode is similar to constant offset indexed except that
the two's-complement value in one of the accumulators (A, B
or 0) and the contents of one of the pointer registers are added
to form the effective address of the operand. The contents of
both the accumulator and the pointer register are unchanged
by the addition. The postbyte specifies which accumulator to
use as an offset and no additional bytes are required. The
advantage of an accumulator offset is that the value of the
offset can be calculated by a program at run-time.
Some examples are:
LOA
B, Y
LOX
O,Y
LEAX B,X
Auto Increment/Decrement Indexed
In the auto increment addressing mode, the pointer register
contains the address of the operand. Then, after the pointer
register is used it is incremented by one or two. This addressing
mode is useful in stepping through tables, moving data, or
for the creation of software stacks. In auto decrement, the
pointer register is decremented prior to use as the address of
the data. The use of auto decrement is similar to that of auto
increment; but the tables, etc., are scanned from the high to
low addresses. The size of the increment/decrement can be
either one or two to allow for tables of either 8- or 16-bit data
to be accessed and is selectable by the programmer. The preA'lQ
Indexed Indirect
$Fl
$50
$F150
$AA
After Execution
A = $AA (Actual Data Loaded)
X= $FOOO
CAT
DOG
LBEQ
LBGT
RAT
RABBIT
NOP
NOP
RAT
RABBIT
(long)
(long)
Relative Addressing
CC
'----- B
' - - - - - - DP
'-------x
'--------y
, - - - - - - - - stu
' - - - - - - - - - - PC
+- Pull Order
Push Order -+
PC
U
Y
X
DP B
A 'CC
FFFF ....... +- increasing memory address ....... 0000
PC
S
Y
X
DP B
A
CC
,440
TFR/EXG
Instruction
LEAX
LEAX
LEAY
LEAY
LEAU
LEAS
LEAS
LEAX
10, X
500, X
A, Y
0, Y
-10, U
-10, S
10, S
5, S
Operation
Comment
X + 10 ~ X
X + 500 ~ X
Y+A ~Y
Y+0 ~Y
U - 10 ~ U
S - 10 ~ S
S + 10 ~ S
S+5 ~ X
FO~RC~
IDE~TI~ATI:ON I
LEAX/LEA YILEAU/LEAS
FCC
'MESSAGE'
MUL
441
$8000
LBSR
Address
8000
8001
8002
FFFF
AOOO
FFFF
AOOO
CAT
5
$ AOOO
6
7
CAT
CYCLE-BY-CYCLE FLOW
Cycle #
1
2
3
4
5
6
7
8
9
DEC
FCB
Address
8000
8001
8002
FFFF
FFFF
FFFF
FFFF
EFFF
EFFE
Date
17
20
00
*
*
*
*
80
03
R/W
1
1
1
1
1
1
1
0
0
Description
Opcode Fetch
Offset High Byte
Offset Low Byte
VMACycie
VMACycle
WACycle
WACycle
Stack High Order
Byte of Return
Address
Stack Low Order
Byte of Return
Address
$AOOO
$80
CYCLE-BY-CYCLE FLOW
Date
R/W
Description
7A
1
Opcode Fetch
AO
1
Operand Address,
High Byte
Operand Address,
00
Low Byte
1
WACycle
*
1
80
Read the Data
1
Wi\Cycle
*
7F
Store the Decreo
mented Data
the data at that particular address.
442
Last Cycle
Sync
of Previous Opcode
Iinstruction, Fetch
Execute
I
I
Last Cycle
of Syn.c
Iinstructlon,
Sync Acknowledge
"
E
Q
Address
Data
Rm~
~
~
BA==:A
BS ==:A
AVMA~
Lie
IRQ
NMI
FI~
,,
\~-------------------
\
...
\
~~
~
i
m~~tPCf
See Note 1
Vm~L~il
V
_ __~s=ee~N~0~te~2~______________________________
IL
~~
:t
C
en
CD
CD
!"
(NOTES) 1. If the associated mask bit is set when the interrupt is r~sted, L1C will go "Low" and this cycle will be an instruction fetch from address
location PC + 1. However, if the interrupt is accepted (NMI or an unmasked FI RQ or iRQ) L1C will remain "High" and interrupt processing
will start with this cycle as 1m) on Fi~re 9 and 10 (Interrupt Timing).
2. If mask bits are clear; IRQ and FIR must be held "Low" for three cycles to guarantee that interrupt will be taken, although only one cycle
is necessary to bring the processor out of SYNC.
3. Waveform measurements for all inputs and outputs are specified at logic "High" = VIHmin and logic "Low" = VILmax unless otherwise
specified.
:t
C
en
CD
J>
o
CD
!"
:t
C
en
CD
CD
CD
::I:
C
Fetch)
G)
00
o
CD
!"I
Opcode (Fetch)
::I:
C
G)
00
Long
Branch
Short
Branch
J>
Immeciia1te and
Implied
Indexed
r--
CD
!"I
Auto
Auto
Opcode +
Inc/Dec Inc/Dec
by1
by2
R + 16 Bits
R+D
Opcode +
VMA
Opcode +
VMA
I
VMA
Extended
Indirect
Offset
ACCA
ACCB
R + 5 Bit
R + 8 Bit
PC + 8 Bit
::I:
G)
m
o
CD
Opcode + Opcode +
VMA
VMA
VMA
VMA
VMA
VMA
VMA
VMA
VMA
VMA
VMA
No
Offset
00
VMA
~
~
~
PC+
16 Bits
VMA
I
VMA
Stack Write
I
Stack Write
VMA
(NOTE)
1. Busy '"' "High" during access of first byte of double byte immediate load.
2. Write operation during store instruction. Busy '"' "High" during first two cycles of a double-t>yte access and the first cycle of read-modify-write access.
3. AVMA is asserted on the cycle before a VMA cycle.
T~+
VMA
Implied Page
0'1
ASLA
ASLB
ASRA
ASRB
CLRA
CLRB
COMA
COMB
DAA
DECA
DECB
INCA
INCB
LSLA
LSLB
LSRA
LSRB
NEGA
NEGB
NOP
ROLA
ROLB
RORA
RORB
SEX
TSTA
TSTB
ABX
RTS
TFR
EXG
PSHU
PSHS
MUL
RTI
CWAI
STACK (R)
I
VMA
VMA
VMA
VMA
VMA
VMA
VMA
STACK (R)
STACK (R)
VMA
SWI
SWI2
SWI3
ADDR
VMA
VMA
VMA
VMA
VMA
PULU
PULS
VMA
~SP
\2
VMA
-V!A
VJA
VMA
VMA
VMA
ADDR ~SP
VMA
ADDR
VMA
VMA {S k (W)} 1?
VMA tac
0
VMA
(Note 3)
VMA
{Stack (R)}
(Note 3) 0
VMA
STACK(W)
STACK (W)
STACK (W)
STACK (W)
STACK (W)
STACK (W)
STACK (W)
STACK (W)
STACK (W)
STACK (W)
STACK (W)
STACK(W)
STACK (W)
STACK (W)
STACK (W)
STACK (W)
STACK (W)
STACK (W)
STACK (W)
STACK (W)
STACK (W)
STACK (W)
ADDR~SP
VMA
E=
.,
STACK (R)
STACK (R)
~TACK
(Note 4)
BUSY~1
..
..
(R)
(R)
(R)
(R)
(R)
(R)
(R)
(R)
(R)
STACK (R)
STACK (R)
00
VMA ~
STACK
STACK
STACK
STACK
STACK
STACK
STACK
STACK
l:
ADDR ~SP
Cb
CO
o
U)
VMA
VMA
,!11
l:
0)
CO
~
o
U)
(NOTES)
1. Stack (W) refers to the following sequence: SP ~ SP - 1, then ADDR ~ SP with R/W = "Low"
Stack (R) refers to the following sequence: AD DR ~ SP with R/W = "High", then SP ~SP + 1.
PSHU, PULU instructions use the user stack pointer (i.e., SP = U) and PSHS, PULS use the hardware stack pointer (i.e., SP = SI.
2. Vector refers to the address of an interrupt or reset vector (see Table 11.
3. The number of stack accesses will vary according to the number of bytes saved.
4. VMA cycles will occur until an interrupt occurs.
,!11
l:
Cb
CO
gI
o
U)
:::c
at
Non Implied
GO
o
CD
!"
:::c
ADCA
ADCB
ADDA
AD DB
ANDA
ANDB
BITA
BITB
CMPA
CMPB
FORA
FORB
LOA
LOB
ORA
ORB
SBCA
SBCB
STA
STB
SUBA
SUBB
LDD
LOS
LOU
LOX
LOY
ASL
ASR
CLR
COM
DEC
INC
LSL
LSR
NEG
ROL
ROR
ANDCC
ORCC
JSR
ADDD
CMPD
CMPS
CMPU
CMPX
CMPY
SUBD
TST
STD
STS
STU
STX
STY
at
GO
~
CD
!"
:::c
VMA
STACK(W)
STACK (W)
at
GO
m
o
CD
~
~
ADDR+
WA'
ADDR+
VMA
ADDIR+(W)
VMA
__ J
(NOTES)
1. Sta.:k (W) refers to the following sequence: SP +- SP - 1, then ADDR +- SP with R/W = "Low"
Sta.:k (R) refers to the following sequence: ADDR +- SP with R/iii = "High", then SP +- SP + 1.
PSl-tU, PULU instructions use the user stack pointer (i.e., SP = U) and PSHS, PULS use the hardware stack pointer (j.e., SP
2. Vec:tor refers to the address of an interrupt or reset vector (see Table 1).
3. The number of stack accesses will vary according to the number of bytes saved.
4. VMA cycles will occur until an interrupt occurs.
= SI.
Operation
AOCA, AOCB
AODA,ADDB
ANDA,ANDB
ASL,ASLA,ASLB
BITA, BITB
CLR,CLRA,CLRB
CMPA, CMPB
DAA
DEC,DECA,DECB
EORA, EORB
EXG R1, R2
LOA, LOB
MUL
Unsigned multiply (A x B ~ D)
ORA,ORB
ROL,ROLA,ROLB
SBCA, SBCB
STA, STB
SUBA, SUBB
TST,TSTA,TSTB
TFR R1, R2
(NOTE) A, B, CC or DP may be pushed to (pulled from) either stack with PSHS, PSHU
(PULS, PULU) instructions.
Mnemonic(s)
AODD
CMPD
EXG 0, R
Exchange D with X, V, S, U or PC
LDD
SEX
STD
SUBD
TFR D, R
Transfer 0 to X, V, S, U or PC
TFR R,D
Transfer X, V, S, U or PC to 0
(NOTE) D may be pushed (pulled) to either stack with PSHS, PSHU (PULS, PULU)
instructions.
447
Mnemonic(s)
Operation
CMPS,CMPU
CMPX,CMPY
EXG Rl,R2
Exchange 0, X, Y, S, U or PC with 0, X, Y, S, U or PC
LEAS, LEAU
LEAX, LEAY
LOS, LOU
LOX, LOY
PSHS
PSHU
PULS
PULU
STS, STU
STX, STY
TFR Rl, R2
Transfer 0, X, Y, S, U or PC to 0, X, Y, S, U or PC
ABX
Operation
SIMPLE BRANCHES
BEQ, LBEQ
Branch if equal
BNE,LBNE
BMI, LBMI
Branch if minus
BPL,LBPL
Branch if plus
BCS,LBCS
BCC,LBCC
BVS, LBVS
BVC,LBVC
BGT,LBGT
SIGNED BRANCHES
BGE,LBGE
BEQ, LBEQ
Branch if equal
BLE,LBLE
BLT,LBLT
BHI, LBHI
BHS,LBHS
UNSIGNED BRANCHES
BEQ, LBEQ
Branch if equal
BLS, LBLS
BLO,LBLO
BSR,LBSR
Branch to subroutine
BRA, LBRA
Branch always
BRN, LBRN
Branch never
OTHER BRANCHES
448
Mnemonic(s)
ANDCC
CWAI
NOP
No operation
ORCC
JMP
Jump
JSR
Jump to subroutine
RTI
RTS
SYNC
449
EXTENDED IMMEDIATE
DIRECT
OP
OP -
ADCA
ADCB
99
09
4
4
2
2
B9
F9
ADD
ADDA
ADDB
ADDD
9B
DB
03
4
4
6
2
2
2
AND
ANDA
ANDB
ANDCC
94
4
4
2
2
OP
A8X
ADC
ASL
ASR
3A 3
#
1
04
ASLA
ASLB
ASL
48
ASRA
ASRB
ASR
47
57
58
2
2
2
2
OP
5
5
3
3
89
C9
BB
FB
F3
5
5
7
3
3
3
B4
F4
5
5
3
3
INDEXED(I)
RELATIVE
2
2
A9 4+
E9 4+
2+
2+
A+ + B+M+C-B
8B
CB
C3
2
2
4
2
2
3
AB 4+
EB 4+
E3 6+
2+
2+
2+
A+M-A
B+M- B
D+M:M+1-D
84
C4
1C
2
2
3
2
2
2
A4 4+
E4 4+
2+
2+
AAM-A
B AM- B
CCA IMM- CC
5 3
DESCRIPTION
OP
OP
-(~
UN~G~ED~
t t t
t t t
t t t
t t t
t t
t t
t t
( - - (1)
08
78
68
6+
2+
07
77
67
6+
2+
1
1
\..~)
\It)
BCC
BCC
LBCC
24
10
24
3
2
5(6) 4
BCS
BeS
LBCS
25
10
25
3
2
5(6) 4
BEQ
BEQ
LBEQ
BGE
BGE
LBGE
27
3
2
10 5(6) 4
27
2C 3
2
10 5(6) 4
2C
BGT
BGT
lBGT
2E
10
2E
3
2
5(6) 4
Branch ZVIN$V)-O
Long Branch
ZV(N $VI=O
BHI
BHI
LBHI
22
10
22
2
3
5(61 4
Branch CVZ=O
Long Branch
CVZ=O
BHS
BHS
24
LBHS
10
24
BIT
BITA
BITB
95
D5
4
4
2
2
B5
F5
5
5
3
3
85
C5
2
2
2
2
AS 4+
E5 4+
2+
2+
Branch C-O
Long Branch
C)= 0
Branch C=1
Long Branch
C,. 1
Branch Z = 1
Long Branch
Z=1
Branch N $V=O
long Branch
N$V=O
Branch
C=O
Long Branch
C=O
Bit Test A (M AAI
Bit Test B (M I\B)
2F
10
2F
3
2
5(6) 4
Branch ZVCN$V)-1
Long Branch
ZVIN $V)=1
BLO
BLO
LBLO
25
10
25
2
3
5(61 4
BLS
BLS
23
lBLS
10
23
Branch C=1
Long Branch
C=1
Branch
CVZ=1
Long Branch
CVZ=1
BLT
BLT
LBLT
20 3
2
10 5(6) 4
20
Branch N $V=1
long Branch
N $V=1
6Mi
6ivii
LBMI
2B
10
2B
BNE
BNE
LBNE
26
10
26
Branch N'"
Long Branch
N"1
Branch Z =0
long Branch
Z-O
BPL
BPL
LBPL
2A 3
2
10 5(61 4
2A
BRA
BRA
LBRA
20
16
3
5
2
3
BRN
LBRN
21
10
21
3
5
2
4
5(6) 4
5(6) 4
3
2
5(6) 4
t
t
BLE
LBLE
Branch N" 0
Long Branch
N-O
Branch Alwavs
Long Branch/
Alwavs
Branch Never
t
t
t t
t t
t
0
0
~H
t t t
t t t
t t t
t
t
t
t
t t
BlE
BRN
(I)
5(61 4
1 0
fl+X- X
1
1
H N Z V C
t 0
t 0
It
"
(to be continued)
450
INS~~~~~ON/:==IM:P=L=I:E=D=:==D:I=R=E=C:T==:=E=X:T=E=N:D=E=D:=I=M=M:E=D=I:A=T=E:==IN=D:E=X=E:D=U=~:=R=E:L=A:T:IV:=E~
#
OP -
OP
OP -
OP
OP -
OP
BSR
80
LBSR
17
BVC
BVC
LBVC
28
10
28
BVS
BVS
LBVS
29
BSR
10
29
CLR
CMP
CLRA
CLRB
CLR
4F
5F
2
2
CMPA
CMPB
CMPD
CMPS
OF
7F
91
01
10
93
11
4
4
7
2
2
3
B1
F1
10
B3
11
BC
11
B3
BC
5
5
8
3
3
CMPU
11
93
CMPX
9C
CMPY
10
10
BC
73
9C
9C
COM
COMA
COMB
COM
CWAI
DAA
DEC
DECA
DECB
DEC
43
53
3C
20
19
4A
5A
1E
INC
INCA
INCB
INC
4C
5C
2
2
1
1
OA
7A
98
08
2
2
B8
F8
5
5
3
3
:4
4+
4+
7+
2+
2+
3+
7C
JMP
OE
JSR
90
96
LOA
LOB
LDD
LOS
06
DC
10
DE
DE
9E
10
9E
LOU
LOX
LOY
LEA
LEAS
LEAU
LEAX
LEAY
LSL
LSLA
LSLB
LSL
48
58
2
2
LSR
LSRA
LSRB
LSR
44
54
3D
11
40
2
2
1
1
3+
6+
2+
3+
63
2+
6+
88
C8
2
2
Branch V = 0
Long Branch
V=O
Compare M from
Compare M from
Compare M: M +
from 0
Compare M: M +
from S
Compare M: M +
from U
Compare M: M +
from X
Compare M: M +
from Y
t
t
0
0
1
1
1
2
2
5
6
@ t
t
t
t
t
t
t
t
t
t to.
t to.
(--- @ll-- )
6A 6+
2+
A8 4+
E8 4+
2+
2+
AeM--+A
BeM--+8
A+1-A
8+1-B
M+1--+ M
EA@--+ PC
6E
3+
2+
AD 7+
2+
B6
F6
FC
10
FE
FE
BE
10
BE
5
5
6
7
3
3
3
4
4+
4+
5+
6+
2+
2+
2+
3+
M--+A
M-8
M: M+ 1 - 0
M: M+ 1--+ S
3
3
A6
E6
EC
10
EE
EE
AE
10
AE
5+
5+
6+
2+
2+
3+
M: M + 1- U
2+
2+
2+
2+
EA@-->
EA@--+
EA@--+
EA@ .....
3
3
4
3
3
4
4+
4+
4+
4+
t
t
6
7
t
t
t
A-1-A
B-1-B
M-l--+M
BD
3
4
(--CD
7E
3
4
0
0
0
CC 1\ IMM - CC
(except 1-E) .
Wait for Interrupt
Decimal Adjust A
2+
CC
1 0
1 0
1 0
t
t
M-+M
6+
10
CE
CE
8E
10
8E
0
0
0
A t
B t
1 t
B-8
6C
2
2
V=1
0 ..... A
0 ..... 8
O->M
2
2
Branch V = 1
Long Branch
86
C6
t
t
Jump to Subroutine.
M: M + 1 -
t t t
t t
M: M+ 1--+ Y
S
U
X
to.
t to.
t to.
t to.
to.
to.
to.
t t
t t t
t t t
t t
t t
08
78
68
6+
2+
~}~.:
04
74
64
6+
2+
~\'iJIIIIIIJ-o: g
itt
t t t
t t
t
t
AxB-D
(Unsigned)
A+ 1 - A
6+1-B
00
12
3+
7+
10 7+
AC
32
33
30
31
50
7+
Branch to
Subroutine
Long Branch to
Subroutine
Rl-R2@
OC
NOP
A1
E1
10
A3
11
AC
11
A3
AC
R1, R2
NEGA
NEGB
NEG
2
2
4
EXG
NEG
10
8C
2
2
5
2+
5(6) 4
H N Z V C
A ..... A
03
EORA
EORB
MUL
81
C1
10
83
11
8C
11
83
8C
6+
2
2
EOR
LD
6F
3
2
5(6) 4
DESCRIPTION
-@
70
60
6+
2+
~+1-M
No Operation
@ t
(to be continued)
451
OP OR
PSH
PUL
ROL
ROR
ORA
ORB
ORCC
PSHS
34 5+@
PSHU
36
5+@
PULS
35
5+@ 2
5+@ 2
PULU
37
ROLA
ROLB
ROL
49
59
RORA
RORB
ROR
46
56
2
2
2
2
DIRECT
EXTENDED
OP
OP
9A
DA
4
4
2
2
BA
FA
5
5
IMMEDIATE
OP
3
3
8A
CA
1A
2
2
3
INDEXED<D
OP
2
2
2
AA 4+
EA 4+
RELATIVE
OP
DESCRIPTION
2+
2+
AVM ..... A
BVM ..... B
CCV IMM ...... CC
Push Registers on
S Stack
Push Registeis on
U Stack
1 0
H N Z
V C
0
0
t
t
(-I""-
(7) f--r)
1
1
09
79
69
6+
2+
06
76
66
6+
2+
1
1
t
t
t
t
t
t
t
t
t
~)co.
t
t
t
t
t
t
t
t
RTI
3B 6/15
Return From
Interrupt
RTS
39
Return From
Subroutine
2+
2+
A-M-C ..... A
B-M-C ..... B
(Q)
(Q)
t
t
t
t
2+
2+
2+
3+
t
I
I
t
t
t
I
I
0
0
0
0
5+
5+
6+
2+
2+
3+
U ...... M: M+ 1
X ...... M: M+ 1
Y ...... M: M+ 1
4+
4+
5+
6+
Sign Extend B
into A
A ..... M
B--+ M
D--+ M: M+ 1
S--+ M: M + 1
t
I
I
I
I
t
0
0
0
AO 4+
EO 4+
A3 6+
2+
2+
2+
I
I
!
t
!
!
t
t
t
SBC
SBCA
SBCB
92
D2
1D
SEX
ST
STA
STB
STD
STS
SWI
SUBA
SUBS
SUBD
SWI@
SWI2@
SWI3@
SYNC
2
2
B2
F2
5
5
3
3
82
C2
2
2
2
2
A2 4+
E2 4+
STU
STX
STY
SUB
4
4
97
07
DD
10
DF
DF
9F
10
9F
4
4
5
6
2
2
2
3
5
5
6
2
2
3
90
DO
93
4
4
6
2
2
2
B7
F7
FD
10
FF
FF
BF
10
BF
5
5
6
7
3
3
3
4
6
6
7
3
3
4
5
5
7
3
3
3
A7
E7
ED
10
EF
EF
AF
10
AF
19
20
1
2
A-M ...... A
II!' I
(8)
B-M ...... B
I
D - M: M + 1 ...... D
I
Software I nterrupt1
Software Interrupt2
20
Software Interrupt3
13 L2
3F
10
3F
11
3F
TFR
R1,R2
1F
TST
TSTA
TSTB
TST
4D
5D
2
2
1
1
BO
FO
B3
80
CO
83
2
2
4
2
2
3
t
t
t
t
Synchronize to
Interrupt
R1 ...... R2'~
OD
7D
6D 6+
2+
Test A
Test B
Test M
( - - <!Ii)f-- )
I
t
I
I
t
0
0
0
(NOTES)
CD This column gives a base cycle and byte count. To obtain total count, and the values obtained from the INDEXED ADDRESSING MODES table.
R1 ami R2 may be any pair of 8 bit or any pair of 16 bit registers.
The 8 bit registers are: A, B, CC, DP
The 16 bit registers are: X, Y, U, S, D, PC
@ EA is the effective address.
@ The PSH and PUL instructions require 5 cycle plus 1 cycle for each byte pushed or pulled.
@ 5(6) means: 5 cycles if branch not taken, 6 cycles if taken.
@ SWI sets 1 and F bits. SWI2 and SWI3 do not affect I and F.
(j) Conditions Codes set as a direct result of the instruction.
@ Value of half-carry flag is undefined.
Special Case - Carry set if b7 is SET.
@ Condition Codes set as a direct result of the instruction if CC is specified, and not affected otherwise.
LEGEND:
OP
Operation Code (Hexadecimal)
Z
Zero (byte)
V
Overflow, 2's complement
Number of MPU Cycles
#
Number of Program Bytes
C
Carry from bit 7
+
Arithmetic Plus
t
Test and set if true, cleared otherwise
Arithmetic Minus
Not Affected
X
Multiply
CC
Condition Code Register
~
Complement of M
Concatenation
Transfer Into
V
Logical or
H
Half-carry (from bit 3)
"
Logical and
~
Logical Exclusive or
N
Negative (sign bit)
452
Mnem
Mode
00
01
02
03
NEG
Direct
04
OP
Mnem
Mode
6
6
ROR
ASR
ASL, LSL
ROL
DEC
6
6
6
LEAX
LEAY
LEAS
LEAU
PSHS
PULS
PSHU
PULU
Indexed
COM
LSR
6
6
2
2
30
31
32
33
34
35
36
37
38
39
3A
3B
3C
3D
3E
3F
05
06
07
08
09
OA
OB
OC
00
OE
OF
INC
TST
JMP
CLR
Direct
10
11
12
13
14
15
16
17
18
19
1A
1B
lC
10
1E
IF
} See
Next Page
NOP
SYNC
20
21
22
23
24
25
26
27
28
29
2A
2B
2C
20
2E
2F
Implied
Implied
6
3
6
2
2
2
2
2
2
2
LBRA
LBSR
Relative
Relative
5
9
3
3
DAA
ORCC
Implied
Immed
ANDCC
SEX
EXG
TFR
Immed
Implied
2
1
2
2
BRA
BRN
BHI
BLS
BHS, BCC
BLO, BCS
BNE
BEQ
BVC
BVS
BPL
BMI
BGE
BLT
BGT
BLE
Relative
Implied
8
6
3
3
3
3
3
3
3
3
3
3
Relative
3
3
3
3
3
3
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
40
41
42
43
44
45
46
47
48
49
4A
4B
4C
40
4E
4F
50
51
52
53
54
Indexed
Implied
4+
4+
4+
4+
5+
5+
5+
5+
Mnem
Mode
2+
2+
2+
2+
2
2
2
2
60
61
62
63
64
65
66
67
68
69
6A
6B
6C
6D
6E
6F
NEG
Indexed
3
6,15
20
11
SWI
Implied
19
NEGA
Implied
COMA
LSRA
RORA
ASRA
ASLA, LSLA
ROLA
DECA
2
2
2
2
2
INCA
TSTA
2
2
CLRA
Implied
NEGB
Implied
COMB
LSRB
2
2
RORB
ASRA
ASLB, LSLB
ROLB
DECB
2
2
2
2
INCB
TSTB
CLRB
OP
RTS
ABX
RTI
CWAI
MUL
55
56
57
58
59
5A
5B
5C
50
5E
5F
2
Implied
1
2
70
71
72
73
74
75
76
77
78
79
7A
7B
7C
70
7E
7F
80
81
82
83
84
85
86
87
88
89
8A
8B
8C
8D
8E
8F
#
6+
2+
COM
LSR
6+
6+
2+
2+
ROR
ASR
ASL, LSL
ROL
DEC
6+
6+
6+
6+
2+
2+
2+
2+
2+
INC
TST
JMP
CLR
Indexed
6+
6+
3+
6+
2+
2+
2+
2+
NEG
Extended
6+
COM
LSR
ROR
ASR
ASL, LSL
ROL
DEC
INC
TST
JMP
CLR
SUBA
CMPA
SBCA
SUBD
ANDA
BITA
LOA
EORA
ADCA
ORA
ADDA
CMPX
BSR
LDX
7
7
7
7
7
4
Extended
Immed
2
2
2
Immed
Relative
Immed
3
3
3
3
3
3
3
3
3
3
3
2
2
2
3
2
2
2
2
2
2
2
2
2
2
2
2
4
7
(to be continued)
LEGEND:
#
453
Mnem
Mode
90
91
92
93
94
95
96
97
98
99
9A
9B
9C
9D
9E
9F
SUBA
CMPA
SBCA
SUBD
ANDA
BITA
LDA
STA
EORA
ADCA
ORA
ADDA
CMPX
JSR
LDX
STX
Direct
SUBA
CMPA
SBCA
SUBD
ANDA
BITA
LDA
STA
EORA
ADCA
ORA
ADDA
CMPX
JSR
LDX
STX
Indexed
BO
B1
B2
B3
B4
B5
B6
B7
B8
B9
BA
BB
BC
BD
BE
BF
SUBA
CMPA
SBCA
SUBD
ANDA
BITA
LDA
STA
EORA
ADCA
ORA
ADDA
CMPX
JSR
LDX
STX
Extended
CO
SUBB
CMPB
C2
C3
C4
C5
SBCB
ADDD
ANDB
BITB
Indexed
Immed
Mode
LDB
Immed
5
5
4+
4+
4+
6+
4+
4+
4+
4+
4+
4+
4+
4+
6+
7+
5+
5+
2+
2+
2+
2+
2+
2+
2+
2+
2+
2+
2+
2+
2+
2+
2+
2+
5
5
5
7
5
5
5
5
5
5
5
3
3
3
3
3
3
3
3
3
3
3
3
7
8
'T~
Mnem
C6
C7
C8
C9
CA
CB
CC
CD
CE
CF
2
2
2
2
2
2
2
2
2
Extended
OP
4
4
6
7
Direct
2
2
2
2
2
2
4
4
AO
A1
A2
A3
A4
A5
A6
A7
A8
A9
AA
AB
AC
AD
AE
AF
Ci
4
4
4
6
4
4
6
6
2
2
2
4
2
2
3
3
3
2
2
2
3
2
2
EORB
ADCB
ORB
ADDB
LDD
LDU
Immed
DO
01
02
D3
D4
05
D6
D7
D8
09
DA
DB
DC
DD
DE
DF
SUBB
CMPB
SBCB
ADDD
ANDB
BITB
LDB
STB
EORB
ADCB
ORB
ADDB
LDD
STD
LDU
STU
Direct
EO
E1
E2
E3
E4
E5
E6
E7
E8
E9
EA
EB
EC
ED
EE
EF
SUBB
CMPB
SBCB
ADDD
ANDB
BITB
LDB
STB
EORB
ADCB
ORB
ADDB
LDD
STD
LDU
STU
Indexed
FO
F1
F2
F3
F4
F5
F6
F7
F8
F9
FA
FB
SUBB
CMPB
SBCB
ADDD
ANDB
BITB
LDB
STB
EORB
ADCB
ORB
ADDB
j
Direct
Indexed
Extended
OP
Mnem
Mode
2
2
LDD
STD
LDU
STU
extr~
FC
FD
FE
FF
2
2
3
2
2
3
4
4
4
6
4
4
4
4
4
4
4
4
Extended
454
2
2
2
2
2
2
2
2
2
5
5
5
5
2
2
4+
4+
4+
6+
4+
4+
4+
4+
4+
4+
4+
4+
5+
5+
5+
5+
2+
2+
2+
2+
2+
2+
2+
2+
2+
2+
2+
2+
2+
2+
2+
2+
5
5
5
3
3
3
3
3
3
3
3
3
3
3
3
5
5
5
5
5
5
5
5
2
2
Extended
6
6
3
3
4
4
4
4
4
4
4
2 Bytes Opcode
1021
1022
1023
1024
1025
1026
1027
1028
1029
102A
102B
102C
102D
102E
102F
103F
1083
108C
108E
1093
109C
109E
109F
10A3
10AC
10AE
10AF
10B3
10BC
10BE
10BF
10CE
10DE
10DF
10EE
10EF
10FE
10FF
113F
1183
118C
1193
119C
11A3
11AC
1183
11BC
~~g. LB::"r
tive
LBCS, LBLO
LBNE
LBEQ
LBVC
LBVS
LBPL
LBMI
LBGE
LBLT
LBGT
LBLE
Relative
Implied
SWI2
CMPD
Immed
CMPY
LOY
Immed
CMPD
Direct
CMPY
LDY
STY
Direct
CMPD
CMPY
LDY
STY
Indexed
CMPD
CMPY
LDY
STY
Extended
LDS
Immed
Direct
LDS
Direct
STS
Indexed
LDS
STS
Indexed
LDS
Extended
STS
Extended
SWI3
Implied
Immed
CMPU
Immed
CMPS
CMPU
Direct
Direct
CMPS
CMPU
Indexed
Indexed
CMPS
CMPU
Extended
Extended
CMPS
5(6)
5(6)
5(6)
5(6)
5(6)
5(6)
5(6)
5(6)
5(6)
5(6)
5(6)
5(6)
5(6)
5(6)
20
4
4
4
4
4
4
4
4
2
4
7
7
4
3
3
6
6
3
3
'ndoi~
7+
7+
6+
6+
3+
3+
3+
3+
eXT'' '
8
8
4
4
7
4
4
4
6
6
3
3
6+
6+
7
3+
3+
4
20
7
7
3
3
7+
7+
3+
3+
(DC-40)
HD6821P, HD68A21P, HD68B21P
FEATURES
Two Bi-directional 8-Bit Peripheral Data Bus for interface to
Peripheral devices
(DP-40)
'--_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ....J
PIN ARRANGEMENT
CAl
CA,
iRQA
iRcii
BLOCK DIATRAM
IRQA 38 _------------~r.:===:l
40
CA,
39
CA,
RS.
RS,
RES
O.
D.
0,
0,
0,
D.
0,
0,
0,
33
32
31
30
29
28
27
26
0,
0,
0,
O.
0,
O.
0,
PA,
6
PA ..
PA,
PA.
9
CSt
E,
PA.,
CS.
VeePin 20
VssPin 1
CS,
CS,
CS,
RS.
RS,
RNi
E
ReS
22
24
23
36
35
21
10
PSg
11
PSI
12
PSI
Vee
~------------~
13 P8,
14
(Top View)
PB"
15 PS,
16 P8,
17 PB.,
25
34
374--------------;_~::~~
455
RNi
HD6821, HD68A21,
HD68B21------------------------------------------
Supply Voltage
Symbol
Vee *
Input Voltage
Yin *
Operating Temperature
Topr
T stg
Item
Storage Temperature
Value
Unit
-0.3 - +7.0
-0.3 - +7.0
-20- +75
V
c
-55 - +150
typ
max
Unit
4.75
5.0
5.25
-0.3
2.0
0.8
Input Voltage
V1L *
V1H *
Operating Temperature
Topr
-20
25
Symbol
Vee *
Item
Supply Voltage
Vee
75
V
c
ELECTRICAL CHARACTERISTICS
Item
min
typ*
max
Unit
2.0
-0.3
Vee
0.8
-2.5
2.5
p.A
Yin
-10
p.A
-200
10
VIH
p.A
-2.4
mA
Test Condition
All Inputs
VIH
All Inputs
Vil
R/W, RES~o, RS l
CSo , CSl. CS l , CAl,
CBI, E
lin
Vin
Do -0 7 PB o -PB 7 CB l
PAo -PA 7 CAl
ITSI
III
VOH
= 0.4-2.4V
= 2.4V
Vil = O.4V
IOH = -205p.A
IOH = -200p.A
IOH = -10p.A
IOH = -200p.A
IOl = 1.6mA
IOl = 1.6mA
IOl = 3.2mA
VOH = 2.4V
VOH = 2.4V**
VOH = 1.5V
VOH = 2.4V
IIH
PB o -PB 7 CB l
Do -0 7 TRO'A. 'i"R'QB
Output "Low" Voltage
VOL
Other Outputs
0 0 -0 7
IOH
PB o -P8'" CB 2
Output Leakage Current (Off State)
rm:lA. fROB"
IlOH
Power Dissipation
Po
PAo -PA 7 PB o -PB 7
CAl, CB l , Do -0 7
Input Capacitance
Output Capacitance
* Ta = 25C. Vee = 5.0V
= Q-5.25V
Cin
IROA.IROB
Cout
456
Yin = OV.
Ta = 25C,
f = 1.0MHz
Yin = OV,
Ta = 25C,
f = 1.0MHz
0.4
0.4
0.6
-205
p.A
-200
p.A
-1.0
-10
mA
10
p.A
260
550
mW
12.5
10
10
2.4
2.4**
Vec-1.0
2.4
pF
pF
Item
Test Condition
HD68A21
HD6821
min
max
min
max
100
ns
tposu
Fig. 1
200
135
tPOH
Fig. 1
Enable -+ CA 2 Negative
tCA2
Enable
tRS1
CA.,CA 2
Unit
max
HD68B21
min
ns
1.0
0.67
0.5
lAS
Fig. 2
1.0
0.67
0.5
III
t r , tf
Fig. 3
1.0
1.0
1.0
lAS
CA. - CA 2
tRS2
Fig.3
2.0
1.35
1.0
lAS
Enable-Peripheral Data
tpow
Fig. 4, Fig. 5
1.0
0.67
0.5
lAS
Enable -+ Peripheral
Data
PAo-PA?, CA 2
tCMOS
2.0
1.35
1.0
lAS
Enable -+ CB 2
tCB2
Fig. 6, Fig. 7
1.0
0.67
0.5
,",S
toc
Fig.5
20
20
20
ns
Enable -+ CB 2
tRS1
Fig.6
1.0
0.67
0.5
#<IS
CA 2 , CB 2
PWCT
550
500
ns
CB. ,CB 2
t r , tf
Fig. 7
1.0
1.0
1.0
#<IS
CB ..... CB 2
tRS2
Fig.7
2.0
1.35
1.0
,",S
TFiOA, iROB
tlR
Fig. 9
1.6
1.1
0.85
i"RClA, TmlB
Fig. 8
1.0
1.0
1.0
""
CA., CA 2 , CB., CB 2
tRS3
PWI
Reset
RES
tRL
Fig. 10
II
low" Time
-+
CA 2 Positive
Fig. 2, Fig. 3
Fig. 2, Fig. 6
Fig. 8
550
500**
1.0
soo
.-
0.66
,",S
soo
ns
0.5
IJ.s
The Reset line must be "High" a minimum of 1.0"" before addressing the PIA.
At least one Enable "High" pulse should be included in this period.
**
2. BUS TIMING
1)
READ
Item
Symbol
Test Condition
HD6821
min
max
HD68A21
min
max
HD68B21
min
max
Unit
tcycE
Fig.11
1000
666
500
ns
PWEH
Fig. 11
450
280
220
ns
PWEL
Fig.11
430
280
210
ns
tEr, tEf
Fig.11
25
25
tAS
Fig. 12
140
140
Setup Time
Address, R/W-Enable
tAH
Fig. 12
tOOR
Fig. 12
tOHR
Fig. 12
457
10
10
320
10
10
220
70
10
10
25
ns
ns
180
ns
ns
ns
WRITE
Symbol
Item
HD6821
Test Condition
min
max
teyeE
Fig.11
1000
PWEH
Fig.11
450
PWEL
Fig. 11
430
tEr, tEf
Fig.11
Setup Time
tAS
Fig. 13
140
tAH
Fig. 13
10
tosw
Fig. 13
195
tOHw
Fig. 13
10
PAo",PA,
Address, RM-Enable
HD68A21
min
max
HD68821
min
280
220
280
210
25
25
140
666
max
500
ns
10
10
80
60
ns
10
10
ns
Enable
Enable
CA 2
CA 2 _ _ _ _ _.1 1~---------
tf
O.4V
'/----""'1
Enable
~ nAV
r-
Enable
tPDW
PBo-PB, _____I
---'~
~)[~2~:-4~-------
CB 2
toe:!
CB 2
(Note)
2.4V~
Assumes part was deselected during the
previous E pulse.
458
ns
ns
Enable
-te~A2
ns
70
.."..-~------r'--
ns
25
Enable
Unit
ns
CA.,CA2
CB CB 2
CB.
CB 2
2.0V
O.SV
~i
0.4V
~f-----.1
Enable
IRQ
tIA---j~2.4V
r-
_ _ _ _ _ _ _ _ _ _ _ _ _- J
2.0V
Enable
O.SV
tAS::...j
RS,
CS.
RS.
CS.
RIW
R/W
2.0V
Data Bus
O.SV
LOAD A
(PAo-PA,. PBo-PB,. CA 2 CB 2 )
LOAD C
LOAD 0
(1m! Only)
5'OV
Test Point
Test Point
C
C-40pF
R-12kn.
lP-......__1......---t__--.
Test Point
C=130pF
R=11kn.
459
~I
3kn.
(CMOS Load) Test Point
0...---....,
(PA o -PA,. CA2 )
'000'
30PF
Reset (RES)
The active "Low" RES line is used to reset all register bits in
the PIA to a logical zero "Low". This line can be used as a
power-on reset and as a master reset during system operation.
These three input signals are used to select the PIA. CS o and
CSl must be "High" and CS 2 must be "Low" for selection of
the device. Data transfers are then performed under the control
of the E and R(W signals. The chip select lines must be stable
for the duration of the E pulse. The device is deselected when
any of the chip selects are in the inactive state.
PIA Register Select (RS o and RS l )
The two register select lines are used to select the various
registers inside the PIA. These two lines are used in conjunction
with internal Control Registers to select a particular register that
is to be written or read.
The register and chip select lines should be stable for the
duration of the E pulse while in the read or write cycle.
The PIA provides two 8-bit bi-directional data buses and four
interrupt/control lines for interfacing to peripheral devices.
Section A Peripheral Data (PAo"""'PA7 )
Peripheral Input lines CAl and CB I are input only lines that
set the interrupt flags of the control registers. The active
transition for these signals is also programmed by the two
control registers.
460
There are six locations within the PIA accessible to the MPU
data bus: two Peripheral Registers, two Data Direction Registers, and two Control Registers. Selection of these locations is
controlled by the RS o and RS I inputs together with bit 2 in the
Control Register, as shown in Table 1.
Table 1 Internal Addressing
Control
Register Bit
:::~;;:N"~",t
~
Input
INTERNAL CONTROLS
----+--<
CRA2
CRB2
0
1
Control Register A
0
0
1
0
x
x
x
x
x
x
x
1
Peripheral Register B*
0
x
Control Register B
Location Selected
Peripheral Register A*
Data Direction Register A
x = Don't Care
* Peripheral interface register is a generic term containing peripheral
data bus and output register.
Initialization
A "Low" reset line has the effect of zeroing all PIA registers.
This will set PAo .......PA7 , PBo-PB 7 , CA2 and CB2 as inputs, and
all interrupts disabled. The PIA must be configured during the
restart program which follows the reset.
Details of possible configurations of the Data Direction and
Control Register are as follows.
+5V
From ORA
RS o
0
0
0
1
1
To Data
Bus
RS,
r------------+~~-.PAx
(a) Section A
From DDR B
+5V
The two Control Registers (CRA and CRB) allow the MPU to
control the operation of the four peripheral control lines CAl,
CA2 , CB I and CB2 In addition they allow the MPU to enable
the intern,lpt lines and monitor the status of the interrupt flags.
Bits 0 through 5 of the two registers may be written or read by
the MPU when the proper chip select and register select signals
are applied. Bits 6 and 7 of the two registers are read only and
are modified by external interrupts occurring on control lines
CAt. CA2 , CB I or CB2 The format of the control words is
shown in Table 2.
To Data Bus
CRA
CRB
(b) Section B
Figure 15 Peripheral Data Bus
461
HD8821, HD88A21,
HD88B21------------------------------------------
CRBO are used to enable the MPU interrupt signals IRQA and
CRAO
(CRBO)
Interrupt Input
CAl (CB I )
Interrupt Flag
CRA7 (CRB7)
+Active
+Active
t Active
t Active
(Notes)
MPU Interrupt
Request
IROA (TROa)
Disabled - I RQ remains
"High"
Goes "Low" when the inter
rupt flag bit CRA7 (CRB7)
goes "1"
Table 4 Control of CA2 and CB2 as Interrupt Inputs - CRAS (CRBS) is "0"
CRA5
(CRB5)
CRA4
(CRB4)
CRA3
(CRB3)
Interrupt Input
CA2 (CB 2 )
Interrupt Flag
CRAS (CRBS)
+Active
+Active
t Active
t Active
(Notes)
MPU Interrupt
--B.!.quest
IROA (lROB)
Disabled - IRO remains
"High"
Goes "low" when the interrupt flag bit CRAS (CRBS)
goes "1"
Disabled - I RO remains
"High"
Goes " low" when the interrupt flag bit CRAS (CRBS)
goes "1"
462
Cleared
"Low" on the positive transition of
the first E pulse after MPU
Write "B" Data Register operation.
Set
"High" when the interrupt flag bit
CRB7 is set by an active transition
of the CB I signal. (See Figure 16)
"High" on the positive edge of the
first "E" pulse following an "E"
pulse which occurred while the
part was deselected. (See Figure 16)
CRB4
CRB3
"Low"
(The content of CR B3 is output on CB 2 )
"High"
(The content of CRB3 is output on CB 2 )
CRA5
CRA4
Set
"High" when the interrupt flag bit
CRA7 is set by an active transition
of the CAl signal. (See Figure 16)
"High" on the negative edge of the
first "E" pulse which occurs during
a deselect. (See Figure 16)
"Low"
(The content of CRA3 is output on CA 2 )
"High"
(The content of CRA3 is output on CA 2 )
463
Initialization
When the external reset input RES goes "Low", all internal
registers are cleared to "0". Periperal data port (pAo-PA7,
PBo-PB 7 ) is defmed to be input and control lines (CAl, CA z ,
CB I and CB z ) are defmed to be the interrupt input lines. PIA is
also initialized by software sequence as follows.
Program the data direction register access bit of the control
register to "0" to allow to access the dada direction register.
The data of the control line function is set into the accumulator, of which Data Direction Register Access Bit shall be
progranuned to "1".
Transfer the control data from the accumulator into the
control register.
Input/output processing
CLR
CLR
LDAA
STAA
LDAA
CRA
DORA
#$04
CRA
PIRA
<Write Operation>
Set the data direction register to "FF"
eLR
eRA
LDAA
STAA
LDAA
STAA
LDAA
STAA
#$04 } .
CRB
DATA}
PIRB
464
<Read>
The following case is that Port A is used and that the rising
edge of CAl indicates the request for read from peripherals.
CLR
CLR
CRA
DORA.
LOAA #$06
STAA eRA
No
LDAA PIRA
465
Load the data from the peripheral interface register into the
accumulator. CRA flag is reset after this read operation.
CRB
#$FF
DDRB
LDAA
STAA
#$06
CRB
LOOP LDAA
BPL
CRB
LOOP
No
LDAA
PIRB
STAB
PIRB
mmr
(3) CRA 7 flag is set and CA2 becomes "High" (CA2 automatically becomes "High" by the interrupt CAl). This
indicates the peripheral to maintain the current data and
not to transfer the next data.
(4) MPU accepts the read request by IRQA hardware interrupt
or CRA read. Then MPU reads the peripheral register A.
(5) CA2 goes "Low" on the following edge of read Enable
pulse. This informs that the peripheral can set the next data
to port A.
<Write Hand-shake>
CRBS = "1", CRB4 = "0" and CRB3 = "0"
(1) A peripheral device requests MPU to write the data by using
CB I input. CB2 output remains "High" until MPU write
data to the peripheral interface register.
(2) CRB7 flag is set and MPU accepts the write request.
(3) MPU reads the peripheral interface register to reset CRB7
(dummy read).
(4) Then MPU write data to the peripheral interface register.
The data is output to port B through the output register.
(5) CB2 automatically becomes "Low" to tell the peripheral
that new data is on port B.
(6) The peripheral read the data on Port B peripheral data lines
and set CB I to "Low" to tell MPU that the data on the
peripheral data lines has been taken and that next data can
be written to the peripheral interface register.
<Pulse mode>
CRAS = "I", CRA4 = "0" and CRA3 = "I"
CRBS = "I", CRB4 = "0" and CRB3 = "I"
This mode is shown in Figure 16, Figure 19 and Figure 20.
466
R!W
CSoRS,oRS o
0 0 -0 7
:0ft!
CII
.!;
CA,
...
" , / , r------
R EAO Request
0
a.
CRA7
CA 2
CRBS
Ready
Timing
CRB4 CRB3
E
R/W
CSoRS,oRS o
0 0 -0 7
PB o -PB 7
CO
1::
0
a.
CB ,
o
o
467
Busy
PIRA
CA,I. .____________
07
PIA
CRA
1_10111010111011/
--1
Peripheral Says:
Here's new data
(Sets CRA7)
= 100
(Hand-shake Mode)
:.~3' f~ b;"~1
Peripheral
--L...-t_
f,~"
~na Ie
signal
(E)
PIRB
CB,14~~--------------~
PIA
Peripheral
CB2~----------~~~1
-.r~
Peripheral
Request for date
468
Enable
signal (E)
Goes "High" on
the negative
edge of the
next E pulse
after a
"Read a
side data"
In'truction
(LOA)
1 .._____. . .
Pulse mode
Pulse output on 'A' side
Data
Ifl
1!1
I
PIRA
PIA
Peripheral
CA,
CRA
7
0
Ixloll1011111xlxl
Pul..
;";';"od ....... 1t
a a
Enable
signal
(E)
- - - '..._ _ _
'---__I'
Pulse mode
Pulse output on 'B' side
Data
III
1
PIRB
..!ll
I
PIA
7
Peripheral
. . x . .". . .". .
CRB
CB 2
at port
for peripheral
469
1.
2.
3.
4.
5.
6.
7.
(DDRA, PIRA)
(CRA)
(DDRB, PIRB)
(CRB)
LDA A #%11110000
STAA
PIAIAD
LDA A #% 11111111
STAA
PIAIBD
LDA A #%00000 I 00
STAA
PIAIAC
STAA
PIAIBC
(4 outputs, 4 inputs)
(Loads A DDR)
(All outputs)
(Loads B DDR)
(Sets Bit 2)
(Bit 2 set in A control register)
(Bit 2 set in B control register)
When all the outputs of given PIA port are to be active "Low"
(True~ 0.4 volts), the following procedure should be used.
a)
b)
c)
d)
e)
1.
2.
3.
4.
5.
6.
7.
8.
1.
2.
3.
4.
LDX
STX
LDX
STX
#$ F004
PIA lAD
#$FF04
PIAIBD
Using the index register in this example has saved six bytes of
program memory as compared to the program shown in the
previous section.
LDA A#4
STA A PIAIBC
LDA B #$FF
STA B PIAIBD
CLR PIAIBC
STA B PIAIBD
LDA A #$27
STA A PIAIBC
The program shown in the previous section can be accomplished using the Index Register.
<Example>
The B side of PIAl is set up to have all active low outputs.
CBI and CBl are set up to allow interrupts in the HANDSHAKE MODE and CBI will respond to positive edges
("Low"-to-"High" transitions). Assume reset conditions. Addresses are set up and equated to the same labels as previous
example.
Example Address
$4004
$4005
$4006
$4007
(DDRA, PIRA)
(DDRB, PIRB)
(CRA)
(CRB)
470
CA2 -CB 2
Input ~
Mode
b1
bO
o
1
1
CA 2 -CB 2
Output ~
Mode
W
b5
b4
0(-)
0(-)
ill
o
1(+)
1(+)
1
1
1
0
0
1
1
b3
o
1
o
1
o-
Handshake Mode
1 - Pulse Mode
~}
b3 Following Mode
b1 = Edge (0 = -, 1 = +)
bO = Mask (0 = Mask, 1 = Allow)
Note that this is the same logic as Bits 4 and 3 for CA 2 -CB 2
when CA2 -CB2 are programmed as inputs.
I~
CAl
..
CA 2
.
-.
PA 6
--. PA 7
liO As Follow:
Control Lines:
CAl - Positive Edge, Allow Interrupt
CA 2 - Pulse Mode
CB I - Negative Edge, Mask Interrupt
CB 2 - Hand Shake Mode
Auume Reset Condition
PIA1AO
PIA1AC
PIA1BO
PIA1BC
..
I....
"A"
...
...
"'"-
PA 3
PA 2
PAl
PA o
I'"
.....
PAs
...... PA
-----------..L
,-
....
...
CB I
CB 2
PB 7
"B"
..
t-----~
.1.71
PB o
HD6840, HD68A40,
HD68B40
Module)
(OC-28)
HD6840P, H068A40P, HD68B40P
FEATURES
BLOCK DIAGRAM
PIN ARRANGEMENT
ilia
(System ",I
C\
G2
0\
02
G.
C2
Do
G3
0\
03
02
C3
HD6840
D3
D.
05
RSo
06
07
rt
v..
Vee
jiB
G, C; 0,
RS 2
R/W
CS\
Vee
CSo
(Top View)
G. C, 0,
472
Item
-0.3"'+7.0
Input Voltage
V in *
-0.3"'+7.0
Operating Temperature
Topr
T stg
- 20"'+ 75
- 55"'+150
Unit
Vee *
Storage Temperature
*
Value
Supply Voltage
Permanent LSI damage may occur if maximum ratings are exceeded. Normal operation should be under recommended operating
conditions. If these conditions are exceeded, it could affect reliability of LSI.
Symbol
min
typ
max
Unit
Vee *
V 1L *
4.75
5.0
5.25
-0.3
0.8
V 1H *
2.2
Vee
75
Supply Voltage
Input Voltage
Operating Temperature
- 20
Topr
25
ELECTRICAL CHARACTERISTICS
DC CHARACTERISTICS (Vee
Item
=5V 5%,
Vss
=OV,
Symbol
Ta
Test Condition
typ*
max
Unit
Vee
0.8
-2.5
2.5
J.1.A
- 10
10
J.1.f!\
2.4
0.4
10
J.1.A
330
550
min
V 1H
2.2
V 1L
-0.3
lin
I TS1
V OH
VOL
I LOH
Power Dissipation
Po
I nput Capacitance
Output Capacitance
V OH
= 2.4V
Cin
V in = OV,
Ta = 25C,
f = 1 MHz
Cout
V in = OV,
Ta = 25C,
f = 1 MHz
(IRQ)
Do'" 0 7
12.5
Other Input
IRQ
5.0
0 1 , O2 , 0 3
473
7.5
10
mW
pF
pF
AC CHARACTERISTICS (Vee = SV S%, Vss = OV, Ta = -20 "" +7SoC, unless otherwise noted.)
Item
Enable Cycle Time
Test
Condition
typ
tcycE
PW EH
0.45
PW EL
0.43
tEr, tEf
tAS
Fig. 1
140
max
min
typ
0.666
10
O.S
10
J,J.s
0.280
4.5
0.22
4.5
J,J.s
0.280
0.21
J,J.s
25
25
25
ns
140
70
ns
320
180
ns
ns
250
ns
220
10
10
10
10
10
480
360
max
min
typ
tH
tAH
t ACC
Unit
10
10
max
4.5
typ
min
max
tOOA
1.0
HD68B40
HD68A40
HD6840
min
ns
Item
HD6840
Test
Condition
typ
min
HD68A40
tcycE
1.0
10
0.666
0.45
4.5
0.280
PWEH
PW EL
0.43
0.280
t Er tEf
25
tAS
140
tosw
195
140
tH
10
10
tAH
10
10
Fig. 2
80
HD68B40
max
min
typ
max
Unit
10
0.5
10
J,J.s
4.5
0.22
4.S
J,J.s
0.21
J,J.s
25
25
ns
70
ns
60
ns
10
10
ns
ns
Item
C,G, RES
C,G,REs
C,G
Test,Condition
tr,t,
Fig. 3, Fig. 4
PWL
Fig. 3
( ASynchrOnOUS)
Mode
PWH
Fig. 4
( ASynChrOnOUS)
Mode
C,G,m
Input Setup Time
C] (.;-8 Pre
scaler Model
C]
C] (';-8 Pre
scaler Model
(.;-8 Pre
scaler Model
01
0]
max
HD68A40
min
max
HD68B40
min
Unit
max
1.0*
0.666*
0.5*
/.IS
teyeE+tsU+tHo
tcycE + tsu +t H0
ns
tcyeE + tsu +t H0
tcyeE+ tsU+tHO
tcveE+tsu+tHo
ns
200
120
75
200
170
170
50
Fig. 5
( Synchronous 'I
\ Moae
I
Fig. 5
( Synchronous )
Mode
50
tHO
50
50
50
ns
PW L ,
PWH
( ASynChrOnOUS)
Mode
125
84
62.5
ns
VoH =2.4V,
Load B
700
460
340
ns
VoH =2.4V,
Load D
450
450
340
ns
VOH=0.7xVcc,
Load D
2.0
1.35
1.0
/.Is
1.2
0.9
0.7
/.IS
TTL
teo
MOS
tem
CMOS
Interrupt Release Time
min
tsu
C, G, RES
Input Hold Time
HD6840
Symbol
tcmOi
t'R
Fig. 6
Fig.7
* t,. tf ~ teveE
474
50
ns
RS,
CS,
R/W
Data Bus
Figure 3
Figure 2
Figure 4
~2.2V
\'---.*
t cmo
*
Figure 5
E_
~-t-IA-J--2-.4-V--
IRQ
-------...1
Figure"
VOH(CMOS)
I RQ Release Time
475
= 0.7
X vcc
Load B
(0 1 .0,.0, )
(TTL Load)
5.0V
Load A
(Do - 0,)
5.0V
RL =2.4 kn
Test Point 0 -......._.--4-....
Test Point
All diode$are
152074 or equiv.
130 pF
0-...--.---l4--....
Adjust RL
so that IOL = 3.2 rnA
then test VOL
12 kn
40 pF
Load C
(i'R'Q Only)
dI
5.0V
T., Po;",
Load
( 1 .0 1 .0, )
(CMOS Load)
(MOS)
U kn
Test Point
3OP
100pF
'
GENERAL DESCRIPTION
These two signals are used to activate the Oata Bus interface
and allow transfer of data from the PTM. With CS o = "Low"
and CSt = "High", the device is selected and data transfer will
<'lCcur.
ReadJWrite (RM)
476
Each of the three timers within the PTM has external clock
and gate inputs as well as a counter output line. The inputs are
high impedance, TTL compatible lines and outputs are capable
of driving two standard TTL loads.
Clock Inputs (t;. C;. C;)
Input pins
C;, and c; will accept asynchronous TTL
voltage level signals to decrement Timers I, 2, and 3, respectively. The "High" and "Low" levels of the external clocks must
each be stable for at least one system clock period plus the sum
c.,
RS t
Operations
R/W
RSo
= "0"
CR20 = "1"
CR20
= "Low"
R/W = "High"
No Operation
of the setup and hold times for the inputs. The asynchronous
clock rate can vary from dc to the limit imposed by Enable
(System 2) Setup, and Hold time.
The external clock inputs are clocked in by Enable (System
2) pulses. Three Enable periods are used to synchronize and
process the external clock. The fourth Enable pulse decrements
the internal counter. This does not affect the input frequency, it
merely creates a delay between a clock input transition and
internal ~cognition of that transition by the PTM. All references to C inputs in this document relate to internal recognition
of the input transition. Note that a clock "High" or "Low" level
which does not meet setup and hold time specifications may
require an additional Enable pulse for recognition. When observing recurring events, a lack of synchronization will result in
477
HD6840. HD68A40. HD68B40----------------------------------------#3 is programmed to utilize its optional 78 prescaler mode. The
maximum input frequency and allowable duty cycles for this
case are specified under the AC Characteristics. The output of
the 78 prescaler is treated in the same manner as the previously
discussed clock inputs. That is, it is clocked into the counter by
Enable pulses, is recognized on the fourth Enable pulse
(provided setup and hold time requirements are met), and must
produce an output pulse at least as wide as the sum of an Enable
period, setup, and hold times.
Enable~~
Input~t-Recog~~
Input
Either
Here
' - or
Here
I-- System
I T Bit Time
---l
Jitter
CR20
#3. Thus, with all Register selects and R/W inputs at "Low"
level. Control Register #1 will be written into if CR20 is a logic
"I". Under the same conditions, control Register #3 can also be
written into after a RES "Low" condition has occurred, since
all control register bits (except CRlO) are cleared. Therefore,
one may write in the sequence CR3, CR2, CRI.
CR10
Bit 1 of Control Register #1 (CRl1) selects whether an internal or external clock source is to be used with Timer #1.
Similarly, CR21 selects the clock source for Timer #2, and
CR31 performs this function for Timer #3. The function of
each bit of Control Register "X" can therefore be defined as
shown in the remaining section of Table 2.
CRX2
CRX3
-J
CRX7
478
CONTROL REGISTER #2
CR20
CONTROL REGISTER #3
CR30
CRX1*
"0"
"1"
CRX2
"0"
"1"
CRX3 CRX4 CRX5
CRX6
"0"
"1"
+8
CRX7
"0"
"1"
Byte of the desired latch data. Three addresses are provided for
the MSB Buffer Register (as indicated in Table 1), but they all
lead to the same Buffer. Data from the MSB Buffer will automatically be transferred into the Most Significant Byte of Timer
# X when a Write Timer #X Latches Command is performed. So
it can'be seen that the HD6840 has been designed to allow transfer of two bytes of data into the counter latches provided that
the MSB is transferred first.
In many applications, the source of the data will be as
HMCS6800 MPU. It should be noted that the 16-bit store operations of the HMCS6800 microprocessors (STS and STX etc.)
transfer data in the order required by the PTM. A Store Index
Register Instruction, for example, results in the MSB of the X
register being transferred to the selected address, then the LSB
of the X register being written into the next higher location.
Thus, either the index register or stack pointer may be transfered directly into a selected counter latch with a single instruction.
A logic "Low" at the RES input also initializes the counter
latches. In this case, all latches will assume a maximum count of
(65,536)10. It is important to note that an Internal Reset (Bit 0
of Control Register 1 Set) has no effect on the counter latches.
COUNTER INITIALIZATION
479
HD6840, HD68A40, HD68B40----------------------------------------Either symmetrical or variable duty-cycle waves can be generated in this mode. The other wave synthesis mode, the SingleShot mode, is similar in use to the Continuous operating mode,
however, a single pulse is generated, with a programmable preset
width.
The WAVE MEASUREMENT modes include the Frequency
Comparison and Pulse Width Comparison modes which are used
to measure cyclic and singular pulse widths, respectively.
In addition to the four timer modes in Table 4, the remaining
control register bit is used to modify counter initialization and
enabling or interrupt conditions .
..
..
..
Wave
Synthesis
Wave
Measurement
Register 2
Reg #3 May Be Written
Reg #1 May Be Written
Register 3
T3 Clk + 1
T3 Clk +8
.j.
.j.
.j.
.j.
480
"Low") condition or internal recognition of a negative transition of the Gate input results in Counter Initialization. A Write
Timer Latches command can be selected as a Counter Initialization signal by clearing CRX4.
The counter is enabled by an absence of a Timer Reset condition and a "Low" level at the Gate input. In the 16-bit mode,
the counter will decrement on the first clock cycle during or
after the counter initialization cycle. It continues to decrement
on each clock signal so long as G remains "Low" and no reset
condition exists. A Counter Time Out (the first clock after all
Initialization/Output Waveforms
Counter Initialization
G~+W+R
-
G~+R
GJ-+W+R
-
G~+R
II
to
TO
TO
l-voH
VOL
TO
n-
II
VOL
---i
to
(L) (T)
f-TO
---l
(L)(TI
OH
t--
TO
481
CRX7
0
1
CRX6
0
1
. \ I;A~~AX31
Control Register X 17
6 15141 31 211
/
CRX2
a
1
I Lx
0
= 1, 2 or 3
CRl<1
0
1
X = 1
X=2
482
0
1
~--------------- M(L+1)+1
Algebraic Expression
03(04 + 1) + 1 =
16 Enables
,,
,
-------it---
Counter Output
2.4V
-------+1r--- O.4V
E
(System 1/>2)
I
I
I
I
I
1 + L - -....,.
....
- - 1 + L - - - t..~:...~- 1 + L -------..,
5 Enable
I
5 Enable
5 Enable
Pulses
Pulses
Pulses
I
I
I
I
4 Enable
Pulses
-1+L:
5 Enable
:
Pulses
(M+!1(~~+11
**
,j
I
I
~
** 1
--'
**
..
Algebraic Expression
(04 + 1) (03 + 1) = 20 Enable or
External Clock Pulses
(M + 1) (L + 1) = Period
M(L + 1) + 1 = "Low" portion of period
L = Pulse width
* Preset LSB and MSB to Respective Latches on the negative transition of the E.
** Preset LSB to LSB Latches and Decrement MSB by one on the negative transition of the E.
483
mode:
1. Output is enabled for only one pulse until it is reinitialized.
Initialization/Output Waveforms
CRX2
CRX4
Counter Initialization
Gl-+W+R
Gl-+R
Ii
TO
to
G.+W+R
Gl-+R
/ lTO
to
1
TO
)(Tll
TO
CRX4
0
CRX5
0
Application
Frequency Comparison
Frequency Comparison
CRX3 = "1"
Condition for Setting Individual Interrupt Flag
Interrupt Generated if Gate Input Period (1 IF) is less
than Counter Time Out (TO)
Interrupt Generated if Gate Input Period (1 IF) is greater
than Counter Time Out (TO)
Interrupt Generated if Gate Input "Down Time" is less
than Counter Time Out (TO)
Interrupt Generated if Gate Input "Down Time" is greater
than Counter Time Out (TO)
condition of G,j.-T-TO is satisfied, since a Time Out has occurred and no individual Interrupt has been generated.)
Any of the timers within the PTM may be programmed to
compare the period of a pulse (giving the frequency after calculations) at the Gate input with the time period requested for
Counter Time-Out. A negative transition of the Gate input
enables the counter and starts a Counter Initialization cycle provided that other conditions as noted in Table 8 are satisfied.
The counter decrements on each clock signal recognized during
or after Counter Initialization until an Interrupt is generated, a
Write Timer Latches command is issued, or a Timer Reset condition occurs. It can be seen from Table 8 that an interrupt
condition will be generated if CRX 5 = "0" and the period of the
pulse (single pulse or measured separately repetitive pulses) at
the Gate input is less than the Counter Time Out period. If
CRX 5 = "1", an interrupt is generated if the reverse is true.
484
= "1",
CRX4
= "0"
Counter Enable
Flip-Flop Set (CE)
Counter Enable
Flip-Flop Reset (CE)
G~'HCE+TO)+R
G~,wRT
W+R+I
G~
G~:-j+R
G~w1FT
W+R+I
TO Before G~
Control Reg
Bit5 (CRX5)
Counter
Initialization
0
1
Interrupt Flag
Set (I)
Before TO
Counter
Initialization
Counter Enable
Flip-Flop Set (CE)
Counter Enable
Flip-Flop Reset (CE)
G~I+R
G~,w'R-1
W+R+I+G
Gt Before TO
G~T+R
G~WR1
W+R+I+G
TO Before Gt
485
Interrupt Flag
Set (II
HD6843,HD68A43
FDC (Floppy Disk Controller)
The HD6843 Floppy Disk Controller performs the complex MPU/Floppy interface function_ The FIX was designed to
optimize the balance between the "Hardware/Software" in
order to achieve integration of all key functions and maintain
flexibility.
The FDC can interface a wide range of drives with a
minimum of external hardware. Multiple drives can be controlled with the addition of external multiplexing rather than
additional FDC's.
HD6843, HD68A43
FEATURES
Format compatible with IBM3740
User Programmable read/write format
(DC-40)
HD6843P, HD68A43P
(DP-40)
PIN ARRANGEMENT
BLOCK DIAGRAM
TRZ
9 t5V
20 I
WOT
ROT
IRO
To H08844 { ______
-_ __-..;,.36,:= hAO
fot OMA
2
Operallon
25
TxAK
D.
0,
0,
D.
DE
!~
~.,CD
--R31
--'j()
TxRO
BO
VFOC
0 ..
0,
...!!.
DE
0,
39
WGT .......
Write Gate
0,
~~-----~~~~-i~
LCT ~_';;;O_ _ _ _ _ _
FIA
AES
18
17
,..L
1-.-..;_ _ _ _ _ _
O.
0,
BO
Low Cunent T'ack
Cs
Rm
AS,
~ CS
0,
O.
W P T . . . , - - - - - - - - W n t e Protect
AS"
AS,
0,
0,
~~~~-----~2~3-iE
19
HD6843
i~==~------~CLK
0,
Wnte Data
~D.
l'-~;-----__:::_::7-i
NC
O.
WDT~-------"
--=------.
~D,
~D,
,..2L.
NC
ADT~ L;.;.";""'
~~a _ _'
~O,
CD
Read
Recovery
Vss
486
(Top View)
---------------------------------------------------HD6843,
HD68A43
Symbol
Value
Unit
Supply Voltage
Vee *
-0.3
Input Voltage
Vin *
-0.3
Operating Temperature
Topr
-20 - +75
V
c
Storage Temperature
Tstg
-55 -
~
~
+7.0
+7.0
+150
min.
typo
max.
Unit
4.75
5.0
5.25
Vee *
V 1H *
2.0
V 1L *
-0.3
Vee
0.8
Operating Temperature
Tapr
-20
25
75
Item
Supply Voltage
V
VC
ELECTRICAL CHARACTERISTICS
DC CHARACTERISTICS (Vcc=5V5%, VSS=OV, Ta=-20"--+75C, unless otherwise noted.)
min.
typ,*
max.
Unit
V 1H
2.0
V 1L
-0.3
Vee
0.8
lin
1.0
2.5
p.A
VOH
Vin =0"--5.25 V
IOH=-205p.A (Do~D7)
IOH=-100p.A (Others)
2.4
VOL
0.4
I TS1
V In =0.4-2.4 V
2.0
10
p.A
I LOH
VoH =2.4V
p.A
Symbol
Item
Power Dissipation
Output Capacitance
Other inputs
1.0
10
Po
600
1000
mW
Vin=OV, Ta =25C,
f=l MHz
12.5
pF
Cin
10
pF
Caut
Vin=OV, Ta =25C,
f=l MHz
10
pF
Do~D7
Input Capacitance
Test Condition
487
Test Condition
Symbol
HD6843
min.
typo
HD68A43
max.
Unit
min.
typo
1.0
JJ.S
JJ.S
25
JJ.S
ns
max.
tcycC
PW HC
Figure 1
1.0
Figure 1
0.4
0.4
PW LC
Figure 1
0.35
0.35
tCrt
Figure 1
25
tcycO
PWHO
Figure 2
2.6
4.0
2.6
4.0
p.s
Figure 2
1.3
1.95
1.3
1.95
JJ.S
PW LO
Figure 2
1.3
1.95
1.3
1.95
tOrr tOf
Figure 2
25
25
JJ.S
ns
tROH
Figure 2
1.0
1.0
tROL
tR001
Figure 2
1.0
1.0
JJ.S
p.s
Figure 2
0.15
1.70
0.15
.....
1.70
tROO2
PW10x
Figure 2
Figure 3
0.15
20.0
1.70
JJ.S
p.s
p.s
Figure 4
450
450
ns
tFIRO
PWFIR
1.70
0.15
20.0
Figure 4
200
200
ns
PW wo
Figure 7
1.0
JJ.S
tcycw
PWSTP
Figure 7
2.0
1.0
2.0
JJ.S
32
32
tcycS *
Figure 5
15
15
JJ.S
ms
15
p.s
tCf
Figure 5
tHLoO
Figure 5
tHORS
Figure 5
tHORH
Figure 5
32
tAS3
Figure 10,11
140
Figure 10,11
10
tAH3
tTR
Figure 10,11
tlR
Figure 6
15
0
32
140
10
450
1.2
ns
JJ.S
ns
ns
240
ns
1.2
JJ.S
Symbol
Test Condition
min.
HD6843
typo
max.
HD68A43
typo
max.
0.666
p.s
JJ.S
0.23
0.23
JJ.S
25
ns
ns
200
ns
340
ns
ns
ns
400
ns
tcycE
PVv'EH
PWEL
Figure 8, 10
1.0
Figure 8,10
0.4
Figure 8, 10
0.4
tEr, tEf
Figure 8, 10
25
tAS
Figure 8, 10
140
140
tooR
Figure 8,10
225
tACC
Figure 8,10
tH
Figure 8, 10
10
tAH
Figure 8, 10
10
tOBo
Figure 8, 10
488
Unit
min.
365
10
10
400
---------------------------------------------------HD6843. HD68A43
2
Item
Symbol
HD6843
Test Condition
t cycE
PW EH
Figure 9, 11
Figure 9, 11
PW EL
Figure 9, 11
min.
1.0
0.4
0.4
tEr, tEf
Figure 9, 11
~~-~
tAS
tosw
tH
tAH
tOBO
min.
0.666
0.23
Unit
/1S
/1S
0.23
25
ns
ns
ns
400
f.1.S
~--
140
100
Figure 9, 11
10
10
Figure 9, 11
140
60
10
10
Figure 9, 11
400
2.0V
O.8V
elK
--- tcr!---PW HC
t'"'--------~tCycC~~~~-----<l~
tOf
2.0V
t------------+--+--tcycO-------1
ROT
max.
Figure 9, 11
Figure 9, 11
typo
---~
25
--~--
HD68A43
typ-:! max.
ns
ns
ns
HD6843, HD68A43-------------------------------------------------
2.4V
FIR
.....----PWFIR----~
..I
HDR
STP
t - - - - - - t c y c s -----4--1
HLD
tlR)
Figure 6 IRQ Release Timing
PWWD
WDT
490
2.4V
---------------------------------------------------HD6843, HD68A43
~--------------------teyeE-----------------.~
E
O.8V
cs
A/W
0 0 -0,
(Output)
tOB~
___________J..J
2.4V
BD
teyeE
PWEH
PWEL
'f-2.0V
-r- O.8V
-j
cs
r-
O.8V
tEf ___
~tEr
tAH~
\l----tAS-
-'to.8V
-1K 2.0V
j
-tosw-
~r-
O.8V
f-2.0V
0 0 -0,
(Input)
.,V---
O.8V
):
A/W
O.8V
-~
-\" O.8V
-toBo
--
O.8V
]r- O.8V
I--
2.0V
-Jl
O.8V
BD
491
tH
....;~
HD6843. H D 6 8 A 4 3 - - - - - - - - - - - - - - - - - - - - - - - - -
tcycE
PWEH
PWEL
'-
O.SV -k-
O.SV....,
tEr-
'f-2.0V
I r----- t T R - '--
TxAK
--tAS3-
I- tOOR"
-r- O.SV
~
r--
tACC-
D,
--tOBO-
utI
~O.SV
l - I - tEf
--
-r-
2.0V
~
- - tAH3
tAH_
'-tAS-
A/W
2.0V
2.4V
-~
O.4V
{:.SV
I--~t--;
~O.4V
-+-2.4V
so
TxAQ
-t--O.4V
~----------------tcycE------------------~~
~------PWEL------~ ~__-----P-W-E-H-======:j
2.0V
E
O.8V
2.0V
O.8V
tEr
2.0V
TxAK
2.0V
A/W
tOBO
so
O.4V
TxAQ
O.4V
492
tH
2.4V
LOAD B (lAQ)
5.0V
AL=2.4kn
AL =2.4kn
Test
Point 0 - -__-..._-..........- - - 4
Test
Point
A
Vee
Vss
ClK
R3
STP
iRa
TxRQ
TxAK
INSTRUCTION
DECODER
&
SEQUENCE
CONTROL
D.
0,
lCT
0,
0,
O.
FI
0,
0,
IDX
0,
TRZ
WPT
+- ROY
RS.
RS,
FIR
HOR
HlD
WGT
RS,
R/W
VFOC
+ WDT
L -_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
BD
DCK
ROT
493
HD6843, HD68A43------------------------------------------------
GENERAL DESCRIPTION
The HD6843 FDC consists of four primary sections; the
Register, Serializing, Bus Interface, and Control sections. The
following explanation of these sections can be followed in the
block diagram of Figure 13.
Register Section
The register section consists of twelve user accessible registers
used for controlling a floppy disk drive. All twelve are
connected by the internal data bus to allow the processor access
to them.
Bus Interface
The Bus Interface section provides the timing and control
logic that allows the FDC to operate with the 6800 bus, and is
comprised of the Data Buffers. Request Control, and the
Register Select circuitry.
Control
The internal timing and control signals which sequence the
FDC are derived from the macro instructions by the control
section.
Power Pins
Vee: +5 volt (5%) power input.
Vss: Power Supply Ground.
Bus Pins
Output
Status Register A (STRA)
The eight bits of STRA are used to indicate the state of the
floppy disk interface.
FIR
WGT
HDR
STP
State of Output
"Low"
"Low"
"Low"
"Low"
Output
HLD
TxRQ
IRQ
WDT
State of Output
"Low"
"Low"
"High"
" Low"
494
-------------------------------------------------HD6843, HD68A43
(HMCS6800 MPU, DMA Controller, etc.) E must be a logic "I"
("High" level) for any transfer to be enabled on Do -D 7 The E
input is normally connected to system 2 .
CS
R/W
1
0
x
x
Register
Selected
DOR
DIR
RS o-RS2
CS
1
BD
R/W
R/W
CS
RS2
RS 1
RS o
R/W
0
1
1/0
0
CM R (Command Register)
0
0
0
1
1
0
Registers
DOR (Data Output Register)
CTAR (Current Track Address Register)
ISR (Interrupt Status Register)
SUR (Set Up Register)
1
0
1
495
HD6843, HD68A43--------------------------------------------------
,-----------,
MPU
Din I
+---~--~--~--~
I
X)------..,.....--'------
FOe
IDout
I
/
Rout/
I
I
I
/ DIE
I
I
/ __________ ...L/
L
HD268T26
Enable
Figure 14
B is read.
File Inoperable (F!) Input
FI is an input to the FDC from the drive. A "High" level
indicates the drive is in an inoperable state. Its current state can
be examined by reading bit 5 of Status Register B (STRB).
Track Zero (TRZ) Input
The TRZ input is reflected by bit 3 of STRA (Status Register
A). The TRZ input must be a "High" level (logic" 1") when the
R/W head of the drive is positioned over track zero. A logic "1"
on this input inhibits step pulses during a Seek Track Zero
command.
Index (lOX) Input
The index input is received from the floppy disk drive and is
used to sense the index hole in the disk media. The lOX signal is
used to initialize the internal FDC timing. The state of the lOX
input is reflected by bit 6 of Status Register A (STRA). A
"High" level (logic" 1") is to indicate the index hole is under the
index sensor. The index input is used to count the number of
disk revolutions while searching for the address 10 field (see
description of STRB bit 3).
Ready (ROY) Input
The ready input is received from the disk drive and can be
read as bit 2 of STRA (Status Register A). A "High" level (logic
"1") indicates the drive is ready and allows the FDC to operate
the drive.
Write Protect (WPT) Input
WPT is an input indicating when the media is Write
Protected. A "High" level during an FDC write operation results
in a Write Error (STRB bit 6) but the FDC continues to perform
the write function. The state of the WPT input can be read by
examining bit 4 of the Status Register A (STRA).
Clock (ClK) Input
The eLK input is used to generate various timing sequences
internal to the FDC. The head settling, seek time, step pulse
width and write data pulse width, etc., are generated from the
eLK input signal. The eLK is 1 MHz frequency and the duty is
50%.
496
---------------------------------------------------HD6843, HD68A43
Data Pins
OCK is used to clock data from the drive into the FOC. It is
generated from the read data received from the drive.
Clock
RDT is the serial data input from the drive. The data stream
includes both the clock and data bits.
FORMAT
Disk
~!-
__G
...sl-_"l...;G;;.:.,....IiJI1
G2
,r---
1rQ~
"High"
I-O-....
G3
~_"";;"--J
Data
Data
ID
WGT
VFOC
2 bits
2 bits
Oisk~'"
~r---IO-"
_ _G..;;.s_-il-G.:...l
G3
6 bytes--
1..._ _G.,;;.<_...J
1 bytes
WGT
497
ID
G3
HD6843,
HD68A43------------------------------------------~-----
SSW, SWD and MSW commands (Single Sector Write, Single Sector Write with Delet Data Mark, and Multi-Sector Write)
W G T - - -....
WDT
(111.0 IlS (typ)
Index~~__________________________~JJr_----------------------~
Track
Format
Gap 1
Preamble
46 Bytes
Gap 2
(Post-Index)
32 Bytes
~~~
t-----t:;:j
Index
Address Mark
Data = Fe
Clock = D7
ID
Sector 1
A~~~~ss
Sector
Format
Sector2
Data = FE
Clock = C7
I /J I
Sector3
Sector 25
Sector 24
Sector 26-v-----'
Gas 5
274 Bytes
(Pre-Index Gap)
Gap 3
(ID Gap)
17 Bytes
Gap 4
(Data Gap)
33 Bytes
~~ ~,--______,I~U
Address ID Field
6 Bytes
Data
Address Mark
Data=FB or F8
1 - Track Address
Clock = C7
2 - 00 Byte
3 - Sector Address
4 - 00 Byte
5- CRC
6- CRC
Data
128 Bytes
CRC
2 Bytes
NextlD
Address Mark
Macro Command
1
2
3
4
STZ
SEK
SSR
5
6
RCR
SWD
MSW
MSR
FFW
FFR
7
8
9
10
S~
498
Bit 3
Bit 2
Bit 1
Bit 0
a
a
a
1
1
0
0
1
0
1
0
1
1
0
1
0
0
0
a
1
1
1
1
a
1
1
1
1
1
1
a
a
a
1
1
0
0
1
1
Hex
Code
2
3
4
5
6
7
D
C
B
---------------------------------------------------HD8843, HD88A43
Seek (SEK)
The SEK command is used to position the R/W head over the
track on which a Read/Write operation is to be performed. The
contents of the GCR are taken as the destination address and
the content of the CTAR is the source address; therefore, the
number of pulses (N) on the STP output are given by:
N = I(CTAR) - (GCR)I
HDR is a "High" for (GCR) > (CTAR) otherwise it is a "Low".
When a SEK command is issued, Busy is set, the head is
raised from the disk, HDR is set as described above, and N
number of pulses appear on the STP output. After the last step
pulse is used, the head is placed in contact with the disk. Once
the head settling time has expired, the Seek Command End flag
(lSR bit 1) is set, Busy is reset, and the contents of the GCR are
transferred to the CT AR.
rl---t--'"Vc~~~~~2
499
H08843, H088A43-------------------------------------------------
500
---------------------------------------------------HD6843,
command with the exception that the data transfer request
(STRA bit 0) is not set. The Status Sense Request interrupt can
be disabled by using the DMA flag of CMR.
Single Sector Write (SSW)
Single sector write is used to write 128 bytes of data on the
disk. After the command is issued, the address search is
performed. The remainder of the instruction's operation is
shown in Figure 22.
HD68A43
Write the
Data
Address Mark
(Clock = C7.
Data = FB)
501
HD8843, HD88A43-----------------------------------------------The basic operation for the MSR and MSW is the same as
that for the SSR and SSW respectively. The basic operation
begins with an address search operation, which is followed by a
single sector read or write operation. This completes the
operation on the first sector. The SAR is incremented, the GCR
is decremented, and if no overflow is detected from the GCR
(i.e., GCR become negative) the sequence is repeated until S
number of sectors are read or written.
The completion of an MSR or MSW is like that of an SSR or
SSW command. First RWCE is set and Busy is reset, after the
settling time has expired, the head is released.
If a delete data mark is detected during an MSR command,
STRA bit 1 (Delete Data Mark Detected) remains set throughout the commands operation.
When a multi-sector instruction is issued, the sum of the SAR
and GCR must be less than 27. If SAR + GCR > 26, an address
error (STRB bit 3 set) will occur after the contents of SAR
becomes greater than 26.
REGISTER DEFINITIONS
Bit 7
f---Function
Interrupt
Mask
Bit6
Bit 5
Bit 4
ISR3
Interrupt
Mask
DMA
Flag
FWF
Bit
3~1
Macro Command
The commands that control the FDC are loaded into the
lower four bits of the CMR. Information that controls the data
transfer 'mode and interrupt conditions are loaded into bits four
through seven.
Bit O-Bit 3: Macro Command
502
---------------------------------------------------HD8843, HD88A43
'IF
Command End
Command Set
HLO
HOR
LCT
:~~=)
----,
Settling
time
-----,
hseek time
STP
--
-k
r"
f--min. 0 ns
Seek time
min. 21's
TRZ
ROY"
-l_L--1-----/n-~I---I-.--~I~n~----~n~.~I~~--~8~2~---------------------r-------~
'I
'\
~----~3
"I"
STRA7
(Busy)
ISRI
(Seek Command End)
STP output is masked when TRZ becomes "High", But if TRZ falls to "Low" again before 82 pulse outputs are all provided,
STP output become available again from that time point,
.. When ROY is "Low" with Command Set, the execution is postponed until ROY becomes "High",
....
GCR Set
ICommand End
Command Set
CTAR Determined
I
-----------'",.------------------------0------1-\1
_pr\___________________..H .._________ 1
-!-l~
tlme-i
i1
-7"'"'"--:~------------n-----------_!I-I-I-___----------+---------::~~~:: gg=~ :~
m
LCT
~
min.
Ons
STP
~________+i____~1
HLO
HOR
tmlP.
---+-----+........ 1
:seek-----l
time
lJ- ---Jl.
2'----.....J 3
r1 ,- ,
L.......
in.32I's
n.1-,____.......J
(Difference between
ROY
"I"
1~:.~Co:m~.--~====:j------------------------1~------------------------------~
mand End)
!;';':I~~:~~~~::!~on
Max lms .
When ROY is "Low" with Command Set. the execution is postponed until ROY becomes "High"
fi03
HD6843, HD68A43--------------------------------------------------LTARSAR
Start Address Search
Set Set
"."."
Command Set
HLD
====i1--;
"
Comm!"nd End
(Address Error!
Settling
time - -
~~I'-------------,.---+-----------------41\
:7~~;ea:~:r ~~,;~~~~e~e~~ri~e
lOX
STRA7
(Busy)
ISRO~1
ISRO
(RIW Command End!
STRB3 =1
RDTVal~id~_ _ _ _~
\'--------
If HLO has already been "High" when the command is set, the FOC starts the address search immediately.
When ROY is "Low" with Command Set, the FOC waits for the execution until ROY becomes "High".
Figure 25 Timing Sequence of SSR, SSW, RCR, SVVD, MSR, MSW Command
(Relation with H LD and lOX)
ID-----~---
Data from
the diskette
FF
00
00
00
00
00
00
IDAM
Track
00
Sector
00
CRC
CRC
FF
FF
Check Timing
of Data
_ _ _ _ _+_-~--+--4--~-+--~--+-~--~-4--~--+-~--+--4-----
lOAM
detection
Track
Equal
CD
.. (!!)
R~e7
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _..J \
- - - - - - -
..
'.
-R~s-;t -
- - - - - - - - - - - Compare with
..
~ ------------------------'~R~S;;--------~\e;t---
LTAR
--------Compare with
Sector
~;~ :
____________________________~
_____~f~-----------
SAR
Sector
Track
Not Equal
Not Equal
Command End
ISR2
IS R 2 set by address
(Sense Request)
detection
@
@
In the case of Track Not Equal, is not set and 'i! CRC equals to the one calculated by FOC, STRAS is set.
In the case of Sector Not Equal, @ is not set and CD & are reset to search the next lOAM.
In the case of CRC Error, @ is not set andCD,& @are reset. (lSRO: Set, STRB1: Set, STRB3: Set)
When CD, , @, & @) are all set, ISR2 is Set. These four signals are reset with Command End.
When @ is ",", go to the data transfer routine.
504
---------------------------------------------------HD6843, HD68A43
:j
-I
Oala from
Ihe disketle
FF
FF
FF
~-GAP-
00
I~
3rd
Oala
127th 12Blh
Oala Oala
CRcl
FF
FF
~GAP-
~------------
mr If ~
iii
n a
DI
STRAO is ge nersted
r----
STRB2
CRC
'--
Read Oala
Valid
STRBO
2nd
Data
1st
Oala
--.,
10CRC
"0"
Data
b;AM
or
DAM
I
r-----------
ID AM undetecled)
Transfer Error
STRBI
I
(C RC Error)
;-L--------- >--------------,
ISRO
STRAI
(DO AM detected)
Error
ISR2
(Sense Reque st)
ISR Read
Unless DAM(FB) or DDAM(F8) is detected within 32 bytes after 10 field has been detected, STRB2 is set to end the command.
r - - - - - - - - - - - - - - Data -----------~
-10
DAM'
or
DDAM
Data from
Ihe disketle
1st
Data
2nd
Data
FF
10CRC
"0"
FF
Wnte Data--
WGT
OOR-OOSR ----+-----~r----~------ir--------~~_L-~J~
Transfer
Writing
on OOR
Transfer Error
STRBO
(Data Transfer Error)
--+------U.------------H---------------------H---------------1 ~--------------------.......I
(SRO
__
(RIW Command End)
(SR2
(Sensa Request!
ISR Read
As Data Address Mark, SSW command writes 'FB' and SWO command writes 'F8'.
505
Command End
HD8843, HD88A43-------------------------------------------------
Command Set
~~-+-T--~--------~--~~--~--------4--lrr_r--~--------~--~---------Address
Search
FOC
Operation
Address
Search
Data Transfer
Address
Data Transfer
GCR-l
Search
Data Transfer
GCR-I
GCR-I
~;~~~~~~----------------------~S~A~R~+~l~---------------~SA~R~+~I~~r-------_ _~S~A~R~+l~(-G-C-R-)=-O-------
,--------- --- ---,------- ------ :::.J ----------- i-----------(RIW eo'~~~n~d~E~nd~I--------~--------------------.p---~",...-=~----~ f---..1-__________.....J Command End
Command End with Address Error
Address Search and Data Transfer in each sector is the same as those of SSR or SSW command.
When Address Error occurs, it results in Command End. If an error relating to Data Transfer occurs,
Error flag is set. But the command continues to be executed to shift into the next sector.
Command Set
HLD
I
1,--------------------------1 r - - - - - - - - - - - - - " " \
Settling
t,me
WGT
ht
Data
OOSR
2nd
Data
STRAO
(Dat8 Transfer Request)
2nd
Data
1st Data
DOR
The first onebyte data must be set into OCR before Command Set,
If HLD has already been "High" when the command is set, WGT becomes "High" immediately.
When '00' command is set into CMR, an interrupt of Command End is not generated,
3~~'
1_------III~~Set
.. oo"Com!mandintOCMR
-i ...,,;~,,~ -j~
~:~
.~_
Data _ _ _ _ _ _ _ _.J
1st
Data
DSR
DIR
~fe~i~9
out _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _H _ _--"~.JI.._
STRAO
(Data Transfer Request)
If HLD has already been "High" when the command is set, Read operation starts immediately without waiting for the settling time.
When "00" command is set into CMR, an interrupt of Command End is not generated.
506
---------------------------------------------------HD6843, HD68A43
Bit 6: ISR3 fnterrupt Mask
CMR bit 6 (ISR3 Mask) is used to control the operation of
ISR bit 3. A logic "I" in CMR bit 6 inhibits output of STRBOR-Interrupt signal to IRQ. If CMR bit 6 (ISR3 Mask) and
CMR bit 7 are "0" STRB-OR-Interrupt signal will be output to
IRQ.
times. For MSR and MSW commands, it is set for each sector.
In the PC I/O mode, an interrupt occurs when Status Sense
Request becomes a logic "1". In the DMA mode, (DMA flag of
CMR is set) Status Sense Request is unchanged and does not
generate an interrupt when the address ID field has been
verified.
Bit 3: STRB-OR
STRB-OR is an "OR" of all of the bits of Status Register B.
Table 5
Causes
of
Interrupt
+ STRB2 + STRB3 +
+ STRB6 + STRB7
+ STRB2 + STRB3 +
+ STRB6 + STRB7
CMR5
(DMA Flag)
ISRO
(Read write
Command End)
ISRO, ISRl, and ISR2 are cleared when the Interrupt Status
Register is read, but ISR3 is cleared only after Status Register B
has been read except when FI input is "High".
ISRl
(Seek Command
End)
ISR2
(Status Sense
Request)
ISR3
(STRB-ORInterrupt)
x = No effect
M = Bits that are used as masks
Bit 3
STRB
-OR
Bit 2*
Bit 1*
Bit 0*
Delay
Seek
Status
Read Write
Sense Command Command
End
Request
End
* Cleared by RES
B
f
4096
f
~------------~~
I 2/--j3
f
A1024
f
------..ll
507
Bit 7*
Busy
Bit 6
Index
Bit 5 * Bit 4
Track
Not
Equal
Write
Protect
Bit 3
Track
Zero
Bit 2
Bit 1 *
Drive
Ready
Delete
Data
Mark
Detected
* Cleared by "'RES
Bit 7: Busy
When Busy is a logic" I ", the FDC is executing a command
and no new commands can be issued. Busy should be confinned
to be "0" before reading ISR or STRB as well as issuing a
command.
Sector Address Register (SAR); Hex address 4, write only
* Cleared by RES
Bit 6*
Hard
Error
Sector Data
File
Write Inoper- Seek
Address Mark
Error
Error Unde- Undeable
tected tected
Bit 5
Bit 4 *
Bit 3
Bit 2* Bit 1 *
CRC
Error
Bit O
Data
Transfer
Error
* Cleared by RES
508
--------------------------------------------------HD6843, HD68A43
Bit 2: Data Mark Undetected
If a valid data mark is not detected in the data block of a
sector, it is indicated by a Data Mark Undetected error.
Bit 3: Sector Address Undetected
The Sector Address Undetected bit can be set on two conditions; not finding the sector address and a CRC error on an
address ID field.
If the disk makes three revolutions during an address search
operation and the sector address specified in the sector address
register is not found in any of the address ID fields, a Sector
Address Undetected condition is indicated.
A CRC error that occurs on an address ID field will set bit 3
also. Table 6 shows how bits I and 3 are related.
Table 6 Relationship of CRC Error and
Sector Address Undetected
CRC Error
(STRB1)
Sector
Address
Undetected
(STRB3)
Condition
0
0
1
1
0
1
0
1
No Error
Sector Address not Detected
CRC Error on a Data Field
CRC Error on Address 10 Field
41
Bit 31 Bit 2
The GCR contains the destination track address for the RjW
head on an SEK Macro Command. The contents of the GCR are
transferred to the CTAR at the end of the SEK Command. For
multi-sector read or write operations (MSR, MSW), the GCR
contains the number of sectors to be read minus one. During the
MSR or MSW execution the GCR is decremented after each
sector is read or written.
CRC Control Register (CCR) ; Hex address 6, write only
Bit 7
Not Used
Not
Used
Bit 1 Bit 0
Shift CRC
CRC Enable
Bit
I Bit 1 I Bit 0
Bit 7
509
HD8843, HD88A43-------------------------------------------------
CRC
Enable
Reset
(CCRO=O)
CRC
Enable
Set
(CCRO=1)
OCK(Oata
Clock Input)
Load Signal
from OISR
to OIR
OTR
CRC Enable_--I~----''''
(CCRO)
CRC
valid
OISR
OIR
CRC Calculation includes Data Byte 1 through Data Byte n.
Shift
CCR Set
(CCRO=1)
Write (CCR1 =1)
Byte n
to OOR
(Data n)
Shift
Clock
Load signal
from OOR
to OOSR
STRAO
(OTR)
CCRO
(CRC Enable)
CCR1
(Shift CRC)
CRCvaiid
OOR
OOSR
WDT
Output
Data 2
The CRC Calculation includes Data Byte 1 through Data Byte n-1.
510
Write Byte
n+2 to OOR
(Data n+2)
CCR Set
(CCRO=O)
(CCR1=O)
---------------------------------------------------HD6843, HD68A43
Table 7 Programming Reference Data
Table 7 is a summary of the information in the data sheet and can be used as a reference when programming the HD6843.
CMR
WO
Bit 7
Bit 6
Bit 5
Bit 4
Function
Interrupt
Mask
ISR3
Interrupt
Mask
DMA
Flag
FWF
Bit 7
ISR
STRB
Bit 6
Bit 6
Busy
Index
Bit 7 *
Bit 6 *
RO
RO
Bit 5
Bit4
Not Used
RO
Bit 7 *
STRA
Hard
Error
Write
Error
Bit 5 *
Track
Not
Equal
Bit 5
File
Inoperable
Bit 4
Write
Protect
Bit 4 *
Seek
Error
Bit 3 *
511
Bit 2 *
Bit 1 *
Bit 0 *
Macro Command
Bit 1 *
Bit 3
Bit 2 *
STRB
-OR
Status
Sense
Request
Bit 3
Bit 2
Bit 1 *
Bit 0 *
Drive
Ready
Delete
Data Mark
Detected
Data
Transfer
Request
Bit 1 *
Bit 0 *
Track
Zero
Bit 3 *
Bit 2 *
Sector
Data
Address
Mark
Undetected Undetected
* Cleared by RES
RO - Read Only
WO - Write Only
R/W - ReadlWrite
Bit 0 *
Read Write
Seek
Command Command
End
End
CRC
Error
Data
Transfer
Error
Instruction
Hex Code
Instruction
STZ
SEK
SSR
SSW
RCR
SWD
A
B
C
D
FFR
FFW
MSR
MSW
4
5
6
7
Set Condition
Track Not
Equal
STRA5
Data
Transfer
Error
STRBO
Reading of STRB
CRC
Error
STRB1
Aeading of STR B
Unchanged
Data Mark
STRB2
Undetected
Reading of STAB
Unchanged
Sector
Address
Undetected
STRB3
(1 1 Sector Address of I D
field is not equal to the
content of SAR.
(21 CRC Error on ID field
Aeading of STRB
SSR, ACR, MSA
after Busy (STRA71
SSW, SWD, MSW
is reset.
Unchanged
(Head remains
loaded after
settling time
has expired.)
Seek Error
STRB4
Aeading of STRB
STZ
Unchanged
FI signal of the
FDD is reset when
"High" pulse output is provided by
reading of STRB
at FI="1".
All commands
Aeading of STRB
Aeading of STRB
All commands
Error
File
Inoperable
Write
Error
STRB5
I STRB6
Hard Error
STRB7
Not Ready
during the
idling
STRA2
Reset Condition
Command
Issuing of SSR,RCR,
MSR, SSW, SWD or SSR, RCR, MSR
SSW, SWD, MSW
MSW Command
Command Execution
These errors except STRB5 and STAA2 are reset by'RE'S inputs.
** Head is unloaded if the new command is not issued during the settling time after Read/Write command ends.
512
Unchanged
No
Unchanged
interrupt
Unload the
Request
head imediatel
(lSAO or (HLD="Low"l
ISA1,
Set WGT to
ISA31
"Low"
Unload the
head imediatel y
(HLD="Low"
Set WGT to
"Low"
Unload the
Request head imediatel y
OSAO or (HLD="Low"l
ISA1,
Set WGT to
ISA3)
"Low"
Unload the
No
head imediatel y
interrupc (HLD="Low")
HD6844, HD68A44,
HD68B44
DMAC (Direct Memory Access
The HD6844 Direct Memory Access Controller (DMAC)
performs the function of transferring data directly between
memory and peripheral device controllers. It controls the
address and data buses in place of the MPU in bus organized
systems such as the HMCS6800 Microprocessor System.
The bus interface of the HD6844 includes select, read/
write, interrupt, transfer request/grant, and bus interface logic
to allow the data transfer over an 8-bit bidirectional data bus.
The functional configuration of the DMAC is programmed via
the data bus. The internal structure provides for control and
handling of four individual channels, each of which is separately
configured. Programmable control registers provide control for
the transfer location and length, individual channel control and
transfer mode configuration, priority of servicing, data chaining,
and interrupt control. Status and control lines provide control
to the peripheral controllers.
The mode of transfer for each channel can be programmed as
cycle-stealing or a burst transfer mode.
Typical applications would be with the Floppy Disk Controller (FDC), etc ..
FEATURES
Four DMA Channels, Each Having a 16-Bit Address
Register and a 16-Bit Byte Count Register
Controller)
~~-
.------------------------i
(DP-40)
' - -_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _--.J
PIN ARRANGEMENT
<J>,DMA
Vss 1
Cs/TxAKB 2
RES
DGRNT
DRaT
DRQH
TxAKA
BLOCK DIAGRAM
TxRQ.
HD6844
TxRQ,
TxRQ,
Os
Data
Bus
Channel Four
Request/ Channel
Grant
Control Controls
513
(Top View)
Value
Unit
Supply Voltage
Item
Vee *
-0.3- +7.0
Input Voltage
Yin *
-0.3 -+7.0
Operating Temperature
Topr
-20 - +75
V
c
Storage Temperature
TS1Q.
-55 -+150
Permanent LSI damage may occur if maximum ratings are exceeded. Normal operation should be
under recommended operating conditions. If these conditions are exceeded. it could affect
reliability of LSI.
Symbol
min
typ
max
Unit
Vee *
V 1L *
4.75
5.0
5.25
-0.3
0.8
V 1H *
2.0
Topr
-20
25
Vee
75
V
c
Input Voltage
Operating Temperature
* With respect
to
typ*
max
Unit
V 1H
2.0
V 1L
-0.3
Vee
0.8
Item
Symbol
Test Condition
lin
Vin=Q-5.25V
-2.5
2.5
JJ,A
I TS1
V in =O.4-2.4V
-10
10
JJ,A
IOH=-205JJ,A
2.4
IOH=-145JJ,A
2.4
IOH=-100JJ,A
2.4
VOL
IOL=1.6mA
less
Vin=OV, Fig. 10
0 0 -0,
Output "High" Voltage
Ao-A lS , R/W
V OH
CS/TxAKB
Po
Power Dissipation
<P2
0MA
R/iii
TxRO oOGRNT
Output Capacitance
r.
~In
3,
Vin=OV, Ta=25C
f=1.0MHz
RES,
Cout
* V ec=5.0V, Ta=2S"C
514
0.4
10
16
mA
500
1000
mW
20
12.5
10
12
pF
pF
I "High" Level
I "Low" Level
HD6844
Test
Condition
min
typ
tcycrJ>
Fig.2
1,000
PWrJ>H
Fig. 2
450
PWrJ>L
Fig.2
trJ>r' trJ>f
Symbol
Item
HD68A44
typ
HD68B44
Unit
max
min
max
min
typ
666
500
ns
280
235
ns
400
230
210
ns
Fig.2
25
25
25
ns
Test
Condition
min
max
min
max
min
max
Item
HD6844
HD68A44
HD68B44
Unit
typ
typ
typ
max
tTQS1
120
120
120
tTQS2
210
210
155
tTQH1
20
10
10
Edge
tTQH2
20
10
10
DGRNT
tOGS
155
115
DGRNT
tOGH
10
125
10
10
Address Output
Delay Time
TxSTB
270
180
Address Output
Hold Time
TxSTB
Address Three-State
Delay Time
Address Three-State
Recovery Time
Edge
TxRQ Setup Time
ns
Fig.3
ns
Ao~A!S, R/W,
ns
Fig.6
Fig.6
Fig.7
30
20
20
tAHO
35
35
35
Fig.7
270
270
270
ns
Ao ~A1S' R/Iii
Fig.7
270
270
270
ns
Fig.5
375
250
210
ns
tTK01
Fig.5
400
310
250
DGRNT Rising
tTK02
Edge
Fig.8
190
160
150
tOE01
Fig.6
300
250
210
DGRNT Rising
tOE02
Edge
Fig.8
190
160
125
max
min
typ
max
min
140
70
tATSR
160
ns
ns
IRQ/DEND Delay
Time
ns
tAD
Ao~A!S, R/W
Delay Time
Fig.4
ns
3. BUS TIMING
1) READ TIMING
Item
Symbol
Ao~A4' R/W,
CS
Ao~A4' R/W,
Cs
D7~D7
Do~D7
Do~D7
Test
Condition
HD6844
min
typ
HD68A44
HD68B44
Unit
140
tAHI
10
10
10
tOOR
320
220
tACC
460
360
tOHR
10
10
tAS
Fig. 2
515
typ
max
-
ns
ns
180
ns
280
ns
10
ns
Symbol
A o -A 4 , R/W,
Cs
Ao -A 4 , R/W,
Cs
D o -D 7
D o -D 7
Test
Condition
HD6844
min
140
tAS
HD68A44
HD68844
Unit
max
min
typ
max
min
typ
max
140
70
ns
ns
tyPo
10
10
10
tosw
195
80
60
ns
tOHW
10
10
10
ns
tAHI
Fig. 2
R/W
BUS
IRQ/
C S/ TxAKB
ORQT - - - 4 - - - - 1
DRQ
DGRNT ---4---~ H /T
DRQH
CONTROL.
CHANNEL
.....- - - . . . , CONTROL.
#0
REGISTER
#1
(6X4)
#2
#3
1------TxRa>
1------TxRQ,
1------TxRQo
1------TxRQo
CONTROL.
RES-
VccVss_
(TxAKB)
516
tcyctP----------..-j
tP,OMA
Ao:::.A4 (Input)
R/W (Input)
~ (Input)
tOOA
~-----tACC------~
2.4V
DO -0 7 (Output)
(Read Operation)
O.4V
DO -0 7 (Input)
(Write Operation)
O.8V
517
1'-------
___________ j2.0V
to:'-I
---------
tP2DMA
~-----2.0V
DGRNT
Hold Timing
<P1DMA
DGRNT
toaD
2.4V
O,4V
2.4V
TxAKA
CS/TxAKB (Output)
O.4V
518
2 DMA
tAD-
2.4V
Ao'::::..A, 5 (Output)
R/W (Output)
TxSTB
O.4V
t DED
2.4 V
O.4V
------------------~
-------------------------
2 DMA
(or DGRNT)
2.4V
O.4V
2 DMA
tAHO
DGRNT
CSfTxAKB (Output)
IRQ/DEND
5.0V
2.4kn
Test terminal
130 pF
11 kn
Ao-A 1S R/W
CS/TxAKB
90pF
30 pF
16 kn
24kn
24 kn
0 0 -0 7
Test terminal D - - - f - - -__--I. .- - - t
0 1 -0 4
50 pF
1S2074(8) or equivalent.
r----------------------------l
I
I
I
HD6844
i
I
I
I
I
TxAKB output
ON
"i____
ri
--.....--)c:>-.....- - - - - f l
ICSS
OFF
D.C. Ammeter
I
I
I
I
I
I
I
I
I
Vss
TxAK ENABLE
Vss
CS input
L ____________ _____________ J
~
520
DEVICE OPERATION
The DGRNT signal must cause the address control and data
lines to go to the high impedance state. The DMAC now
supplies the address from the Address Register of the channel
requesting. It also supplies the R/W signal as determined from
the Channel Control Register. After one byte is transferred,
control is returned to the MPU. This method stretches the 4>1
and 4>2 clocks while the DMAC uses the memory.
The second method of cycle-stealing is the Halt Steal mode.
This method actually halts the MPU instead of stretching the 4>1
clock for the transfer period. This mode is initiated by the
DMAC bringing the DRQH line "Low". This line connects to
the MPU HALT input. The MPU Bus Available (BA) line is the
DGRNT input to the DMAC. While the MPU is halted, its
Address Bus, Data Bus, and R/W are in the high impedance
state. The DMAC now supplies the address and R/W line. After
one byte is transferred, the HALT line is returned "High" and
the MPU regains control. In this mode, the MPU stops internal
activity and is removed from the system while the DMAC uses
the memory.
The third mode of transfer is the Halt Burst mode. This
mode is similar to the Halt Steal mode, except that the transfer
does not stop with one byte. The MPU is halted while an entire
.block of data is transferred. When the channel's Byte Count
Register equals zero, the transfer is complete and control is
returned to the MPU. This mode gives the highest data transfer
rate, at the expense of the MPU being inactive during the
transfer period.
INPUT/OUTPUT FUNCTIONS
Initialization
Transfer Modes
Address lines Ao-A 4 are both input and output lines. In the
MPU mode, these are high impedance inputs used to address the
DMAC registers. In the DMA mode, these lines are outputs
which are set to the contents of the Address Register of the
channel being processed.
521
indicl1ting that the MPU has halted and turned control of its
busses over to the DMAC. For a design involving TSC Steal and
Halt mode transfers, this input must be the OR of the clock
driven DMA Grant and the MPU BA.
(/>2 DMA
Each of the four channels has its own high impedance input
request for transfer line. The peripheral controller requests a
transfer by setting its TxRQ line "High" (a logic" I "). The lines
are sampled according to the priority and enabling established in
the Priority Control Register. In the Steal mode and the first
byte of the Halt Burst mode, the TxRQ signals are tested on the
positive edge of (/>2 DMA and the highest priority channel is
strobed. Once strobed, the TxRQs are not tested until that
channel's data transfer is finished. In the succeeding bytes of the
Halt Burst mode transfer, the TxRQ is tested on the negative
edge of (/>2 DMA, and data is transferred on the next (/>2 DMA
cycle if TxRQ is "High".
Reset (RES)
Two DMA request output lines and a DMA Grant input line,
together with the system clock, synchronize the DMAC with the
MPU system.
DMA Request Three-State Control Steal (DRQT)
begun.
CS/TxAKB
TxAKA
Channel #
o
o
2
3
522
on~he address which the MPU reads out is the renewed one,
that is, the memory address for the next transfer. When I-block
transfer has completed, final memory address +1 is read out.
Symbol
A4
A3
A2
At
Ao
Address
(Hexadecimal)
Channel
Address Register
ADRH
ADRl
0
0
0
a
0
a
0
a
0
a
0
1
00
01
BCRH
BCRl
0
a
a
a
0
a
a
a
1
1
a
1
02
03
Address Register
ADRH
ADRl
1
1
a
a
a
a
1
1
a
a
0
1
04
05
BCRH
BCRl
1
1
a
a
a
a
1
1
1
1
a
1
06
07
Address Register
ADRH
ADRl
2
2
a
a
1
1
a
a
a
0
a
1
08
09
BCRH
BCRl
2
2
a
a
1
1
a
a
1
1
a
1
OA
OB
Addres~
ADRH
ADRl
3
3
a
a
1
1
1
1
a
a
a
1
OC
aD
BCRH
BCRl
3
3
a
a
1
1
1
1
1
1
a
1
OE
OF
CHCR
CHCR
CHCR
CHCR
0
1
2
3
1
1
1
1
0
a
a
0
a
a
a
a
0
a
1
1
a
1
a
1
10
11
12
13
PCR
14
Register
ICR
15
DCR
16
(NOTE)
1) All the registers can be accessed by R/W operation. Unused bit of the register is read out "0".
2) H/L of ADR and BCR means the higher (H) a bits/the lower (L1a bits of a 16-bit register.
3) 16-bit ADR and BCR can be read or written by one instruction, using MPU's 2-byte LOAD/STORE instruction.
Register Address
e.g.LDX $t-*Oc
............ [(ADRH3)--> (Index RegisterHll
Address of DMAC
(ADRL 3) --> (Index Register Ll
523
Name
Function
R/W
R/W
R/W
"a"
"1"
Burst/Cycle Steal
R/W
Burst Mode
TSC/HALT
R/W
TSC Mode
HALT Mode*
3
4
Address down/up
R/W
Address: -1
Address: +1
Not used
Not used
Busy/Ready Flag
Busy
(DMA Transfer Operation)
Ready
(No DMA Transfer Operation)
DEND Flag
No Interrupt
524
Bit
No.
Name
R/W
R/W
"1"
"0"
R/W
R/W
Tx RO of Channel 2 is accepted.
R/W
Not used
6
7
Rotate Control
R/W
1~2~3.
Rotate Mode
525
Bit
No.
Function
Riw
Name
I RQ Enable #0
R/W
"1"
fRO of Channel 0 is able to be output.
"0"
I RQ output of Channel 0 is masked.
I RQ Enable #1
R/W
I RQ Enable #2
R/w
I RQ Enable #3
R/W
Not used
IRQ Flag
Bit
No.
0
1
2
3
Name
Data Chain Enable
Data Chain Channel
2/4-Channel Mode
5
6
7
Not used
Function
R/W
"D"
"1"
R/W
R/W
R/W
R/W
OCR
Bit 1
OCR
Bit 2
Channel #0
Channel #1
Channel #2
or
r------OGANT
! &
CS
- - - CS Input
-----<X
(SA of MPUI
Input
---tJ-- -- - CS
1
1
1
1
1
1_ _ _ _ _ _ - - -
526
: 3-state buffer
1
'-------
TxRQo~TxRQ3
[Note]
:----- M P U ----
Dead
~2oMA
tTQH1~r-~~CD~~.-~~~~---.--~~~~~~~~~
", "
~"""f...:...":"';"";"~"----~-~--: ,:
:
~~~~--+-~--~4--~~~: :
__ L- :
TxRQo-TxRQ3
oRQH
oGRNT
- - -_______________~ ___J
,_..l.-j--'~t.::;;-r-=Qo:;....-~-_ ~_ v
:
(MPU BA)
TxSTB
'tAO
..;:----...;:~~~'
- - - - - - - - - - -...
: --,
:---:t TK01
,):
TxAKA
::
TxAKB
(output)
CS(input)
"
""--<,:
\!)II
ii
~tTKoi
: :,@
---------------,--~,-----..;:~Nt:::::::;:::;i-J~
rl tAS ~ tAHI :-;. t TK02
______-'x~____.J,X:s.'_!
-.....;i....1
Ao-A1S,R/W
(output)
Ao-A., R/W
(input)
;--,tAO
....;....1
.,.;:=:;6. . .
iJ:'
MPU
:!
tOGS
~~'-@--~'~-----
,:
'
MPU
00-07 (output)
00-07 (input)
:
~ tOE01 ~ tOE01
,.le'\'.J'* * *
'tOE02
OMA
END
H t OE0 1
.'
~-----
**
527
Wait for
TxRQ
Input
Checked - - ,
2DMA
L-
DMA Transfer
lAo - AI s, R/Vii, TxSTB,
TxAKA/B Output)
Burst
Mode
528
tP2DMA
TxRQ
\~-_e_---{).----J
DGRNT
TxSTB
DRQH
\~--------+---~~----~
( For this period, both the MPU and the DMAC
\ are in the wait state.
DMA
tP2DMA
TxRQ
OGRNT
TxSTB
529
HD6844. HD68A44. HD68B44----------------------------------------When BCR is not "0", TxRQ is checked at the falling edge
of tP2 DMA.When TxRQ is at "High" level, DMA transfer is
performed through '" again. When TxRQ is not at
~igh" level, DMAC waits for becoming "High" level.
IRQ/DEND output goes to "Low" level.
@ DRQH output rises to "High" level and MPU gets into
Instruction Cycle again.
@ Ao '" A 1S and R/W get into high impedance state.
@ DGRNT falls to "Low" level.
The transfer of the first byte (CD - ) is performed in the
same way as that in cycle steal mode. But in the second-byte
and subsequent transfer, TxRQ is checked at the falling edge of
tP2 DMA and if TxRQ is at "High" level, DMA transfer is performed at the following cycle. Therefore, a high-speed response
which is not exceeding 2-clock-cycle is feasible.
In burst mode, TxRQ should be also, in principle, set to
"High" when I/O request is asserted, and reset to "Low" when
TxSTB goes to "Low". If TxRQ is asserted as level input without being reset, DMA transfer is performed at all cycles of
lP2 DMA since TxRQ is always at "High" level at the falling edge
of lP2 DMA. Its example is shown in the second-byte and the
third-byte transfer in Fig. 16.
First-byte
Dead
--------MPU----~
Second-byte Final-byte
rDMATDummYTDMATDMA"1
Dead
ORQR
DGRNT
(MPU BA)
TxSTB
---------~,-----+~~
f-t TK01 '
__
TxAKA
r--MPU--
!-....!
~~--~~l~__~~--t+AO~'~,-------~-------: ~ tTKD2
! :~
TxAKB
(output)
CS(input)
(output)
Ao-A4, R/W
IRQ/DENB
-l
t-tATSR:
IGrs
Ao-A,S, R/W
(input)
-__-_-_-_-_-__-_-_-_-_-_-_-_-_-_-_-_-_-_-_-___--i-
i-tAO
iii
:-tAD :--:tATSO
(i):~@I)
: @
'---
\'---............
,
<I X
f- t OE02
530
MPuioeadToMA1--oeadTMPu~2MPU
TxRQ
DRQT
DGRNT
(DGRNT output of
the CPG)
TxSTB
I
I
: tTKO!
r----
hKO!
.-----,
: ~@:
TxAKA
;\;
TxAKB
(output)
CS(intput)
__________
~x~
______ __J;r:
~
~
Ao-AI5, R/W
tATSR
-------_~:---@;DMA
I
I
I ;,tOED!
u
~tATSO
! ~)-,..'cn~Q)- - - - - - - - - - -
(~)
__M_P_u__~i__~~>--~--------~--<<=,____+_--M-P-U~----Xu-_
I
____M_P_U
__~X~
__~________~x~
~ :-tAHO
(output)
Ao-A., R/W
(input)
~~
__________________
tOED!
I tOED!
~.:J
~ tOED!
\\ ____
I
__ u
__
~WhenlRaiS
put out
Priority Control
Basic p.iority Control
There are two kinds of the DMAC priority control function.
One is to mask TxRQ on each channel by TxRQ Enable bit.
The other is priority-order-determining-circuit which th~ DMAC
has as a hardware.
Moreover, the priority- order- determining- circuit has two
operation modes (the rotate mode and the normal mode).
Structure of the priority control circuit is shown in Fig. 18.
As shown in Fig. 18, TxRQ of the channel whose TxRQ Enable
bit is at "1" level becomes an input of the priority-order-determining-circuit. Then it is checked whether TxRQ is at "High"
level or not.
"0".
531
o
The channel which is
executing DMA transfer
now becomes "1".
All other lines are
at "0" level.
TxRQ 3
Executing-Channel-Number
Latch-Circuit
ci>lDMA
______----J!
LJ
TxSTB
Strobesignal
Grant
of executing
channel
lj
1 -------------t------------r-''"'''"''I------------I
:.
Strobe
possible
Strobe
prohibited
'Channel cannot
be changed.)
Strobe
possible
Strobe possible
(But channel under executing
DMA transfer is prohibited.l
532
~----------
DMA
---------1
~--
MPU - - -
1/J 2 DMA
TxSTB
__________~r_\~______I
LJ
IRQ/DEND
Strobe
)
Grant signal
of executing
channel
Rotate Mode
There are two operation modes in priority-order-determining
circuit. These are Normal Mode and Rotate Mode. In the normal
mode, the order of priority is fIxed at numerical order. (Channel
o is given a first priority and then is followed by Channel 1 ~ 2
~ 3.) In the rotate mode, the channel next to the channel with
Channel Number
#0
1. Order of Priority
in the reset state
#1
#2
....... 2
....... 3
#3
....... 4
DMA transfer
2. Order of Priority
immediately after
Channel #1 has
performed DMA
transfer
3. Order of Priority
immediately after
Channel #0 has
performed DMA
transfer
--4
~1
~1
--2
--2J
These numerals
show the
order of
priority.
DMA transfer
--3J
533
HD6844, HD68A44,
HD68B44------------------------------------------
TxSTS
::i: Channel
----------------~
!EXecuting
IRO/DEND
#0
#1
J;
#2
# 1
#3
#2
#3
~~
a:
I #0
\EXecutin g
::i: Channel
# 1
# 1
#3
#3
----------------------------------~
IAO/DEND
[Notel Suppose that TxAO o - TxA0 3 = "High", SeA =2 and TxENo - TxEN 3
=",". All channels are assumed to be in HALT cycle steal mode.
534
----I
r-
Dead
DMA
-T -Dead -T
DMA -:
Dead
r----
MPU -
1>2DMA
TxRQa
TxRQ/i
DGRNT
(MPU BA)
I :
TxSTB
I--{ tTKDI
\~
CHa
TxAKB
CH/3=:=\
t--1 tTKDI
TxAKB
'g
C:CHa
(output)
CS (input)
<
Ao- AI5, R /W
(output)
- -
c.__. . .XIl.-_
- - - - - - - - - - - - -- - - - - -- - -
---
MPU
OMA
~~
>
)(
>
\Input}
CH/3=='=/
-->-
HALT Mode)
MPU
__________________
~r-I~
____________________
;2OMA
TxRQa
TxRQB
ORQT
OG RN T
"I
I, , , , , ,
\~
, , , I
_____
_________________JI
r.""----------..
_ _ _ _ _ _. . . . / . - - - - - -......~
~~~
't-,- - - - - - - - ' :
TxAKA
Ha!
TxAKB
CS- (input)
\,-__CHb=~_--J1
: . . . . . . ______.:7
..
tATSO
. . . . . . .______....1'--
-----------t---:::::===::::;:,::::~~,~~------~---<:::::===::::)>------------
(input)
------
u------t-"
!>
'._____ __r-j_
; :>
~ tOEDI
Ao-A., R/W
IRQ/DENO
(output)
CHa!
(output)
Ao-Als,R/W
'----------
----------+----~~r-----~--~:----~'------J~---------
C. __ :oJ
<___________~X__
tDI::OI
\:._._.7
535
Dead
HALT
OMA -j
TSC
Dead
Dead
I.
TxRQ.8
ORQH
i5RQf
HALT
Dead
OMA -1 Dead
. I
~=~---------------\\]~::3>:\~_______.-------------------------_ _ _ _ _ _- - J
--------------,,~
__________
~/r------------~-------------------------
~:~~PGCGRNT)---L:..~~~~~~~~~~~~:=~\----------~----------Jlr-------------. -CPG
t-;'STe
rr----~--------~
CHa--....,...-----CH,I:/
TxAKA
TxAKB
'--___
__
CHa
CH=-"a::-:_....,.!"_-_-:_-:_CH,I:/~_____ir_r
-....J
CHa - - - - -
!......:=
C'S(input)
Ao-A,s. R/W
(output)
:-:t"TSD
--<
Ao-A . R /W
>'
C:=.::::>--
>-._-------
<
(input)
iRQ/DEND
__
~;
._.:1
'~
____________________ ./ '_._.=.1
MPU*
DMA
'2DMA
TxRQ
DRQH
\\\\ . \
f \'--______..J/
\lilZJ
kJ
DGRNT
(SA)
TxSTB
TxAKA
TxAKB
,'--------
'--J
I
Figure 26 Successive 2byte Transfer of One Channel (HALT Cycle Steal Mode)
HALT ~ HALT (by one channel)
536
- - - - - - - - - - - - - - - - - - - - H D 6 8 4 4 . HD68A44. HD688.44
Status Flag
DMAC has BUSY Flag, DEND Flag and ZERO Flag on each
channel. The former two of these flags can be read out by
MPU, but ZERO Flag cannot be read out. Set and reset timing
of each flag are shown in Fig. 27.
BUSY /READY Flag
This flag is set to "I" when it accepts the first-byte TxRQ
of its corresponding channel. After I-block transfer has completed and BCR becomes "0", it is reset to "0". Therefore,
while this flag is "I", that is, its corresponding channel is being
used, the next block transfer cannot be performed.
DEND Flag
This is the interrupt flag to indicate the end of DMA transfer of its corresponding channel. After I-block transfer has completed and BCR becomes "0" , this flag is set to " 1". This flag is
reset to "0" immediately after the Channel Control Register
having this flag is read out.
ZERO Flag
This is the internal flag to indicate whether the data stored in
the BCR is "0" or not (It cannot be read out).
MPU
;2DMA
TxRQ
TxSTB
IRQ/DEND
-------t--------------.
BUSY/READY _ _ _ _ _ _- - J
Flag
DEND Flag
-------------------4----J
ZERO Flag
MPU Write
BCR
BCR
MPURead _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _~r1~
______
CHCR
Figure 27 Timing of Status Flag (Suppose that BeR is 2 in the initial state)
When BCR is "0", ZERO Flag is "0". When BCR is not "0",
it is "1".
In the reset state, this flag is "0". If data that is not "0" is
written into BCR, this flag is set to "1". When BCR becomes
"0" after I-block data transfer has completed, or MPU writes
"0" into BCR, this flag is reset to "0".
The function of ZERO Flag is to prohibit accepting TxRQ
of its corresponding channel while this flag is "0" (that is, BCR
is "0") (See Fig. 18). While ZERO Flag is "0", TxRQ is not
accepted even if TxEN is "1". This function avoids an false
operation even if "High" input is provided to TxRQ before the
initialization of the register.
When RES pin goes to "Low", this flag becomes "0", but the
number in BCR is not reset to "0". Therefore, the state of this
flag and BCR are not the same. In this case new data should be
written into BCR (Then ZERO Flag becomes" 1").
DENDpin.
The function of DEND output is to inform I/O controller of
the end of I-block transfer. After I-block transfer has been
completed and BCR becomes "0", DEND output provides
"Low" pulse whose cycle is one clock, being synchronous with
the final I-byte data transfer. 4 channels have only one DEND
output in common, so each channel determines whether DEND
output is its own output or not, combining with TxAK signal.
When TxAK of the channel is "Low" and DEND is "Low",
it shows that the cycle is the last one of DMA (See Fig. 29 and
30).
The function of IRQ output is to inform MPU of the end of
I-block transfer by interrupting it. As shown in Fig. 28, IRQ
output is logical AND-OR of the interrupt flag (DEND Flag)
and IRQ Enable bit of each channel.
IRQ and DEND outputs are multiplexed. IRQ/DEND pin is
used as DEND output during DMAC cycle and IRQ output
during MPU cycle. Moreover, DGRNT signal separates DEND
and IRQ by its "High" or "Low". In detail, see Fig. 29 and
Fig. 30.
i*1
DEND Flag
(CHCR Bit 7)
- - - IRQ Output
;; 2
>---------+-+---i
i* 3
)-----t-+--+--i
~3~2#It::O
'-----v----'
IRQ Enable Bit (PCR Bit 0-3)
Figure 28 Logic of
iFfo Output
----------~~~----------~
II' ___________ r::--:1
M- 1 I
+-__--'
~2DMA
#0
TxAK
~I
___
IRQ/DENO
DGRNT
(BA)
oEND
\:0, ________~-_In-th-e-c-a-se-w-h-e-re-ot-h-e-r------~
"
-----~--~------------------------------~--------------
538
DGRNT
Channel Number
IRQ/DE-NO
~:':IDEMJ
TxSTB
DMAC
I
T.AKA
;f
OJ
#1
TxAK
Decoder
ADR
eCR
#0
#0
# I
;I:
#2
#2
#3
#3
----
I
"---nl)
OCR specifies
the channel to
which the contents
of Channel #3 are
transfered.
539
r--DMA
MPU---
fz'DMA
TxRQa
It ',' ,7
\~------------------------~----~I
DRQH
______________________
,'-------
--J~
DGRNT
(MPU BA)
TxSTB
\'-_ _ _..J
TxAKA
TxAKB
(output)
CS
(input)
:'
______
~x~
___
CHa
,'-___>C
~7
Ao-Als, R/W
(output)
Ao-A., R/W
(input)
CHa
<
______~x~_____~xc:::::::---~----~---~-----<c~:::~~::x::
tOED2 : _ :
\ ' -_ _ _...
-"--'--------,
, The contents of ADR & BCR
of Channel #3 are transfered
to Channel Q.
--
MP U
I-
-----j
DMA
I'
0\
f---------,
;2DMA
f2MPU
TxRQa
t.. . . :1
DRaT
\.
\
DGRNT
(CPG DGRNT)
TxSTB
TxAKA
TxAKB
Bia
CHa
;;>
><
CS(input)
<
Ao--A I 5. R/W
(output)
>-
Au-A., R/W
(input)
IRQ/OEND
'
.--_.
__ ._------.
---
\
The contents of ADR & BCR of
Channel #3 are transfered
to Channel Q.
540
MPU
-'-
f---First BIOCk---j
rsecond BIOCk--l
r T h i r d Block-
TxAK
DEND Flag
BUSY Flag
Channel #3
~g~)
Write Signal
Read Signal
of CHCR of the
Specified Channel
DMAC PROGRAMMING
request, set the appropriate enable bit (bits 0-3) of the Priority
Control Register, as well as the Rotate Control bit.
If an interrupt on DMA End is desired, the enable bit (bits
0-3) of the Interrupt Control Register must be set.
If data chaining for the channel is necessary, it is programmed into the Data Chain Register and the appropriate
data must be written into the Address and Byte Count Registers
for channel #3.
Address
(Hex)
Register Content
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 2
TSC/
Halt
Burst!
Steal
Read/Write
(R/W)
TxRQ
Enable #2
(TxEN21
TxRO
Enable #1
(TxEN1)
TxRQ
Enable #0
(TxENO)
IRQ
Enable #3
(tE3)
IRQ
Enable #2
(tE2)
IRO
Enable #1
(tEl)
IRO
Enable #0
(tEO)
Two/Four
Channel
Select (2/4)
Data Chain
Channel
Select B
Data Chain
Cbannel
Select A
Data Chain
Enable
Channel
Control
1x*
DMA End
Flag
(DEND)
Busy/Ready
Flag
Not Used
Not Used
Address
Up/Down
Priority
Control
14
Rotate
Control
Not Used
Not Used
Not Used
TxRQ
Enable #3
(TxEN3)
Interrupt
Control
15
IRQ
Flag
Not Used
Not Used
Not Used
Data Chain
16
Not Used
Not Used
Not Used
Not Used
541
HD6844, HD68A44, H D 6 8 B 4 4 - - - - - - - - - - - - - - - - - - - - - Table 9 Maximum Transfer Speed & Response Time of the DMAC when tCyc<,/> equals 1 p.sec.
Maximum Transfer
Speed (p.sec/byte)
Mode
first byte
since seoond
byte
3.5 + tTQS1
+3.5 - tTQH1
2 - tTQH2
-------1 + tTQS2
3.5 - tTQH1
2.5 + tTQH1
1---------------------
minimum
maximum
(executing time
of one instruction)
(executing time of
one instruction) + 3
++
1-
Regist.,
Address High
I_
Address Low
i
Byte Count High
Byte
Count
Low
---.-.--------Address High
Address Low
Byte Count High
Byte Count Low
CS/TxAK
DGRNT
DENDo
IRQ/DEND
DENDI
Channel
a -
0
0
I A,'I1::i'
a
1
2
3
-----------4
5
1
1
6
7
Address High
Address Low
Byte Count High
Byte Count Low
2
2
2
2
8
9
A
B
Address High
Address Low
Byte Count High
Byte Count Low
3
3
3
3
IRQ (Open
-t----------
C
D
E
F
Collector)
TxSTB
TxAKA
DGRNT
CS
IRQ/DEND
TxSTB
TxAKA~-----4-~
P--;~~----+---~----~TxAK
/Q~----+----r----~TxAK
ICS/TxAKBt
(Open
Collector!
P--;~~--------~----+--TxAK
;;;0----------------<1>- TxAK
CS
Figure 37 Four-Channel
542
Address Bu5
( 16)
Deta Bus
(8 ) " 2
ITII
Ao-A,s
-'\
00-0,
--I
HD6800
(MPU)
r--
) +5V
CS, Ao-A.
---
IRQ
,--
00-0, HM6810
--
3.3kQ
IVW
;2
'!.MAIRQ
R/W(RAM)
HM68 10
(RAM)
<PI
VMA
BA
;:=L>-
f--
HALT
2MPU
lMPU
I---
2TTL
H026501
t--
(CPG)
~..,..,
ORQH
DGRNT
--
IRQ
Decoder
Ao-A.
--
As-A"
11
=D-
-->,.
00-0,
R/W
es
HD6843
(FDC)
E
00-0,
--I
8
H06844
(DMAC)
RES
TxSTB
~~
I--
TxAK
TxRQo
I--
TxRQ
R/W
I--
Vee
(f==
Vss
Decoder
.-
CS/TxAKB
I - -l -
I--
;2DMA
I---
Figure 38
II
543
DB
H06800
(M PU)
Ao-Als
00-07
lAI'r-
R/W
.---
VMA
IRQ
,...... '
BA
TSC
AB
HALT
liMA
R/W
;MEM
I fliQ
DB
~
~~
I--
~~
AB
"
;MEM
HM6810
READY
REFRESH REQ
REF GRNT
on
;,
'--
lMPU
MEM
'--
tPzMPU
MRDY
.. f - - m~
;,
on
mf-- on
~
OJ
c(
0
..
RRQ
HD26501
(CPG)
f--
RGRNT
OGRNT
---
""
~H>
I--f-
DRQ
f--
c(
-DRQH
TT
--.-
DRQT
As-A"
HD6844
(DMAC)
TxSTB
TxAKA
----
RES
K>o
f--
K>oU
f--
:fl-
R/W
kDMA
DEVICE
DB
CONTROLLER
TxRQ
~
f-
Deco~er
CS
TxRQJ-TxRQ3
1/0
CS
k=
#0-3
CS/TxAKB
TxAK
-
HD74155
DMAENO
R/W
IIcc
Vss
I~
00-07
iRQ/DENO
c=J
Ao-A.
L-
V ~~
OGRNT
LJ
P
f--
f--
f--
Open Collector
544
HD6843
(FCC)
etc.
#2
(1) ADRO
16 bit x 4
16 bit x 4
(1 CHCR on each channel) (6 bit x 4)
"1"
"0"
Transfer
Direction
Read
Write
Transfer
Mode
Burst
TSC
Cycle steal
HALT
Address
up/down
-1
+1
B/R
Busy
Ready
DEND
Control bit
J Status fl ag
(5bitxl)
0
"1"
"0"
#0
TxRQ #1
Enable #2
Enable/
Mask
#3
Specify Rotate
Rotate / Fixed
(5 bit x 1)
"1"
"0"
#0
IRQ
#1
Enable #2
Enable / Mask
#3
IRQ Flag
(4 bit xl)
~4/21
[:=E
~_]
"1"
Specify
Data Chain
Specify Data
Chain Channel
Specify
4/2-Channel
mode
"0"
o
o
0
1
1 0
#3
#3
#3
#0
..... #1
..... #2
545
HD6845S,HD68A45S,
HD68B45S
CRTC
(CRT Controller)
FEATURES
Number of Displayed Characters on the Screen, Vertical
Dot Format of One Character, Horizontal and Vertical
Sync Signal, Display Timing Signal are Programmable
3.7 MHz High Speed Display Operation
Line Buffer-less Refreshing
14-bit Refresh Memory Address Output (16k Words
max. Access)
Programmable Interlace/Non-interlace Scan Mode
Builtin Cursor Control Function
Programmable Cursor Height and its Blink
Built-in Light Pen Detection Function
Paging and Scrolling Capability
TTL Compatible
Single +5V Power Supply
Compatible with MC6845tr1, MC68A45tr1, MC68B45tr1
(DP-40)
PIN ARRANGEMENT
VSYNC
HSYNC
_____
______
RA.
RA,
MA.
MAl
MA,
MA,
RA,
RA,
RA.
0.
0,
~':,:8U'
0,
0,
0.
0,
0,
0,
cs
RS
E
R/W
ClK
(Top View)
ORDERING INFORMATION
LPST8
CRTC
HD6845S
HD68A45S
HD68845S
546
Bus Timing
CRT Display
Timing
1.0 MHz
1.5 MHz
2.0 MHz
Symbol
Value
Unit
-0.3- +7.0
Input Voltage
Vee *
Vin *
-0.3 - +7.0
Operating Temperature
Topr
- 20- + 75
V
c
Supply Voltage
Storage Temperature
c
Tstg
- 55- +150
With respect to Vss (SYSTEM GND)
[NOTE] Permanent LSI damage may occur if maximum ratings are exceeded. Normal operation should be under recommended operating
conditions. If these conditions are exceeded, it could affect reliability of LSI .
Symbol
min
typ
max
Vee *
V 1L *
4.75
5.0
5.25
-0.3
0.8
Vee
75
V
c
V 1H *
Topr
Operating Temperature
2.0
- 20
25
Unit
ELECTRICAL CHARACTERISTICS
DC CHARACTERISTICS (Vee
Item
Test Condition
typ*
max
Unit
Vee
0.8
-2.5
2.5
p.A
-10
10
p.A
2.4
0.4
V
pF
pF
min
V 1H
2.0
V 1L
-0.3
I in
ITS1
V OH
VOL
Input Capacitance
Cln
Output Capacitance
Cout
Power Dissipation
Po
547
12.5
10.0
10.0
pF
600
1000
mW
typ
teyee
270
ns
130
ns
PWCH
PWCL
ns
t cr , tCf
20
ns
tMAD
160
ns
tRAD
160
ns
250
ns
ns
Item
Symbol
--------_._----
Test Condition
130
Fig. 1
r-_-!Q.liL_
max
Unit
~CDD
250
t HSO
200
ns
250
ns
tvso
PW LPH
60
ns
t LPDl
70
ns
t LP02
ns
Fig. 2
Symbol
Test
Condition
ttycE
HD6845S
HD68A45S
HD68B45S
min
typ
max
min
typ
max
min
-. 1.0
-0.45
--
0.666
0.22
0.40
0.280
25
0.280
0.5
25
140
70
220
10
10
10
360
PW EL
tEr, tEt
t AS
140
tOOR
320
tH
10
tAH
10
tACC
460
max
min
typ
max
min
0.666
0.2BO
0.22
25
Fig. 3
-_.
--
0.21
10
typ
max
Unit
#AS
/JS
25
/JS
ns
ns
180
ns
ns
250
ns
ns
Symbol
Test
Condition
tcyc,e
PW EH
0.45
PW EL
0.40
tEr, tEt I
t AS
tosw
1.0
Fig.4
HD6BA45S
HD6845S
min
140
195
tH
10
tAH
10
typ
548
0.2BO
25
140
10
10
BO
HD6BB45S
0.5
0.21
70
60
10
10
typ
max
Unit
#AS
#AS
#AS
ns
25
ns
ns
ns
ns
~ -------I
PW eL
2.0V
O.8V
ClK
I
ter
2.4V
MAo -MAil
-------------4--.../
2.4V
RAo-RA. _________________
~---J
2.4V
DISPTMG __________________
~-----'
2.4V
CUDISP
teDD
teDD
2.4V
HSYNC
VSYNC
LPSTB _________
549
elK
M +2
\~-
lPSTB - - - - - - - H
_________~~--------JI'--~------------------~I~<--------------L
2.0V
lPSTB
Figure 2 LPSTB Input Timing & Refresh Memory Address that is set into the light pen register.
~-----------t~E
2.0V
E ----------+-----'1
cs-----
R/W, R S - - - - - '
Do-D7-________________________
550
--------<..,
2.OV
------+---..1
tosw
cs---~
2.0V
R/W
RS (Address
Register)
RS _ _ _ _..1
O.8V
(Control Register)
S.OV
D,
Test Point
()--~~--<.--~.......-
..
130pF (Do -D 7 )
30pF (Output signals except Do - D 7)
l1kn (Do -D 7 )
R
24kn (Output signals except Do -D 7 )
D, -D4 are lS207~or equivalent.
SYSTEM DESCRIPTION
551
.Ol
II
Horizontal Displayed
Register
ClK
Horizontal Total
Register
Horizontal Sync
Position Register
HSYNC
Sync
Width Register
Maximum Raster
Address Register
Vertical Displayed
Register
Vertical Total
Register
Start Address
Register
Cursor Start
Raster Register
CUDISP
Cursor End
Raster Register
Cursor Register
RAO-\c--..-J~
RA.
VSYNC
2,2'
~____~
___ oj
Figure 6 Internal Block Diagram of the CRTC
552
En~ble(E)
553
REGISTER DESCRIPTION
CS
Register
Register Name
Program Unit
READ
WRITE
Character
Horizontal Displayed
Character
Horizontal Sync*
Position
Character
AR
Address Register
RO
Horizontal Total *
R1
R2
R3
Sync Width
Vertical-Raster,
HorizontalCharacter
R4
Vertical Total *
Line
R5
Raster
R6
Vertical Displayed
Line
R7
Vertical Sync *
Position
Line
RS
R9
Maximum Raster
Address
Raster
R10
Raster
R11
Raster
R12
Start Address( H)
R13
Start Address( L)
R14
Cursor(H)
R15
Cursor (L)
R16
Light Pent H)
R17
Light Pent L)
[NOTE]
554
wv3
wv2
wv1
wvO
wh3
wh2
wh1
whO
2'
26
25
24
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
Pulse Width
16H
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
H; Raster period
23
22
21
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
1
1
1
0
0
0
0
1
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
555
Pulse Width
- (Note)
1 CH
2
3
4
5
6
8
9
10
11
12
13
14
15
Non-interlace Mode
Total Number of Rasters 5
1-----Programmed Value Nr = 4
2-----The same as displayed )
(
total number of rasters
3-----
} Non-interlace Mode
Interlace Sync Mode
Interlace Sync & Video Mode
4-----
Raster Address
In the non-interlace mode, the rasters of even number
field and odd number field are scanned duplicatedly. In the
interlace sync mode, the rasters of odd number field are
scanned in the middle of even number field. Then it is
controlled to display the same character pattern in two
fields. In the interlace sync and video mode, the raster scan
method is the same as the interlace sync mode, but it is
controlled to display different character pattern in two field.
o------
----------------------
Raster Address
5
01
DO
o
o
DISPTMG Signal
Non-skew
One-character skew
Programnled Value Nr = 3
(Total number of rasters )
displayed in the even field
and the odd field.
Two-character skew
Table 7 Cursor Display Mode (2 6 , 2 S )
Non-output
B
o
0
--------
CO
0
0
Non-blink
Non-skew
Non-skew
One-character skew
Two-character skew
Blink Period
light
~~-----------~~---
Non-output
16 or 32 Field Period
556
dark
6) 2 ~Nr ~30
7) 3 ~ Nht (Except non-interlace mode)
5 ~ Nht (Non-interlace mode only)
>
"0
-0
er
Q>
Q>
.s::.
(,)
a:
co
t-
"0
<{
~A~ ~B~ ~C
'0
>
<0
Ci
~
'f ~
Q>
>~
(J
'0
'f
Q>
.0
'0
>
Horizontal
Retrace
Period
Q>
co
Display Period
Q>
E~
::I
} Line
<0
.s::.
(J
]
E
::I
557
Register Name
Value
Register
RO
Rl
Horizontal Total
Horizontal Displayed
Nht
R9
Rl0
I
I
Nhd
Nhsp
Nvsw, Nhsw
R2
R3
Sync Width
R4
Vertical Total
Nvt
R5
R6
Vertical Displayed
Nadj
Nvd
R7
Nvsp
R8
[NOTE]
Register Name
Nr
Rl1
R12
Value
R13
R14
Cursor (H)
R15
Cursor (l)
R16
R17
Nhd<Nht, Nvd<Nvt
I nterlace Control
Fig. 8 shows an example where the same character is
displayed in the non-interlace mode, interlace sync mode, and
video mode.
Non-interlace Mode Display
0 ____. _______________
e
e
2 e
Q
- ~ - - - - - - - - - - - 0- - 2
3 G
Q
--e-----------i)---3
9
e e
9
e
e
4
5
9
e e 9 e
--~--1
- -&--- - - - - - --- 4 - -
5 GeeeQeo
6 - -:-0 -e-o-~-.
t-- 5
--G- - -- -- - -----0--6
7 ~__ -n-----!---7
8
e
~
9
- -& - - - - - - - - - - -0 -G
0
A ---0----------4--9
-----------------A
8----------------- - - - - - - - - - - - - - -- 8
8
Non-interlace Mode
~~l~~~~~----~~=~i-~~ l
C
"'--0-&-0-0-0-8-&---5 jline #0
II
-----4--
--0-- - ---.- -
--
6 e
--1)--8 e
----
------<>---7
_::g __
--
--
--
']
3
5
line #0
A--&----- -------0---9
A --0-- ---------9-- 9
~ ~~~~
:~f~~:~--~~:T ~ 1
- - - - - - - - - ~--~ ~ 1
(l~~~~---~~~--~~r~~~
6 e
e
8- -:- - - - - - - - - - -
line #1
t-- 7
5~G-e--e-e-~-- 4
- -0 - - - - - - - - - -Q-- - 6
7 e
Q
--e-----------&--- 8
9 0
9
line #,
- - - - - - - - - - - - - - - -- A
A- -0- -- - - - - - - -1)--9
558
~
Number of
Rasters in a Line
Odd
Even
Even Line
Odd Line
Even Field
Odd Field
Even Address
Odd Address
Even Address
Odd Address
Odd Address
Even Address
0-+-+-+-+-+-+-+-
o-+~-+~~-+-+-
1-+-+-+-+-+-+-+-
1-+-+-+-+-+~~-
2-+~-+-+~~-+-
2-+~~~~~-+-
3-+~~~~~~-
3~~~~~~-+-
4-+-+-+-+-+-+-+-
4-+-+~-+-+-+~-
5-+~~~~~~-
5~~-+~~~-+-
6-+~~~~~~-
6~-~~~~~-+-
7-+~~~~~~-
7~~~~~~-+-
8-+-+~~~-+-+-
8~-+~-+~-+-+-
9-e~~~~~~~
9-e~~~~~~r
10-+-+~~~-+~-
10-&~HIl~~~~~
O-+-+-+-+-+-+~1-e~~~~~~~
2-e~~~~~~~
3-&~~Hm~~~~
4-&~~~HmHm~~
5 -&HB~~Hm~HIl~
6-+-+-+-+-+-+-+-
Cursor Control
559
J:
C
_________ stn__
CD
CO
ClK
Nhsp
Nht
Nhsp+l
DISPTMG
I_
I.
NhspTc
HSYNC
Nhsw'TC~1
_ _ _ _ _ _ _ _ _ _ _--J
MAo-MA~~
---- -------
--~-x:::r::.Nhdl
Nhd
RA o --RA 4
=----
Raster Period Tr
I 0
_ _ _ _
NI'od
RAo-RA~
01
0>
I'I!ht
.
.
~i
~
~
(I)
--------~--------_._-----....
J:
C
I.
___
CD
CO
OJ
~
Nhl
_ _ _ _
_ _ _
Tr-----,
(I)
Nhd+l
V
_ ___ .-A
. . . . .
'I'
01
-::J2J..'x:n:rr. --------- ~
0!1L -----v.v.~~"
('"'"
..:...~ :::~:::
~Nr===t--~~~::::..:
Nhd
.... -"=A..
\
line
~-----------------LinePeriOdTL---------------------___
Fr===
line
--I
Vert;caID;splayPer;odNvd,T L
I Nvd I
Vertlc~t D~Plaved Characters
Nvsp
,_
\..
_ .l~:tlcal
Nvt
I I
SeeFig.11
__________________________
I---TVSW
~n
'r- ~~~~~~~:a~te:r~cal
nnn---
NIV'-nn.'-1lIIIl--.JUUL
Retrace Period
~------------------N~p'TL--------------------_1
VSYNC
~~;:tlr;~ Sync
"
~-, , @ / ' - , @
--nnn--nnn--nnn.-----------------------------.,
.JUUL.JUU.....
_. _ ____ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
!--Tadj
1 -I
FramePenodT FAM
Number of
DISPTMG
G)
01
----------------~
J:
C
CO
1-
MAo --MA 1 !
Nh\
ClK
Raster Period
Tr" (Nht+1}'T C
01
fn
II~r.JLJL.
'.
II
See Fig. 12
LineNumber~------------~N~w~-~2------------~------------~N~~~-~1------------~--__~N~w~_____________________________
DISPTMG
---:::~
-.::-..:.n.nL-__________
Figure 11 Switching from Vertical Display Period over to Vertical Retrace Period (Expansion of Fig. 10-
LineNumbert::::::::::!N~~~::::::::::::::::~~~~~~~~~~~~::::::::::::::]O~::::::::::::~::::::::c:::::
DISPTMG
f--------------------------------------I
Figure 12 Fine Adjustment Period of Frame in Vertical Display
(Expansion of Fig. 10- <ij) )
561
HD6845S, HD68A46S, H D 6 8 B 4 5 S - - - - - - - - - - - -
562
-RAo-RA,
line *0
I- - - - - - - 1
Nr
"I
1
Line #2
Une P"1
2131-------1
"I
Nr
1 - - - - - - -I
Nr
"I1
/---- - - ---""',,
: n n n
CUOISP
" --------
)
.;'
Nhd + 1
MAo-MAl
Nhd
Nhd + 2
Nhd + 1
Nhd + Nht
- - - - - - -I
1 Nhd 1
Nhd t 2
I
-----
Nhd + 1
Nhd + Nht
I
I
__
Nhd t 2
I
Nhd
Nhd t 1
Nhd + Nht
-------1
\
Nhd
Nhd + Nht
Nhd + 2
1 '1-------1
I
01
RAo-RA.
0')
(,.)
CUOISP
r-
r--[NOTE]
Cursor register ~ Nhd+2
Cursor Start
Raster Register = 1
Cursor End
Raster Register = 3
J:
C
0)
Q)
~
CJI
fn
J:
C
Q)
Q)
en
fn
J:
0)
Q)
aJ
~
CJI
fn
Cb
CD
...
en
Raster address - - - ,
Line"Umber~
- 0
+
0
,N,
+r
N=f
[J TNhd
0.
Nhdl
Nhd
2Nhr
2f
2Nhd
Nhdtl
2Nhdl
2Nhd
2NhO+l
JNhdl
N'
2Nhd
2Nhd+l
3Nhd'
...en
~
Nhl
Nhd
Nhr
Cb
CD
Nhdl
I
! I
~
%
-_
Nhl
tI)
NhThl
3T
3Nhd
Nhd+Nht
2Nhd+Nhl
CD
GI
...
2Nhd+Nht
en
(I)
r
r
o
0'1
0>
~
,N,
o
tNvd-lI'Nhd
Nvd' Nhd
,N, ~~
N'" [0
tNvdll N~~
Nvd
Nvd' Nhd'
N vd ' Nhd-t
Nhd+l
fNhd+l}Nhd
tNhd-llNhd
-1
Nvd Nhd
tNhd+1)Nhd
INhd"l)Nhd
Nyt 'Nhd+l
lNh.
INvd-I"
Nhd
N vd ' N hd
Nvd . Nhd+Nht
Nhd . Nhd+Nhl
I
I
I
N,
I
Nald'
N:~
N",' Nhd
Nvl 'lhd+l
(NvttlINhdl
NYl'Nhd
NV1'Nhd+l
(NV1+1}Nhdl
Nhd
{NVI+lINhd
+1
INvttl.,Nhd
{NVI+1)'Nhd
+1
tNVltr
IN . )
Nh~
(Nvt+l)Nhd
(Nvl+l}Nhd
Nvt . Nhd+Nht
N vt ' Nhd+Nht
INvl+2) Nhd
INvl+2) . Nhd
IN~!1I:::1
~)
--~--------------------------------HD6845S,
Interface to MPU
As shown in Fig. 17, the CRTC is connected with the standard bus of MPU to control the data transfer between them. The
CRTC address is determined by CS and RS, and the R/Woperation is controlled by R/Wand Enable signals. When CS is "Low"
and RS is also "Low", the CRTC address register is selected.
When CS is "Low" and RS is "High", one of 18 internal regis
HD68A45S, HD68845S
ters is selected.
RES is the system reset signal. When RES becomes "Low",
the CRTC internal control logic is reset. But internal registers
shown in Table 1 (RO~ R17) are not affected by RES signal and
remain unchanged.
The CRTC is designed so as to provide an interface to microcomputers, but adding some external circuits enables an interface to other data sources.
AB o-AB 7
RS
VMA
CS
R/Vil
R/ViI
HD6800
CRTC
MPU
DB o-DB 7
Do-D7
RES
RES
L -_ _ _ _ _ _ _ _
to PIS SHIFT
}
565
REGISTER
DOTCP-P
Q 2 ' - - -....
......-+--------'
CHCP-P (ClK)
I-----One Horizont81---~
Character Time
566
14 max
Refresh
Memory
MA
5 max
RA
Character
Generator
-v
CRTC
DISPTMG
~
CLK
CUDISP
......
HSYNC
.....
Video
Signals
Video Control
VSYNC
Sync
Signals
D
0
I
Figure 20 Interface to Display Control Unit
F1
CUDISP
CHCP-N
DISPTMG
VIDEO
CRTC
MA
Refresh
Memory
CG
~====:=.:1.j.
S
RA
CLK
CHCP-P
troubles about delay time of MA during horizontal onecharacter time on high-speed display operation, system shown in
Fig. 23 is adopted. The time chart in this case is shown in Fig.26.
Character video signal is delayed for two-character time because
each MA outputs and refresh memory outputs are latched, and
they are made to be in phase with CUDISP and DISPTMG
signals by delaying for two-character time. Table 10 shows the
circuitry selection standard of display units.
Case
tCH
Block
Diagram
Cl
CO
01
DO
0
1
0
0
Fig. 22
0
0
Fig. 23
Fig. 21
> RM Access
F2
OISPTMG
CRTC
Refresh
MA
CG
5
RA
ClK
CHCP-P
L-_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ I
~_~CU~D~IS~P-------------------__4D Q~----------~
CHCP-N-_..........!T
F2
OISPTMG
CRTC
MA
P
I===~ ~
Refresh
Memory
RA
ClK
L-_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _~C~H~C~P~-P~OOT COUNTER~-~--~
568
OSC
CHCPP
MA
DISPTMG
--I--~
CUDISP
____
~----~--~~----------~-----J
F2Q
F1Q
RMOU1
CGOUT
__
_I---~~~~~-J'~~~_I---,~~~~--~~~~~---,,~~~~--J
__~---J~~~'~--~'~~~'~--~'~~.u~__~'~~.u'~---J
VIDEO
\
CRT Display
Figure
(1)
CHCPP
MA
CUDISP
F2Q
FlQ
lATCH
(11
--Jr~--------~~------~~------JI~-------~---------~I'~--
CGOUT ____
~~
____
,~
__
~J~
____
_J'~~_J~
____
,~
____
J~
_____
,~~_J~
VIDEO
CRT Display
569
__
_J~
__
~/~
CHCPP
MA
DISPTMG
-----~
CUDISP
LATCH(2)
-+______
~'~
o
______
J~------~'I-------JI\--------'I--------I\--------
F2Q
FlQ
RMOUT
LATCH(1)
CGOUT
VIDEO
CRT Display
fh
tc (Nht + 1)
where,
............. (a)
570
I'
-I
I
I
LI--- ~~O~!:~ --+ ~=ontal-+-~~~~~O;!::Od ---..t
_________
lH
OISPTMG - - '
HSYNC.n-_ _ _ _ _ _ _~n~
I'
r-~~~~~a~eriod
I I H I
~:~~al--+OI'J---~~~~~~eriod~
~I_ _ _---.Ii-I___I---JJ~
DISPTMG--.J
I.
.1
1 Frame
,HO';'O.'" C""""'en
Don Number of
Character Fo nt
'"
aracter
Soace
'
Dot Number of
Vertical Characters
(Number of Rasters)
Une
Space
571
10
13
"0""0"
"0"
I I
I
I
Seria I Data
Shift Register
1[,I
Number of Horizontal Displayed Characters
tc
~
Horizontal Character Time
572
2'
Scan Mode
Main Usage
Normal Display of Characters
Non-interlace
& Figures
Fine Display of Characters
Interlace Sync
& Figures
Display of Many Characters
Interlace Sync
& Video
[NOTE]
High-resolution CRT
...
MPU
...
D7-D~
MA
r---
osc
H~'
-~~
CLK
,
BUS DRIVER
MULTIPLEXER
!l
REFRESH
MEMORY
(RAM)
CRTC
RA
~
CHARACTER
GENERATOR
lL
DISPTMG
CUDISP
HSYNC
VIDEO
CONTROL
VSYNC
573
VIDEO
SYNC
SIGNAL
0
0
HD6845S, HD68A45S, HD68B45S--------------------------------------bus, while refresh memory is read out successively by the CRTC
to display a static pattern on the screen. Refresh memory is
accessed by both MPU and the CRTC, so it needs to change its
address selectively by multiplexer. The CRTC has 14 MA
(Memory Address output), but in fact some of them that are
needed are used according to capacity of refresh memory.
Code output of refresh memory is provided to character
generator. Character generator generates a dot pattern of a
specified raster of a specified character in parallel according to
code output from refresh memory and RA (Raster Address
output) from the CRTC. Parallel-serial converter is normally
composed of shift register to convert output of character
generator into a serial dot pattern. Moreover, DISPTMG,
A1s-A o
MPU
II
II
0 7 -0 0
MA
r-OSC
II
Jl
DOT
ClK
I - - - COUN- I - - TER
---
MULTIPLEXER
BUS DRIVER
.Jl
REFRESH
MEMORY
(RAM)
Blr
k
B bit Da ta (1 word)
Color
~
1[
CRTC
RA
....
'\
IRIG BI
High order
I
Low
CHARACTER
GENERATOR
~~
P-S
DISPTMG
CUDISP
HSSNC
R. VIDEO
G. VIDEO
VIDEO CONTROL
B. VIDEO
SIGNAL
0
0
VSYNC
t
SYNC SIGNAL
574
. A,s-A o
MPU
D,-D o
MA
).
DOT
COUNTER
~~
Ii
BUS
DRIVER
MULTIPLEXER
ClK
,.
REFRESH
MEMORY
(RAM)
OSC
RA
CRTC
IF
1~
"\
RA GRAPHIC
ICHARACTER
PATTERN
IGENERATOR ~ GENERATOR
JI
~
P
DISPTMG
R. VIDEO
CUDISP
G. VIDEO
HSYNC
VIDEO CONTROL
B. VIDEO
0
0
VSYNC
SYNC SIGNAL
575
refresh memory is dot memory that stores all the dot patterns,
so its output is directly provided to parallel-serial converter to
be displayed. Dot memory address to refresh the screen is set
up by combination of MA output and RA output of CRTC.
MPU
,
OSC
DOT
COUNTER
7
MA
BUS DRIVER
RA
~~.
MUL TIPLEXER
~
DOT MEMORY
(RAM)
CRTC
11
P
1
DISPTMG
HSYNC
VIDEO
(VIDEO
SYNC
CONTROL
SIGNAL
VSYNC
576
CJ
0
RA2
RA,
RAo
MAo
MAs
MA7
MA.
MAs
CRTC
E~jw 1
Refresh Memory
Address
IJIOIIII
8 rasters
(1 line)
24 lines
x 8 rasters
= 192 rasters
1 b ye
t (8 "b"It )
32
64
96
1
33
65
97
31
63
95
127
224
225
255
:
,,
,
I
:
,
,
,
,,
:
,
,,
:
:
:
6112
6113
6148
Value of ma
Figure 37 Memory Address and Dot Display Position on the Screen for Full Graphic Display
577
Fig. 38 shows a system of color full graphic display by 7color display. Refresh memory is composed of three dot
memories which are respectively used for red, green, and blue.
These dot memories are read out in parallel at one time and
MPU
"
l>
BUS
DRIVER
I~US
DRIVER
i...--
OSC
FH
MA
DOT
COUN
TER
l>-
RA
II
I,.
~S~
DRIVE
--:; r-
MULTIPLEXER
B
G
R
DOT
MEMORY (RAM)
CRTC
I-
Ib:
.~
7
P
DJ
RED VIDEO
DISPTMG
HSYNC
VIDEO
CONTROL
GR$r~EO
BLUE
VIDEO
SIGNAL
0
0
VSYNC
f
SYNC SIGNAL
578
A,s-A o
MPU
0,-0.11
11
il
MA
~1
II
MUL TIPLEXER
DOT
COUNTER
II
11
II
#2
#n
L..S..
.......
CHARACTER
GENERATOR
a:
LL
CHARACTER
GENERATOR
~~
VIDEO
CONTROL
CUDISP
HSYNC
VIDEO
CONTROL
VSYNC
I----
---
DISPTMG
I----
I-- :::>
co I----
- - - ---
JJ
p -
r--
IT
IT
~~
CJ1
w I---f---- LL
11
#1
IT
co
- - --
REFRESH
MEMORY
:::>
I--
.tr
IBUS
DRIVER:1
REFRESH
MEMORY
a:
~ ~ ~ CHARACTER
r---v LL ~ GENERATOR
I--
IBUSI
DRIVER
REFRESH
MEMORY
CRTC
BUS
DRIVER
-----._-----
(YJ
#1
J:
VIDEO
CONTROL
----
I
OEJ
#2
0
--
en
.,.
CD
UI
U)
I...-
J:
C
0)
(IJ
#n
CD
~
.,.
UI
U)
0
-
J:
en
CD
.,.
UI
U)
Specification
Character Format
5 x 7 Dot
Character Space
1 p.s
Refresh Memory
1 kB
Address Map
28
27
26
2s
24
Refresh
Memory
CRTC
Address
Register
CRTC
Control
Register
2 3 22
21
20
HVSYNC Method
Table 13 Specification of Character Display
Item
Specif ication
Scan Mode
Non-interlace
15.625 kHz
60.1 Hz
Dot Frequency
8 MHz
8 x 12 (Character Font 5 x 9)
40x 16
HSYNCWidth
4 p.s
VSYNCWidth
3H
Cursor Display
Paging, Scrolling
Not used
580
Name
Initializing Value
Hex (Decimal)
Symbol
RD
Horizontal Total
Nht
3F
Rl
Horizontal Displayed
Nhd
28
(40)
R2
Nhsp
34
(52)
R3
Sync Width
R4
Vertical Total
-----------~---+L-~-_-N-V-S~-',-V~~h=-------_ ~:
(20)
R5
(63)
R6
Vertical Displayed
R7
RS
R9
R1D
B, P, NCSTART
Rll
NCEND
R12
R13
:::114
Cursor (H)
00
( 0)
R15
Cursor (L)
00
( 0)
Nr
OB
OA
(10)
00
( 0)
00
-.~--
Cursor
581
(11)
49
( 0)
~--.---~----
l:
C
RE-S
II
i
i I
HD74LS 10
HD74LSli
II
I
II
I CRTC
'/i;!TTL
SEL-N
R;W
pn tl r
~
G)
CD
~
Db Os 0
OJ 0
01 [)
GI
en
l:
C
II~t~b6
D.
G)
CD
~
DISPREGSEL
-N
HD~-'
IIf'~:
I I I I
I I I
GI
en
l:
C
Cb
~====~~~~~ilU
H074LSOO
CD
m
~
GI
D.
0;
lY
01
<
. :-- -.
DISPREAD-N
I :
I II
~'~i~lllk.1
=P
I :
Serial Data
VIOEO-P
I ,HSYNC
VSVNC
H07486
D r - - - - - - - HVSYNC-P
R, :51n
cj
en
Differences between the HD6845R (Motorola MC6845 Compatible) and the HD6845S (Enhanced)
No.
Video Mode
Display
Programming
Method
of
number of
vertical
characters
HD6845R
HD6845S
,---------------
Programming
unit for
number of
vertical
characters
2--------------3--------------4---------------
Number of
raster per
character
line
ABC
2 _ _ _ _ _ _ _ _ _ ___
,-----------3 _ _ _ _ _ _ _ _ _ _ ___
4 _______________
} Programming
unit for
number of
vertical
characters
5 ____________________
6 ___________________
7 _____________________
8 _______________
9 ________________
; =i=~==~==~=i=; } \
6
--0-----------0--5
a
a
--0-----------0--7
~ =:;:=~~=:;===~}
a
a
2
4
--0-----------0--3
a
a
--0-----------0--5
Character
line address
o --0-----------0-Number of raster
Ch~i~~~~dress
--o--e--e--O-----7
8 --'--'--'--'----------------9
Number of raster = 10 scanline (specified)
However. number which is programmed into
register is calculated as follows.
Programmed number (Nr)
= (Number specified) - 1
JI ~ =t=========I= ; }
-.8.--h---ht- 3 t
4
6
-.8.-~--~h~-!- 5
a
a
--0-----------0-- 7
Character!
line address
~ ~I:~~:~~i: ~I,
: =~=~~=~==== J
aaaa
=t=========1= ~
~ =~=~==~=~=:;:=
_.8._hh_h_!_ ~ }
3
5
a
a
a a a a
--------------- 8
--0-----------0-- 6
Number of raster
= 10 scan line
(specified)
Number of raster
= 9 scan line
(specified)
= (Number specified) - 2
Cursor
Display
0------
0-------------------- 1
5
7~ EVEN number
__
EVEN nu.mber
EVEN number'
--------------- 7
4 _~__ ~__~h~_~
6 _~__ ~__~h~_~
__
=l=l:i=:i=i= ~
: -f-fi-i-f:- ~
2
8-----0-------------------- 1
o ____ .! __________
2 _
4 --o--e--e--o---o-- 5
6------ 7
8--------------------
6-------------------- 7
0-----2
=1=1:;;;=i= :...
8------4
B ~-------------- 7
583
ODD number
No.
Vertical Sync
PulaeWldth
HDl845R
Functlon.1 DHference
(16H)
r-Fixed at 16
scan cycle
(VSYNC output)
HDl845S
-.J
VS~
R3
Not used
3
SKEW Function
--.t
I--+-Specified
by
high order
4 bits of R3
V~
I I I I
I I
R3
I I I I
IWV31WV21WV11WvOi
~~
Not included
R8
R8
I I I I I I I I
V
I I
V / S /
CUDISP DISPTMG
Not used
Write Only
Read or Write
-----Synchronous reset
Other Outputs
Output signals of MAo - MA,3. RAo - RA
synchronized with ClK "lOW' level. go to
"lOW' level. after RES has gone to "lOW."
Other outputs go to "lOW" immediately after
RES has gone to "lOW" level.
CharacteristiC Difference
Symbol
teyee
min.
330
PWCH
150
PWc..
150
HD6845R
typo
THaD
PWLPH
80
TL~Dl
TCA. TCF
TL~DI
584
max.
min.
HD6845S
typo
270
15
250
60
80
10
130
130
max.
Unit
ns
'20
ns
200
ns
na
ns
ns
70
n8
n8
HD6846
COMBO
The H06846 combination chip provides the means, in conjunction with the H06802, to develop a basic 2-chip microcomputer system. The H06846 consists of 2048 bytes of maskprogrammable ROM, an 8-bit bidirectional data port with controllines, and a 16-bit programmable timer-counter.
This device is capable of interfacing with the H06802 (basic
H06800, clock and 128 bytes of RAM) as well as the H06800
if desired. No external logic is required to interface with most
peripheral devices.
HD6846
FEATURES
2048 8-Bit Bytes of Mask-Programmable ROM
8-Bit Bidirectional Data Port for Parallel Interface plus
Two Control Lines
(DC-40)
TYPICAL MICROCOMPUTER
Vee
Vee
Standby Vee
Vee
Vee
PIN ARRANGEMENT
A.
Counter/Timer 1/0
iRa
Po
P,
Plra"ell/O
MR
RE
BA
REs
{ eTO
eTG
eTe
es o
E
P,
P,
p.
p.
VMA
E
RJW
A,
A,"
HALT
REs
iR6
NMI
H06B02
(CPU)
0- 0 ,
CP,
CP,
XTAL
Do
P,
Control
{c::
EXTAL
Ao ..... A IS
CP1
-+
40 pins
Vss
VSS
This is. block diagram of a typical cost effective microcomputer. The MPU IS
the center of the mICrocomputer system and IS shown in 8 minimum system interfacing with a ROM combination chip. It is not Intended that this system be limited to
this function but that it be expandable with other parts in the HMCS6800 Micro-
Ao
D,
A,
D,
A,
D,
A.,
D,
VCC
Ds
P,
D.
P,
D,
P,
CS,
P,
computer family_
(Top View)
Value
Symbol
-0.3
Input Voltage
Vee *
Vin *
Operating Temperature
Topr
-20
Storage Temperature
TS1g
-55
Supply Voltage
Unit
~+7.0
-0.3~
+7.0
Item
Symbol
min
typ
Vee *
4.75
5.0
5.25
V 1L *
-0.3
0.8
Vee
75
Supply Voltage
+75
V
c
Input Voltage
+150
Operating Temperature
V 1H *
2.0
Topr
-20
25
max Unit
ELECTRICAL CHARACTERISTICS
DC CHARACTERISTICS (Vcc=5.0V5%, VSS=OV, Ta=-2~+75C, unless otherwise noted.)
Symbol
Item
Test Condition
min. typo
max. Unit
All Inputs
V 1H
2.0
All Inputs
V 1L
-0.3
Vee
0.8
Vee
-0.5
Vee
+0.5
Vss
-0.5
Vss
+0.5
Vos
~CPl.CTG,
V
V
lin
-2.5
2.5
fJA
hSI
-10
10
fJA
= -205fJA
=-200fJA
2.4
10 H = -200fJA
2.4
10L = 1.6mA
CTC, E. Ao"'Alo
Three-State (Off State)
I nput Current
0 0"'0 7 , PO "'P 7
CP 2
0 0"'0 7
CP 2 , PO "'P 7
10H
VOH
10H
CTO
Output "Low" Voltage
Output "High" Current
(Sourcing)
0 0"'0 7
Other Outputs
0 0-0 7
VOL
= 2.4V
= 2.4V
205
200
-1.0
10L = 3.2mA
V OH
10H
V OH
CTO. CP 2 PO"'P 7
CP 2 , PO "'P 7
10H
V OH = 1.5V
0 0-0 7
Other Outputs
10L
VOL = O.4y
IRQ
I LoH
Cin
0 0-0 7
Power Oissipation
Capacitance
2.4
0.4
0.4
fJA
fJA
-10 mA
1.6
3.2
mA
VOH = 2.4V
10
fJA
800
mW
20
Cin
Vee = OV
7.5
pF
pF
pF
pF
PO-P 7 CP 2 , CTO
Gout
Ao-A 10 R/W
~n
V in = OV
Ta = 25C
RES,~,CSl'
CP1.CT
~n
f = 1MHz
10
pF
IRQ
Cout
7.5
pF
Po
586
12.5
10
-----------------------------------------------------------HD6846
AC CHARACTERISTICS (VCC=5.0V5%, VSS=OV, Ta=-20~+75C, unless otherwise noted.)
1. BUS TIMING
Item
Symbol
430
PWEL
min
1.0
-- r - - - - - -
-----------
~--
PW EH
430
tAS
140
tooR
tH
--
Test Condition
tcycE
typ
max
10
Unit
J.lS
- - - ~-- 1----------
4500
ns
f-----f------
4500
--1-------
ns
----ns
320
10
tAH
10
tEf,tEr
tosw
195
J.lS
1.6
J.lS
tRL
tlR
Fig. 1
2
Fig. 2
ns
ns
f--------- 1------ns
25
ns
ns
---
CP 2
Symbol
Test Condition
min
tposu
Fig.3
200
ns
tpr, tpf
Fig. 5
1.0
J.lS
1.0
ns
1.0
J.lS
tCP2
-- -----
toc
tRS1
Fig.4
20
typ
max
Unit
f------
J.lS
tRS2
Fig.5
2.0
J.lS
tpow
Fig.4
1.0
J.lS
tpsu
100
ns
tpOH
15
ns
typ
max
Unit
Fig.9
Symbol
tCr. tCf
tpWH
tpwL
tsu
thd
tCTO
Test Condition
min
Fig.6
Fig. 7
Fig. 8
100
ns
::r~cr
ns
::r~6'
ns
200
ns
50
ns
1.0
J.lS
HD8848-------------------------------------------------E
E
CP,
R/W
'AS';
Ao-A ,o
CP 2
CS o CS ,
(Output)
2.4V
COMBO..... MPU
0 0 -0 7 (Write)
------
MPlJ-+COMBO
_1
2 0V
\"---
tIR---~-t.1
L.
------------------
2 4V
.
~.OV
P,-P, -------
~~~:~:~s-u-~-,-------t2.0V
_~OV
.
____
I---tCTO~
-2-.4-V-----
CTO
..,:O:,;;.4;.,v=--_ _ __
PO -P 7
(Output) _ _ _ _- . J
~~_ _
CP 2
CP,
(Output)
588
-----------------------------------------------------------HD6846
fii'Ki)
LOA~B
LOAD A
ID.-D"CTO,
CP"p.-P,)
5.0V
1.5 kl1
Test Point
rP.st Pomt
r~'
GENERAL DESCRIPTION
The HD6846 combination chip may be partitioned into
three functional operating sections: programmed storage, timercounter functions, and a parallel I/O port.
Programmed Storage
The mask-programmable ROM section is similar to other
ROM products of the HMCS6800 family. The ROM is organized
in a 2048 by 8-bit array to provide read only storage for a
minimum microcomputer system. Two mask-programmable
chip selects are available for user definition.
Address inputs Ao ,.... AlO allow any of the 2048 bytes of
ROM to be uniquely addressed. Bidirectional data lines (Do ,....
D 7 ) allow the transfer of data between the MPU and the HD
6846.
p.
P,
P,
P,
p.
P,
0,
0,
0,
0,
D,
D,
0,
0,
p.
P,
CP,
CP,
cs.
CS,
A.
A,
A,
A,
A.
A,
A.
A,
A,
A,
A"
Timer-Counter Functions
Under software control this 16-bit binary counter may be
programmed to count events, measure frequencies, time intervals, or similar tasks. Internal registers associated with the I/O
functions may be selected with A o , Al and A 2 It may also be
used for square wave generation, single pulses of controlled
duration, and gated signals. Interrupts may be generated from a
number of conditions selectable by software programming.
Vee
Vss
CTO
C'ffl
ETC
589
HD8848-----------------------------------------------------------
CP,
CP,
imiBuffo,
Stot! ROIIi"o,
_-----4
P,
P,
P,
P,
p.
P,
Peripheral
0. ..
Reginer
p.
I
.....- P ,
SIGNAL DESCRIPTION
Bus Interface
Reset (RES)
Read/Write (R/W)
590
--------------------------------------------------------------HD6846
loads (3.2 rnA). They are also capable of sourcing up to 1.0 mA
at 1.5 Volts (Logic "1" output.)
When programmed as inputs, the output drivers associated
with these lines enter a three-state (high impedance) mode.
Since there is no internal pull-up for these lines, they represent
a maximum 1OfJA load to the circuitry driving them -regardless of logic state.
A logic zero at the RES input forces the peripheral data lines
to the input configuration by clearing the Data Direction
Register. This allows the system designer to preclude the
possibility of having a peripheral data output connected to an
external driver output during power-up sequence.
Internal Addressing
Input
E
CTC Input
Recog.
Input
Output
.----------4:f--
' - -_ _oJ
1----\ I,-----:111-either
here
or Here
591
1---------1
____ j I
1 System
Bit Time
Jitter
HD6846-------------------------------------------------------CS.
t---_ I/O-TIMEA
SELECT
A2
0
0
0
0
1
1
1
1
x
At
0
Ao
0
1
1
0
1
0
0
0
1
x
ROM Select
The active levels of CS o and CSl for ROM and I/O select are
a user programmable option. Either CS o or CSt may be programmed active "High" or active "Low", but different codes
must be used for ROM or I/O select. CSo and CSt are mask
programmed simultaneously with the ROM pattern. The ROM
Select Circuitry is shown in Figure IS.
Initialization
TIMER OPERATION
592
-----------------------------------------------------------HD6846
Counter Initialization
STATE
TCR2
0
1
0
1
0
TCR3
TCR4
TCR5
1
x
x
x
TCRl
TCR6
TCR7
0
1
0
1
BIT DEFINITION
STATE DEFINITION
Internal Reset
Timer Enabled
Clock Source
78 Prescaler
Enabler
Operating Mode
Selection
See Table 3
Timer Interrupt
Enable
593
Mode
Set
Clear
(G=Low) -
CE - C
TO
RS-RT orCI
G ~ +R
(G=Low)
R
-R
CE - C
TO
RS-RT or CI
Ci ~
CE - C
TO
RS-RTorCI
Ci
CE - C
TO
RS-RTor CI
G ~ -T+R
CE' C
Ci ~ -T+R
CE - C
Gt before RS-RT or CI
orW
TO
G ~ -T+R
CE - C
Gtbefore
TO
Cascaded Single
Shot Mode
Normal Single
Shot Mode
+W+R
~ +R
CE+TOFCE)G.j,i
+R
CE set=(H-W-R-T
CE reset=W+R+1
CE - C
Interrupt Flag
Counter Clock
"CC"
G ~ +W+R
0
0
Pulse Width
Comparison
Mode
Counter Enable
0
0
Continuous
Mode
Counter
Initialization
orW
TO
RS-RT or CI
orW
ern
CONTINUOUS MODE
(TCR3=O, TCR7=1, TCR5=O)
~~~~'i~~
TCR4
0
1
INITIALIZATION/OUTPUT WAVEFORMS
Counter
Initialization
~ '" +W+R
~~+R
CTO
1~IN+lIlTf-.I~:N+lIlT1-I~IN+l)
II
,
to
TO
TO
11
~H
VOL
TO
594
-----------------------------------------------------------HD6846
CTO
(N
+ 1)
TCR7 = Output
After Timeout
CTO
(NOTE) All time intervals shown above assume the Gate (CTG)
and Clock (CTC) signals are synchronized to Enable with the
specified setup and hold time requirements.
=0)
TCRS
APPLICATION
Frequency
Comparison
Frequency
Comparison
Pulse Width
Comparison
Pulse Width
Comparison
595
CSR211 CSR 1
CP2
IRQ
CP2
I/O OPERATION
IRQ I
TCR6
596
HD6846
5) Bit 6 of the HD6846 Peripheral Control Register is not
used. Bit 7 (PeR7) is an Internal Reset Bit not available on
the HD6821.
6) The Peripheral Data lines (and CP2 ) of the HD6846 feature
internal current limiting which allows them to directly drive
the base of Darlington NPN transistors.
PCR7
PCR6
PCRS
PCR4
PCR3
PCR2
PCR1
I 0=
CP 2 DIRECTION CONTROL
CP Is INPUT
2
1 = CP2 Is OUTPUT
--------------------------
I
CP2 IS INPUT(PCRS = O}
PCR4
II
PCR3
PCR4
PCR3
r--
PCRO
I oCP= INPUT
INPUT LATCH CONTROL
DATA NOT LATCHED
0= NORMAL OPERATION
1 = RESET CONDITION (CLEARS PERIPHERAL
DATA & DATA DIRECTION REG + CSR1 & CSR2)
I
I
597
OOR 1
Restart Sequence
Summary
A2
AI
Ao
REGISTER SELECTED
R
R/iN
R/iN
R/iN
R
R/iN
R/iN
R/iN
R
0
0
0
0
0
0
1
1
1
1
1
1
0
0
1
1
1
1
1
1
CSR2
CSRl
III o
CSRO
I
I
598
CPs INTERRUPT
NO INT REQ.
1 = INT REQUESTED
o=
-----------------------------------------------------------HD8848
TCR7
TCR6
TCRS
TCR4
TCR3
TCR2
IINTERRUPUT ENABLE
o = IRQ MASKED
1 = IRQ ENABLED
INTERNAL RESET
0= TIMER ENABLED
1 = INT REQUESTED
SOURCE
oCLOCK
= EXTERNAL
CLOCK
-- -- - - ----------- --------
o=
(CTC)
1 = INTERNAL CLOCK (<1>2)
TCR3
TCR4
TeR5
CONTINUOUS
CTG
+W + R
TO
CTG
+W+ R
TO
CONTINUOUS
CTG ~ + R
TO
0
1
CTG ~ + R
TO
R =
W =
TO =
CE =
TCRO
o = OUTPUT
-
TCR1
COUNTER INITIALIZATION
FREQUENCY COMPARISON
PULSE WIDTH COMPARISON
I
I
CTG
CTG ~1 + R
TO BEFORE CTG
CTG ~T + R
CTG t BEFORE TO
CTG ~ . T+ R
TO
BEFORE TO
BEFORE CTG t
RESET CONDITION
WRITE TIMER LATCHES
COUNTER TIME OUT
COUNTER ENABLE
T = INTERRUPT
PCR7
PCR6
PCRS
PCR4
PCR3
PCR2
I oCP= CPDIRECTION
CONTROL
Is INPUT
2
CP2 Is OUTPUT
= POSITIVE
(~) EDGE
(t) EDGE
o=
o = NEGATIVE
1
o = INPUT
I CP IS INPUT (PCRS = 0) I
I PCR4 I PCR3 I
I
I
ACTIVE EDGE SELECT
o = NEGATIVE
PCRO
CP2
peR1
CP 2 INT. ENABLE
INT. MASKED
= CP 2 INT. ENABLED
PCR4
PCR3
o = CP2
1
599
OOR 1
CP 2 IS OUTPUT (PCRS = 1)
INTERRUPT ACKNOWLEDGE
INPUT/OUTPUT ACKNOWLEDGE
PROGRAMMABLE OUTPUT
(CP 2 REFLECTS DATA
WRITTEN INTO PCR3)
ORGANIZATIONAL DATA
HD6846 COMBINATION ROM-I/O-TIMER
Customer:
Hitachi Use Only:
Company
Part No.
Quote:
Originator
Part No_:
Phone No.
Specif. No.:
cS o
cS I
DO
DO
ROM SECTION
1 ~2.0V
I/O-TIMER SELECT
0 0
Au
x'
A,
D D 0
A.
A,
A6
1
DD
O~O.8V
x
x
x
x
NOT USED
I/O-TIMER SECTION
SECTION
ENGINEER
COMPANY
DATE
I III II I II II I
DATA FORMAT
1.
2.
coding media
01.
n.,
L-I
BNPF format
paper tape
initial ROM address (decimal)
processed data
approved data
600
-----------------------------------------------------------HD8848
PAPER TAPE
(Example)
0000000000000000000000000000000000000000
data
leader
more than
600 frames
trailer
more than
600 frames
contents
column
1 to 71
72
73 to 80
CARD
DATA FORMAT
upper
07
06
1
D.
D.
03
O2 0,
,0
Do
0
J
bit weight
(corresponding to
ROM output)
<
I~d"
50
51
51
51
601
ROM
S1
Addr...
S1
S1
S1
leader (NUllS)
00
(CR)
OA
(LF)
00
00
4 x NULL
00
frame
00
S: start of the
53
record
CC: type of
CC
record
(0.10r9)
1
70 frames
max
r--
r--
-r
Check
sum
Byte
count
r--
-}
r--
-}
602
(2
Start address
of data in this
record
data
data
check sum
HD6846
3) Example of load module format
S
0
31
30
36
06
31
36
16
30
30
30
30
0000
31
31
30
30
1100
34
38
48-H
39
38
98
34
34
44-0
data
35
32
52-R
check
sum
32
42
2B
(check sum)
frame
start of record
type of record
3
4
byte count
5
6
7
8
start address of
data in this
record
9
10
data
data
CC=39
end of file
record
CC=31
data
record
53
CC=30
header
record
00
30
!1
39
30
33
03
30
30
30
30
.
0000
I
FC (check sum)
02
A8
(check sum)
ROM
vacancy
(filled with 00)
vacancy
(filled with 00)
(a)
(c)
(b)
603
(d)
000
00
o
0 00000
0 0
OOOOOOOOOOOOOOOOOOO~ooooo~~og~~~~~OOOOOOOOOOOOOOOOOOOO000
o
00000000
0000000
o
S
0
0
0000
00000
00000
000
00000 0
2BFF44
14906C466
BNPF format
1) Each word is expressed as BNPF slice which begins word
opening mark B, has 8 character bit contents shown by P or
Nand fmishes with end mark F.
00000
0000
0000000000000000000000000000000000
0000
0000
0000000000
n1T~~unn
BNNNN
PPPPF
bit weight
Note 2)
Note 3)
604
-----------------------------------------------------------HD8848
Customer
HITACHI
ROM code
Customers PIN
chip select &
other information
Choice
of Media
"Organizational Data"
"Specification Confirmation Sheet"
"ROM code"
or
same as
input
medium
information
Customer's
responsibility
HITACHI's
responsibi lity
Mask
making
report
605
HD6850, HD68A50
ACIA (Asynchronous Communications
Interface Adapter)
The HD6850 Asynchronous Communications Interface
Adapter provides the data formatting and control to interface
serial asynchronous data communications information to bus
organized systems such as the HMCS6800 Microprocessing Unit.
The bus interface of the HD6850 includes select, enable,
read/write, interrupt and bus interface logic to allow data
transfer over an 8-bit bi-directional data bus. The parallel data
of the bus system is serially transmitted and received by the
asynchronous data interface, with proper formatting and error
checking.
The functional configuration of the ACIA is programmed via
the data bus during system initialization. A programmable
Control Register provides variable word lengths, clock division
ratios, transmit control, receive control, and interrupt control.
For peripheral or modem operation three control lines are
provided.
FEATURES
Seria'l/Parallel Conversion of Data
Eight and Nine-bit Transmission
Insertion and Deleting of Start and Stop Bit
Optional Even and Odd Parity
Parity, Overrun and Framing Error Checking
Peripheral/Modem Control Functions (Clear to Send
CTS, Request to Send RTS, Data Carier Detect DCD)
Optional
HD6850, HD68A50
(DC-24)
HD6850P, HD68A50P
(DP-24)
Modes
Up to 500kbps Transmission
Programmable Control Register
N-channel Silicon Gate Process
Compatible with MC6850 and MC68A50
14
R/W
RS'
ARRANGEMENT
BLOCK DIAGRAM
TxClK
cs.
~
~N
Tx
13
~o
Tx
Data
11
24 CTS
22
21
20
19
18
17
16
15
. . .---t------
IRQ
23 DCD
5
RTS
(Top View)
Ax Data
606
-------------------------------------------------HD6860.
HD68A60
Supply Voltage
Symbol
Vee *
Input Voltage
Vin *
Operating Temperature
Topr
Tstg
Item
Storage Temperature
Value
Unit
-0.3 - +7.0
-0.3'" +7.0
-20- +75
V
c
-55 - +150
Permanent LSI damage may occur if maximum ratings are exceeded. Normal operation should be
under recommended operating conditions. If these conditions are exceeded. it could affect reliability of LSI.
Symbol
Vee *
min
4.75
typ
Input Voltage
V1l *
V1H *
-0.3
2.0
Topr
-20
25
Operating Temperature
5.0
max
5.25
Unit
0.8
Vee
75
V
c
ELECTRICAL CHARACTERISTICS
DC CHARACTERISTICS (Vcc=5V5%, VSS=OV, Ta=-2G-+7SoC, unless otherwise noted.)
Item
Symbol
All Inputs
All Inputs
V1H
V1l
lin
0 0 -0 7
ITS1
0 0 -0 7
Output "High" Voltage
VOH
TxOata, RTS
min
typ*
max
Unit
2.0
-0.3
Vee
0.8
Vin =G-5.25V
-2.5
2.5
/J.A
Vin =0.4-2.4 V
-10
10
/J.A
IOH=-205/J.A, Enable
Pulse Width ~ 25JJ.s
2.4
10 H--10~A, Enable
Pulse Width ~ 251.ts
2.4
Test Condition
All outputs
VOL
10l =1.6mA,Enable
Pulse Width ~ 251.ts
0.4
IRO
I loH
VOH=2.4V
10
/J.A
300
525
mW
12.5
Power Dissipation
Po
0 0 -0 7
Input Capacitance
Output Capacitance
E, TxCLK, RxCLK,
RNi, RS, RxOata, CS o
CSt, CS2 , CTS, DCD
Cin
Vin=OV, Ta=25C,
f=1.0MHz
7.5
Cout
Vin=OV, Ta =25C,
f=1.0MHz
5.0
RT-S, TxOata
IRO
607
10
pF
pF
Test
Condition
Symbol
Item
+16, +64 Modes
+16, +64 Modes
PWCL
PWCH
min
typ
Fig. 1
600
Fig. 2
600
--
t TOO
Fig.3
+ 1 Mode
t ROSU
Fig. 4
500
+ 1 Mode
tROH
Fig. 5
500
tlR
Fig. 6
tRTS
t r , tf
Fig. 6
Clock Frequency
+1 Mode
+16, +64 Modes
Except E
fc
max
Unit
ns
ns
500
kHz
800
1.0
IlS
ns
ns
1.2
IlS
1.0
IlS
1.0*
IlS
Symbol
Test
Condition
min
HD6850
typ
max
HD68A50
min
typ
max
tcycE
PW EH
Fig.7
1.0
0.666
Fig. 7
0.45
25
0.28
25
IlS
PW EL
Fig. 7
0.43
0.28
IlS
tAS
Fig.7
140
140
ns
320
ns
10
ns
10
220
25
25
ns
HD6850
typ
max
min
tOOR
Fig. 7
tH
Fig. 7-
10
tAH
Fig. 7
10
tEr, tEf
Fig. 7
Symbol
Test
Condition
Unit
IlS
ns
2) WRITE
Item
min
tcycE
PW EH
Fig. 8
1.0
0.666
Fig. 8
0.45
25
0.28
PW EL
Fig. 8
0.43
tAS
Fig. 8
140
tosw
Fig. 8
195
tH
Fig. 8
10
tAH
Fig.8
10
ter, tEf
Fig.8
608
HD68A50
typ
max
Unit
IlS
25
IlS
u.~o
... n
jiS
140
ns
80
ns
ns
10
ns
25
25
ns
10
----------------------------------------------------HD6850, HD68A50
PW CL
Tx elK
or
Rx elK
or
Rx elK
PWCH
tTDD~
2.4V
Tx Data
~O;:.;.4-V-----
tlR----i-
_ _ _ _ _ _J-.J22 . 44VV
Enable
RS,
es, R/Iii
Data Bus
609
H06850, H068A50--------------------------------------------------t----tcycE----.../
Enable
Data Bus
Load A
5.0V (Vee)
(IRQ Only)
R L=2.4kn
o-_ _........__
Test Point
Test point
5'OV
3kn
I'OOpF
MARKING
r -I
I
I
SPACING
M9~
BIT TIME
1__
DATA BITS
msec
START
BIT
I..
Do
Dl
D2
D3
D4
Ds
D6
610
PARITY
BIT
STOP STOP
BIT
BIT
---------------------------------------------------HD6850, HD68A50
MARKING
lJ
r --
r--n-----
~;E~::LE
~_-l __ .J __..J_~~_;;,~.1 -
_.1 __ ..J__
1.._ - - -
BELOW)
START
BIT
Do
D6
D3
......------CHARACTER TIME
PARITY STOP
BIT
BIT
BAUD RATE
150
300
CHARACTERS/SEC
15
30
6.67
3.33
66.7
33.3
BIT TIME
SEC
BAUD RATE
MARK
I
START
D2
D,
D5
D.
PARITY
STOP
STOP
NEXT
CHAR.
SPACE
DATA OF ACIA
HD6850 is an interface adapter which controls transmission
and reception of Asynchronous serial data. Some exainples of
serial data are shown in Figs. 10 - 12.
INTERNAL STRUCTURE OF ACIA
HD6850(ACIA) provides the following; 8-bit Bi-directional
Data Buses (Do-D7 ), Receive Data Input (Rx Data), Transmit
Data Output (Tx Data), three Chip Selects (CS o , CS 1 , CS 2 ),
Register Select Input (RS), Two Control Input (Read/Write
(R/W), Enable(E) , Interrupt Request Output(IRQ), Clear-toSend (CTS) to control the modem, Request-to-Send (RTS),
Data Carrier Detect{DCD) and Clock Inputs(Tx CLK, Rx CLK)
used for synchronization of received and transmitted data. This
ACIA also provides four registers; Status Register, Control
Register, Receive Register and Transmit Register.
24-pin dual-in-line type package is used for the ACIA. Internal Structure of ACIA is illustrated in Fig. 13.
ACIA OPERATION
Master Reset
611
HD6850, HD68A50---------------------------------------------------
ACIA
r-------------------------------i
Vss
(GND) - - - - ,
vee
(+5)
WRITE ONLY
----;
I I
0,
0.1 0,
0.1 ~,I 0,
I I "'I___
0,
D.
S_E_RI_A_L_DA_T_A_O_U_T_ _T_X_D_
.....I.......
~,,~ }.~~JJJ/)
I
1
I
I
LINES (PARALLEL
TO SERIAL CONVERTER)
DATA
LINES
TO
OR
FROM
MPU
READ ONLY
I
I
I
I
"I
WRITE
ONLY
I
1
irI
RxCLK
~~~~
D.
0,
0,
0,
D.
0,
0,
D.
RECEIVE
SERIAL DATA IN
' -
RUPT
INT\'6
CLOCK
TRANSMIT
CLOCK
MPU
~~AD
~~I;
MPU
ENABLE
(AO)
REGISTER
~6EAR
~~~t?AL
:::a~~M
~~~EST
-CrS,
Rx Data
"-----v---'
CHIP SELECT
FROM MPU
~I~~~ESS
MODEM
DATA
g~~~~~R
WU
ffi~
ADDRESS
LINE
MODEM
Transmit
A typical transmitting sequence consists of reading the ACIA
Status Register" either as a result of an interrupt or in the
ACIA's turn in a polling sequence. A character may be written
into the Transmit Data Register if the status read operation has
indicated that the Transmit Data Register is empty. This
character is transferred to a Shift Register where it is serialized
and transmitted from the Transmit Data output preceded by a
start bit and followed by one or two stop bits. Internal parity
(odd or even) can be optionally added to the character and will
occur between the last data bit and the first stop bit. After the
first character is written in the Data Register, the Status
Register can be read again to check for a Transmit Data Register
Empty condition and current peripheral status. If the register is
empty, another character can be loaded for transmission even
though the first character is in the process of being transmitted
(because of double buffering). The second character will be
automatically transferred into the Shift Register when the first
character transmission is completed. This sequence continues
until all the characters have been transmitted .
Receive
Data is received from a peripheral by means of the Receive
Data input. A divide-by-one clock ratio is provided for an
externally synchronized clock (to its data) while the divide-by16 and 64 ratios are provided for Internal synchronization. Bit
synchronization in the divide-by-16 and 64 modes is initiated by
612
---------------------------------------------------HD6850, HD68A50
Table 1 Definition of ACIA Register Contents
Buffer
Address
Data Bus
****
RS=l R/W=O
RS=1 R/W=l
RS=O R/W=O.
RS=O R/W=l
Transmit Data
Register
Receiver Data
Register
Control Register
Status Register
(Write Only)
(Read Only)
(Write Only)
(Read Only)
Data Bit 0*
Data Bit 0
Counter Divide
Select (CRO)
Data Bit 1
Data Bit 1
Counter Divide
Select (CR1)
Data Bit 2
Data Bit 2
Word Select 1
(CR2)
Data Bit 3
Data Bit 3
Clear to Send
(CTS)
Data Bit 4
Data Bit 4
Word Select 2
(CR3)
Word Select 3
(CR4)
Data Bit 5
Data Bit 5
Tx Control 1
(CR5)
Overrun
(OVRN)
Data Bit 6
Data Bit 6
Framing Error
(FE)
Tx Control 2
(CR6)
Rx Interrupt Enable
(CR7)
Parity Error
(PE)
Interrupt Request
(IRQ)
= Bit 0
CRO
Function
+1
+16
+64
Master Reset
Control Register
The ACIA Control Register consists of eight bits of writeonly buffer that are selected when RS and R/Ware "Low". This
The Word Select bits are used to select word length, parity,
and the number of stop bits. The encoding format is as follows:
613
CR3
CR2
0
0
0
0
0
0
1
1
0
0
1
1
1
1
1
Function
7 Bits + Even Parity + 2 Stop Bits
7 Bits + Odd Parity + 2 Stop Bits
1
0
1
0
1
0
1
Word length, Parity Select, and Stop Bit changes are not
buffered and therefore become effective immediately.
Transmitter Control Bits (CR5 and CRG)
CR5
o
o
RTS
RTS
Function
"Low", Transmitting Interrupt Enabled.
Disabled.
the Transmit Data Output.
Transmitting Interrupt Disabled.
[ '".~, "'""'-
RIE
I
iRQ
OVRN Flag
i5Cci Flag
Transmitter
[ '""~"O"""
CTs Input
The DCD bit will be "1" when the DCD input from a modem
has gone "High" to indicate that a carrier is not present. This bit
going" 1" causes an Interrupt Request to be generated when the
Receive Interrupt Enable is set. It remains" 1" after the DCD
input is returned "Low" until cleared by first reading the Status
Register and then the Data Register or until a master reset
occurs. If the DCD input remains "High" after read status and
read data or master reset has occurred, the interrupt is cleared,
the DCD status bit remains" 1" and will follow the DCD input.
Clear-to-Send (CTS), Bit 3
Receiver
TORE Flag
The CTS bit indicates the state of the CTS input from a
modem_ A "Low" CTS indicates that there is a CTS from the
modem. In the "High state, the Transmit Data Register Empty
bit is inhibited and the CTS status bit will be "1". Master reset
does not affect the Clear-to-Send Status bit.
Framing Error (FE), Bit 4
614
Clock Inputs
The PE flag indicates that the number of" 1"s (highs) in the
character does not agree with the preselected odd or even
parity. Odd parity is defined to be when the total number of
ones is odd. The parity error indication will be present as long as
the data character is in the RDR. If no parity is selected, then
both the transmitter parity generator output and the receiver
parity check results are inhibited.
Separate high impedance TTL compatible inputs are provided for clocking of transmitted and received data. Clock
frequencies of I, 16 or 64 times the data rate may be selected.
Transmit Clock (Tx ClK)
The IRQ bit indicates the state of the IRQ output, Any
interrupt condition with its applicable enable will be-indicated
in this status bit. Anytime the IRQ output is "Low" the IRQ bit
will be "1" to indicate the interrupt or service request status.
IRQ is cleared by a read operation to the Receive Data E,egister
or a write operation to the Transmit Data Register.
data. (In the -;- 1 mode, the clock and data must be
synchronized externally.) The receiver samples the data on the
positive transition of the clock.
Serial Input/Output lines
SIGNAL FUNCTIONS
through which data is received in a serial format. Synchronization with a clock for detection of data is accomplished internally when clock rates of 16 or 64 times the bit rate are used. Data
rates are in the range of 0 to 500 kbps when external
synchronization is utilized.
Modem Control
Read/Write (R/W)
Clear-to-Send (CTS)
This high impedance TTL compatible input provides automatic control of the transmitting end of a communications link
via the modem CTS active "Low" output by inhibiting the
Transmit Data Register Empty (TDRE) status bit.
Request-to-Send (RTS)
This high impedance TTL compatible input provides automatic control, such as in the receiving end of a communications
link by means of a modem DeD output. The 0C1) input inhibits
and initializes the receiver section of the ACIA when "High". A
"Low" to "High" transition of the DeD initiates an interrupt to
the MPU to indicate the occurrence of a loss of carrier when the
Receive Interrupt Enable bit is set.
615
HD6852, HD68A52
SSDA (Synchronous Serial
The HD6852 Synchronous Serial Data Adapter provides a
bi-directional serial interface for synchronous data infonnation
interchange. It contains interface logic for simultaneously
transmitting and receiving standard synchronous communications characters in bus organized systems such as the
HMCS6800 Microprocessor systems.
The bus interface of the HD6852 includes select, enable,
read/write, interrupt, and bus interface logic to allow data
transfer over an 8-bit bi-directional data bus. The parallel data
of the bus system is serially transmitted and received by the
synchronous data interface with synchronization, fill character
insertion/deletion, and error checking. The functional configuration of the SSDA is programmed via the data bus during
system initialization.
Programmable control registers provide control for variable
word length, transmit control, receive control, synchronization
control and interrupt cOlltrol. Status, timing and control lines
provide peripheral or modem control.
Typical applications include data communications tenninals,
floppy disk controllers, cassette or cartridge tape controllers and
numerical control systems.
FEATURES
Programmable Interrupts from Transmitter, Receiver,
and Error Detection LogiC
Character Synchronization on One or Two Sync Codes
External Synchronization Available for Parallel-Serial
Operation
Programmable Sync Code Register
Up to 600kbps Transmitter
Peripheral/Modem Control Functions
Three Bytes of FIFO Buffering on Both Transmit and
Receive
6, 7, or 8 Bit Data Transmission
Optional Even and Odd Parity
Parity, Overrun, and Underflow Status
BLOCK
Data Adapter)
HD6852, HD68A52
(DC-24)
HD6852P, HD68A52P
(DP-24)
PIN ARRANGEMENT
DIAGRAM
616
Tx Oa18
TUF
24
CTS
23
i5Co
iRa
Rx Data
Rx elK
SM/OTR
(Top View)
---------------------------------------------------HD6852, HD68A52
Symbol
Value
-0.3 - +7.0
Input Voltage
Vee *
Yin *
-0.3 - +7.0
Operating Temperature
Topr
- 20- + 75
V
c
Storage Temperature
T stg
-55 - +150
Supply Voltage
Unit
Permanent LSI damage may occur if maximum ratings are exceeded. Normal operation should be under recommended operating
conditions. If these conditions are exceeded, it could affect reliability of LSI.
Symbol
min
typ
max
Unit
Supply Voltage
Vee *
V 1L *
4.75
5.0
5.25
-0.3
0.8
V'H *
Topr
2.0
- 20
25
Vee
75
Input Voltage
Operating Temperature
ELECTRICAL CHARACTERISTICS
All Input
V'H
All Input
V'L
0 0 -0 7
V OH
Tx Data
DTR,TUF
All Output
V OH
VOL
Test Condition
min
typ*
2.0
-0.3
0.8
2.4
2.4
0.4
max
Unit
TxCLK, RxCLK,
Input Leakage Current
Rx Data, E,
lin
Yin = 0 - 5.25V
-2.5
2.5
pA
Do'" 0 7
ITS1
-10
10
pA
IRQ
I LOH
V OH = 2.4V
10
pA
300
525
12.5
7.5
10
RES, RS,Rm
CS, DCD, CTS
Po
Do'" 0 7
RxData, RxCLK,
Input Capacitance
Yin = OV,
Ta = 25C,
TxCLK, RES,
CS, RS, Rm, E,
Cin
f = 1 MHz
mW
pF
DCD,CTS
Output Capacitance
Cout
5.0
pF
HD6852, HD68A52---------------------------------------------------v
HD6852
Test
Condition
Symbol
typ
Fig. 1
min
700
min
400
Fig. 2
700
400
600
1.0
PWCL
PWCH
Clock Frequency
fc
tRoSU
Fig. 3,7
350
tROH
Fig.3
350
tSM
Fig.3
tToO
Fig. 4,6
Fig.4
0.666
IlS
1.0
0.666
IlS
1.0
0.666
IlS
1.2
0.8
IlS
0.666
Ils
ns
1.0*
Fig. 5
1.0
Fig.6
200
tRES
tCTS
toco
Fig. 7
500
t r, tf
0.8V to 2.OV
1.0~
ns
kHz
1.0
tlR
1,000
IlS
I RQ Release Time
ns
0.666
Fig. 5
tTUF
I
Unit
HD68A52
typ
max
tOTR
Transmitter Underflow
max
200
I
200
150
350
1.0*
ns
ns
ns
IlS
2. BUS TIMING
1) READ
Item
Enable Cycle Time
Enable "High" Pulse Width
Enable "Low" Pulse Width
Symbol
Test
Condition
tAS
max
Fig.8
HD68A52
min
max
Unit
Ils
0.45
25
0.28
25
IlS
0.43
0.28
IlS
140
140
ns
ns
1.0
tcycE
PW EH
PW EL
HD6852
min
0.666
tOOR
320
220
tH
10
10
ns
tAH
10
80
10
ns
tEr, tEf
25
80
25
ns
2) WRITE
Item
Symbol
Test
Condition
HD6852
min
max
HD68A52
max
min
Unit
tcycE
PW EH
0.666
Ils
0.45
25
0.28
25
IlS
PW EL
0.43
0.28
IlS
tAS
140
140
ns
tosw
195
80
tH
10
10
ns
Data Hold Ti me
Address Hold Time
tAH
10
10
ns
tEr, tEf
25
25
ns
1.0
Fig.9
618
ns
----------------------------------------------------HD6852, HD68A52
Tx elK
or
Rx elK
Tx elK
or
Rx elK
Rx elK
Rx Data
O.4V
~---
:::. Rx elK
Period
Figure 3 Receive Data Setup and Hold Times and Sync Match Delay Time
Tx
elK
Enable
tOT A
Tx
Data
TUF
IRQ
n = Number of bits
in character
Rx ClK
Tx elK
Rx Data
Tx Data
At least two Rx elK pulse should be input after the last bit of the last data
before the next falling edge of OeD occurs.
619
HD6852. HD68A52-------------------------------------------------
Enable
Enable
---~..".~'-L..-~...pr'"~---
Data Bus
Data Bus
Load A
(Do - 0" DTA, Tx Data, TUF)
Load B
(lAQOnly)
Test point
Test point
~r
5.0V
3k
100pF
C-13OpF for Do -0 7
-3OpF for DTA, Tx Data, and TUF
All diodes are 1S2074 or Equivalent:
A=11kO for 0 0 "'0,
"'24kO for DTA, Tx Data, and TUF
DEVICE OPERATION
At the bus interface, the SSDA appears as two addressable
memory locations. Internally, there are seven registers: two
read-only and five write-only registers. The read-only registers
are Status and Receive Data; the write-only registers are Control
1, Control 2, Control 3, Sync Code and" Transmit Data. The
serial interface consists of serial input and output lines with
independent clocks, and four peripheral/modem control lines.
Data to be transmitted is transferred directly into the 3-byte
Transil"Jt Data First.. ln First=Out (FIFO) Register from the data
bus. Availability of the input to the FIFO is indicated by a bit
in the Status Register; once data is entered, it moves through
the FIFO to the last empty location. Data at the output of the
FIFO is automatically transferred from the FIFO to the
Transmitter Shift Register as the shift register becomes available
to transmit the next character. If data is not available from the
FIFO (underflow condition), the Transmitter Shift Register is
automatically loaded with either a sync code or an all "I "s
character. The transmit section may be programmed to append
even, odd, or no parity to the transmitted word. An external
control line (CTS) is provided to inhibit the transmitter without clearing the FIFO.
Serial data is accumulated in the receiver based on the
synchronization mode selected. In the external sync mode used
for parallel-serial operation, the receiver is synchronized by the
620
----------------------------------------------------HD6852, HD68A52
Initialization
Transmitter Operation
Receiver Operation
Synchronization
Receiving Data
Once synchronization has been achieved, subsequent characters are automatically transferred into the Receive Data FIFO
and clocked through the FIFO to the last empty location by E
pulses (MPU System 2). The Receiver Data Available status bit
HD6862, HD68A62-------------------------------------------------(RDA) indicates when data is available to be read from the last
FIFO location. (#3) when in the I-byte transfer mode. The
2-byte transfer mode causes the RDA status bit to indicate data
is available when the last two FIFO register locations are full.
Data being available in the Receive Data FIFO causes an
interrupt request if the Receiver Interrupt Enable (RIE) bit is
set. The MPU will then read the SSDA Status Register, which
will indicate that data is available for the MPU read from the
Receiver Data FIFO register. The IRQ and RDA status bits are
reset by a read from the FIFO. If more than one character has
been received and is resident in the Receive Data FIFO,
subsequent E clocks will cause the FIFO to update and the
RDA and IRQ status bits will again be set. The read data
operation for the 2-byte transfer mode requires an intervening E
clock between reads to allow the FIFO data to shift. Optional
parity is automatically checked as data is received, and the
parity status condition is maintained with each character until
the data is read from the Receive Data FIFO. Parity errors will
cause an interrupt request if the Error Interrupt Enable (EIE)
has been set. The parity bit is not transferred to the data bus
but must be checked in the Status Register. NOTE: In the
2-byte transfer mode, parity should be checked prior to reading
the second byte, since a FIFO read clears the error bit.
Other status bits which pertain to the receiver section are
Receiver Overrun and Data Carrier Detect (DCD). The Overrun
status bit is automatically set when a transfer of a character to
the Receive Data FIFO occurs and the first register of the
Receive Data FIFO is full. Overrun causes an interrupt if Error
Interrupt Enable (EIE) has been set. The transfer of the
overrunning character into the FIFO causes the previous
character in the FIFO input register location to be lost. The
Overrun status bit is cleared by reading the Status Register
(when the overrun condition is present), followed by a Receive
Data FIFO Register read. Overrun cannot occur and be cleared
without providing an opportunity to detect its occurrence via
the Status Register.
A positive transition on the DCD input causes an interrupt if
the EIE control bit has been set. The interrupt caused by rx;o
is cleared by reading the Status Register when the
status
bit is "1", followed by a Receive Data FIFO read. The DCD
status bit will subsequently follow the state of the DCD input
when it goes "Low".
om
SSDA REGISTERS
Seven registers in the SSDA can be accessed by means of the
bus. The registers are defined as read-only or write-only
according to the direction of information flow. The Register
Select (RS) input selects two registers in each state, one being
read-only and the other write-only. The Read/Write (R/W) input
dermed which of the two selected registers will actually be
accessed. Four registers (two read-only and two write-only) can
be addressed via the bus at any particular time. These registers
and the required addressing are defined in Table 1.
Control Register 1 (C1)
Control Register 1 is an 8-bit wirte-only register that can be
directly addressed from the data bus. Control Register 1 is
addressed when RS = "Low" an.d R/W = "Low".
Receiver Reset (Rx Rs), C1 Bit 0
The Receiver Reset control bit provides both a reset and
inhibit function to the receiver section. When Rx Rs is set, it
clears the receiver control logiC, error logic, Rx Data FIFO
622
---------------------------------------------------HD6852, HD68A52
enable control for the SM/DRT output in the Sync Match mode.
A one-bit-wide pulse is generated at the output when PC2 is "0",
and a match occurs between the contents of the Sync Code
Register and the incoming data even if sync is inhibited (Clear
Sync bit = "1 "). The Sync Match pulse is referenced to the
negative edge of Rx CLK pulse causing the match.
The Data Terminal Ready (DTR) mode is selected when PCI
is "0". When PC2 = "1" the SM/DTR output ="Low" and vice
versa. The operation of PC2 and PCI is summarized in Table 4.
1-Byte/2-Byte Transfer (1-Byte/2-Byte). C2 Bit 2
When 1-Byte/2-Byte is set, the TDRA and RDA status bits
will indicate the availability if their respective data FIFO
registers for a single byte data transfer. Alternately, if I-Byte/
2-Byte is reset, the TDRA and RDA status bits indicate when
two bytes of data can be moved without a second status read.
An intervening Enable pulse must occur between data transfers.
Word Length Selects (WS1. WS2. WS3). C2 Bits 3. 4. 5
Word length Select bits WSI, WS2, and WS3 select word
length of 7, 8, or 9 bits including parity as shown in Table 3.
Transmit Sync Code on Underflow (Tx Sync). C2 Bit 6
When Tx Sync is set, the transmitter will automatically send
a sync character when data is not available for transmission. If
Tx Sync is reset, the transmitter will transmit a Mark character
(including the parity bit position) on underflow. When the
underflow is detected, a pulse approximately a Tx CLK "High"
period wide will occur on the underflow output if the Tx Sync
bit is "1". Internal parity generation is inhibited during
underflow except for sync code fill character transmission in 8
bit plus parity word lengths.
Error Interrupt Enable (EIE). C2 Bit 7
When EIE is set, the IRQ status bit will go "1" and the IRQ
output will go "Low" if:
1) A receiver overrun occurs. The interrupt is cleared by reading
the Status Register and reading the Rx Data FIFO.
2) DeD input has gone to a "High". The interrupt is cleared by
reading the Status Register and reading the Rx Data FIFO.
3) A parity error exists for the character in the last location
(#3) of the Rx Data FIFO. The interrupt is cleared by
reading the Rx Data FIFO. The interrupt is cleared by
readi.!!&.lhe Rx Data FIFO.
4) The CTS" input has gone to a "High". The interrupt is cleared
by writing a "1" in the Clear CTS bit, C3 bit 2, or by a Tx
Reset.
5) The transmitter has underflowed (in the Tx Sync on
Underflow mode). The interrupt is cleared by writing a "1"
into the Clear Underflow, C3 bit 3, or Tx Reset.
When EIE is a "0", the IRQ status bit and the IRQ output
are disabled for the above error conditions. A "Low" level on
the RES input resets EIE to "0".
Control Register 3 (C3)
Control Register 3 is a 4-bit write-only register which can be
programmed from the bus when RS = "High" and R/W
"Low" and Address Control bit ACI ="1" and AC2 ="0".
External/Internal Sync Mode Control (E/I Sync). C3 Bit 0
When the E/I Sync Mode bit is "1", the SSDA is in the
external sync mode and the receiver synchronization logic is
disabled. Synchronization can be achieved by means of the DCD
input or by starting Rx CLK at the midpoint of data bit "0" of
623
Receiver
At Synchronization
Receiver automatically strips the sync character(s) (two sync
characters if '2 sync' mode is selected) which is used to establish
synchronization. And parity is not checked for these sync
characters.
After Synchronization is Established
When 'strip sync' bit is selected, the sync characters (fill
characters) are stripped and parity is not checked for the
stripped sync (fill) characters. When 'strip sync' bit is not
selected (0), the SY!lc character is assumed to be normal data
and it is transferred into FIFO after parity checking. (When
non-parity format is selected, parity is not checked.)
Strip Sync
(C1 Bit 2)
Data Format
(C2 Bit 3-5)
With Parity
Without Parity
Operation
No transfer of sync
code.
No par ity check of
sync code.
Transfer data and
sync codes.
Par ity check.
Transfer data and
sync codes.
No parity check.
* Subsequent to synchronization
x .... don't care
bit. The Overrun bit will be set when the overrun occurs and
remains set until the Status Register is read, followed by a read
of the Rx Data FIFO.
Unused data bits for short word lengths (including the parity
bit) will appear as "O"s on the data bus when the Rx Data FIFO
is read.
The TDRA status bit indicates that data can be loaded into
the Tx Data FIFO Register. The first register (#1) of the Tx
Data FIFO being empty will be indicated by a '~1" in the TDRA
status bit in the I-byte transfer mode. The first two registers
(#1 and #2) must be empty for TDRA to be "1" When in the
2-byte transfer mode. The Tx Data FIFO can be loaded with
two bytes without an intervening status read; however, one E
pulse must occur between loads. TDRA is inhibited by the Tx
Reset or IrnS'. When Tx Reset is set, the Tx Data FIFO is
cleared and then released on the next E clock pUlse. The Tx
Data FIFO can then be loaded with up to three characters of
data, even though TDRA is inhibited. This feature allows
preloadin~ta prior to the release of Tx Reset. A "High" level
on the CTS" input inhibits the TDRA status bit in either sync
mode of operation (one-sync-character or twosync-character).
CfS does not affect TDRA in the external sync mode. This
624
--------------------------------------------------HD6852, HD68A52
the Tx Rs bit. TUF indicates that a sync character will be
transmitted as the next character. A TUF is indicated on the
output only when the contents of the Sync Code Register is to
be transferred (transmit sync code on underflow = "1 ").
enables the SSDA to operate under the control of the CTS input
with TDRA indicating the status of the Tx Data FIFO. The crs
input does not clear the Tx Data FIFO in any operating mode.
Data Carrier Detect (DCD), S Bit 2
The parity error status bit indicates that parity for the
character in the last register of the Rx Data FIFO did not agree
with selected parity. The parity error is cleared when the
character to which it pertains is read from the Rx Data FIFO or
when Rx Rs occurs. The DCD input does not clear the Parity
Error or Rx Data FIFO status bits.
Register
Address
Control
Register Content
AC1
Bit 7
Bit 6
Bit 3
Bit 2
Bit 1
Bit 0
Interrupt
Request
(lRO)
Receiver
Parity
Error
(PE)
Receiver Transmitter
Overrun Underflow
(TUF)
(Rx Ovrn)
Clearto
Send
(CTS)
Data Carrier
Detect
(DCD)
Transmitter
Data
Register
Available
(TDRA)
Receiver
Data
Available
(RDA)
Address
Control 2
(AC2)
Address
Control 1
(AC1)
Receiver Transmitter
Interrupt Interrupt
Enable
Enable
(RIE)
(TIE)
Clear
Sync
Strip Sync
Characters
(Strip Sync)
Transmitter
Reset
(Tx Rs)
Receiver
Reset
(Rx Rs)
07
D.
05
04
03
O2
0\
Do
Control 2
(C2)
Error
Interrupt
Enable
(EIE)
Transmit
Sync Code
on
Underflow
(Tx Sync)
Word
Length
Select 3
(WS3)
Word
Length
Select 2
(WS2)
Word
Length
Select 1
(WS1)
1Byte/2-Byte
Transfer
(1-Byte/2-Byte)
Peripheral
Control 2
(PC2)
Peripheral
Control 1
(PC1)
Control 3
(C2)
Not Used
Not Used
Not Used
Not Used
Clear
Transmitter
Underflow
Status
(CTUF)
Clear CTS
Status
(Clear CTS)
OneSync
Character/
TwoSync
Character
Mode Control
(1 Sync/
2 Sync)
Sync Cod:
07
D.
05
D.
D.
0,
D\
Do
Trans;.;'it
Data FIFO
07
D.
05
04
03
0,
0\
Do
RS
R/W
Status (S)
Control 1
(C1)
Receive
Data FIFO
...
AC2
Bit 5
Bit 4
--
625
---External/
Internal
Sync Mode
Control
(E/I Sync)
Bit
7
~
Status
Aegister
(S)
Symbol
IRQ
Function
The IRQ flail is cleared when the source of the IRQ is cleared. The source is determined by
the enables in the Control Registers: TIE. RIE. EIE.
PE
----------Rx Ovrn
---------TUF
-65------
--------DCD
~-----------------------
-A7.,.;-i~t~CTUF(C3Bit3)-~int~--
'~rhe;ffl-;ig~lr~;;:"------
Conditions
for Set
e--------------
~-----------------
Conditions
for Reset
-----------------f-!~~t~:
_____________ _
t---------------------
RDA
- ------------
r-1ByteT-;:-a~sfe7Mod~;~h-;~--
TDRA
~-------------------
AC2
RI E
:::
When "1". strips all sync codes from the received data stream.
Ax As
EIE
When "1". enables the PE. Rx Ovrn. TUF. CTS. and DCD interrupt flags (S Bits 6 through 2).
Tx Sync
Status bit and output. When "0". an all mark character is transmitted on underflow .
WS3
WS2
WS1
1.. Byte/2.Byte
When "1". enables the TDAA and R DA bits to indicate when a 1-byte transfer can occur; when
PC2
::::::::
::!~:~~:::::::::::::: :::i!!.~~:~:::~::.:!~~~~~:~~~:!~:~!~i~~:~~~:!~~:~~~:i~~~~:~~~~!~~~:::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::
o
7
6
..............
5
4
3
..................................
::~:::.~~~.:~.~~.~.~~.~.~~.~!!~.~~~~~~~.~.~~~~.~.?. .~y.~~.~~~~~~~~.~!!~.~:~~~: ............................................. .
1
PC2
'2"
3
Control
Aegister 3
(C3)
CTUF
cl~~~rn Whe~;;1;;:cle~~;rnisBitjY:~ricjl'R<lifen~bied:
................... _................................................
... '1'" .T.sYrici2:Sv~"c; ... Whe~' ;;1;;: ~el~ct;' the 'i>ne:sy~C~h~;~ct;; '~~de';' ~t;~~' ";0';: ~eiect~ th~ t~~:~yh~~h~~;;~t~r ;;'-~d~: ............... .
"'0'" eiiSyn"c; Wheri;;i;;:selectsitieexternaisyncmode;when'"O;..:selectstheYriiernaisyricniode: .............. .
Bit 4
WS2
Bit 3
WS1
Word Length
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
626
---------------------------------------------------HD6852, HD68A52
Table 4 SM/OTR Output Control
Bit 1
PC2
0
0
1
1
Bit 0
PCl
0
1
0
1
RDAPE
Rx Ovrn
CTS
DCD
TUF
TDRA
RDA
Enable (E)
Read/Write (R/W)
Reset (RES)
Separate high impedance TTL compatible inputs are provided for clocking of transmitted and received data.
Clear-to-Send (CTS)
627
DTR
TxRs
RxRs
#1
TxData
#2
#3
1#4
RxData
TDRA
628
..
--."""",,~~."."'"
(Usual Case)
RxCLK
RxData
07
D.
07
RDA flag_ _ _ _- . I
.~--_r--_r----------------------------------~~--------
RxData
RDA
Os
0,
07
D.
Os
07
flag~------~...It.'-t-----------------------.J L.-_ _
DCD input
--------~~
Figure 13 Exceptional External Sync Operation
!_...JX
RxData. _ _ _ _-..I..1....
,
,
'
I
. t, . t2
Do
0,
t2
t,
>0
500 nsec
629
HD4650S, HD4650S-1,
HD4650SA, HD4650SA-1
ADU (Analog Data Acquisition Unit)
The HD46S08 is a monolithic NMOS device with a lO-bit
analog-to-digital converter, a programmable voltage comparator,
a 16-channel analog multiplexer and HMCS6800 microprocessor
family compatible interface.
Each of 16 analog inputs is either converted to a digital data
by the analog to-digital converter or compared with the specified value by the programmable comparator. The analog-todigital converter uses successive approximation method as the
conversion technique. It's intrinsic resolution is 10 bits but it
can be 8 bits if the programmer so desires. The programmable
voltage comparator compares the input voltage with the value
specified by the programmer. The result (greater than, or
smaller than) is reflected to the flag in the status register.
The device can expand its capability by controlling the
external circuits such as sample holder, pre-amplifier and
external multiplexer.
With these features, this device is ideally suited to applications such as process control, machine control and vehicle
control.
PIN ARRANGEMENT
AI.
AI,
AI,
AI,
D.
FEATURES
l6-channel Analog multiplexer
Programmable AID Converter resolution (10-bit or 8-bit)
Programmable Voltage comparison (PC)
Conversion Time 100~s (AID), 13~s(PC)
External Sample and Hold Circuit Control
Auto Range-switching Control of External Amplifier
Waiting Function for the Settling Time of External
Amplifier
Interrupt Control (Only for AID conversion)
0,
AI,
0,
AI,
0,
AI.
D.
AI,
D,
AI.
AI,
AI,.
AI"
AI"
AI"
AI,.
AI"
REF(+I
COMMON
COMPIN
REFH
(Top View)
BLOCK DIAGRAM
Comparator
r-"Input
I
ICOMPINI
~ ___ Common __
-+--------1'"
5V 1Veel
GNo 1Vssl
+-------.
ClK (1MHzl
Output
ICOMMONI
AI,
AI,
0" - 0,
Analog
Inputs
~S,
~-------+-- ~,
RS,
Alu
RS,
RtW
Ext"net
~---------4~. ~
Control
SigNl
(GAINSEll
5V
Analog GNO
IREF(+)1 (REF(-I!
630
ORDERING INFORMATION
ADU
HD46508A
Bus Timing
Non Line.ritv
1 MHz
HD46508Al
1.5 MHz
HD46508
lMHz
HD465081
1.5 MHz
il LSB
i3 LS8
0 0 -0
~(==============================~============================~
A
IRQ
IE
CS o
IE
CS,
R/W CONTROL
IE
C. START
SYNCHRONOUS
CIRCUIT
ClK
I...
CD
RS o
I~
RS,
IE
R/Vil
IE
RES
(Reg. 0)
BASIC
TIMING
GENERATOR
SUCCESSIVE
APPROXIMATION
D/A
(1024 lADDER
RESISTANCE &
DECODER)
REGISTER
EXPAND
CONTROL
@
ST
Alo
::E:
C
.,.
0)
AI,
PC,GS,GO,G1@'@
en
CD
(Reg. 0, 1)
(Reg.O)
::E:
C
.,.
ANALOG
MPX
MODE SELECT
& GAINSEl
CONTROL
0)
en
CD
I
~
AI,.
COMPARATOR
@
00-03 (Reg. 1)
MI
GAINSEl
REF(+) REFH
COMPIN
COMMON
::E:
C
~
0)
en
o
CD
l>
::E:
.,.C
0)
en
CD
l>
I
Value
Unit
Supply Voltage
Item
-0.3- +7.0
Input Voltage
Yin *
-0.3 - +7.0
VAin *
-0.3 - +7.0
Operating Temperature
Topr
T sts
- 20- +75
c
c
Storage Temperature
- 55- +150
[NOTE] Permanent LSI damage may occur if maximum ratings are exceeded. Normal operation should be under recommended operating conditions.
If these conditions are exceeded, it could affect reliability of LSI.
Symbol
Vee *
Supply Voltage
Input "Low" Voltage
V 1H *
V 1l *
VAin *
~.REF(+) *
VREF(-l *
Reference Voltage
min
typ
max
Unit
4.75
5.25
2.0
VCf:,
-0.3
0.8
5.0
5.0
Vee+0 . 25
-0.1
Vee
-2-
- 20
25
Topr
Test Condition
min
V 1H
2.0
V 1l
-0.3
Do -D 7
Output "High" Voltage
GAINSEl
IOH
VOH
IRQ
IOH
= -2051lA
= -2001lA
IOH = -101lA
0 0 -0" GAINSEL
75
IOl
2.4
2.4
Vee -l.0
typ
max
Unit
Vee
0.8
V
V
0.4
=3.2 mA
0.4
-2.5
2.5
IlA
-10
10
IlA
10
IlA
IOl = 1.6 mA
VOL
V~e+0.25
Symbol
Item
E, ClK, R/W
Input leakage Current
RES, RS o , RS 1
CSo , CS 1
lin
Vin = 0- 5.25V
Do - D7
ITS1
Vin
IRQ
I LoH
V OH = 2.4V
Output leakage
Current
Power Dissipation
=0.4"" 2.4V
Po
Input Capacitance
----
Output Capacitance
Do"" D7
E, ClK, R/W
--
500
mW
12.5
pF
10.0
pF
10.0
pF
RES, RSo , RS 1
CSo , cS7
Cin
IRQ, GAINSEl
Cout
= 1 MHz
Yin
= OV, Ta = 25C
f = 1 MHz
632
Test Condition
= S.OV,
= 4.75V, Ta = 25C
VAin = S.OV
Vee = 4.75V, Ta = 25C
VAin
Vee
COMMON
VAin
Vee
V REF (+1
VREF (-)
kn
10
100
nA
-10
nA
7.S
pF
10
40
kn
Unit
._--
= OV
-100
max
= OV, Ta = 2SoC
= 4.7SV, COMMON = SV
Ladder Resistance
typ
min
= 5.0V
= OV, Ta = 25C
CONVERTER SECTION (Ta = 2SoC, Vee = VREF(+I = 5.0V, tcyc:C = 11lS, unless otherwise noted.)
1. 10-BIT A/D CONVERSION
H046508, H046508-1
H046508A, H046508A-1
Item
min
typ
1/2
Zero-Error
Full-Scali Error
1/2
1/4
3/4
1/2
Resolution
Non-linearity Error
Quantization Error
Absolute Accuracy
typ
max
Unit
max
min
bits
LSB
1/2
LSB
1/2
LSB
1/2
1/2
LSB
3/2
LSB
10
10
Resolution
Non-linearity Error
min
Zero-Error
Full-Scali Error
Quantization Error
Absolute Accuracy
H 046508, H 046508-1
HD46S08A, H046508A-1
Item
typ
max
min
typ
max
Unit
bits
1/4
3/4
LSB
3/8
1/2
LSB
3/8
1/2
LSB
1/2
LSB
3/4
S/4
LSB
1/8
1/4
1/4
3/8
1/4
3/8
1/2
S/8
3/4
max
min
Item
min
Resolution
Non-linearity Error
Zero-Error
Full-Scali Error
Absolute Accuracy
typ
H046508, H046508-1
typ
max
Unit
1/8
1/4
1/4
3/4
LSB
1/4
3/8
3/8
1/2
LSB
1/4
3/8
3/8
S/8
633
bits
3/8
1/2
LSB
1/2
LSB
HD46508, HD46508-1, HD46508A, HD46508A-1--------------------------- AC CHARACTERISTICS (Vee= 5.0V 5%, Vss = OV, Ta = -20- +75C, unless otherwise noted.)
1. CLOCK WAVEFORM
Item
Test
Conditions
Symbol
t cvcc
PW CH
PW CL
Fig. 2
Unit
max
min
typ
max
0.5
0.22
0.21
10
4.5
4.0
5
2.2
2.1
J1.s
J1.s
25
25
ns
1.0
0.45
0.40
tCr, tCf
CO* = 1
CO* = 0
typ
min
2.0V
J1.s
2.0V
O.8V
ClK
~----PWCH------~_tCf~-----PWCL-----~
1------------- tcvcC------------~
Symbol
Item
I RQ Release Time
tlR
tGSD1
tGSD2
Test condition
Fig. 3
Fig. 4
min
typ
_E _ _...J
tlR-1
--'1
I"irn _ _ _ _ _ _ _ _ _ _
634
24V
max
650
750
750
Unit
ns
ns
ns
--IX'OV
CLK_ _
I
i
VCCxO.7*
GAINSEL
*CMOS Load
CLK
O.8V
VccxO.7* ,"
~/~-----------------
*CMOS Load
tGS01
tGS02
Symbol
Test
Condition
min
max
min
typ
max
0.666
J.l.s
0.28
0.28
25
25
J.l.s
ns
ns
tcycE
PWEH
1.0
0.45
PWEL
0.40
tEr,tEf
tAS
tOOR
tACC
Fig.5
140
Unit
typ
HD4650S-1
HD4650SA-l
HD4650S
HD4650SA
tH
10
tAH
10
635
J.l.s
140
320
220
ns
460
360
ns
10
ns
ns
10
Symbol
Test
Condition
HD4650S
HD4650SA
min
1.0
0.45
0.40
t cvcE
PW EH
PW EL
tEr, tEf
tAS
140
195
tosw
tH
Address Ho Id Ti me
tAH
Fig. 6
typ
10
10
max
HD4650S1
HD4650SAl
typ
min
max
0.666
0.2S0
fJ.S
f./.S
25
ns
ns
0.2S0
25
140
80
10
. 10
Unit
f./.s
ns
ns
ns
joE--------- tcvcE----------..,~
E
~------PWEL-----~
cs.
R/W. CS o
636
2.0V
tEr
O.8V
rI
O.8V
t A S + - P W E H --------..!
~-------PWEL------~
2.0V
2.0V
O.8V
O.8V
5.OV
Test Point
LOAD B (IRQ)
LOAD A (Do-D,.GAINSEL)
I
T,"""",1
= 2.4kO
= 130pF
__e
RL
o------i~4---~__
11kO
RL
= 2.4kO
= 3kf2
= 100pF
Diode = 182074<8>
Diode = 18207418
or Equivalent
I~P'
LOAD C (GAIN8EL)
637
or Equivalent
(Note)
0 - - YES
x --NO
638
bth6D~~~~~
"1"
"0"
See Table 2
Mode Select
Not Used
Not Used
Not Used
..
Settl ing Ti me
Available
Not Available
ClK Divider
ClK/2
ClK
Interrupt Enable *
Enable IRQ
Mask IRQ
*RES doesn't affect IE bit.
17161514131211101
I sc I GS I PC I MI I 03 I 02 I 01 I DO I
I
'
..
I
"1"
"0"
See Table 3
MPX Inhibit
Inhibited
Not Inhibited
GAINSEl Enable
GAINSEl Enable
GAINSEl Disable
Short-cycle Conversion
8-bit length
10-bit length
"1"
"0"
See Table 4.
Programmable
Comparator Output
VAin> Vp
VAin <Vp
Busy flag
Under Conversion
Conversion Completed
IRQ flag
Requested
Not Requested
Not Used
639
1.--_ _ _ _ _ _ _ _
IE bit:
(Interrupt Enable)
="1",
fIE ="0",
CD ="1",
iE
Interrupt is rett8ested
tluough the I
output.
Interrupt is masked.
CD bit:
(Clock Divider)
ST bit:
(Settling Time)
L=.'O. ,
GS bit
(GAINSEL Enable)
GO
0
1
0
1
GS = "I"
GAINSEL signal is
enabled. The function of
GAINSEL is specified by
(GO, G I) bits.
GAINSEL signal is disabled. ("Low" level)
PC bit
{PC = "I" Programmable voltage
(program comparator)
, comparator mode
PC ="0", AID conversion mode
IMI="I", Internal MPX channel is
inhibited in order to use
external MPX channel.
MI ="0", Internal MPX channel is
used.
MIbit
(MPX Inhibit)
DO-D3
(MPX channel)
TIlese bits are used to specify the function of GAINSEL signal when GS bit
is "I".
GO,GI bit;
(Mode select)
Mode Select
Sample & Hold
Auto RangeSwitching x 2
Auto Range-Switching x 4
Programmable Gain Control
6
7
8
9
10
11
12
13
14
15
640
03
02
01
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
DO
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Analog Input
Alo
All
AI2
AI3
AI4
Als
AI6
AI7
Ais
AI9
AI IO
AI11
AI12
AI 13
AI14
AilS
Function
10 bit AD CONV.
SC
0
8 bit AD CONV.
OVbit
(Over scale)
Pea bit
(GO,G1)
GS
0
1
0
1
DISABLE
ENABLE
DISABLE
ENABLE
DISABLE
(programmable
comparator
Output)
x = Do not care
= See Table 6
(R4)
(C8, C9)
These bits store upper 2-bit data mea(Upper bit data) sured by 10 bit length conversion.
DWbit
(Data weight)
BSY bit
(Busy)
IRQ bit
(Interrupt
Request)
Set
Mode
("1 ")
410
VAin < 1024 VREF (+)
VAin
206
VAin
: Analog Input Voltage to be measured
VAEF(+) . Voltage Applied to REF(+)
641
Reset
("0")
410
VAin> 1024 VREF (+)
VAin>
206
"ca
GI
WRITE WRITE
,Reg.
Reg, 1
: : :
cs,
~~isterO
::;~,:"~
""""
"
_. -
"ca
o
....
GI
CD
GI
CD
I~
ca
GI
CD
--W
~----~jr--;-T"4R~"-~"'~
rna
I)
Analog
~
{
BSY
I
I
1--"-- "
ca
~"""""""""""""""""""~"""""""""""""""""""""""""""""""""""""""""""""""""""""""",
Control
MPX Out
""_o~
0)
.j:::o.
I\)
I
I
R::~::l=:
Conversionstart
I
Reg. 2 Reg. 3
I
I
: : :
R/W,CS"
ContrOl
o
!II
READ READ
If
1
~
~t:t'a"~~g~:~ (H)~.$ff~
(R21
AID Data
Register(Ll~~~~~~4{{f'~
(R3)
JY4@!@!Y~4@lff~d$?4~
III
...~
h'c:yc=1J..LS)
Conversion Start
Conversion End
~~: ::~::)
(GS=
"0"
2
(LSB)
2) Basic Sequence
(When overscale
is detected)
Overscale check Cycle
(Analog Input is compared with V REF (+).)
3) Expanded Sequence
"0")
SC =
( ST = "1"
GS= "0"
Switching Control
Sequence
sc = "0"
r ST = "0"
I
GS
= "1"
J1(-GO=
"0"
G1 "1")
=
or
GO - "1"
(G1 : "0,,)
'--;:-1--_ _ _
5) Auto Range-
-+-_--l.__.L..._-'-__.L._...L._--..JL-_-'-':':::::.:J
-GO= "0"
(G1 = "1")
or
GO = "1"
(G1 = "0")
b) Analog Input>
& Hold
Control Sequence
6) Sample
~~: ::~::)
GS = "1"
GO = "0"
G1 = "0"
643
~~: ::~::)
GS= "1"
GO= "1"
Gl = "1"
8) Programmable
Gain & Expansion
Control Sequence
~~: ::~::)
GS= "1"
GO = "1"
Gl = "1"
~~: ::~::)
( GS=
"0"
Additional conversion cycle
for rounding the LSB - 1 Bit .
.j.
2) Expanded Sequence
"1")
SC =
( ST = "1"
GS= "0"
~
~
1) Basic Sequence
"1")
PC =
ST = "0"
2) Expanded Sequence
PC="l"\
(
ST="l"j
Functions of GAINSEL
The ADU is equipped '.vith progranunable GAINSEL output signal. By using GAINSEL output and external circuit,
the ADU is able to implement following control.
Gl
GO
"Low"
"High"
0
0
*
*
"High"
GAINSEL
Control Mode
OW
0
0
**
**
644
COMMON
GA'N
SEL
VII
REF H
COMP'N
ADU
Overseale Check
x1 Sample 81 Hold
HD14066
OR EaU
r-------------------
2" -1
REF(-)
COMPIN
100,
I
I
011:
010:
0011
I-
ADU
is
c;
GAINSEL
~ADU
101:
..J
Vss
: oversea" are.
110:
8
COMMON
ideal t,ansition
111:
'
000'
"
I,
~.t
R/2 R
::
3A/2
8'/8 oversea I.
refl" voltage
OVAEF(+)
(FSI
645
Usage of the PC
The ADU has a programmable threshold voltage comparator (PC) function. The threshold voltage is pre-setable
from OV to SV range with 8 bit resolution. The comparator's
ADU
.--......~---; +
to
bfrom
MPU
r
L________________________ _
'---_..I
r-
0
Rq
SC
GS
PC
MI
address
03
I I
02
ev
OW
B3
B2
R211RQ
R41 B7
I I pce I
BSY
B6
B5
B4
I I
01
DO
C9
C8
B1
BO
(a) General PC
(c) Check and AID conv.
(b) Window comparator
646
(S bit AID
conversion)
External MPX
------,
,..----.---,
(Addressed at MI=l)
COMMON
CH2. ADDRESS
PC=l SET
(Programmable
Voltage
Comparison)
COMPIN
ADU
(NOTE)
R/W
CS I
Au
CS o
VMA
HD46508
AOU
H06S00
MPU
Ao
AI
0 0 -0 7
AilS
+5V
IRQ
647
Alo
AIW
AI.
Signal
Source
r====8=
CSt CS o
H046508
AOU
AS o
AS.
Alas
Ao
A.
A u -A 2
Ao
H06800
Aa
MPU
0 0 -0,
5v
COMMON
iim
I-- +
COMPIN
CLK
I-- f -
GAINSEL AEF(+)
~RErl
I
I
I
{ CLOCK
Alo
E
A/W
All
CS I
Signal
Source
I
I
CSo
H046508
AOU
I
I
Lf1t
Alas
Ao
A
AS o
AS.
0 0 -0,
r-------.,
i
I
PA
I
I
~ _______ j
iim
OOMMON
COMPIN
CLK
GAINSEL AEF(+)
REr I
SEE
GAIN SEL
USAGE
648
4~
+5V
0- ----i
AEF
HD146818-------------RTC
- PRELIMINARY-
HD146818P
(DP-24)
FEATURES
Time-of-Day Clock and Calendar
Counts Seconds, Minutes, and Hours of the Day
Counts Days of Week, Date, Month, and Year
Binary or BCD Representation of Time, Calendar, and Alarm
12- or 24 Hour Clock with AM and PM in 12-Hour Mode
Automatic End of Month Recognition
Automatic Leap Year Compensation
Interfaced with Software as 64 RAM Locations
14 Bytes of Clock and Control Register
50 Bytes of General Purpose RAM
Three Interrupt are Separately Software Maskable and Testable
Time-of-Day Alarm, Once-per-Second to Once-per-Day
Periodic Rates from 30.51ls to 500ms
End-of-Clock Update Cycle
Programmable Square-Wave Output Signal
Three Time Base Input Options
4.194304 MHz
1.048576 MHz
32.768 kHz
Clock Output May be used as Microprocessor Clock Input
At Time Base Frequency +4 or + 1
Multiplexed Bus Interface Circuit of HD6801, HD6301 and
8085
Low-Power, High-Speed, High-Density CMOS
Motorola MC146818 Compatible
PIN ARRANGEMENT
NC
VCC
SQW
PS
CKOUT
AD,
CKFS
iRQ
A~
OS
NC
AD.
Riw
AD,
AS
Vss
(Top View)
Value
Unit
-0_3 - +7.0
I nput Voltage
VCC *
V in *
Operating Temperature
Topr
o -+70
Storage Temperature
T stg
-55 - +150
Item
Supply Voltage
-0.3 - +7.0
(NOTE)
Permanent LSI damage may occur if maximum rating are exceeded. Normal operation should be under
recomended operating condition. If these conditions are exceeded. it could affect reliability of LSI.
~AI'\
c
c
HD148818-------------------------------------------------------
typ
max
Unit
Vee
V 1L
4.5
5.0
5.5
-0.3
0.7
Topr
Vee- 1.O
0
Vee
70
Symbol
min
*
*
V 1H *
25
ELECTRICAL CHARACTERISTICS
DC CHARACTERISTICS (Vee 5.0V 10%, Vss = OV, Ta = 0 -+70 C, unless otherwise noted.)
Symbol
Item
A~-AD"
R
Test Condition
CE, AS,
, OS, CKFS, PS
V 1H
RES
OSCI
A~ -AD" CE, AS,
V 1L
RES
OSC~E, AS, R/W,
OS, R
, CKFS, PS
max
Vee
Vee- 1.O
Vee- 1.O
Vee
-0.3
0.7
2.5
p.A
10
p.A
10
p.A
-0.3
Ilinl
ADo-AD,
IITSd
IRa
I LOH
ADo-AD,
Output "High" Voltage
SaW,CKOUT
ADo-AD,
ADo-AD,
CKOUT
IOH =-1.6mA
4.1
IOH <-10p.A
Vee- 0 .1
0.5
12.5
pF
12.5
pF
12.5
pF
10
300
500
10
60
100
IOL = 1.6 mA
IOL = 1.6 mA
C in
Output Capacitance
Cout
Supply Current
(MPU Read/Write
operating)
Crystal
Oscilla
Supply Current tion
(MPU not operating)
fose = 4 MHz
Supply Current
(MPU Read/Write
operating)
fosc = 4 MHz
Supply Current
(MPU not operating)
= 1 MHz
fosc = 32 kHz
fosc = 4 MHz
Icc *
fosc = 1 MHz
fosc = 32 kHz
fosc = 1 MHz
External
Clock
fosc = 32 kHz
fosc = 4 MHz
0.8
ADo-AD,
fosc
0.8
IOL = 1.6 mA
VOL
IRa, saw
I nput Capacitance
Vee
Unit
V OH
SaW,CKOUT
typ
Vee- 2 .0
-0.3
OSCI
Input Leakage Current
min
Icc *
fosc = 1 MHz
fosc = 32 kHz
V in = OV
Ta = 25C
f = 1 MHz
Vee = 5.0V
saw: disable
CKOUT = fosc
(No Load)
tCYC = 1p.s
Circuit: Fig. 10
Parameter:
Table 1
Vcc = 5.0V
saw: disable
CKOUT = fosc
(No Load)
OSC 2 : open
tcyc = lp.s
Circuit: Fig. 15
650
mA
5
5
rnA
pA
mA
mA
pA
--------------------------------------------------------HD148818
AC CHARACTERISTICS (Vee
BUS TIMING
Item
Symbol
min
typ
max
953
tcyC
PW ASH
100
Cycle Time
tASO
40
DS Rise Time
tosr
DS Fa'II Time
tOSf
PW OSH
325
PW OSL
300
tASOS
tAS1
15
tAS2
55
tAH
10
AS Rise Time
AS Fall Time
tASr
t ASf
.,
tASL
90
50
tosw
tOHW
tOOR
tOHR
10
Symbol
min
tAHL
20
195
30
Unit
ns
I
I
ns
ns
I
30 _.ns
---ns
30
ns
30
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
220
ns
ns
typ
max
Unit
100
1000
Oscillator Startup
tRC
ms
tRwL
5.0
tRLH
5.0
J.1.s
tPWL
5.0
J.1.s
tpLH
5.0
J.1.s
tlRoS
2.0
J.1.s
tlRR
2.0
J.1.S
tVRTO
2.0
J.1.s
32 kHz
J.1.s
HD146818P (X type)
~---------------T----~
2B2
(
HD146818P
JAPAN
Please set "0" to DSE bit (Daylight Saving Enable bit) on initializing the control register B.
DSE = "1" is prohibited.
""illl~Vnl
HD148818------------------------------------------------------
~~
AS
OS
-tASOSVIH
... VIL
...,~
eye
I--PWASH_
r-tAS.
tASO
--- "'1
...,/
VIL
tos.
I---
hS!
~ VIH
~\
..l
VIL
PW OSH
PWOSL
:K
-
~ VIH
~VIL
tAS2
lAsl
f--
f- tAM
,(
AOu- AD;
(Write )
AD7
(Re ad)
tAHL
tOHW
f4--tosw-
VIH
"'~
'~VIL
.,1(
tASL
J~VIH
'\
VII..
!--
VIL -'t-
tASL
r-
VIH
'I
\ ... VIL
tAHL
f---
I--
~tOOR-
}~VOH
\.
/
I
(NOTE)
VIL - O.7V
VOLe O.5V
652
---
..l\
I{
tOHR
------------------------------------------------------HD146818
t eye
VIH
I/~
ALE
(AS pin)
RO
WR
PWASH
tAS;;-
tAS.
VIL
I--
J~
(OS pin )
I\~
t ASOS
tAS!
I~
KV'H
PWOSH
~ V1L
tASD
PWOSL
Vj
(R/Wp in)
tOOR
CE
-I-
tASt I - r-
r--
tAH
VIH.\
V 1L oJ ...
t ASL
tAHL
I--ADo-A D7
/~
tOHR
r--
f--",,",VIH
~~OH
,,~
VVIL
YvDL
(NOTE)
V1H
VIL
= VOH = Vee-2.OV
= O.7V,
VOL = O.SV
teyc
ALE
tASO
RO
PWASH
-tAS.
VIL
r-
~tASf
(OS pin )
tASOS
tASD
V1H
WR
(AS pin)
;\IH
,...
J
~f\
PWOSH
VILj
t ASt
(R;"Wp in)
PW OSL
tAH
VIH,\
V 1L
I---
If
...,~
tOHW
tAHL
f---tosw-
tASL
ADo-A D7
/~
3,V 1H
"\~
VV 1L
/f-
~IH
"\r
..,VvIL
(NOTE)
653
t--
HD148818--------------------------------------------------------
~----------tR~----------~
os
""=1_
tIROS--j
IRQ _ _
(NOTE)
------'~
IRQ
VOH
---------
(NOTE)
VIL"'O.8V
VOH"' VCC-2.0V
Vee
--O-v--
I~----------~~~~-----------------SV
t~H
----.j
PS ________________J
"1"
r-
"I'"
, _o_. ____~---------~I~_,,~o_,,________~------
VR_T_B_i_t_ _ _ _ _ _ _ _ _ _
(NOTE)
VIH - Vcc-2.0V
VIL -O.7V
The VRT bit is set to a "1" by reading control register #0. There is no additional way to clear the VRT bit.
Vee
(NOTE)
654
VIH - Vcc-1.OV
---------------------------------------------------------HD146818
S.OV
5.0V
3kn
Test Terminal
Test Terminal
Diode
1S2074
Of-------t...
100pF
@ or equiv.
C = 130pF
RL = 2k.l1
R = 2.SSk.l1
~
~~ PHZ
Clock
Output
Tkn-~R~ I
OSC I
osc
Input/Osc
~j
+32
~
Vss
y rM
I
os; -
::)
Clock/
Calendar
Update
it'"
BCD/
Binary
Increment
AS; -
<X>
~.
32
i 11l
Square
Wave
Out
~
v
Bus
Interface
32
+2
R/Wi___..
~ J ~.
CKFS
Divider
Control
Vee
+ 32
CKOUT
.A
'"
rr
v
Registers 4 Bytes
Clock, Alarm,
Calendar RAM
(10 Bytes)
User RAM
(SO Bytes)
"v
Figure 9 Block Diagram
~I - saw
,---
RES
- - PS
Paramete
Rs
Rf
HD146818
150 kn
33 pF
33pF
150kn
22 pF
22 pF
Cin
Cout
CL
CI
(NOTE)
80 n (max)
700n (max)
32.768 kHz
150kn
5.6Mn
15 pF
33 pF
33 pF
40 kn (max)
(2) Pin 3 signal line should be wired apart from pin 4 signal
line as much as possible. Don't wire them in parallel, or
normal oscillation may be disturbed when this signal is
feedbacked to OSC I .
(3) A signal line or a power source line must not cross or go
near the oscillation circuit line as shown in the right fIgure
to prevent the induction from these lines and perform the
correct oscillation. The resistance among aSCI, asc 2 and
other pins should be over 10Mn.
The following design must be avoided.
HD146818
HD146818
656
------------------------------------------------------HD148818
H0146818
Pin Signal.
AS
ALE
Figure 12 shows the bus control circuit. This circuit automatically selects the processor type by using AS/ ASE to latch
the state of DS/RD pin. Since DS is always "Low" and RD is
always "High during AS/ALE, the latch automatically indicates
which processor type is connected.
DS.E.or~2
R/W
8085
Internal
Signals
Bus
6801
Bus
OS
Read Enable
Rfiii
Write Enable
ADDRESS MAP
The processor program obtains time and calendar information by reading the appropriate locations. The program
0
00
Seconds
00
Sec Alarm
01
Minutes
02
Min Alarm
03
Hours
04
Hr Alarm
05
Day of Wk
06
Date of Mo
07
Month
08
14
Bytes
13
00
14
50
Bytes
User
RAM
63
Year
09
Register A
0A
Register B
0B
Register C
0C
Register~
0o
Binary
or BCD
Contents
Range
Decimal
Range
Example*
BCD Data Mode
Binary
Data Mode
BCD
Data Mode
21
Seconds
0-59
$00-$3B
$00-$59
15
Seconds Alarm
0-59
$00-$3B
15
21
Minutes
0-59
$00-$3B
$00-$59
$00-$59
3A
58
Minutes Alarm
0-59
$00-$59
$01-$12 (AM) and
$81 -$92 (PM)
58
1-12
$00-$3B
$01-$OC (AM) and
$81-$8C (PM)
3A
Hours
(12 Hour Mode)
05
05
Hours
(24 Hour Mode)
0-23
$00-$17
$00-$23
05
05
Hours Alarm
(12 Hour Mode)
1-12
05
05
Hours Alarm
(24 Hour Mode)
0-23
$00-$17
$00-$23
05
05
1-7
$01 -$07
$01-$07
05
05
Function
1-31
$01-$1F
$01-$31
OF
Month
1-12
$Ol-$OC
$01-$12
02
15
02
Year
0-99
$00-$63
$00-$99
4F
79
INTERRUPTS
The RTC plus RAM includes three separate fully automatic
sources of interrupts to the processor. The alarm interrupt
may be programmed to occur at rates from once-per-second
to one-a-day. The periodic interrupt may be selected for rates
from half-a-second to 30.5 17 J).S. The update~nded interrupt
may be used to indicate to the program that an up-date cycle
is completed. Each of these independent interrupt conditions
are described in greater detail in other sections.
The processor program selects which interrupts, if any, it
wishes to receive. Three bits in Register B enable the three
interrupts. Writing a "1" to a interrupt~nable bit permits
that interrupt to be initiated when the event occurs. A "0" in
the I interrupt~nable bit prohibits the IRQ pin from being
asserted due to the interrupt cause.
If an interru...e!...flag is already set when the interrupt becomes
enabled, the IRQ pin is immediately activated, though the
interrupt initiating the event may have occurred much earlier.
Thus, there are cases where the program should clear such
658
----------------------------------------------------------HD146818
earlier initiated interrupts before first enabling new interrupts.
When an interrupt event occurs a flag bit is set to a "1" in
Register C. Each of the three interrupt sources have separate
flag bits in Register C, which are set independent of the state
of the corresponding enable bits in Register B. The flag bit
may be used with or without enabling the corresponding enable
bits.
In the software scanned case, the program does not enable
the interrupt. The "interrupt" flag bit becomes a status bit,
which the software interrogates, when it wishes. When the
software detects that the flag is set, it is an indication to software that the "interrupt" event occurred since the bit was
last read.
However, there is one precaution. The flag bits in Register
C are cleared (record of the interrupt event is erased) when
Register C is read. Oouble latching is included with Register
C so the bits which are set are stable throughout the read
cycle. All bits which are high when read by the program are
cleared, and new interrupts (on any bits) are held until after
the read cycle. One, two, or three flag bits may be found to
be set when Register C is read. The program should inspect
aU utilized flag bits every time Register C is read to insure that
no interrupts are lost.
The second flag bit usage method is with fully enabled
interrupts. When an interrupt-flag bit is set and the corresponding inter~~nable bit is also set, the IRQ pin is asserted
"Low". IRQ is asserted as long as at least one of the three
interrupt sources has its flag and enable bits both set. The
A.
Divider Control
The. divider-control bits have three uses, as shown in Table
3. Three usable operating time bases may be selected (4.194304
MHz, 1.048576 MHz, or 32.768 kHz). The divider chain may
be held reset, which allows precision setting of the time. When
the divider is changed from reset to an operating time base,
the first update cycle is., one second later. The divider-control
bits are also used to facilitate testing the H0146818.
Divider Bits
Register A
Operation
Mode
Divider
Reset
Bypass First
N-Divider Bits
DV2
DV1
ova
a
a
Yes
N=a
Yes
N=2
32.768 kHz
a
a
a
N=7
a
a
Yes
Any
No
Yes
Any
No
Yes
4.194304 MHz
1.048576 MHz
(NOTE) Other combinations of divider bits are used for test purposes only.
659
RS3
RS2
RS1
RSO
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
UPDATE CYCLE
32.768 kHz
Time Base
Periodic
Interrupt Rate
tpi
None
3.90625 ms
7.8125 ms
122.070 JlS
244.141 Jls
488.281 Jls
976.562 JlS
1.953125 ms
3.90625 ms
7.8125 ms
15.625 ms
31.25 ms
62.5 ms
125 ms
250ms
500ms
saw Output
Frequency
None
256 Hz
128 Hz
8.192 kHz
4.096 kHz
2.048 kHz
1.024 kHz
512 Hz
256Hz
128 Hz
64 Hz
32 Hz
16 Hz
8 Hz
4 Hz
2 Hz
every update cycle which indicates that over 999 ms are available to read valid time and date information. During this time
a display could be updated or the information could be transfered to continuously available RAM. Before leaving the interrupt service routine, the IRQF bit in Register C should be
cleared.
The second method uses the update-in-progress bit (UIP)
in Register A to determine if the update cycle is in progress
or not. The UIP bit will pulse once-per-second. Statistically,
the UIP bit will indicate that time and date information is
unavailable once every 2032 attempts. After the UIP bit goes
"1", the update cycle begins 244 JlS later. Therefore, if a "0"
is read on the UIP bit, the user has at least 244 JlS before the
time/calendar data will be changed. If a "1" is read in the
UIP bit, the time/calendar data may not be valid. The user
should avoid interrupt service routines that would cause the
time needed to read valid time/calendar data to exceed 244 Jls.
Tne third method uses a periodic interrupt to determine if
an update cycle is in progress. The UIP bit in Register A is set
"1" between the setting of the PF bit in Register C (see Figure
14) Periodic interrupts that occur at a rate of greater than
tBue + tue allow valid time and date information to be read
at each occurrence of the periodic interrupt. The reads should
be completed within (tPI + 2) + tBue to insure that data is
not read during the update cycle.
POWER-DOWN CONSIDERATIONS
660
-----------------------------------------------------HD148818
consumption, and ensure hardware reliability.
The chip enable (CE) pin controls all bus inputs (R/W, OS,
AS, ADo"'" AD,). CE. when negated, disallows any unintended
modification of the RTC data by the bus. CE also reduces
power consumption by reducing the number of transitions
seen internally.
Power consumption may be further reduced by removing
UIP bit in
,----,
UF bit in
Register C
!---tPI + 2---1
PF bit in
Register C
tp'-------t-ll
il1I1m
tP1 + 2 --!vuw _ _
~--------~
hmm
tPI
PeriodiC Interrupt Time Interval (500 ms, 250ms, 125 ms, 62.5 ms, etc.)
tue Update Cycle Time (248",. or 1984",s)
taue Delay Time Before Update Cycle (244 ",5)
SIGNAL DESCRIPTIONS
Vee, Vss
DC power is provided to the part on these two pins, Vcc
being the most positive voltage. The minimum and maximum
voltages are listed in the Electrical Characteristics tables.
OSC 1, OSC 2
vee
Optional
(Vee-1.OV)
4.194304 MHz
2
1.048576 MHz ---~.......---~... OSC I
or
32.768 kHz
(Open)
OSC 2
M
..2-
HD146818
nIDDV...
..
Time Base
(OSCd
Frequency
Clock Frequency
Select Pin
(CKFS)
Clock Frequency
Output Pin
(CKOUT)
4.194304 MHz
4.194304 MHz
1.048576 MHz
1.048576 MHz
32.768 kHz
32.768 kHz
"High"
"Low"
"High"
"Low"
"High"
"Low"
4.194304 MHz
1.048576 MHz
1.048576 MHz
262.144 kHz
32.768 kHz
8.192 kHz
The bus control circuit treats the R/W pin in one of two
ways. When 6801 family type processor is connected, R/W is
a level which indicates whether the current cycle is a read or
write. A read cycle is indicated with a "High" level on Rfil
while OS is "High", whereas a write cycle is a "Low" on R/W
during OS
The second interpretation of R/W is as a negative write
pulse, WR, MEMW, and I/OW from 8085 type processors. This
circuit in this mode gives R/W pin the same meaning as the
write (W) pulse on many generic RAMs.
The chip-enable (c'E) signal must be asserted ("Lo~
for a bus cycle in which the H0146818 is to be accessed. CE
is not latched and must be stable during OS and AS (in the
6801 case) and during RO and WR (in the 8085 case). Bus
cycles which take place without asserting CE cause no actions
to take place within the HDl46818. When CE is "High", the
multiplexed bus output is in a high-impedance state.
When CE is "High", all address, data, OS, and R/W inputs
from the processor are disconnected within the H0146818.
This permits the H0146818 to be isolated from a powereddown processor. When CE is held "High", an unpowered device
cannot receive power through the input pins from the realtime clock power source. Battery power consumption can thus
be reduced by using a pullup resistor or active clamp on CE
when the main power is off.
The IRQ pin is an active "Low" output of the HOl46818
that may be used as an interrupt input to a processor. The IRQ
output remains "Low" as long as the status bit causing the
interrupt is present and the corresponding interrupt-enable bit
is set. To clear the IRQ pin, the processor program normally
reads Register C. The RES pin also clears pending interrupts.
When no interrupt conditions are present, the IRQ level is
in the high-impedance state. Multiple interrupting devices
may thus be connected to an IRQ bus with one pullup at the
processor.
The RES pin does not affect the clock, calendar, or RAM
functions. On powerup, the RES pin must be held "Low" for
the specified time, tRLH, in order to allow the power supply
to stabilize, Figure 16 shows a typical representation of the
RES pin circuit.
When RES is "Low" the following occurs:
a) Periodic Interrupt Enable (PIE) bit is cleared to "0".
b) Alarm Interrupt Enable (AlE) bit is cleared to "0".
c) Update ended interrupt Enable (UIE) bit is cleared to
"0".
d) Update ended Interrupt Flag (UF) bit is cleared to "0".
e) Interrupt Request status Flag (IRQF) bit is cleared to
"0".
f) Periodic Interrupt Flag (PF) bit is cleared to "0".
g) Alarm Interrupt Flag (AF) bit is cleared to "0".
h) IRQ pin is in high-impedance state, and
i) Square Wave output Enable (SQWE) bit is cleared to "0".
662
---------------------------------------------------------HD146818
During powerup, the PS pin must be externally held "Low"
for the specified time, tpLH. As power is applied the VRT bit
remain "Low" indicating that the contents of the RAM, time
System
Vee - -....
--.M---....--......1.0 k
Battery
Backup
registers, and calendar are not guaranteed. When normal operation commences PS should be permitted to go "High". Figure
17 shows a typical circuit connection for the power-sense pin.
01
System _ _~----4........- - - - -....- - - J _ .___ Battery
Vee
B~~p
Vee
Vee
H0146818
H0146818
PS~---.
(NOTE)
0.005.,
0.005.'
(NOTE)
REGISTERS
The HDI46818 has four registers which are accessible to the
processor program. The four registers are also fully accessible during the update cycle.
OV2, OV1, OVO - Three bits are used to permit the program
to select various conditions of the 22-stage divider chain. The
divider selection bits identify which of the three time-base
frequencies is in use. Table 3 shows that time bases of 4.194304
MHz, 1.048576 MHz, and 32.768 kHz may be used. The divider
selection bits are also used to reset the divider chain. When the
time/calendar is first initialized, the program may start the
divider at the precise time stored in the RAM. When the divider
reset is removed the first update cycle begins one second later.
These three read/write bits are never modified by the RTC and
are not affected by RES.
Register A ($OA)
MSB
,......-..,.----r--~---r---r--....,....-
LSB
___r_____.
Read/Write
Register
except UIP
~-~-~---~--~--~-~-~~~
UIP - The update in progress (UIP) bit is a status flag that may
be monitored by the program. When UIP is a "1" the update
cycle is in progress or will soon begin. When UIP is a "0"
the update cycle is not in progress and will not be for at least
244 IlS (for all time bases). This is detailed in Table 6. The
time, calendar, and alarm information in RAM is fully available
to the program when the UIP bit is zero - it is not in transition.
The UIP bit is a read-only bit, and is not affected by Reset.
Writing the SET bit in Register B to a "I" inhibit any update
cycle and then clear the UIP status bit.
RS3, RS2, RS1, RSO - The four rate selection bits select one
of 15 taps on the 22-stage divider, or disable the divider output.
The tap selected may be used to generate an output square
wave (SQW pin) and/or a periodic interrupt. The program
may do one of the following: 1) enable the interrupt with the
PIE bit, 2) enable the SQW output pin with the SQWE bit, 3)
enable both at the same time at the same rate, or 4) enable
neither. Table 4 lists the periodic interrupt rates and the squarewave frequencies that may be chosen with the RS bits. These
four bits are read/write bits which are not affected by RES and
are never changed by the RTC.
Time Base
(OSC.)
Update Cycle
Time (tud
Minimum Time
Before Update
Cycle (tBud
1
1
1
0
0
0
4.194304 MHz
1.048576 MHz
32.768 kHz
4.194304 MHz
1.048576 MHz
32.768 kHz
2481ls
2481ls
19841ls
2441ls
2441ls
244 1ls
MSB
LSB
Read/Write
Register
SET - When the SET bit is a "0", the update cycle functions
normally by advancing the counts once-per-second. When
the SET bit is written to a "1", any update cycle in progress is
aborted and the program may initialize the time and calendar
HD146818----------------------------------~---------------------
MSB
~=:=:=T=~I=:=6=~I==~==:I=~=o==~=:=3=~I==:2==:I=b=~==~1=:=O~IR'~~~
VRT - The valid RAM and time (VRT) bit indicates the condition of the contents of the RAM, provided the power sense
(PS) pin is satisfactorily connected. A "0" appears in the
VRT bit when the power-sense pin is "Low". The processor
program can set the VRT bit when the time and calendar are
initialized to indicate that the RAM and time are valid. The
VRT is a read/only bit which is not modified by the RES pin.
The VRT bit can only be set by reading the Register D.
Register C ($DC)
MSB
LSB
LSB
Read-Only
Register
664
ADVANCED INFORMATION
FEATURES
High performance, low power CMOS process
technology
Two Bi-directional 8-Bit Peripheral Data Bus for interface to Peripheral devices
Two Programmable Control Registers
Two Programmable Direction Registers
Four Individually-Controlled Interrupt Input Lines: Two
Usable as Peripheral Control Outputs
Handshake Control Logic for Input and Output Peripheral Operation
High-Impedance 3-State and Direct Transistor Drive
Peripheral Lines
Program Controlled Interrupt and Interrupt Disable
Capability
CMOS Drive Capability on Side A Peripheral Lines
Two TTL Drive Capability on All A and B Side Buffers
Compatible with MC6821, MC68A21 and MC68B21
(DP-40)
L - - -_ _ _ _ _ _ _ _ _ _ _ _
PIN ARRANGEMENT
CA,
CA,
iRCiA
iRQij
BLOCK DIAGRAM
~ 384-------------------------~:::::::l
40
CAl
39
CA,
AS.
AS,
ReS
D.
D,
D,
D,
D,
D.
D.
D,
D,
33
32
31
30
29
28
27
28
0,
0,
D.
D.
D.
D.
6
PA,
PA.
0,
PAt
PA,
PA,
cs,
CS.
CS.
10 PS,
11 PBI
cs,
CS,
CS,
RS,
RS,
RiW
e
RES
_ 22
24
23
36
35
21
25
34
12
13
14
15
16
17
-.--------------~
P8,
P8,
PB.
P8.
PS,
PS,
(Top View)
18 C8,
~ 374-------------------------1-~::~~
19 CS,
665
Alii
HD6340, HD63A40,----,-----HD63B40
CMOS PTM (Programmable Timer Module)
The H06340 is a programmable subsystem component of the
HMCS6800 family designed to provide variable system time
intervals.
The H06340 has three 16-bit binary counters, three corresponding control registers and a status register. These counters are
under software control and may be used to cause system interrupts
and/ or generate output signals. The H06340 may be utilized for
such tasks as frequency measurements, event counting, interval
measuring and similar tasks. The device may be used for square
wave generation, gated delay signals, single pulses of controlled
duration, and pulse width modulation as well as system interrupts.
ADVANCED INFORMATION
FEATURES
High Performance, Low Power CMOS Process Technology
Operates from a Single 5 Volt Power Supply
Single System Clock Required (E)
Selectable Prescaler on Timer 3 Capable of 4 MHz for
the HD6840, 6 MHz for the HD68A40 and 8 MHz for the
HD68B40
Programmable Interrupts (IRQ) Output to MPU
Readable Down Counter Indicates Counts to Go until"
Time-Out
Selectable Gating for Frequency or Pulse-Width
Comparison
RES Input
Three Asynchronous External Clock and Gate/Trigger
Inputs Internally Synchronized
Three Maskable Outputs
Compatible with MC6840, MC68A40 and MC68B40
PIN ARRANGEMENT
BLOCK DIAGRAM
Vss
CI
01
G2
02
C2
G3
03
G.
C3
RES
IRQ
RSo
RSI
HD6340
o.
05
D.
07
E
CS I
CSo
Vee 14
(Top View)
666
Do
01
02
03
ADVANCED INFORMATION
FEATURES
High Performance, Low Power CMOS Process
Technology
Serial/Parallel Conversion of Data
Eight and Nine-bit Transmission
Insertion and Deleting of Start and Stop Bit
Optional Even and Odd Parity
Parity, Overrun and Framing Error Checking
Peripheral/Modem Control Functions (Clear to Send
CTS, Request to Send RTS, Data Carrier Detect (DCD)
Optional.;- 1, .;- 16, and .;- 64 Clock Modes
Up to 500kbps Transmission
Programmable Control Register
Compatible with MC6850, MC68A50 and MC68B50
(DP-24)
PIN ARRANGEMENT
BLOCK DIAGRAM
Tx ClK 4
14
RM
13
CSt
.~
RS
~o
Tx Data
f1
IRQ
24 CTS
D.
22
21
03
03
D.
Os
0,
D~
Tx Data
HD6350
CS.
CSl
20
19
18
17
16
15
IRQ
23 DCD
RTS
(Top View)
RxeLK
Ax Data
3----------------------~
667
668
16-BIT MICROCOMPUTE
HMCS68000 MULTI-CHI
SERlE
669
670
MPU
HD68000-4, HD68000-6,
HD68000-B, HD68000-10
(DC64)
PIN ARRANGEMENT
FEATURES
32-Bit Data and Address Registers
16 Megabyte Direct Addressing Range
56 Powerful Instruction Types
Operations of Five Main Data Types
Memory Mapped 1/0
14 Addressing Modes
Compatible with MC6BOOOL4, MC6BOOOL6, MC68000LB,
and MC6BOOOL 10
D.
D.
D,
D.
0,
0 1
D"
D..
Du
Du
0"
Vss
BGACK I
iml
PROGRAMMING MODEL
A"
Au
A"
H068000
31
Vee
A,.
0
DO
01
A"
All
02
Au
A..
03 Eight
Data
04 Registers
05
Au
AI.
I
07
FC.
AO
AI
A1
A,
A,
A2 Seven
Address
A3 Registers
A4
87
~--------------~
(Top View)
0
User Byte
A.
A,
A.
As
A5
15
A.
A.
A6
ISystem Byte:
A"
AI.
FC I
31
Au
Au
06
Status
Register
671
..
Item
Symbol
Supply Voltage
Input Voltage
Vee
V ln
Topr
Storage Temperature
Tit\!
Value
Unit
-0.3 -+7.0
-0.3-+7.0
0-+70
c
c
-5S - +1S0
Item
Supply Voltage
Symbol
min
typ
max
Unit
Vee
V IH *
V IL *
4.75
5.0
5.25
2.0
-0.3
Vee
0.8
25
70
Input Voltage
Operating Temperature
T opr
ELECTRICAL CHARACTERISTICS
DC CHARACTERISTICS (Vee 5V 5%, VSS OV, Ta 0"" +70C, Fig. 1, 2, 3, unlel' otherwise noted.)
Symbol
Item
Test Condition
min
typ
max
Unit
V IH
2.0
V IL
Vss-O3
Vee
0.8
lin
@5.25V
HALT. 'RES
Three-5tate (Off State)
I nput Current
AS. A,-A2to'i0-DIS.
FCo - FC2 0 RIW. UDS'.
VMA
ITSI
@2.4V/O.4V
V OH
IOH .. -400p,A
AS.A.-A2~G.~~
FCo-FC2. LD R
VMA
E*
UD
V ee -O 75
HALT
Output "Low" Voltage
IOL 1.6mA
VOL
~.
2.4
IOL -S.3mA
MA
Power Dissipation
Capacitance (Package Type Dependent)
Po
f =8MHz
Cln
2.5
p,A
20
20
p.A
O.S
O.S
O.S
O.S
1.S
10.0
20.0
pF
+5V
Test
POint
910n
RES
lS2074@
or
Equivalent
~7OpF
Figure 1 RES Test Load
rm .
672
Item
Symbol
Test
Condition
4MHz
6 MHz
8MHz
10MHz
H068000-4
H068000-6
H06S000-S
H06S000-10
min
min
min
max
max
max
min
max
Unit
Frequency of Operation
2.0
4.0
2.0
6.0
2.0
S.O
2.0
10.0
MHz
Clock Period
tcyc
250
500
167
500
125
500
100
500
ns
(2
tCl
115
250
75
250
55
250
45
250
ns
tCH
115
250
75
250
55
250
45
250
ns
(4
tCf
10
10
10
ns
SO
70
SO
70
100
80
10
10
120
1)
tCr
(6
tClAV
tCHFCV
(j)
tCHAZx
tCHAZn
Clock High to
tCHSlx
SO
70
~O)
Clock
tCHSln
tAVSl
55
35
tFCVSl
SO
70
tClSH
(lf51
90
SO
5)
C~
<1' ~
1 ~
1111
_Q4
,5
(~4 ~
OS High
10
90
90
ns
ns
60
ns
ns
ns
60
55
ns
0
50
ns
60
70
55
ns
20
ns
195
105
ns
150
30
tSHAZ
60
30
tSl
535
40
337
240
2S5
170
2S5
1S0
10
55
70
10
115
20
95
ns
ns
ns
1 11
{6
Clock High to
tCHSZ
120
100
80
70
ns
(1
tSHRH
60
50
40
20
ns
(~
tCHRHx
90
80
70
60
ns
9)
tCHRHn
ns
tCHRl
90
80
70
60
ns
tAVRl
45
25
60
50
tRlSl
200
140
SO
50
ns
SO
tFCVRl
20
FC Valid to Rm Low
tClDO
90
SO
70
55
ns
iI
tSHDO
60
40
30
tDOSl
55
35
30
20
ns
IJI
p
tDICl
30
25
15
20
15
ns
tSHDAH
240
160
120
90
ns
tSHDI
tSHBEH
ns
tDAlDI
180
120
90
65
ns
tRHrf
200
200
200
200
ns
tCHGl
90
80
70
60
ns
tCHGH
90
80
70
60
ns
BR Low to BG Low
tBRlGl
1.5
3.0
1.5
3.0
1.5
3.0
1.5
3.0
Clk. Per.
BR High to BG High
tBRHGH
1.5
3.0
1.5
3.0
1.5
3.0
1.5
3.0
Clk. Per.
tGAlGH
1.5
3.0
1.5
3.0
1.5
3.0
1.5
3.0
Clk.Per.
tGlZ
120
100
80
70
ns
~!
BG Width High
tGH
1.5
Clk. Per.
1.5
1.5
tBGl
1.5
Clk. Per.
20
50
ns
ns
35
1.5
BGACK Width
1.5
II
10
Clk. Per.
\&
I'll
~1 ~
,6
Clock High to
1m' Low
Clock High to
m High
tSH
Fig.4 - 7
70
1.5
tASI
30
25
tSElDAl
50
50
tCHDO
tRlDO
55
tHRPW
10
1.5
20
50
30
20
10
10
ns
ns
ns
ns
ns
ns
ns
(to be continued)
673
Item
Number
Symbol
Test
Condition
4MHz
6MHz
8MHz
10MHz
HD68000-4
HD68000-6
HD68000-B
HD68000-10
min
max
min
max
min
max
min
80
tCHRZ
120
100
tCLVML
90
80
tCLE
100
85
4~
tErf
25
25
tVMLEH
325
240
200
tSHVPH
240
160
tELAI
55
35
30
tELSI
-80
-80
E Width High
tEH
900
E Width Low
tEL
1400
tCIEHX
80
).4
tELO~Z
60
E Low to AS,
(NOTES) 1.
2.
3.
4.
5.
6.
OS Invalid
Fig. 45,46
600
450
900
700
80
40
-80
80
30
Unit
max
70
ns
70
ns
55
ns
25
ns
150
ns
120
90
ns
10
ns
70
70
25
-80
350
550
80
20
ns
ns
ns
ns
ns
For a loading capacitance of less than or equal to 50 picofarads, subtract 5 nanoseconds from the values given in these columns.
Actual value depends on clock period. _ _
If #4 7 is satisfied for both DT ACK and 8E R R, #48 may be 0 ns.
After VCC has been applied for 100 ms.
For the mask version 68000 #14 and #14A are one clock period less than the given number.
If the asynchronous setup time (#47) requirements are satisfied, the DTAcK low-to-data setup time (#31) requirement can be ignored.
The data must only satisfy the data-in to clock-low setup time (#27) for the following cycle.
~---------------tcyc------------~
tCr
674
t---CD51
@
31+--- ~ 50
ClK
It--
@- 1-"
~J~~
53
52
54
56
55
57
L rLr L--I\-
'--(j)
j~
~
~@
I--@
~W
~~
R/W
f-:"
"-I
I+-@
t+--@
f4-r
-
15
~@-~
~+--..
I - - ,-@
Asynchronous
Inputs
(Note 1)
f--@--
"
.~
~@
BERR/BR
(Note 2)
-+
~-r - - -
I+-@--
-,
I-@
@-~
Data In
I--@
j.--..
t-----------
~.,.
~--
i*-@-1
-----------------~
(NOTES) 1. Setup time for the asynchronous inputs BGACK, IPl o - IPl2 and VPA guarantees their recognition at the next falling edge of the clock.
2. SR need fall at this time only in order to insure being recognized at the end of this bus cycle.
3. Timing measurements are referenced to and from a low voltage of 0.8 volts and a high voltage of 2.0 volts, unless otherwise noted.
Figure 5
675
50
eLK
52
51
----:;,
-~
54
"' ~
'------J
57
56
55
K-./\-Jr--
-@
'-
r--
~@
.J~ .@
@..
.Jf-
-...
....
..
......
-~
I+- r-@
4-@-...
(J)--
I+-
-.
15
4-@~
...
.,
"""
"""
~:
1--
,~
It.
~~
-----
f--
-I(
'J
Data Out
~f-
I-@
@"
-----
R/iii
so
...-@
~H .... -.
--10
53
):
Asynchronous
Inputs
...
~
~
-...
I+-
f--@
@~@-+
I+--~
}r-
\ ..
f4--@
~~
J'r:'"-
(NOTE)
Timing measurements are referenced to and from a low voltage of 0.8 volts and a high voltage of 2.0 volts, unless otherwise noted.
676
Strobes
and R/W - - - - - - - - - - '
....
~-------4
~------4~------~
BGACK --~--------------------~~~______+-_~----~~--~~----------------------~---
14----@---~
@I4--.+o..---@
BG -------------------~~
ClK
(NOTES) 1. Setup time for the asynchronous inputs BERR, BGACK, BR, DTACK, IPlo -IPl 2 , and VPA guarantees their recognition at the
next falling edge of the clock.
2. Waveform measurements for all inputs and outputs are specified at: logic high = 2.0 volts, logic low =0.8 volts.
3. These waveforms should only be referenced in regard to the edge-to-edge measurement of the timing specifications. They are
not intended as a functional description of the input an output signals. Refer to other functional descriptions and their.. related
diagrams for device operation.
SIGNAL DESCRIPTION
The following paragraphs contain a brief description of the
input and output signals. A discussion of bus operation during
the various machine cycles and operations is also given.
SIGNAL DESCRIPTION
The input and output signals can be functionally organized
into the groups shown in Figure 8. The following paragraphs
provide a brief description of the signals and also a reference
(if applicable) to other paragraphs that contain more detail
about the function being performed.
;;V~CC~(2~),...r-------,Addres
GND~)
B~
ClK
Do-DIS
Processor {
Status
FC o
FC
FC,
HMCS6800{
Peripheral
Control
E
VMA
VPA
S'istem {
Control
RAk }
UDS
HD68000
icroprocesso
lDS
DT ACK
Bus
Control
BR
BG
B A
BERR
RES
IPl o
IPl 1
RAIT
iPL
Asynchronous
if
}
Bus
Arbitratibn
Control
Interrupt
Control
677
HD68000-4, HD88000-8, HD88000-8, H D 8 8 0 0 0 - 1 0 - - - - - - - - - - - Upper and Lower Data Strobes (UDS, LOS)
These signals control the data on the data bus, as shown
in Table 1. When the R/W line is high, the processor will read
from the data bus as indicated. When the R/W line is low, the
processor will write to the data bus as shown.
Table 1 Data Strobe Control of Data Bus
UDS
High
LOS
High
R/W
-
Low
Low
High
High
Low
High
Low
High
High
Low
Low
Low
High
Low
Low
Low
High
Low
08 - DIS
No valid data
Valid data bits
8-15
No valid data
Val id data bits
8 -15
Valid data bits
B -15
Valid data bits
0-7*
Valid data bits
8-15
0 0 - 0,
No valid data
Valid data bits
0-7
Valid data bits
0-7
No valid data
Valid data bits
0-7
Valid data bits
0-7
Valid data bits
8 -15*
678
devices that there is a valid address on the address bus and the
processor is synchronized to enable. This signal only responds
to a valid peripheral address (VPA) input which indicates that
the peripheral is a HMCS6800 family device.
PROCESSOR STATUS (FC o , Fe!, FC 2 )
These function code outputs indicate the state (user or
supervisor) and the cycle type currently being executed, as
shown in Table 2. The information indicated by the function
code outputs is valid whenever address strobe (AS) is active.
Table 2 Function Code Outputs
FC 2
Low
Low
Low
Low
High
High
High
High
FC!
Low
Low
High
High
Low
Low
High
High
Cycle Type
(Undefined, Reserved)
User Data
User Program
(Undefined, Reserved)
(Undefined, Reserved)
Superviser Data
Supervisor Program
Interrupt Acknowledge
FCo
Low
High
Low
High
Low
High
Low
High
CLOCK (CLK)
The clock input is a TTL-compatible signal that is internally
buffered for development of the internal clocks needed by the
processor. The clock input shall be a constant frequency.
SIGNAL SUMMARY
Table 3 is a summary of all the signals discussed in the
previous paragraphs.
Three State
Mnemonic
Input/Output
Address Bus
Al - A23
output
Active State
high
Data Bus
Do - DIS
AS
input/output
high
yes
output
low
yes
RM
output
read-high
write-low
yes
UDS, lDS
output
low
yes
DTACK
BR
input
low
input
low
no
no
BG
BGACK
IPl o , IPl I , IPl 2
output
low
no
input
low
no
input
low
no
BERR
input
RES
input/output
no
no*
HALT
E
input/output
output
VMA
output
lo~
low
low
high
low
low
high
high
Address Strobe
ReadIWrite
Upper and lower Data Strobes
Data Transfer J.l.cknowledge
Bus Request
Bus Grant
Bus Grant Acknowledge
Interrupt Priority level
Bus Error
Reset
Halt
Enable
Valid Memory Address
VPA
input
FCo,FC I ,FC 2
output
Clock
ClK
input
Power Input
Ground
Vcc
Vss
input
input
Open drain
yes
no*
no
yes
no
yes
no
OPERAND SIZE
BUS OPERATION
DATA REGISTERS
ADDRESS REGISTERS
STATUS REGISTER
System Byte
Interrupt
Mask
Zero
Overflow
Read Cycle
During a read cycle, the processor receives data from memory or a peripheral device. The processor reads bytes of data
in all cases. If the instruction specifies a word (or double word)
operation, the processor reads both bytes. When the instruction
specifies byte operation, the processor uses an internal Ao bit to
determine which byte to read and then issues the data strobe
required for that byte. For bytes operations, when the Ao bit
equals zero, the upper data strobe is issued. When the Ao bit
equals one, the lower data strobe is issued. When the data is
received, the processor correctly pOSitions it internally.
A word read cycle flow chart is given in Figure 11. A byte
read cycle flow chart is given in Figure 12. Read cycle timing is
given in Figure 13. Figure 14 details word and byte read cycle
operations. Refer to these illustrations during the following
detailed.
Carry
680
14
13
12
11
10
Byte 000000
8
7
6
WordlOOOOOO
Byte 000001
Word 000002
Byte 000002
Byte 000003
~
WOrd{FFFFE
Byte FFFFFE
Byte FFFFFF
15
14
13
SB
12
11
10
I nteger Data
1 Byte = 8 Bits
9
8
7
6
Byte 0
n+2
Bit Data
1 Byte = 8 Bits
4
3
2
0
n+1
Byte 1
LSBI
Byte 2
Byte 3
n+3
1 Word = 16 Bits
15
n+t
14
13
12
11
10
SB
0
n+1
Word 0
LSBI
Word 1
Word 2
n+4
15
14
MSB
13
12
11
10
n+3
n+5
High Order
I- - - Long Word 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Low Order
n+2
LSB
n+1
n+4
n+5
n+3
n+6
n+9
n+8
- - -Long Word 2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
n+11
n+10
15
14
MSB
I- - -
n+2
n+4
:::
13
12
11
10
Addresses
1 Address = 32 Bits
9
8
7
6
Address 0 - - - - - - - -
High Order
- - - - - - - - - - - - - - - - - - - - Low Order
LSB
- - Add,.., 1 - - - - - - - - - - - - - - - - - - - - - - - - - -
-.----1..
n+3
n+5
n+7
n+9
n+1
~_________________________________________________..J
n+11
12
Decimal Data
2 Binary Coded Decimal Digits = 1 Byte
11
10
9
8
7
6
5
4
BCD1
BCD4
LSD
BCD5
BCD3
n+1
BCD6
BCD7
n+3
682
BCD2
1)
2)
3)
4)
5)
SLAVE
Input Data
1) Decode Address
2) Place Data on Do -0 15
3) Assert Data Transfer Acknowledge
(DTACK)
Terminate Cycle
1) Remove Data from Do - 015
2) Negate DTACK
Terminate Cycle
1) Remove Data from Do - 0, or 0 8
2) Negate DTACK
015
50 51
Input Data
1) Decode Address
Acquire Data
1) Latch Data
2) Negate iJDS or IDS"
3) Negate AS
Acquire Data
1) Latch Data
2) Negate iJDS and I15S"
3) Negate AS
Figure 11
SLAVE
Address Device
1) Set RIW to Read
2) Place Function Code on FCo - FC2
3) Place Address on AI - Au
4) Assert Address Strobe (AS)
5) Assert Upper Data Strobe (UDS) and Lower Data Strobe (IDS) (based on Ao)
Address Device
Set R/W to Read
Place Function Code on FCo - FC 2
Place Address on AI - A 23
Assert Address Strobe (AS)
Assert Upper Data Strobe (UDS) or Lower
Data Strobe (D5S)
BUS MASTER
52 53 54 55 56 S7 50 51 52 53 54 55 56 57 50 S1 52 53 54
S5 S6 57
ClK
~~-------r~~-------r~~------------~~
_____________
~r-
______________rI
AI-Au
AS
UOS
lOS
1\
I
\
>-rr-
Ao*
I
I
R/W
OTACK
0 8 -015
Do -0 7
Fe o -FC 2
:J
<
(
>
:::>
::::x
+---
1\
<
>
<
>
+ --
;-
rx::=
----1
Write Cycle
684
BUS ARBITRATION
685
1)
2)
3)
4)
5)
6)
BUS MASTER
SLAVE
Address Device
Place Function Code on FC o - FC 2
Place Address on AI - An
Assert Address Strobe (AS)
Set R/iN to Write
Place Data on Do - 0 7 or D. - DIS (according
to Ao)
6) Assert Upper Data Strobe (UDS) or Lower
Data Strobe (C5S") (based on Ao)
1)
2)
3)
4)
5)
Address Device
Place Function Code on FC o - FC 2
Place Address on AI - An
Assert Address strobe (AID
Set R/W to Write
Place Data on Do - DIS
Assert Upper Data Strobe (UDS) and
lower Data Strobe ([i5S")
Input Data
1) Decode Address
2) Store Data on Do - 0 7 if D5S is asserted
Store Data on D. - 015 if 0l5S is asserted
3) Assert Data Transfer Acknowledge
(DTACK)
Input Data
1) Decode Address
2) Store Data on Do - 015
3) Assert Data Transfer Acknowledge
(GTACR')
I
1)
2)
3)
4)
SLAVE
1)
2)
3)
4)
Terminate Cycle
Terminate Cycle
1) Negate~
1) Negate
l5T'A'CR
~
Start Next Cycle
SO S1 52 53 54 55 56 57 SO S1 52 S3 54 55 S6 57 50 51 S2 53 S4
ClK
Ao
AS~
I
\,
LOS
RIWr-\
DTACK
D. -DIS
Do -0 7
FC o -FC 2
)
)
(
(
/\
I
)
)
:x
\
<
1- - - - Word Write -
UDS
--
/\
I
r-
rr
}-
>
>-
+ --
>
--1- - -
686
>r-
---I
1)
2)
3)
4)
5)
SLAVE
Address Device
Set R/W to Read
Place Function Code on FCo - FC.
Place Address or AI -A a
Assert Address Strobe (AS)
Assert Upper Data Strobe (UDS) or
Lower Data Strobe (LOS)
Input Data
1) Decode Address
2) Place Data on Do -0 7 or 0 8 - 015
3) Assert Data Transfer Acknowledge
(DTACK)
j
Acquire Data
1) Latch Data
2) Negate ~ or I1J'S
3) 5tart Data Modification
Terminate Cycle
1) Remove Data from Do - 0 7 or 0 8
2) Negate'DTA'CK
Input Data
1) Strobe Data on Do - 0 7 or 0 8 - 0 ..
2) Assert Data Transfer Acknowledge
(DTACK)
r
Terminate Output Transfer
1)
2)
3)
4)
015
Terminate Cycle
1) Negate DTACK
I
Start Next Cycle
/
/
\
UDS or LD5
R/W
DTACK
0 8 -DIS
FC o -FC.
::x
\
\
<
>
\
<
- - - -
- -
687
rr>-x::::
---I
015
REQUESTING DEVICE
I
Grant Bus Arbitration
11 Assert Bus Grant (613)
I
Terminate Arbitration
1) Negate BG(and wait for BGACK to be
negated)
ClK
AS
LDS/UDS
R/IN
DTACK
Do -DIS
FC o -FC 1
BR
BG
BGAK
Processor - -
I ~--------_\~==~------~I
I ~----------~\====~--_I
\
I
\\.....-----+--+- - - - -+---DMA Device
Figure 21
Processor - - -
688
DMA Device - - - -
RA
Internal Signal v a l i d - - - - - - - - - .
External Signal samPled.
1+
CLK
BR (Externall-----~
@
BR I I n t e r n a l l - - - - - - - - - - - - + _
Asychronous
I nput Delay *
Figure 22
689
ClK
50 51 52 53 54 55 56 57 50 51
50 51 52 53 54 55 56 57
SR
BG
Processor
Bus released from three state and processor starts next bus c y c l e - - - - - - - - - - - - - - - .
BGACKnegated--------------------------------------.,
BG asserted and bus three stated----------...,
BR valid internal _ _ _ _ _ _ _ _--.
BR asserted - - - - - - - - - - - - - ,
ClK
50 51 52 53 54 55 56 57
50 51 52 53 54
BR
\
BG _ _ _ _--..;._ _ _ _.....!===~\------J
~~
--{r~::::::::::~::::::::==::~------~::::::::~---------~~~(;;:::::
AS~_ _ _ _ _ _
I '
~
AI-An
FC o
UDS~
I~--~~~==~\~---------------------~
LDS~
-FC 2
R/W
DTACK
Do-DIS
'--
---------:----~(:::::)--~~~---------------~~---~~------------------~~:::
Processor
_I_ Bus Inactive _I.
Alternate Bus Master
.,_
Processor
690
50 51 52 53 54 55 56 57
BR
BG
BGACK
AI -A 23
AS
UD5
LD5
FC o -FC 2
50 51 52 53 54 55 56 57 50 51
==x
I'
I'
..
(
Processor
Do -0 15
r--"\
r-"'\
r-"'\
R/W
DTACK
,---
LI
>
~I-
>-C
-,-
(
Processor
}~
Exception Sequence
When the bus error signal is asserted, the current bus cycle
is terminated. If BERR is asserted before the falling edge of
S4, AS will be negated in S9 in either a read or write cycle.
As long as BERR remains asserted, the data and address buses
will be in the high-impedance state. When BERR is negated,
the processor will begin stacking for exception processing.
Figure 27 is a timing diagram for the exception sequence.
The sequence is composed of the following elements.
(1) Stacking the program counter and status register
(2) Stacking the error information
691
same function codes, the same data (for a write operation), and
the same controls. The bus error signal should be removed at
least one clock cycle before the halt signal is removed.
(NOTE) The processor will not re-run a read-modify-write cycle. This
restriction is made to guarantee that the entire cycle runs correctly and that the write operation of a Test-and-Set operation
is performed without ever releasing AS. If BERR and HALT
are asserted during a read-modify-write bus cycle, a bus error
operation results.
eLK
AS
\~
-J/-
__________________________
1---
LDS/UDS - - - - "
R/W
DTACK
Do -DIS
FC o -FC,
~~-----~(
:::x
BERR
'-
-:
-+- ___
..j.- __ 1!!it~t!.Blls__ _
Error Stacking
CLK
___\
,r-----
\ ....._____--J/
\
\
AS
LDS/UDS
~--------------------------
R/W
DTACK
Do - 015
FC o - FC 2
:::><
BERR
HALT
\
~- - -
I
/
- -
Read -
+ - - -- ---
Figure 28
Halt - -
- -
692
-..j. - - - -
Rerun- -
---I
\'-----..,,/
__----------------------------------------~\
\~------------------~I
I-- - --Read- -
-Halt -
-~ -
/r---
-Read- -
---{
+5V
RUN/SINGLE STEP
* OPEN COLLECTOR
DEVICE
SINGLE
STEP
Q
STEP
694
For the mask version 68000, HALT and BERR must be asserted at
the same time.
Case No.
DTACK
BERR
HALT
DTACK
BERR
HALT
DTACK
BERR
HALT
DTACK
BERR
HALT
DTACK
BERR
HALT
DTACK
BERR
HALT
DTACK
BERR
HALT
3
4
7
Legend:
N A NA X S -
Control Signal
Asserted on Rising
Edge of State
N
N+2
S
A
NA
X
NA
X
S
A
NA
X
S
A
NA
A
NA
NA
S
A
X
X
A
S
NA
NA
NA
X
A
S
NA
A
X
X
S
A
S
A
NA
X
NA
A
A
S
Result
*
The number of the current even bus state (e.g., S4, S6, etc.)
Signal is asserted in this bus state
Signal is not asserted in this state
Don't care
Signal was asserted in previous state and remains asserted in this state
Control Signal
Bus Error
Re-run
Re-run
Normal
Normal
BERR
HALT
BERR
HAIl'
BERR
HALT
13DfR
HALT
BERR
HALT
Negated on Rising
Edge of State
N
N +2
or
or
or
or
or
none
RESET OPERATION
695
HALT
t > 100 M i l l i s e c o n d s - - - l _ - - - - - - - - - - - - - - -
1-------1 t < 4
Bus Cycles
(2)
(NOTES)
1) Internal start-up time 4) PC High read in here
2) SSP High read in here 5) PC low read in here
3) SSP low read in here 6) First instruction fetched here.
Figure 31
(3)
(4)
(6)
XXXXXX
>--<
PROCESSING STATES
PRIVILEGE STATES
NORMAL
INSTRUCTION
EXECUTION
(INCLUDING STOP)
EXCEPTION
INTERRUPTS
TRAPS
TRACING ETC.
HALTED
HARDWARE HALT
DOUBLE BUS FAULT
696
REFERENCE CLASSIFICATION
When the processor makes a reference, it classifies the kind
of reference being made, using the encoding on the three function code output lines. This allows external translation of addresses, control of access, and differentiation of special processor states, such as interrupt acknowledge. Table 6 lists the
classification of references.
EXCEPTION PROCESSING
Before discussing the details of interrupts, traps, and tracing,
a general description of exception processing is in order. The
processing of an exception occurs in four steps, with variations
for different exception causes. During the first step, a temporary copy of the status register is made, and the status register
is set for exception processing. In the second step the exception
vector is determined, and the third step is the saving of the
current processor context. In the fourth step a new context is
obtained, and the processor switches to instruction processing.
EXCEPTION VECTORS
Exception vectors are memory locations from which the
processor fetches the address of a routine which will handle
that exception. All exception vectors are two words in length
(Figure 32), except for the reset vector, which is four words.
All exception vectors lie in the supervisor data space, except
for the reset vector which is in the supervisor program space.
A vector number is an eight-bit number which, when multiplied
by four, gives the address of an exception vector. Vector numbers are generated internally or externally depending on the
cause of the exception. In the case of interrupts, during the
interrupt acknowledge bus cycle, a peripheral provides an 8-bit
vector number (Figure 33) to the processor on data bus lines Do
through D7 The processor translates the vector number into
a full 24-bit address, as shown in Figure 34. The memory
layout for exception vectors is given in Table 7.
As shown in Table 7, the memory layout is 512 words
long (1024 bytes). It starts at address 0 and proceeds through
address 1023. This provides 255 unique vectors; some of these
are reserved for TRAPS and other system functions. Of the
255, there are 192 reserved for user interrupt vectors. However,
there is no protection on the first 64 entries, so user interrupt
vectors may overlap at the discretion of the systems designer.
KINDS OF EXCEPTIONS
Exceptions can be generated by either internal or external
causes. The externally generated exceptions are the interrupts
and the bus error and reset requests. The interrupts are requests
from peripheral devices for processor action while the bus
error and reset inputs are used for access control and processor
restart. The internally generated exceptions come from instructions, or from address error or tracing. The trap (TRAP), trap
on overflow (TRAPV), check register against bounds (CHI()
and divide (DIY) instructions all can generate exceptions as
part of their instruction execution. In addition, illegal instructions, word fetches from odd addresses and privilege violations
cause exceptions. Tracing behaves like a very high priority,
internally generated interrupt after each instruction execution.
Reference Class
(Unassigned)
User Data
User Program
(Unassigned)
(Unassigned)
Supervisor Data
Supervisor Program
Interrupt Acknowledge
697
AO=O,A1=0
Word 1
AO=O,A1=1
DB 07
DO
Ignored
Where:
v7 is the MSB of the Vector Number
vO is the LSB of the Vector Number
A10 A9 AB A7 A6 A5 A4 A3 A2 A1 AO
All Zeroes
Address
Assignment
Dec
Hex
Space
0
4
000
SP
004
SP
Reset: Initial PC
2
3
008
SO
Bus Error
12
Address Error
16
OOC
010
SO
SO
014
SO
Illegal Instruction
Zero Divide
20
24
018
SO
CHK Instruction
28
01C
SO
TRAPV Instruction
32
020
SO
Privilege Violation
9
10
36
40
024
SO
Trace
028
44
02C
SO
SO
11
12
48
'030
SO
(Unassigned, reserved)
13
52
034
SO
(Unassigned, reserved)
14
56
038
SO
(Unassigned, reserved)
15
60
03C
SO
16 - 23
24
64
04C
95
05F
SO
(Unassigned, reserved)
96
060
SO
Spurious Interrupt
Level 1 Interrupt Autovector
25
100
064
SO
25
27
104
068
SD
108
06C
SO
28
29
112
070
SO
116
074
30
31
120
124
SO
SO
32-47
128
191
48- 63
64 -255
078
07C
080
OBF
192
oeo
255
OFF
256
100
1023
3FF
SO
SO
SO
(Unassigned, reserved)
SO
698
699
Exception
Reset
Bus Error
Address Error
Trace
Interrupt
Illegal
Privilege
TRAP, TRAPV
CHK,
Zero Divide
Processing
Exception processing begins
within two clock cycles.
700
Yes
INTERRUPTS
H068000-4, H068000-6, H068000-8, H 0 6 8 0 0 0 - 1 0 - - - - - - - - - - - - the interrupt being acknowledged on the address bus. If external
logic requests an automatic vectoring, the processor internally
generates a vector number which is determined by the interrupt
level number. If external logic indicates a bus error, the interrupt is taken to be spurious, and the generated vector number
references the spurious interrupt vector. The processor then
proceeds with the usual exception processing, saving the program counter and status register on the supervisor stack. The
saved value of the program counter is the addrt:ss of the instruction which would have been executed had the interrupt not
been present. The content of the interrupt vector whose vector
number was previously obtained is fetched and loaded into the
program counter, and normal instruction execution commences
in the interrupt handling routine. A flow chart for the interrupt
acknowledge sequence is given in Figure 37, a timing diagram
is given in Figure 38, and the interrupt exception timing sequence is shown in Figure 39.
PROCESSOR
INTERRUPTING DEVICE
Request Interrupt
r
Grant Interrupt
1) Compare interrupt level in status register
and wait for current instruction to complete
2) Place interrupt level on AI A2. A3
3) Set R/W to read
4) Set function code to interrupt acknowledge
5) Assert address strobe (AS)
6) Assert lower data strobe (~)
I
Provide Vector Number
1) Place vector number of Do - 0,
2) Assert data transfer acknowledge (OTACK)
I
Table 9 Internal Interrupt Level
Level
12
11
10
Interrupt
7
6
1
1
Non-Maskable Interrupt
0
0
0
(NOTE)
Maskable Interrupt
B.!!!!!!
1) Negate OT ACK
No Interrupt
Start Interrupt Processing
The internal interrupt mask level 112 .,ll. 10) are inverted to the
logic level applied to the pins (11'''[2 It" LI WCn l.
Figure 37
'---_----J1
\ ______.-1
\ .
--~----/-------~~----\~---------------_I-------------------------------~~
I~
I
'-----f
---~=====-/--~\~--------------------------------------------\
~___________Jj___J\
\~__________________I
~-----\~====
--~==~r_A~------------------------------~(====
~~----------~(r~---~)------------~<~-----
-~~~..-----..;.~\'=======
--------------------~~~~--------~---------------------------------------------~I
lACK Cycle
(Vector Number Acquisition
702
Stack and
Vector Fetch
Stack
PCl
(SSP)
Read
Vector
High
(A16 - A 2 3)
r-
lACK
Cycle
(Vector Number
Acquisition)
Stack
Status
(SSP)
Read
Vector
low
(Ao - A 15 )
f----
Stack
PCH
(SSP)
UNINITIALIZED INTERRUPT
MOVE OP WORD
~
0011
100111
fMOVE
t
IMMEDIATE
WORD
SPURIOUS INTERRUPT
word bit patterns which are not the bit pattern of the frrst
word of a legal instruction. During instruction execution, if
such an instruction is fetched, an illegal instruction exception
occurs.
000
t
DATA
REGISTER
DIRECT
000
REGISTER
NUMBER
"0"
PRIVILEGE VIOLATIONS
703
HD68000-4, HD68000-6, HD68000-8, H D 6 8 0 0 0 - 1 0 - - - - - - - - - - - - error, or address error exception. If the instruction is indeed executed and an interrupt is pending on completion, the trace
exception is processed before the interrupt exception. If, during
the execution of the instruction, an exception is forced by that
instruction, the forced exception is processed before the trace
exception.
As an extreme illustration of the above rules, consider the
arrival of an interrupt during the execution of a TRAP instruction while tracing is enabled. First the trap exception is processed, then the trace exception, and fmally the interrupt exception. Instruction execution resumes in the interrupt handler
routine.
TRACE MODE
IF T = 1
STATUS REGISTER
the bus error occurred. The processor is processing an instruction if it is in the normal state or processing a Group 2 exception; the processor is not processing an instruction if it is processing a Group 0 or a Group 1 exception. Figure 40 illustrates
how this information is organized on the supervisor stack.
Although this information is not sufftcient in general to effect
full recovery from the bus error, it does allow software diagnosis. Finally, the processor commences instruction processing
at the address contained in the vector. It is the responsibility
of the error handler routine to clean up the stack and determine
where to continue execution.
If a bus error occurs during the exception processing for a
bus error, address error, or reset, the processor is halted, and
all processing cases. This simpliftes the detection of catastrophic
system failure, since the processor removes itself from the
system rather than destroy all memory contents. Only the
RESET pin can restart a halted processor.
ADDRESS ERROR
RETURN TO
EXECUTE
NEXT
INSTRUCTION
ADDRESS OBTAINED
FROM VECTOR TABLE
BUS ERROR
Hitachi's extensive line of HMCS6800 peripherals are directly compatible with the HD68000. Some of these devices
that are particularly useful are:
HD6821
Peripheral Interface Adapter
H06843
Floppy Disk Controller
HD6845S CRT Controller
HD46508 Data Acquisition Unit
HD6850
Asynchronous Communication Interface
Adapter
HD6852
Synchronous Serial Data Adapter
To interface the synchronous HMCS6800 peripherals with
the asynchronous HD68000, the processor modiftes its bus
cycle to meet the HMCS6800 cycle requirements whenever an
HMCS6800 device address is detected. This is possible since
both processors use memory mapped I/O. Figure 44 is a flow
chart of the interface operation between the processor and
HMCS6800 devices.
DATA TRANSFER OPERATION
Three signal on the processor provide the HMCS6800interface. They are: enable (E), valid memory address (YMA), and
valid peripheral address (VPA). Enable corresponds to the
E or 412 signal in existing HMCS6800 systems. The bus frequency is one tenth of the incoming HD68000 clock frequency.
The timing of E allows 1 MHz peripherals to be used with
an 8 MHz HD68000. Enable has a 60/40 duty cycle; that
is, it is low for six input clocks and high for four input clocks.
This duty cycle allows the processor to do successive VPA accesses on successive E pulses.
HMCS6800 cycle timing is given in Figure 45 and 46. At
704
14
13
12
11
10
lower Address
IRIWI I/N
Function Code
High
r- - . Access Address--------- - - - - - - - - - - - - - - - - - - - - - - - - - - .
low
Instruction Register
Status Register
High
r- - - Program Counter - -
- - - - -- - - - - - - - - - - - -- - -- - - - - - - - - - --.
low
15
14
13
12
11
10
Status Register
lower Address
High
- - - - Program Counter - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Higher Address
low
Figure 41
ClK
A.-Au
AS
UDS
lOS
I
I
I
Do - DIS
I.
<
Read
>
-I-
~\
'i
R/W
DTACK
<
Aerr
Write
Approx.8 Clocks t
- ..
Idle
- ..
'----
'-'--
<
Write Stack
state zero (SO) in the cycle, the address bus is in the high.
impedance state. A function code is asserted on the function
code output lines. OnehaIf clock later, in state 1 the address
bus is released from the high.impedance state.
During state 2, the address strobe (AS) is asserted to indicate that there is a valid address on the address bus. If the
bus cycle is a read cycle, the upper and/or lower data strobes
are also asserted in state 2. If the bus cycle is a write cycle,
705
..
Do - 0 7 (or D. - 015)
Do -0 7
"
lb
Decode for
~HMCS~
Address
Bus
~h::I'
AS
HD68000
Address
&
CS's
CS
Block of
HMCS6800
Devices
VPA
CS
VMA
PROCESSOR
Initiate Cycle
1) The processor starts a normal Read or
Write cycle
(VMA)
Transfer Data
1) The peripheral waits until E is active and
then transfers the data
Terminate Cycle
1) The processor waits until E goes low. (On a
706
51
52
53
54
55
56
57
50
ClK
AI - AB
A5
VPA
VMA
Data Out
~~In------------------------------------------
J,________________________________________________________________________
FC -FC2 ______
o
(NOTE)
~~-----
This figure represents the best case HMCS6800 timing where VPA falls before the third system clock cycle after the falling edge of E.
50 51 52 5354 w w w w w w w w w w w w w w w w w w w w w w w w w w w w 55 565750
ClK
..n...r-~M~F- ~
J-{
AS
\
---t
5J
1I
VPA
--
VMA
r-@
I
+-@
~
r-@
'--@
.1.
UD5/lD5
Read
R/WWrite
Write
@-
Data In
ODS/CD!
f--@
R/W
(Read)
Data Out
@,j
I--@
@ .... 1.-
t--
FCo - FC2
707
periPhera~,"
HMCS6800"
'50 n S 3 Type B
180 ns
Type A
270 ns
Std
~
HMCS6800 VMA.
R/W
HMCS6800Address
,. ----
70 ns
140 ns
140 ns
).....: 10 ns HMCSGBOO"
Peripheral"
Type B ~ 180 n s = = = s
Type A
220 ns
~ 10 ns Peripheral
Std
HD68000Address
VPA
A
Std
f-- 10 ns HMCS6800"
-...j
-----I
320 ns
-------------~!III!/hW
Type B
Type A
Std
Type
==~;;;;~---===~----~"""~~~~~
_ _ _ _ _ _ _ _ _ _ _ _ _ __
--I
--I
Type B
Type A
Std
~pero~~e~:3'"
~ 10 ns Penpheral
)1>-----I
80 ns
195 ns
---------------(1$/$
...
-J..------
~"",W,""I';""______________________
II1II
--
-----------~~~~
HD6BOOO (8 MHz)
~-----------~~m.~~
~---~~====~----------~
Write Data
HD68000CLK
33k
AS
i7MA
00 -DIS
II"'!
-I
AI -Au
-v
c5
c5
~ I.;
-<
cs;
HD68000
oi
.;.
iiJiA
FC,
FC,
FC.
<l:=
}NC
~ ~ ~
'7
~ .i
I1'C
II'L.
RES
E
RIW
708
RSCS.
HD6850ACIA
R/W
3.3k
IT~
.;. loi
~,CS,
+jV
!PC
n:m
E R/iii
.,.
flj
6800 Address
AS
VMA
.----.--,-.--,--.., I
00-0"
A,-A"
?
"
--v
<i
74lS
A3 A 138
A.
As
III
I!?
8
C
"
'0
c(
~I ~1<l17
c(
~
> .('1 <i
3.3k
1;7
cs,
HD6821 PIA
HD68000
.....,
( l:g II:l
!!:!!:a:
CO
I~
wa:
CS, CSo RS
HD6850 ACIA
I~
:z:
c
G)
I~
a:
CO
o
o
~TG,"
FC,
~
--L
III
+5
3.3k
I IE.
r<
:z:
c
G)
CO
o
o
o
!
I
74lS
:z:
c
348
or
74lS
Ao 148
AI
Az
CO
o
o
o
SD
RES
RIW
Figure 49 l HMCS6800 Interface - Example 2
:z:
c
0)
CO
o
o
o
INTERRUPT OPERATION
50
52
54
56
58
there are six normal interrupt vectors and one NMI type vector .
As with both the HMCS6800 and the 80680oo's normal
vectored interrupt, the interrupt service routine can be located
anywhere in the address space. This is due to the fact that
while the vector numbers are flXed, the contents of the vector
table entries are assigned by the user.
Since VMA is asserted during autovectoring, the HMCS6800
peripheral address decoding should prevent unintended accesses.
50
-------{:::::::::J~~-------------------------------~
\~
______
~r---\~
______________________________
\'-___~r---\
r---\
__J,___
,___
,___
----------~\
\'-____~I
L-J
------------~c:::J~-----------------------------------
c:::J
______-n____________- J
L\'-----------------------------~,---
Five basic data types are supported. These data types are:
Bits
BCD Digits (4-bits)
Bytes (8-bits)
Word (16-bits)
Long Words (32-bits)
In addition, operations on other data types such as memory
addresses, status word data, etc., are provided for in the instruction set.
The 14 addressing modes, shown in Table 10, includs six
basic tVDes:
R~gister Direct
Register Indirect
Absolute
Immediate
Program Counter Relative
Implied
Included in the register indirect addressing modes is the capability to do postincrementing, predecrementing, offsetting and
indexing. Program counter relative mode can also be modified
via indexing and offsetting.
710
Mode
Regilter Direct Addressing
Data Register Diredt
Address Register Direct
EA=Dn
EA=An
EA = (Next Word)
EA = (Next Two Words)
EA = (PC) + d16
EA = PC) + (Xn) + d a
EA = (An)
EA = (AN), An +-An + N
An +-An - N, EA = (An)
EA = (An) + d 16
EA = (An) + (Xn) + d a
Implied Addressing
Implied Register
EA
(NOTES)
EA = Effective Address
An = Address Register
On = Data Register
Xn = Address or Data Register used
as Index Register
SR = Status Register
PC = Program Counter
( ) = Contents of
da
= SR,
USP, SP, PC
= Eight-bit Offset
(displacement)
d 16 = Sixteen-bit Offset
(displacement)
N = 1 for Byte, 2 for
Words and 4 for Long
Words
+- = Replaces
Table 11
Mnemonic
Description
ABCD
ADD
AND
ASL
ASR
Bee
BCHG
BCLR
BRA
BSET
BSR
BTST
Branch Conditionally
Bit Test and Change
Bit Test and Clear
Branch Always
Bit Test and Set
Branch to Subroutine
Bit Test
CHK
CLR
CMP
DBee
DIVS
DIVU
Mnemonic
Instruction Set
Description
EOR
EXG
EXT
Exclusive Or
Exchange Registers
Sign Extend
JMP
JSP
Jump
Jump to Subroutine
LEA
LINK
LSL
LSR
MOVE
MOVEM
MOVEP
MULS
MULU
Move
Move Multiple Registers
Move Peripheral Data
Signed Multiply
Unsigned Multiply
NBCD
NEG
NOP
NOT
OR
Description
Mnemonic
PEA
RESET
ROL
ROR
ROXL
ROXR
RTE
RTR
RTS
SBCD
Sec
STOP
SUB
SWAP
TAS
TRAP
TRAPV
TST
Logical Or
UNLK
Unlink
1
-
Variation
ADD
ADDA
ADDQ
ADDI
ADDX
Add
Add
Add
Add
Add
AND
AND
ANDI
Logical And
And Immediate
CMP
CMP
CMPA
CMPM
CMPI
EOR
EORI
EOR
Instruction
Type
Description
Variation
Description
MOVE
MOVE
MOVE A
MOVEQ
MOVE from SR
MOVE to SR
MOVE to CCR
MOVE USP
Move
Move Address
Move Quick
Move from Status Register
Move to Status Register
Move to Condition Codes
Move User Stack Pointer
Compare
Compare Address
Compare Memory
Compare Immediate
NEG
NEG
NEGX
Negate
Negate with Extend
OR
OR
ORI
Logical Or
Or Immediate
Exclusive Or
Exclusive Or Immediate
SUB
SUB
SUBA
SUBI
SUBQ
SUBX
Subtract
Subtract
Subtract
Subtract
Subtract
Address
Quick
Immediate
with Extend
ADDRESSING
Instructions for the HD68000 contain two kinds of information: the type of function to be performed, and the location
of the operand(s) on which to perform that function. The
methods used to locate (address) the operand(s) are explained
in the following paragraphs.
Instructions specify an operand location in one of three
ways:
Register Specification - the number of the register is given
in the register field of the instruction.
Effective Address - use of the different effective address
modes.
Implicit Reference - the defmition of certain instructions
implies the use of specific registers.
Address
Immediate
Quick
with Extend
Operand Size
32
32
Operation
RXB-Ry
EA~An
An~SP@-
LINK
MOVE
16,32
MOVEP
16,32
MOVEQ
PEA
SWAP
8
32
32
(NOTES)
s = source
d = destination
[ 1 = bit numbers
SP~An
SP+ d ~SP
(EA)s~ EAd
(EA)~An, On
An, On~ EA
(EA)~ On
8,16,32
MOVEM
UNLK
712
On~EA
#XXX~
On
EA~SP@-
On[31:16] **On[15:0]
An~Sp
SP@+~An
@@
Operand Size
On + (EA) -+ On
(EA + On-+ EA
(EA) + #Xxx -+ EA
AN + (EA) -+ An
ADD
CLR
16,32
8,16,32
16,32
8,16,32
8,16,32
Ox + Oy + X -+ Ox
Ax@-+Ay@-+ X -+ Ax@
OIVS
OIVU
EXT
MULS
MULU
NEG
NEGX
0-+ EA
16,32
32 + 16
32+ 16
8 -+ 16
16 -+ 32
16*16 -+ 32
16*16 -+ 32
8,16,32
8,16,32
8,16,32
On/(EA) -+ On
On/(EA) -+ On
(On)8 -+ On16
(Onh6 -+ On32
On *(EA) -+ On
On *(EA) -+ On
o - (EA) - X - EA
On (EA)
(EA)
An -
16,32
(EA) -+ On
- On -+ EA
- #Xxx -+ EA
(EA) -+ An
SUBX
8,16,32
Ox - Oy - X -+ Ox
Ax@- -Ay@- -X-+Ax@
TAS
8
8,16,32
(EA) - 0,
(NOTE)
14
1 -+ EA[7]
(EA) -0
13
12
11
10
EFFECTIVE ADDRESS
] = bit number
15
REGISTER SPECIFICATION
0- (EA) -+ EA
SUB
TST
PROGRAM/DATA REFERENCES
The HD68000 separates memory references into two classes: program references, and data references. Program references, as the name implies, are references to that section of
memory that contains the program being executed. Data references refer to that section of memory that contains data.
Generally, operand reads are from the data space. All operand
writes are to the data space.
On - (EA)
(EA) - #Xxx
Ax@+ - Ay@+
An - (EA)
CMP
INSTRUCTION FORMAT
Operation
8,16,32
AOOX
Operation Word
(First Word Specifies Operation and Modes)
Immediate Operand
(If Any. One or Two Words)
Source Effective Address Extension
(If Any. One or Two Words)
Destination Effective Address Extension
(If Any. One or Two Words)
Figure 51
Instruction Format
4
3
2
Effective Address
Mode
Register
713
EXAMPLE
MPU
COMMENTS
MEMORY
EA = On
$001FOO
Machine Level Coding
MOVE DO, $1 FOO
10000ABCDI DO
0011
-=r
Move
Word
0001
1100
0000
II~
Absolute
Short
OWL
31CO
OWL+2
1FOO
Data
Register
Direct
EXAMPLE
MEMORY
MPU
/00001234/ A4
COMMENTS
EA= An
I Taro~
OWL
33CC
OWL + 2
0020
OWL+4
1000
t-------t
714
Word Absolute
Long
--LAddress
Register
Direct
COMMENTS
MEMORY
EA = An
Address Register Sign Extended
Machine Level Coding
MOVE $201000, A4
1000012341 A4
0011
1000
0111
1001
~1[I
Word
Absolute
Long
Reg#4
Address
Register
Direct
MOVE $201000, A4
OWL
3879
OWL+2
0020
OWL+4
1000
COMMENTS
MPU
MEMORY
EA = (An)
1000010001 AO
Word
OWL
3010
1--------1
MOVE (AO!. DO
71C::
ljOOOTQ.1:
Register
Direct
Reg #0
ARI
(Address
Register
Indirect)
HD68000-4, HD68000-6, HD68000-8, H D 6 8 0 0 0 - 1 0 - - - - - - - - - - - - address register is the stack pointer and the operand size is
byte, the address is incremented by two rather than one to
keep the stack pointer on a word boundary. The reference is
classified as a data reference.
MPU
MEMORY
COMMENTS
EA = (An); An + M-An
Where An __ Address Register
M --1,2,or4
(Depending Whether
Byte, Word, or
Long Word)
Machine Level Coding
MOVE (A4) +, $2000
$2000
OWL
MOVE (A4) +,$2000
OWL + 2
~----~
31DC
MOVE - (A3),$4000
lr:
Move
Word Absolute
Short
AR I with
Increment
~------4
2000
register is the stack pointer and the operand size is byte, the
address is decremented by two rather than one to keep the
stack pointer on a word boundary. The reference is classified
as a data reference.
101
~----~
MPU
0001
MEMORY
COMMENTS
An - M-An; EA = (An)
Where An __ Address Register
M -1,2,or4
(Depending Whether
Byte, Word, or
Long Word)
Machine Level Coding
MOVE - (A3), $4000
iIo
001
Move
Word
OWL
OWL
+2
31E3
~----~
4000
~------I
716
Absolute
Short
1i~lUUll
with
Predicrement
Reg #3
This address mode requires one word of extension. The address of the operand is the sum of the address in the address
MPU
MEMORY
$3000 t - - - - - - - - f
MOVE $100(AO),$3000
ADDRESS
CALCULATION:
AO = 00001000
dl6 = 00000100
00001100
MOVE $100(AO),$3000
EXAMPLE
MPU
MEMORY
$1000 t - - - - - - - 4 " \
100002000 I AO
$4BEO
1110
1000
I
Reg#0
ARI
with
Displacement
Move
Word
I------~
COMMENTS
EA = An + Rx + dB
Where
An _
Pointer Register
Rx Designated Index Register,
(Either Address Register or
Data Register)
d. ___ 8-Bit Displacement
Rx & d. are Sign Extended
Rx may be Word or Long Word
Long Word may be Designated with Rx.L
Machine Level Coding
MOVE $04(AO, DO), $1000
0011
--=r
Move
Word
ADDRESS
CALCULATION:
AO = 00002000
DO =00002BDC
d =00000004
00004BEO
0001
eight bits of the extension word, and the contents of the index
register. The reference is classified as a data reference with the
exception of the jump and jump to subroutine instructi9ns.
-=r=:-1
Absolute
Short
OWL t--_...;;.3_1E.;;.8,--_~
OWL + 2
0100
1-------1
OWL +4
3000
1-------1
100002BDCI DO
COMMENTS
EA = An + d l6
Where An ---Pointer Register
d l6 ----16-Bit Displacement
dl6 Displacement is Sign Extended
Machine Level Coding
OWL
OWL + 2
OWL +4
0001
ARI
with
Index
t--------I
0004
1000
I------~
0000
0000
olT~l
Reg #0
717
0000
Short
31FO
I------~
1111
-==r:=-I~
Absolute
Reg #0
0000
0100
Constant Zeros
EXAMPLE
MEMORY
MPU
COMMENTS
EA = (Next Word)
16-Bit Word is Sign Extended
$2002
t.w~
Absolute
Not Instruction
NOT.L $2000
OWL
46BB
OWL+2
2000
MEMORY
MPU
$1000
I-----"""'>O'~
1000
Short
COMMENTS
EA = (Next Word)
16-Bit Word is Sign Extended
$2000
.......------1
0011
0001
1111
Absolute
Short
OWL
31F8
OWL+2
1000
OWL+4
2000
718
1000
--.rMove
--r~
Word
Short
EXAMPLE
MEMORY
MPU
COMMENTS
EA = (Next Two Wordsl
NEG $014000
0100
0100
0111
1001
=-Cke--=:I
NEG
I nstruction
OWL
NEG $014000
4479
OWL+21--__0_0_0_1 _--I
OWL +4
4000
the extension word. The value in the program counter is the address of the extension word. The reference is classifIed as a program reference.
EXAMPLE
MPU
Absolute
Long
MEMORY
COMMENTS
EA = (PC) + d 16
d\6 is Sign Extended
Machine Level Coding
MOVE (LABEll. DO
0011
0000
0011
1010
I TJ:th
Move
Word
MOVE (LABEll. DO
ADDRESS
CALCULATION:
PC = 00008002
d = 00001000
00009002 <LABEL>$9002 1--_ _ _ _--1
719
Dat~
Register
Direct
Displacement
EA
Extension Word
7654320
Displacement Integer
Beginning }
Address of
PC + d.
Data Table
Desir~ D~ta
LocatIon In Table
} PC
DIA
: Data Register'" 0, Address Register - 1
Register: Index Register Number
WIL
: Sign-extented, low order Word integer
in Index Register = 0
Long Word in Index Register'" 1
+ d + Rx _
EXAMPLE
MEMORY
MPU
$8000~
$8002~
<LABEL>
1..$8012~
COMMENTS
EA ... (PC) + (Rx) + d a
Where
PC-Current Program Counter
Rx-Designated Index Register
(Either Data or Address Register)
d a -8-Bit Displacement
Rx and d a are Sign Extended
Rx may be Word or Long Word
Long Word is Designated with Rx.L
Machine Level Coding
MOVE (LABEL) (AO), DO
0011
Move
Word
0000
0011
1011
-r-- p!
with
~Inde)(
Data Register
Direct
1000
Add.re~J
ADDRESS
CALCULATIONS:
PC '" 00008002
AO'" 00001010
d '" 00000010
00009022
0000
fT
00010000
~Iacement
RegIster I~
Register
Constant Zeros
Number
I ndex Length
720
Extension Word
15
10
0:
Byte
or
15
Word
t---15
MEMORY
MPU
B 7
a a a a a a
COMMENTS
Data = Next Word(s)
Data is Sign Extended
for Address Register
but not Data Register
Machine Level Coding
MOVE #$1000, AO
0000
0111
1100
J ,J 1 ,Jmod;.to
#0
Data
Move
Word
Address
Register
Direct
MOVE #$1000, AO
EXAMPLE
MEMORY
MPU
COMMENTS
Inherent Data
Data is Sign Extended to Long Word
Destination must be a Data Register
Machine Level Coding
I0OO0005A I 03
MOVEQ #$5A, 03
0111
011
0101
1010
I~Jxed
~
Move
Zero
Data
Quick
OWL
t---=""---4
MOVEQ #$5A, 03
7?1
or
Long Word ____ - ___
- -
-I
A selected set of instructions may reference the status register by means of the effective address field. These are:
ANDI to CCR
ANDIto SR
EORI to CCR
EXAMPLE
EORI to SR
ORIto CCR
MPU
MEMORY
ORIto SR
COMMENTS
EA = (Next Word)
Note: This Example is a Privileged
Instruction
Machine Level Coding
MOVE $1020, SR
0100
:27r;SA
0110
1000
~
Absolute
Short
0010
OWL
MOVE $1020, SR
1111
f
Move to SR
OWL+2
46FS
1020
1-------1
stack pOinter (SSP), the user stack pointer CUSP), or the status
register (SR).
SYSTEM STACK
Mode
Register
000
001
010
register number
011
register number
100
register number
101
register number
110
register number
Absolute Short
Absolute Long
111
111
000
001
111
010
111
111
011
100
Immediate
register number
register number
USP
SSP
Accessed when S = 0
PC is Stacked on
Subroutine Calls in
User State
IMPLICIT REFERENCE
Increasing Addresses
722
Accessed when S = 1
PC is Stacked on
Subroutine Calls in
Supervisor State
Used for Exception
Processing
User stacks can be implemented and manipulated by employing the address register indirect with postincrement and predecrement addressing modes. Using an address register (on of
AO through A6), the user may implement stacks which are filled
either from high memory to low memory, or vice versa. The
important things to remember are:
- using predecrement, the register is decremented before its
contents are used as the pointer into the stack,
using postincrement, the register is incremented after its
contents are used as the pointer into the stack,
byte data must be put on the stack in pairs when mixed
with word or long data so that the stack will not get
misaligned when the data is retrieved. Word and long
accesses must be on word boundary (even) addresses.
Stack growth from high to low memory is implemented with
An@- to push data on the stack,
An@+ to pull data from the stack.
After eigher a push or a pull operation, register An points to
the last (top) item on the stack. This is illustrated as:
low memory
bottom of stack
top of stack
(free)
high memory
QUEUES
low memory
(free)
An---+-
next get
top of stack
last put
Aput---+-
(free)
high memory
bottom of stack
high memory
723
Instruction
Operation
(free)
8,16,32
ASR
8,16,32
lSl
8,16,32
next get
lSR
8,16,32
0-1
I- 0
~
j.-o
.. HX/CI
ROl
8,16,32
~.
j.,..J
ROR
8,16,32
ROXl
8,16,32
ROXR
8,16,32
last put
Aget-
high memory
LOGICAL OPERATIONS
Dn/\(EA)-+ Dn
(EA)/\ Dn- EA
(EA) 1\ #xxx -+ EA
OR
8,16,32
Dn v (EA) --+ Dn
(EA) v Dn--+ EA
(EA) v #xxx --+ EA
EOR
8,16,32
(EA)<Il Dy --+ EA
(EA) <Il #xxx --+ EA
NOT
8,16,32
-(EA)- EA
[NOTE] - = invert
kTI
~.
I.[D.J
I..jx H
kTI
Operation
8,16,32
AND
..
Instruction
Operand Size
ct:
~.
ASl
Aput_
Operand Size
Operation
BTST
8,32
BSET
8,32
- bit of (EA) -+ Z
1-+ bit of EA
BClR
8,32
- bit of (EA) -+ Z
0--+ bit of EA
BCHG
8,32
Multiprecision arithmetic operations on binary coded decimal numbers are accomplished using the following instructions:
add decimal with extend (ABCD), subtract decimal with extend
(SBCD), and negate decimal with extend (NBCD). Table 19 is
a summary of the binary coded decimal operations .
724
Operand Size
Operation
ABCD
Dx,o + Dy,o + X -+ Dx
Ax@ -'0 + Ay@ -'0 + X-+ Ax@
SBCD
Dx,o - Dy,o - X -+ Dx
Ax@ - 1 0 - Ay@ - I 0 - X -+ Ax@
NBCD
0- (EA),o - X --+ EA
System control operations are accomplished by using privileged instructions, trap generating instructions, and instructions
that use or modify the status register. These instructions are
summarized in Table 21.
Table 21 System Control Operations
Instruction
DBee
See
Unconditional
JMP
JSR
Branch always
8-and 16-bit displacement
Branch to subroutine
8- and 16-bit displacement
Jump
Jump to subroutine
Returns
RTR
RTS
BRA
BSR
Trap Generating
TRAP
TRAPV
Conditional
Bee
Operation
Instruction
Privileged
RESET
RTE
STOP
ORI to SR
MOVE USP
ANDI to SR
EORI to SR
MOVE EA to SR
CHK
Trap
Trap on overflow
Check register against bounds
Status Register
ANDI to CCR
EORI to CCR
MOVE EA to CCR
ORI to CCR
MOVE SR to EA
8 7
15
Operation Code
Operation Word
8 bit Displacement
Extension Word
MEMORY
MPU
$5000~
BEQ NEXT
$5020
PC+2=5002
d = OOtE
5020
Next OP Code
COMMENTS
Offset Contained in 8 LSBs of Op Word
Offset is 2's Complement Number
If Offset = 0 then Word Offset is Used
Machine Level Coding
BEQ NEXT
0110
0111
Brtnch'
0001
1110
T - 51k"
arakm
Equal
=0
EXAMPLE
MEMORY
MPU
$4000
Branch If
Not Equal
$4020 t--_ _
66_D_E_---t
BNE NEXT
PC
~L~
1-------1
+ 2 =4022
d '" FFDE
4000
MEMORY
MPU
; J : h l z e r o Offset
Branch If
Carry Clear
Bee NEXT
$5002
Next OP Code
PC + 2 = 4002
d=+1000
5002
v -
C - Carry
The condition code register portion of the status register contains fIve bits:
N - Negative
Z - Zero
Overflow
X - Extend
The fIrst four bits are true condition code bits in that they
reflect the condition of the result of a processor operation.
The X-bit is an operand for multiprecision computations. The
carry bit (C) and the multiprecision operand extend bit (X)
are separate in the HD68000 to simplify the programming
model.
726
transparent to data movement. When affected, it is set the same as the C-bit.
The notational convention that appears in the representation
of the condition code registers is:
* set according to the result of the operation
not affected by the operation
o cleared
1 set
U undefmed after the operation
X (extend)
ABCD
C = Decimal Carry
Z = Z' Rm' ... RO
ADD,ADDI,
AD DO
AODX
AND, ANOI,
EOR, EORI,
MOVEO, MOVE,
OR,ORI,
CLR, EXT,
NOT, TAS, TST
CHK
SUB, SUBI
SUBO
-.-- ---t I
I I
?
SUBX
CMP, CMPI,
CMPM
DIVS,DIVU
-- 1----,;-
SBCD, NBCD
BTST, BCHG,
BSET, BCLR
ASL
ASL (r = 0)
LSL, ROXL
LSR (r = 0)
ROXL (r = 0)
-----
ROL
ROL (r = 0)
ASR, LSR, ROXR
ASR, LSR (r = 0)
ROXR (r=O)
ROR
ROR (r =0)
- Not affected
U Undefined
? Other- see Special Definition
V = Sm Om FIm It Sm !Jm Rm
C = Sm Om + FIm Om + Sm Am
Z = Z' Rm' ... RO
V=Sm'Dm'Rm+Sm'Dm'Rm
C =Sm' Dm+ Rm' Dm+Sm' Rm
Z = Z' Rm' ... RO
V = Sm Om Am + Sm Om Rm
C = Sm Om + Rm Om + Sm Rm
V = Division Overflow
C = Decimal Borrow
Z = Z' Rm' ... RO
?
?
?
?
V = Om Rm, C = Om + Rm
V = Om .:....Bm, C =.Q.m + Rm
Z = Z' Rm' ... RO
Z = On
I
-
-
V=Sm'Dm'Rm+Sm'Dm'Rm
C = Sm Om + Rm Om + Sm Am
NEG
NEGX
?
?
---- - - - - -
MULS, MULU
Special Definition
0
0
?
?
I----f--
0
0
?
?
General Case:
X=C
N=Rm
Z c Riii ....
RO
7')7
C = Om-r+1
C=X
C = Dm -r+1
C = Dr _1
C=X
C = 0r-1
Sm Om Rm n r
-
HI
LS
Condition
CC
low or same
carry clear
CS
carry set
NE
EQ
not equal
equal
VC
overflow clear
VS
overflow set
PL
plus
MI
minus
GE
greater or equal
LT
less than
GT
greater than
LE
less or equal
INSTRUCTION SET
Encoding
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
true
false
high
Test
1
0
CZ
C+Z
C
C
Z
Z
V
V
N
N
NV+NV
NV+Nv
NVZ+NVZ
Z+NV+NV
memory or data alterable. The former refers to those addressing modes which are both alterable and memory addresses, and
the latter refers to addressing modes which are both data and
alterable.
ADDRESSING CATEGORIES
INSTRUCTION PRE-FETCH
7-28
#xxx
Mode
Register
Data
000
001
010
011
100
101
110
111
111
111
111
111
register number
register number
register number
X
X
X
X
X
X
X
X
X
X
X
register number
register number
register number
register number
000
001
010
011
100
Addressing Categories
Memory
Control
Alterable
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
-
AICO
Add Otglts
ADD
Add
81n"y
AOOA
Add Address
AOOI
Add Immed
AOOO
Add QUICk
AOOK
Add Multi
oreCI$lon
AIIO
logIC.1 Md
AIIDI
Md Immed
ASL. ASII
Anthmetlc
ShtH
Memory
ICHG
Test and
Diange
ICLII
Test"d
Dear
ISET
TeSiand
Set
ITST
81tTesl
bIt~lmm
b>j::1)!
btl:: Imm
B btl::'1)!
bit
~:Imm
blll:'On
b>jl:lmm
B bit 11. On
bIt~>lmm
bll:tDn
bIt::lmm
CHI(
Dieck Reg
ISler Ag.,"st
Bounds
CLII
ae,,~er.nd
7
2
2
4
6
2
2
2
8
8
8
8
16
4
8
4
2
4
6
2
2
2
2
8
8
16
6'2n
6+2n
8+2n
8+2n
2'1
MXlA
g
~I
8
8
MXlA
MXlA
2'
2
4
8
2
4
6
2
2
2
2
2
2
4
6
12
8
20
14
12
14
16
28
12
20
12
8
20
14
16
28
2
2
2
2
2
2
4
6
2
2
2
2
2
4
6
d(An)
d(An.Xi)
Abs.W
l:
II
II
II
2
2
2
2
2
2
2
4
6
2
18
14
10
22
16
14
16
18
30
14
22
4
4
4
4
4
4
6
8
4
4
16
12
24
18
16
18
20
32
16
24
4
4
4
4
4
4
6
8
4
4
4
4
4
4
4
4
6
8
4
4
16
12
24
18
16
18
20
32
16
24
6
6
6
6
6
6
8
10
6
6
18
2
2
2
2
2
4
6
30
i4
10
22
16
18
30
12
8
20
14
12
14
16
28
12
20
12
8
20
14
16
28
4
4
4
4
6
8
16
12
24
18
20
32
4
4
4
4
6
8
18
14
26
20
18
20
22
34
18
26
18
14
26
20
22
14
4
4
4
4
6
8
16
12
24
18
20
32
Abs.L
20
16
28
22
20
6
6
6
6
8
10
20
16
28
22
24
36
12
12
16
2'
2
4
12
12
16
2'
2
4
14
14
18
4'
4
6
16
16
20
4'
4
6
18
18
22
4'
4
6
16
16
20
6'
6
8
20
20
24
2
4
12
16
2
4
12
16
2
4
14
18
4
6
16
20
4
6
18
22
4
6
17
20
6
8
20
24
2 < 10
4 <14
d(PC)
II
d(PC.Xi)
II
s~lmm.d
d~SRICC
II
12
14
4
4
4
18
16
18
4
4
4
20
18
20
6
4
6
14
12
14
2
4
12
16
2
4
12
16
2
4
14
i8
4
6
16
20
4
6
18
22
4
6
16
20
6
8
20
24
2
4
8
12
2
4
8
12
2
4
10
14
4
6
12
16
4
6
14
18
4
6
12
16
6
8
16
20
12
14
18
20
6
4
1100
1100
110 I
110 I
110 I
110 I
110 I
1101
0000
6
10
<40 -trap8'
d 2
d, 2
s,2
s 2
4
6
4
6
s 2
s' 2
6
6
d' 4
d 6
d
d
8
14
lo~
<44
<44
2
2
12
<46
<48
4
14'
12
<50
4
<48
6
20'
16'
12
16
4
6
<48
<52
4
18'
16'
4
6
Compare
L d,Ol
81nary
W d,M
CM'A
Comp.re
L d.M
Address
S W s,lmm
CM,t
Compare Imm l sdmm
S"W s(I<1) f
CM'M
Compare
L S,(M) ,
Memory
W d,1)!
OtVS
OIV1deSlgned
W dOl
DtVU
I~~~,"g.
Registers
EXT
S1gnE'lend
LEA
Lo.dEflect
IveAddress
UIII(
L,nk.nd
Allocale
S W s-I)!
-**00
IOee eeee
SSEE EEEE
d<and>l:~d
-**00
i::r?-
*****
I II 0 rr rf
1110 QQQI
1I10rrrf
1110 QQQI
11100001
0000 rrr I
0000 1000
0000 rr r I
0000 1000
0000 rr r I
0000 1000
0000 'rr I
0000 1000
0000 rr, I
0000 1000
0000 rr, I
0000 1000
0000 rr, I
0000 :000
0000 'rr I
0000 1000
01000001
SSIO
SSOO
10 I 0
1000
IIEE
OIEE
OIEE
OIEE
OIEE
10EE
10EE
10EE
10EE
II EE
II EE
II EE
II EE
OOEE
OOEE
OOEE
OOEE
IOee e eee
0000
0000
0000
0000
EEEE
EEEE
EEEE
EEEE
EEEE
EEEE
EEEE
EEEE
EEEE
EEEE
EEEE
EEEE
EEEE
EEEE
EEEE
EEEE
EEEE
12'
~~
-(bit)l: of d-Z.
-(bit)l: of d
(bif)lIofd
- - *--
d~Z.
- - *--
-(bit)1I of
O~(bit)1I
of d
-(bit) II of
d~Z,
l-~(bit)l:
of d
-(bit)tI: of
d'~Z
~MPU
- - *--
- -*--
- * UU U
12
20
8
14
14
22
10
16
4
4
4
4
16
24
12
18
4
4
4
4
18
26
14
20
4
4
4
4
16
24
12
18
6
6
6
6
20
28
16
22
0100 00 I 0
SSEE EEEE
2
2
2
4
4
12
18
4
4
14
20
4
6
8
14
10 II DODO
SS e
Ol-s
-****
6
6
2
2
10
14
2
2
10
14
2
2
12
16
4
4
14
18
4
4
16
20
4
4
12
18
18
22
4
4
14
18
4
4
16
20
4
6
10
14
10 II AAAO
10 II AAAI
Ilee eeee
Ilee eeee
M-s
-****
CMPA
CMPA
4
6
12
20
4
6
2
2
12
20
12
20
4
6
14
22
6
8
16
24
6
8
18
26
6
8
16
24
8
10
20
28
0000 1100
SSEE EEEE
d-Ii
-****
10 II RRR I
5S00 I rr,
d-s
-****
0l32/s1~
7.
~d
-0100
s' 2 <158
2 <162 2 <162 2 <164 4 <166 4 <168 4 <166 6 <170 4 <166 4 <168 4 <162
1000 0001
Ilee eeee
s. 2 < 140
2 <144 2 <144 2 <146 4 <148 4 <150 4 <148 6 <152 4 <148 4 <150 4 <144
1000 DODO
II . . . . . .
10 II 'rr I
SSEE EEEE
deOl~d
-**00
d ell-+d
- * *0 0
s-d
-----
Ol(rQ)
12
20
2
2
12
20
2
2
14
22
4
4
16
24
4
4
18
26
4
4
16
24
6
6
20
28
B W sdmm
L s,lmm
d 4
d 6
8
16
4
6
16
28
4
6
16
28
4
6
18
30
6
8
20
32
6
8
22
34
6
8
20
32
8
10
24
36
L s.Ol
,.,..
d 2
d 2
6
6
4
4
L d'M
d 2
d, 2
s
value
st.: Number of Prolram Bytes
-: Number 01 Clock Periods
d<.nd>Ol~d
()1<and>s-1)!
d<and>I)!'-d
I)!<.nd>s-I)!
2
2
2
2
2
2
Word only
*****
12
20
8
14
4
8
*****
2
2
2
2
2
4
20
12
12
12
16
111000001
\IIOOAAAI
11000001
0100 1000
0100 1000
0100 AAAI
0100 1110
0100
0100
1000
1000
1100
Ilee
0000
IAAA
IAAA
0000
0000
eeee
0101 OAAA
0l32!sl~
l)!(rQ)
bit 7~bit8-15
bitlbbit16-31
- *** 0
-***0
- **00
s~I<1
. - . --
I<1~-(SP)
-----
51"-+'"
SP+disp~SP
<: Maximum
*****
::: 'd
4
6
d 2
d, 2
disp . lmm
.-.-.
2'
2
L s1)!
"'s .,..
d'::: 'd
d- s+X +d
DIVide
lkIsigned
1011
Exclusive 00
LoglC.1
EOllt
ExcluSive 00
Immediate
*****
+d
,I)!
'd
.I)!
SSOOOrrr
SSOO I rr r
1000 Orr r
1000 I rr r
SSEE EEEE
55 ee ee ee
I OEE EEEE
trap
SW
*u*u*
d ~Ol
()1s
d1)!
()1.\
110 I RRRI
II 0 I RRRI
1101 RRR I
1101 RRRI
11000001
8
1100 DODO
1100 0001
14
1100 DODO
20 . 0000 00 10
4
18'
dl0+slO+X -d
d~
<44
<50
RRR I OOOOOrrr
RRRI 0000 I" r
DDDl SSEE EHE
DODO SSe e e ee e
DODO I OEE EEEF.
0001 IDee teee
AAAO Ilee eeee
AAA I I lee e e ~ e
0 II 0 SSEE EEEF.
SSEE EEH
14
18
4
16'
I l..n
0101 QQQO
2 <8
4 <12
2
4
Condition
Cod
XNZVC
24
36
20
28
2'
2
4
2 <8
4 <12
d
d
d
d
d
d
d
d
d
d
2
2
7
2
(An)
::
(An) "
l:
It
s 2
(bound)
S'W d1)!
CM'
d1)!
II
I:
B sOl
d
s (M)
d
B W sOl
d
d'Ol
s
L ;ilI
d
dOl
s
W dlo
s
L dlo
s
8 W s Imm
d
L slmm
d
8 W s'lmm3
d
L S Imm3
d
8 W sill
d
s (M)
d
l sill
d
S (M)
d
8 W sill
d
dill
s
d
L sill
d'ill
s
8 W s Imm
d
L s Imm
d
8 W count-Dl
d
caunl ::]-8d'
l counll)!
d
count::1-8d
W counl1
d
8 btl:: I)!
d
btl::lmm d
L btl::Ol
d
bl!::-Imm d
B bll:tOn
d
(An)
An
On
Adilr .
Modo
M.... onle
Sin
Ope,ation
0: Data Rel,ster #:
C; Test Condition
R: Destination Register
$: Size: OO-Byte
Ot-Word
IO-Long Word
It-Another OperatIon
V: Vector #
(to be continued)
730
MOVE
Mov.O.I.
MOVE
Mov. 10 Con
dillon Codes
MOVE
d
d
d
d
d
d
s
d
d
d
d
d
d
d
d
d
d
d
d
d
d
d
d
d
d
s Imm
W dSR
Move 10 from
sSR
StaI05R.g
L s USP
MOVE
Move to from
dUSP
User SP(Al)
W dM
MOVEA
Move A:fdress L dM
W sXn
MOVEM
Mov. Mulltpl.
dXn
RegIsters
Move
Peripheral
(An)
::
deAn)
::
d(An.Xi) Abs.W
::
::
Abs.L
,-I.. m.d
d(PC.Xi) doSR/CC
::
#
d(PC)
::
26-2n
2 6 2n
28'2n
282n
d
s
2
2
2
2
2
4
4
4
6
4
4
4
2
2
2
2
2
4
4
4
6
4
4
6
2
4
4
8
8
10
12
14
12
16
12
14
8
4
4
12
12
14
16
18
16
10
16
18
12
12
s
d
2
2
12
6
d
d
d
s
4
4
MtwA
MtwEA
MtwEA
MOVEA
MtwEA
MtwA
MtwA
MMA
MtwA
MtwA
MOVA
MOVA
MtwEA
MtwA
M(WA
MtwA
MtwA
MtwA
MtwA
MtwA
MOVA
MOVA
MtwA
MOVA
1
1
4
4
1
2
4
4
2'
2
2
2
2
2
4
4
4
6
4
4
4
2
2
4
4
6
2
12
8
8
12
12
14
16
18
16
20
16
18
12
12
12
20
20
22
24
26
24
28
24
26
20
16
2'
2
2
2
2
2
4
4
4
4
4
4
4
2
2
2
2
2
4
4
4
4
4
4
6
2
2
2
16
12
2
2
,
2
II
8
12
12
14
16
18
i6
20
i6
18
12
12
12
20
20
22
24
26
24
28
24
26
20
18
4
4
4
4
6
6
6
8
6
6
6
4
4
4
4
4
6
6
6
8
6
6
8
4
16
12
18
14
4
4
?
8
2
12
2
2
484n
4 1240 4 1240
1
2
4880
4 1280 4
W s()l
S.d(M)
L s()l
S.d(M)
L s.tml'18
d
d
d
d
d
4
2
2 < 70
144'
i2 2'
8 2
8 2
12 2
12 2
14
2
16 4
18 4
4
16
20 6
16 4
18 4
12 4
12 2
2
12
20 2
20 2
22 2
24 4
26 4
24 4
28 6
24 4
26 4
20 6
16
2
sXn
MOVED
Move ~lCk
W d.()l
MULl
Multlpty
Signed
W d()l
!lULU
Mutllply
tklSlgned
B
IIICD
Neg.t. ilIgll
BW
IIEG
Neg.l.anary L
BW
IIEG!
Neg.l. Mult,
L
(An)
::
d,Xn
MDVl'
(An)
::
::
::
8W counl ()l
counl ::1-8
L count:D'I
counl ::1-8
W count!
8 W s()l
.M
S'(M)
SCM)'
s (M)
S'd(M)
Sd(MX)
s AbsW
sAbsL
sd(PC)
sd(PC.X)
s Imm
s.()l
l
SM
SCM)
S(M)s (M)
Sd(M)
s d(MX)
sAbsW
sAbsL
sd(PC)
sd(PCXI
W HeR
An
On
Addr.
Modi
2
2
20
16
4
4
18 4'
14 4
14 4
18 4
18 4
20 4
22 6
24 6
22 6
26 8
22 6
24 6
18 6
18 4
18 4
26 4
26 4
28 4
30 6
32 6
30 6
34 8
30 6
32 6
26 8
4
22
16
12
12
16
16
18
20
22
20
24
20
22
16
16
16
24
24
26
28
30
28
32
28
30
24
10
6'
6
6
6
6
6
8
8
8
iD
8
8
8
6
6
6
6
6
8
8
8
iD
8
8
iD
6
20
16
16
20
20
22
24
26
24
28
24
26
20
20
20
28
28
30
32
34
32
36
32
34
28
24
4
4
10
16
6
6
24
20
22
18
10 4
14
4 12
2
12 4
14 4 16 4 18 4
2
16
48.4n 6 124n 6 144n 6 124
8
12
10
22
16
0100 0100
20
22
16
0100 0110
01000000
lite trte
IIEE EEEE
0100 1110
0100 1110
0110 IAAA
01 10 OAAA
4
6
16
4
6 20
8 164n
12
16
4
4
14
18
4
6
8
12
ll~
16 4'
12 4
12 4
16 4
16 4
i8 4
20 6
22 6
20 6
24 8
20 6
22 6
16 6
16 4
16 4
24 4
4
24
26 4
28 6
30 6
28 6
32 8
28 6
30 6
24 8
10 4
&1
16
24
16
24
4
0011 AAAO
0010 AAAO
0100 1000
.7-.0
0100 1100
.7 - .0
0100 1000
.7 .0
0100 1100
.7 .0
OOOODDDI
0000 DDDI
0000 DDDI
0000 DDDI
0111 DDDO
!Iet
tE'f'r
Ditto tett'
1 I.en
~:r=J-o
0.
O~i
s'd
- 00
s-OCR
.....
.....
s-'SR
d -MPU
SRd
USP-M
M-"'USP
._-.~
- --
S M
-.".-
Xn 'd
-----
Dlee et'ef'
10EE EEEE
d7-dOt
lOee eeee
d7 - dO
IIEE EEEE
d7- dOt
Condition
Cod
XNZVC
s -Xn
In 'd
lIee tett
s Xn*.
d71000
0000
1100
0100
QQQQ
()l-dbybyles
s-~()l by byles
()t-od by bytes
s '()lbybyles
::-'()l
-.-.-
dO
IAAA
IAAA
IAAA
IAAA
QQQQ
-.00
<78
<82
4 <78 4
<80 4
<74
1100 DDDI
lIte eeee
()lxs .()l
",.00
4 <80
4 <78
<82
<78 4
<80 4
<74
1100 DODO
I ~ e e e e ('
()lxs .()l
-*.00
<74
2 <74
2 <76 4 <78 4
<74
2 <74
2 <76 4 <78
<80
s.2
<70
d 2
12
12
14
16
18
16
20
0100 1000
OOEE EEEE
0 dlO - X--'d
d
d
d.
d
2
2
2
2
4
6
4
6
2
2
2
2
12
20
12
20
2
2
2
2
12
20
12
20
2
2
2
2
14
22
14
22
4
4
4
4
16
24
16
24
4
4
4
4
18
26
18
26
4
4
4
4
16
24
16
24
6
6
6
6
20
28
20
28
0100 0100
5SEE EEEE
O-d 'd
0100 0000
SSEE EEEE
O-d- X -d
d 2
d 2
4
6
2
2
12
20
2
2
12
20
2
2
14
22
4
4
16
24
4
4
18
26
4
4
16
24
6
6
20
28
0100 0110
SSEE EEEE
-d'd
- 00
2
2
2
2
4
6
2
12
8
20
14
16
II
14
2
2
2
2
4
6
12
8
20
14
16
II
2
2
2
2
4
6
14
10
22
16
18
32
4
4
4
4
6
8
4
16
12
24
18
20
34
18
4
4
4
4
6
8
4
18
14
26
4
4
4
4
6
8
4
16
12
24
18
20
34
18
6
6
6
6
8
20
16
28
22
24
1000
1000
1000
1000
0000
DDDI
DODO
DDDI
DDDO
0000
SSEE EEEE
55H teee
I DEE EEEE
IOte teee
SSEE EEEE
d<or>()l~d
00
10
38
22
0100 1000
Diu eeee
1110 r rr 1
SS II IDDD
1110 QQQI
1110 rr rf
1110 QQQI
11100111
SSOI
1011
1001
IIEE
.....
.....
"'U.U.
preCISion
IIOT
LoglCat
Compl.menl
011
IncluSlv, OR
LoglC.1
B!W
L
8/W s.()l
d.()l
L s.()l
d.()l
B'W "Imm
0111
OR Immedlale l sl.. m
l
"A
Push Effect
d
s'
d'
s
d
d
s
2
2
4
6
4
8
8
16
20
22
36
22
4
4
4
12
18
4
4
18
14
10
4
6
4
8
14
20
22
/VeJddress
IIDII.IIOL
fbtate
Without X
Memory
B'W
count~D1
d 2 6+2n
count. #1-8 d. 2 6+20
d 2 8+2n
L counl.1)!
counl.#1-8 d~ 2 8+20
W count1
d
2'
<.Maxlmum value
#:: Number of Program Bytes
~
2'
12
2'
14
4'
16 4'
18 4'
16 6'
20
Address Relister #
C; Test Condition
0; Data Reaister
P; Displacement
Q: QuiCk Immediate Data
r; Source Register
IS
()l<or>s-()l
d<or>#'~d
- 00
s--(SP)
-----.
~c
- 00
c~
R; Destination Register
S; Slle; OO-Byte
01 -- Word
IO-long Word
ll--Another OperatIon
V; Vector
* * .The
d<or>()l'~d
#:
e;Source Effective Address
E;Oestlnltion Effective Address
12
IDDD
IDDIl
IDDD
EEEE
()l<or>s-()l
(to be continued)
(An)
An
On
Addr.
Modo
(An) ..
-(An)
'-
It
d, 1
1I0XII.ItOXL S W count1l1
count-III-8d, 1
Rotate
d- 1
count()1
through X
l
countIII-8d 1
dMemory
count1
\.()1
d- 1
SlCO
dSubtract
\ ("')
d(An)
d(An,Xi) Abs.W
Il
Il
Abs.L
II
Il
d(PC)
::
d(PC.Xi)
II
~ ~~m:,C~
:: -
12
1"
12
l'
14
B cc
SSII
550 I
10 II
100 I
II EE
0000
0000
010 I
ccce
IIEE EEEE
If ectrue.l's 'd
Else. a's 'd
100 I
1001
1001
100 I
100 I
1001
DDIJI
DODO
0001
DODO
AAAO
MAl
SSEE EEEE
d()1'd
()1s-[)r
d()1-d
24
]6
0000 0100
SSEF. EEEE
d :: 'd
20
28
010 I QQQI
S5EE EEEE
d :: 'd
100 I
100 I
100 I
100 I
0100
S5000rrr
5500 I r rr
1000 Orr r
1000 I rr r
01000000
4'
16
4'
18
4'
16
6'
20
16
18
16
20
18
14
26
20
IS
20
IB
d.
I 2
d
s 1
1- 2
s 2
B W ~()1
do[)r
s[)r
l
1Io[)r
W 110'"
l
d'"
SUIA
Sublract
A.:ldress
SUll
Subtract
BW s:lmm
l
12
2 64
8
16
s-Imm
12
14
SOOA
1'1 4
SUBA
8
8
8
12
8
20
14
12
14
12
8
20
14
12
14
14
10
22
16
14
16
16
12
24
18
16
18
SUBA
SUBA
16
28
16
28
18
30
20
]2
12
16
12
16
14
22
~I
16
11
24
18
16
18
22
]4
20
]2
18
26
16
24
20
16
28
22
20
22
8
10
r~l~
rrrl
QQQf
rr' f
QQQf
0 I0 I
RRR I
RRR I
dlRlts
Scc
Set
Conditionally
SUI
Subtract
Blilary
1 10.
1110
1110
1110
1110
1110
1000
1000
6'10
6.10
8 + 10
S + 10
l'
14
11
14
12
14
20
18
20
18
16
18
55tt
OUDD
0000
0000
0000
EEEF.
0",
I rr, dlOslOX'd
B W \'lmm3
\'lmm3
l
Subtract
2'
2
4
4
16
24
4
4
fftt
10EE EEEE
lOre f f f t
Ilee f f f t
Ilee f f t t
[)r's~[)r
,., I''''
~lCk
sun
B W \-[)l
Subtract
Multiprec!Slon
SWA'
Swap ReglSter Halves
TAS
Test and Set
Operand
TST
(,.,)
s[)r
s- (An)
d
d
d
d
1
2
18
30
1
2
RRR I
RRR I
RRRI
RRR I
1000
I"X~d
[)r(3116)~-'
\)1(150)
d
14
BW
Test
8
12
d-
UIUI
14
8
12
16
18
20
10
14
4
4
12
16
4
4
14
18
18
12
16
IlIA
Branch
Always
- 00
16
20
0100 10 10
SSEE EEEE
testd 'ec
- 00
0100 II 10
0101 lAM
In--SP
(SP) - 'An
ecce
pppp PPPP
.fcctrue.
bra
not
bra
bra not
~ra
taken
taken
taken
taken
10
8
10
14'
10
10
0110
0110 0000
pppp pppp
PC+dISP-PC
20
0110 0001
pppp PPPP
PC- (SP),
PC ..... drsp -PC
20
dlsP
dilP
Branch
to Subroutine
Dice
dlSP
dlSD Imm
Decrement
Counter, &
Branch Until
Condition
counter
10
1
4 112
14
cc
false
true
fatse
Countor
1
I
eKpned
-.00
testd 'ec
I--blt 7 of d
dlsP
1511
.....
.....
II EE EEEE
dlsp
dlsP
.....
.....
0100 10 10
~---'--'---
Icc
Branch
Conditionally
UU.
22
12
lklhnk
0.
~x.,gJ
Immediate
sun
Condition
Cod. .
XNZVC
Iranch
PC+'dISP~PC
010 I
ccce
yes
True or
Count' I
1M'
Jump to
lSI
Jump to
Subroutine
III'
4
16
10
14
10
12
10
14
0100 1110
II EE EEEE d-PC
18
22
18
20
18
22
0100 1110
10EE EEEE
PC~
(Sp)d 'PC
0100 1110
0111 0001
illS IT
ResetE'ter
nalDevlces
132
0100 II 10
01 II 0000
assertRESETprn
1111
20
0100 II 10
0111 0011
Return Irom
Exception
IITII
(SP) --SR
(SP)"-PC
20
0100 1110
0111 0 II I
tt~eratlon
(SP)+~CC
(SP) . . . -PC
Return from
Subroutine
Restore CC
ITS
16
34
0111 0 101
0100 1110
0111 0010
0100 1110
0100 VVVV
0100 1110
0111 0 I 10
II-SR.W"t lor
Interrupt
PC-~ (ssp),
SR~ (SSP),
(Vector) -PC
IIVlttrenPC(SSPlSR (SSP'
(TRAPVvector)'PC
~". NOP
0100 1110
.....
.....
Return trom
Subroutine
STOI'
LoadSR'Stop
TIIA'
Trap
34
4
TlIA'Y
Trap If
tNerflow Set
Note: Aef.r to Conclltlon Code Computations
as for COndttlon Code
. Word only
< : Ma.imum
v.tut
Trap taken
Trap not
takjn
ht Destination EA Mode
P:Olsp!aeement
R;Oestmatlon Rellster
$: Size; 00- Byte
OI-Word
IO-lona Word
11- Another Operation
V: Vector #:
732
('"
'he MOVE ,n"rue"on)
Ol-Byte
IO-Lonl Word
ll-Word
*.*
Operation
0000
Bit Manipulation/MOVEP/lmmediate
0001
Move Byte
0010
Move Long
0011
Move Word
0100
Miscellaneous
0101
ADDO/SUBOISee/DB ee
0110
0111
Bee
MOVEO
1000
OR/DIV/SBCD
1001
1010
SUB/SUBX
(Unassigned)
1011
CMP/EOR
1100
AND/MUL/ABCD/EXG
1101
ADD/ADDX
1110
Sh ift/R otate
1111
(Unassigned)
14
13
11
12
10
Register
Effective Address
Static Bit
15
14
13
12
11
10
Type
Effective Address
Bit Type Codes: TST = 00, CHG = 01, CLR = 10, SET = 11
MOVEP
15
14
13
12
11
10
Register
Op-Mode
Register
OR Immediate
15
14
13
12
I0 I0 I0 I0
11
0
10
I0
Effective Address
Size
AND Immediate
15
14
13
12
11
10
I I I I I
0
"'71')1')
Size
Effective Address
=I
15
13
12
11
14
13
12
14
13
12
14
13
12
I I
10
10
Size
Effective AddrAss
ADD Immediate
15
I0 I0
11
I I I I
0
11
10
Size
Effective Address
EOR Immediate
15
Size
Effective Address
CMP Immediate
15
I0 I0
11
10
I0
Size
Effective Address
MOVE Byte
14
15
13
12
11
10
Destination
Register
Source
Mode
Register
Mode
14
13
12
11
10
Destination
Register
Source
Mode
Mode
Register
14
13
12
11
10
Destination
Register
Source
Mode
Register
Mode
NEGX
15
13
12
11
10
14
13
12
11
10
14
13
12
11
10
14-
Size
Effective Address
MOVE from SR
15
0
I I
1
Effective Address
CLR
15
0
734
Size
Effective Address
14
13
12
11
10
Size
Effective Address
MOVE to CCR
15
14
13
12
11
10
Effective Address
NOT
15
14
13
12
11
10
Size
Effective Address
MOVE to SR
15
14
13
12
11
10
Effective Address
NBCO
15
14
13
12
11
10
Effective Address
PEA
15
14
13
12
11
10
Effective Address
SWAP
15
14
13
12
11
10
3
Register
10111010111010101011101010
MOVEM Registers to EA
15
14
I0 I 1
13
1 0
12
1 0
11
1 1
10
1 0
1 0
1 0
1 1
1 Sz
Effective Address
EXTW
15
14
13
12
11
10
543
Register
10111010111010101110101010
EXTl
15
14
13
12
11
10
543
I0 I0
0
Register
TST
15
14
13
12
11
10
6
Size
011101011101110
Effective Address
TAS
15
14
13
12
11
10
543
Effective Address
14
13
12
I0 I1 I0 I0
11
1 1
10
I1
1 0
I 0 I 1 I 5z
Effective Address
TRAP
8
I0 I1 I0 I0 I1 I1 I1 I0
I1
1 0
15
14
13
12
11
10
Vector
LINK
15
14
13
12
11
10
I0 I1 I0 I0 I1 I1 I1 I0 I0 I1 I0 I1 I0
Register
UNLK
15
I
14
1
13
12
11
10
543
0
Register
MOVE to USP
15
14
13
12
11
10
I0 I1
0
Register
I0
14
1 1
13
1 0
12
1 0
11
10
1 1
1 1
1 1
I0
1 1
1 1
1 0
1 1
Register
RESET
15
14
13
12
11
10
/0111010111111101011111110
01010
NOP
15
14
13
12
11
10
1011101011111110101111111001011
STOP
15
14
13
12
11
10
1011\0101111111010\1\11110011\0
RTE
15
14
13
12
11
10
I1 I1
RTS
15
14
13
12
11
10
01110101111\1101011111110111011
TRAPV
15
14
13
12
11
10
10110101111111010111111\0111110
736
14
13
12
11
10
15
14
13
12
11
10
JSR
Effective Address
JMP
15
14
[~J>
13
12
11
10
10
10
1 1
1 1
1 1
13
12
11
11
11
Effective Address
CHK
15
14
10
Effective Address
Register
LEA
15
14
13
12
11
10
Effective Address
Register
14
13
12
11
10
I0
Data
Effective Address
Size
SUBQ
15
14
13
12
11
10
Data
8
1
Effective Address
Size
Sec
15
14
13
12
11
10
Condition
1 1
1 1
Effective Address
DBee
15
14
13
12
11
10
Condition
0
Register
14
[11
13
11
12
11
10
10
8 bit Displacement
Condition
BSR
15
14
13
12
11
10
8 bit Displacement
14
13
12
11
10
Register
I0
737
Data
15
14
13
12
11
10
Register
B
000 001
100 101
Op-Mode
Effective Address
Op-Mode
L
010
Dn V EA-+Dn
110
EA V Dn -+EA
DIVU
14
13
12
I1 I0
14
13
12
14
13
12
15
11
10
Register
Effective Address
DIVS
15
11
10
Register
Effective Address
SBCD
15
11
10
Destination
Register
Source Register
=0, memory -
memory
=1
15
14
13
12
11
10
Register
B
15
Effective Address
000 001
100 101
011
SUBX
7
Op-Mode
14
Dn-EA-+Dn
EA-Dn-+EA
An-EA-+ An
13
12
11
10
Destination
Register
Source Register
=0, memory -
memory
=1
14
13
12
11
10
Register
B
000 001
011
CMPM
15
14
Op-Mode
Effective Address
Op-Mode
L
010
Dn-EA
111
An-EA
13
12
11
10
Register
Size
0
Register
EOR
15
14
13
12
11
10
Register
Effective Address
15
14
13
12
11
10
Register
B
7
Op-Mode
Op-Mode
L
Dn 1\ EA-+Dn
EA 1\ Dn -+EA
738
Effective Address
14
13
12
13
12
13
12
11
10
Register
Effective Address
MULS
15
14
11
10
Register
Effective Address
ABCD
14
15
10
11
Destination
Register
Source Register
=0, memory -
memory
=1
EXGD
14
15
13
12
11
10
Data Register
Data Register
EXGA
15
14
13
12
11
10
Address Register
0
Address Register
EXGM
15
13
14
12
11
10
Address Register
Data Register
15
12
13
11
10
Register
Op-Mode
Effective Address
Op-Mode
8
On + EA~Dn
EA + On ~EA
An + EA~An
ADDX
15
14
13
12
10
11
Destination
Register
Source Register
=0, memory -
memory
=1
14
13
12
11
10
Count/Register
Register
Memory Shifts
15
I1
14
13
12
11
10
Type
739
Effective Address
Table 27 lists the number of clock periods required to compute an instruction's effective address. It includes fetching
of any extension words, the address computation, and fetching of the memory operand. The number of bus read and
write cycles is shown in parenthesis as (r/w). Note there are
no write cycles involved in processing the effective address.
(NOTE) The number of periods includes instruction fetch and all applicable operand fetches and stores.
Byte, Word
Long
Register
On
An
o (O/O)
OlDIe)
O{O/O)
o (O/O)
An@
An@+
Memory
Address Register Indirect
Address Register Indirect with Postincrement
4{1/0)
4{1/0)
8{2/0)
8(2/0)
An@An@(d)
An@{d,ix)*
xxx. ~'.J
6(1/0)
8{2/0)
10(2/0)
8{2/0)
10{2/0)
12(3/0)
14(3/0)
12{3/0)
xxx.L
PC@(d)
Absolute Long
Program Counter with Displacement
12{3/0)
8{2/0)
16(4/0)
12(3/0)
PC@(d,ix)*
#xxx
10{2/0)
4{1/0)
14{3/0)
8(2/0)
The size of the index register Ox) does not affect execution time.
740
On
4(1/0)
4(110)
8(210)
An
4(1/0)
4(1/0)
8(2/0)
An@
An@+
Destination
An@-
An@(d)
An@(d,ix)*
8(1/1)
8(1/1)
12(211 )
8(1/1)
8(111)
12(2/1)
8(111 )
8(111 )
12(2/1 )
12(2/1 )
12(211 )
16(3/1)
14(2/1)
14(2/1)
18(3/1)
An@+
An@An@(d)
8(210)
10(2/0)
12(3/0)
8(2/0)
10(2/0)
12(3/0)
12(211)
14(211)
16(311)
12(211 )
14(211)
16(311 )
12(2/1 )
14(2/1 )
16(311 )
An@(d,ix)*
xxx.W
xxx.L
PC@(d)
PC@(d,ix)*
#xxx
14(3/0)
12(3/0)
16(4/0)
14(3/0)
12(3/0)
16(4/0)
18(311)
16(311)
20(4/1 )
18(3/1)
16(3/1)
20(4/1)
18(3/1 )
16(3/1 )
20(411 )
16(3/1)
18(3/1)
20(4/1)
22(4/1)
20(4/1)
24(5/1)
12(3/0)
14(3/0)
8(210)
12(3/0)
14(3/0)
8(2/0)
16(3/1 )
18(311)
12(2/1)
16(311 )
18(311)
12(2/1)
16(3/1)
18(3/1 )
12(2/1 )
20(4/1)
22(4/1)
16(3/1 )
Source
On
An
An@
xxx.W
12(2/1)
12(2/1)
16(3/1)
xxx.L
16(3/1 )
16(3/1)
20(4/1)
18(3/1)
20(3/1)
22(4/1)
24(4/1)
22(4/1)
26(5/1)
16(3/1 )
18(3/1)
20(4/1)
20(4/1 )
22(4/1)
24(5/1)
22(4/1)
20(4/1)
24(5/1)
26(511)
24(511 )
28(6/1 )
22(4/1)
24(4/1)
18(3/1)
20(4/1)
22(4/1)
16(3/1 )
24(5/1 )
26(5/1)
20(4/1 )
- The size of the index register lix) does not affect execution time.
An
4(1/0)
4(1/0)
12(3/0)
An@
An@+
Destination
An@-
An@(d)
An@(d,ix)*
On
An
An@
On
4(1/0)
4(110)
12(3/0)
12(1/2)
12(1/2)
20(3/2)
12(1/2)
12(1/2)
20(3/2)
12(1/2)
12(1/2)
20(3/2)
16(2/2)
16(2/2)
24(4/2)
18(2/2)
18(2/2)
26(4/2)
xxx.W
16(2/2)
16(2/2)
24(4/2)
xxx.L
20(3/2)
20(3/2)
28(5/2)
An@+
An@An@(d)
12(3/0)
14(3/0)
16(4/0)
12(3/0)
14(3/0)
16(4/0)
20(3/2)
22(3/2)
24(4/2)
20(3/2)
22(3/2)
24(4/2)
An@(d,ix)*
xxx.W
xxx.L
PC@(d)
PC@(d,ix)*
#xxx
18(4/0)
16(4/0)
20(5/0)
18(4/0)
16(4/0)
20(5/0)
26(4/2)
24(4/2)
28(5/2)
26(4/2)
24(4/2)
28(5/2)
20(3/2)
22(3/2)
24(4/2)
26(4/2)
24(4/2)
28(5/2)
24(4/2)
26(4/2)
28(5/2)
30(5/2)
28(5/2)
32(6/2)
26(4/2)
28(4/2)
30(5/2)
32(5/2)
30(5/2)
34(6/2)
24(4/2)
26(4/2)
28(5/2)
30(5/2)
28(5/2)
32(6/2)
28(5/2)
30(5/2)
32(6/2)
34(6/2)
32(6/2)
36(7/2)
16(4/0)
18(4/0)
12(3/0)
16(4/0)
18(4/0)
12(3/0)
24(4/2)
26(4/2)
20(3/2)
24(4/2)
26(4/2)
20(3/2)
24(4/2)
26(4/2)
20(3/2)
28(5/2)
30(5/2)
24(4/2)
30(5/2)
32(5/2)
26(4/2)
28(5/2)
30(5/2)
24(4/2)
32(5/2)
34(6/2)
28(5/2)
Source
- The size of the index register (jx) does not affect execution time.
EOR
MULS
MULU
OR
SUB
Size
Byte, Word
Long
Byte, Word
Long
Byte, Word
Long
op < ea >, On
4(110) +
6(1/0) +
6(110) +
Byte, Word
Byte, Word
Long
Long
Byte, Word
Long
op<ea>,An
8(1/0) +
6(110) + -*
8(1/0) +
6(1/0) + **
4(1/0) +
6(1/0) + -*
6(1/0) + **
4(1/0) +
opDn,<M>
8(1/11 +
12(1/2) +
8(111) +
12(1/2) +
6(1/0) +
158(1/0) + *
140(1/0) + *
4(1/0) ***
8(110) ***
70(1/0) + 70(1/0) + *
4(110) +
6(1/0) + **
4(1/0) +
6(1/0) + **
8(1/1)+
12(1/2) +
8(111) +
12(1/2)+
8(1/1)+
12(1/2) +
.. total of 8 clock periods for instruction if the effective address is register direct
.. - onlv available effective address mode is data register direct
7111
Size
Byte, Word
ADDI
Long
AD DO
8(1/1) +
8(1/0)
8(1/0)
12(1/2) +
Byte, Word
SUBO
12(2/1) +
20(3/1) +
8(2/0)
8(2/0)
8(2/0) +
14(3/0)
14(3/0)
12(3/0) +
8(2/0)
12(2/1) +
16(3/0)
20(3/2) +
20(3/2) +
Long
4(1/0)
Byte, Word
8(2/0)
16(3/0)
Byte, Word
8(2/0)
Long
Byte, Word
Long
16(3/0)
Long
SUBI
8(2/0)
16(3/0)
Long
ORI
Long
Long
MOVEO
12(2/1) +
20(3/2) +
8(1/0)*
Byte, Word
EORI
op#,M
4(1/0)
Long
CMPI
op #, An
Byte, Word
Byte, Word
ANDI
op#, On
8(2/0)
16(3/0)
4(1/0)
8(1/0)
8(1/0)*
8(1/0)
12(211) +
12(2/1) +
20(3/2) +
8(1/1)+
12(1/2) +
Register
4(1/0)
Size
Byte, Word
6(1/0)
Long
Byte
Memory
8(1/1) +
12(1/2) +
Byte, Word
Long
6(1/0)
4(1/0)
6(1/0)
8(1/1)+
8(111) +
Byte, Word
4(1/0)
12(1/2) +
8(1/1) +
Long
6(1/0)
12(1/2) +
Byte, Word
Long
4(1/0)
6(1/0)
12(1/2) +
Byte, False
4(1/0)
8(111)+
Byte, True
6(1/0)
8(111) +
Byte
4(1/0)
10(1/1) +
Byte, Word
4(1/0)
4(1iOi +
Long
4(1/0)
4(1/0) +
8(1/1)+
742
Register
Memory
Byte, Word
6 + 2n(1/0)
8(1/1) +
Instruction
ASR,ASL
LSR, LSL
ROR, ROL
ROXR, ROXL
Long
8 + 2n(1/0)
Byte, Word
6 + 2n(1/0)
8(1/1) +
Long
8 + 2n(1/0)
Byte, Word
6 + 2n(1/0)
8(1/1)+
Long
8 + 2n(1/0)
Byte, Word
6 + 2n(1/0)
8(1/1) +
Long
8 + 2n(1/0)
Dynamic
Size
Memory
Register
Memory
8(1/1)+
12(2/1) +
Byte
8(1/0)*
Long
Byte
10(1/0)*
Long
Byte
8(1/0)*
Long
Byte
Long
Static
Register
6(1/0)
8(1/1)+
8(1/1)+
12(2/0)*
12(2/1) +
14(2/0)*
12(2/1) +
12(2/0)*
4(1/0) +
10(2/0)
8(2/0) +
Displacement
Trap or Branch
Taken
Trap of Branch
Not Taken
Byte
10(2/0)
8(1/0)
Word
10(2/0)
12(2/0)
Byte
10(2/0)
Word
10(2/0)
Byte
18(2/2)
Word
18(2/2)
CCtrue
12(2/0)
CCfalse
10(2/0)
14(3/0)
40(5/3) + *
10(1/0) +
34(4/3)
34(5/3)
4(1/0)
HD68000-4, HD68000-6, HD68000-8, H D 6 8 0 0 0 - 1 0 - - - - - - - - - - - - Table 36 JMP, JSR, LEA, PEA, MOMEM Instruction Clock Periods
An@
An@+
An@-
JMP
JSR
8(2/0)
LEA
16(2/2)
4(1/0)
10(2/0)
18(2/2)
8(2/0)
12(2/0)
PEA
12(1/2)
16(2/2)
20(2/2)
MOVEM
Word
12+4n
(3+n/0)
12+4n
(3+n/0)
16+4n
(4+n/0)
18+4n
(4+n/0)
16+4n
(4+n/0)
M-+-R
Long
12+8n
(3+2n/0)
12+8n
(3+2n/0)
16+8n
(4+2n/0)
18+8n
(4+2n/0)
MOVEM
Word
8+4n
(2/n)
Long
8+8n
(2/2n)
Instr
R-+-M
Size
An@(d)
An@(d,ix)*
14(3/0)
22(2/2)
xxx.L
12(3/0)
20(3/2)
PC@(d)
18(2/2)
14(3/0)
22(2/2)
8(2/0)
12(3/0)
16(2/2)
20(3/2)
8(2/0)
16(2/2)
12(2/0)
20(2/2)
16+4n
(4+n/0)
16+8n
(4+2n/0)
18+4n
(4+n/0)
16+8n
(4+2n/0)
20+4n
(5+n/0)
20+8n
(5+2n/0)
xxx.W
10(2/0)
18(2/2)
8+4n
(2/n)
12+4n
(3/n)
14+4n
(3/n)
12+4n
(3/n)
16+4n
(4/n)
8+8n
(2/2n)
12+8n
(3/2n)
14+8n
(3/2n)
12+8n
(3/2n)
16+8n
(4/2n)
PC@(d,ix)*
10(2/0)
18+8n
(4+2n/0)
Table 37 indicates the number of clock periods for the multiprecision instructions. The number of clock periods includes
the time to fetch both operands, perform the operations, store
the results, and read the next instructions. The number of read
and write cycles is shown in parenthesis as: (r/w).
In Table 37, the headings have the following meanings: Dn =
data register operand and M = memory operand.
Size
op On, On
Byte, Word
4(1/0)
opM,M
18(3/1)
Long
Byte, Word
8(1/0)
30(5/2)
12(3/0)
20(5/0)
18(3/1)
30(5/2)
Long
Byte, Word
Long
4(1/0)
8(1/0)
ABCD
Byte
6(1/0)
18(3/1)
SBCD
Byte
6(1/0)
18(3/1)
SUBX
Table 38 indicates the number of clock periods for the following miscellaneous instructions. The number of bus read and
write cycles is shown in parenthesis as: (r/w). The number of
clock periods plus the number of read and write cycles must be
added to those of the effective address calculation where indicated.
744
Size
Word
Memory
Memory -+ Register
12(2/0)
12(2/0)
12(2/0) +
16(2/2)
16(4/0)
24(2/4)
24(6/0)
4(1/0)
Long
4(1/0)
16(2/2)
4(1/0)
4(1/0)
132(1/0)
20(510)
20(5/0
16(4/0)
4(010)
4(1/0)
12(3/0)
RTR
RTS
STOP
UNLK
Word
SWAP
Register
8(1/1)+
12(2/0) +
RESET
NOP
Memory
6(110)
RTE
MOVE to USP
6(1/0)
Long
LINK
MOVE from USP
Register
4(110)
Periods
50(4/7)
Address Error
Bus Error
50(4/7)
Interrupt
44(5/3)*
Illegal Instruction
34(4/3)
Privileged Instruction
34(4/3)
Trace
34(4/3)
7AC:
APPENDIX
The Mask Version Deviation Between 68000R and 68000
Table 40 DC Characteristics (Vee = 5V 5%. Vss = OV, Ta = 0-+70C, unless otherwise noted.)
~,:::sion
Item
Symbol
68000
68000R
Test Condition
min
typ
max
Test Condition
Unit
min
typ
max
VIH
2.0
VIL
VSS-O3
Vee
0.8
2.0
VsS-O3
Vee
0.8
2.5
1.0
20
2.0
7.0
jl.A
AC~L~
fi>"Lo
-IPL VPA
lin
@5.25V
HALT. RES
Three-State
(Off Statel
Input Current
AS. AI
- A.td-o - D 15
FCo -~ LD RIW.
A
Dl5S",
ITSI
@2.4V/0.4V
E*
Output High
Voltage
VOH
IOH=-400jl.A
20
2.4
IOH=-400jl.A
2.4
0.5
IOL =1.6mA
0.5
IOl =3.2mA
0.5
0.5
0.5
IOL=5.0mA
0.5
IOL=5.3mA
1.5
Clock Frequcney=8MHz
1.0
Vin=OV, Ta = 25C,
Frequency = 1 MHz
10.0
20.0
pF
IOL =1.6mA
\oj. =3.2mA
IOL=5.3mA
VOL
ASt1&s
E,
-D 15 , LDS,
R/W, UD ,VMA
IOL =5.3mA
Power Dissipation
Po
Capacitance
C in
Vin=OV, Ta = 25C,
Frequency = 1 MHz
jl.A
HALT
RES
Vee- 0 .75
Output" Low"
Voltage
746
10.0
20.0
0.5
0.5
Symbol
68000R
68000
4 MHz
6 MHz
S MHz
10 MHz
4 MHz
6MHz
SMHz
HD6SOOO-4
HD6SOoo-6
HD6SOoo-8
H 068000-1 0
HD680oo-4
HD680006
HD68000-8
min
min
min
min
min
min
max
max
max
min
max
max
max
Unit
max
Frequency 01 Operation
2.0
4.0
2.0
6.0
2.0
S.O
2.0
10.0
2.0
4.0
2.0
6.0
2.0
S.O
Clock Period
leye
250
500
167
500
125
500
100
500
250
500
167
500
125
500
MHz
ns
tCL
115
250
75
250
55
250
45
250
115
250
75
250
55
250
ns
ICH
115
250
75
250
55
250
45
250
115
250
75
250
55
250
ns
ICf
10
10
10
10
10
ns
10
10
10
10
10
10
ICr
10
10
10
ns
ICLAV
90
80
70
55
90
90
90
ns
ICHFCV
90
SO
70
60
ns
ICHAZx
120
100
SO
70
120
100
100
ns
tCHAZn
20
20
20
ns
tCHSLx
SO
--
70
60
55
80
70
70
ns
tCHSLn
20
20
ns
tAVSL
55
35
30
20
20
55
35
30
ns
tFCVSL
SO
70
60
50
ns
tCLSH
90
SO
70
55
90
SO
70
ns
tSHAZ
60
20
30
ns
195
40
240
170
115
ns
170
115
2S5
95
ns
285
180
150
105
ns
tCHSZ
120
100
tSHRH
60
50
40
ao
-
60
337
30
535
40
tSL
tCHRHx
90
80
ns
tCHRHn
ICHRL
90
IAVRL
45
tFCVRL
80
IRLSL
200
25
tCLOO
tCHRZ
ISHOO
Clock low to M,
OS High
285
180
150
70
120
100
20
60
50
30
ao
-
70
60
90
80
70
10
10
10
ns
80
70
60
90
80
70
ns
20
45
25
80
70
60
50
200
ns
10
50
80
60
140
80
ns
90
SO
SO
ns
SO
100
55
120
70
120
100
SO
60
40
30
20
60
55
35
30
20
55
IOICL
30
25
15
15
30
40
tOOSL
tSHOAH
240
160
120
90
240
tSHOI
tSHBEH
a
a
a
tOALOI
ISO
120
90
65
180
tRHrf
200
200
200
200
200
70
60
60
90
70
AS,
00 Width
AS, OS High
tSH
Impedance
Time)
90
70
SO
Clock High to
BG
Low
tCHGL
90
SO
Clock High to
1m High
tCHGH
90
SO
70
2S5
140
ns
ns
ns
30
ns
ns
30
15
nS
160
120
nS
ns
120
90
ns
200
200
nS
SO
70
ns
90
80
70
ns
35
25
ns
ns
8R Low to BG Low
tBRLGL
1.5
3.0
1.5
3.0
1.5
3.0
1.5
3.0
1.5
3.0
1.5
3.0
1.5
3.0
Clk.Per.
BR High to BG High
tBRHGH
1.5
3.0
1.5
3.0
1.5
3.0
1.5
3.0
1.5
3.0
1.5
3.0
1.5
3.0
Clk.Per.
tGALGH
1.5
3.0
1.5
3.0
1.5
3.0
1.5
3.0
1.5
3.0
1.5
3.0
1.5
3.0
Clk.Per.
tGLZ
120
100
SO
70
1.5'
1.5'
1.5'
BG Width High
tGH
1.5
1.5
1.5
1.5
1.5
tCLVML
70
70
55
100
tErf
25
25
90
S5
70
100
SO
tCLE
90
25
25
25
mA low to E High
AS, 00" High to VJ5A High
tVMLEH
325
240
200
150
325
tSHVPH
240
160
120
90
tELAI
55
35
30
10
55
1.5
1.5
1.5
20
50
50
50
1.5
25
-SO
-80
-SO
450
BGACK Width
tBGL
1.5
tASI
30
tBELOAL
50
tELSI
-SO
E Width High
tEH
900
600
E Width low
tEL
1400
900
700
tCIEHX
80
SO
SO
tCHDO
tELDOZ
60
40
tRLOO
55
35
30
30
tHRPW
10
10
10
E low to AS,
OS Invalid
747
ns
1.5
Clk.Per.
SO
70
ns
S5
70
ns
25
25
ns
240
200
ns
240
160
120
ns
35
50
ns
50
30
50
-SO
-SO
-80
ns
350
900
600
450
ns
550
1400
900
700
ns
80
ns
20
10
20
0
20
30
20
1.5
1.5
25
20
1.5
20
Clk.Per.
ns
ns
ns
20
ns
Clk.Per.
ns
1)
2)
3)
4)
5)
SLAVE
Address Device
Set R/W to Read
Place Function Code on FC o - FC 2
Place Address on AI - An
Assert Address Strobe (AS)
Assert Upper Data Strobe (UOS) or
Lower Data Strobe (LOS)
Input Data
1) Decode Address
2) Place Data on 00 - 0, or D. - Ou
3) Assert Data Transfer Acknowledge
(OTACK)
Acquire Data
1) Latch Data
Terminate Cycle
1) Remove Data from
00 - 0, or O. - 011
2) Negate OTACK
2) Place Data on 00 - 0, or D. - Ou
3) Assert Upper Data Strobe (UOS) or Lower
Data Strobe (LOS)
1)
2)
3)
4)
Terminate Cycle
1) Negate l5TA&
sa
SO S1 S2 S3 54 S5 S6 S7
S9 S10S11S12S13S14S15516517S18519
CLK
\~~====~~~~/~
UDSor~ =~~~---~_\~========~/-----------~r:--1=.==~\~-_~~----~1
\~ __ ).
R/W
OTACK
D. - 015
FC - FC
o
2
~
(
r-
r--
c::(~-===~}-
.:::x__________________x::
t- - - -- - - - - - -
--..I
748
eLK
'~______________
AS
\~
Ir--------------------------~\~
UDS/LDS - - - - - - ,
________________~
________
-J
Rm -------------------------------------------------------------------------------------------------------DTACK
Oo - DIS
a
FCo - FC
BERR
HAIT
\(::.====~~
r=::x~===~--------JX
x:::
\~
~/~================================~==
(
__________
----------\~_-_-_-_~_\~
_____________________~/
I-- - - - - - Read -
-+ ----
- - -
Halt- -
+ --
-Re-run -
SO S1 S2 S3 S4 S5 S6 S7 SO S1 S2 S3 S4 S5 S6 S7 SO S1 S2 S3 S4 w
w w S5 S6 S7
CLK
AI-Au
AS
UDS
05S
R/W
i5fACj(
D. - DIS
Do -0 7
FCo - F~
::x
\
<
<
t-- - - -
Reed -
>
>
X
\
\
I
I
>
)
Write -
>-
<
>>-
<
+ --- -
7AQ
>-
\
\
<
<
-+ - - -
>-<
Slow Reed -
-...,
:s::
c
G)
CO
8
o
~
9.5 clocks-----f
1.5 clocks
ClK
A4 - Au
..JLnnSlJLfU1Il..fLIUl..,
-- >-<
I
I
'l
I
I
I
II
'1
I
I
AS
UOS
: I
I
I
I
l'
0. - 015
I
I
'\.
_ I - -_ _.(f----------...,Ir------{~--
0, --~---_
~--
FCo - FC2
_>--<__
I
:
I
I
I
I
:l
I
I
BEAA
o
o
o
:s::
c
G)
CO
o
o
o
,-
V-
!
:s::
c
G)
I~
o
o
7 - .{
\~------fII
)
t
'l
I
I
I
\~------------~
l'
'
,/
\
~
IT""
_--------~
l'
I\.,,______________--1fr-
l l ' /
~~g~------~l'~-----~-----------------+__
~~
.l
HALT
CO
,I
""I
/""?
Write Cycle Without Bus Error
V /
')
I
--------------...LI-----~
I
r---------------~I----~I ___
00
1~
:l
OTACK
r--
G)
'l
~------------------~I----~I---~
C1I
0
'1
~-----------+---~I
ANi
......
I
I
iI
,I
l:
I: r
I
lOS
l"-'/
~
'\.~----------f
__
AI -A 3 __ ) - {
IJlSL~n
~
:s::
l'
Cycle Terminates
CD
o
-a
o
I
LS273
Vee
LS175
0
Level 1
Ho68000
10
1Q
Level 2
20
2Q
Level 3
3D
3Q
10
1Q
Level 4
40
4Q
AI
20
2Q
IPLI
level 5
50
5Q
A2
3D
3Q
IPl2
level 6
60
6Q
Level 7
70
7a
GS
NC
EI
EO
NC
CLK
NC
IPLo
40
4Q
NC
50
5Q
NC
6a
NC
ClK
ClK
levell - level7
lS273 Output
lS175 Output
\\.-_----'1
}'---
.XXX'tti
....
-.a.;....._ _ _ _ _ _ _ _ _ _ _ _ _ _ _...
: _ __
___________x'-___________________~-----
tASI ~ 20 nsec
--------..X i
a..--.t
tASI
751
HD68450---------------
DMAC
-ADVANCE INFORMATIONHD68450
(OC-64)
PIN ARRANGEMENT
FEATURES
HMCS68000 Bus Compatible
Interfaces Directly with HMCS68000/HMCS6800 Peripherals
Memory-to-Device, Deviceto-Memory, and MemorytoMemory Transfers.
Continue Mode and Array Chained, Linked Array Chained
Operations
4 Independent Channels with Programmable Priorities
Handles Byte, Word, and longword Data Sizes
External Request Mode and Auto-Request Mode
Maximum Transfer Rate of 2 Mega Word/Sec
56iR
lSiIA
HIBYTE
lOA!
OWN
iii
5SG
A,
A2
A,
A,
5 As
PROGRAMMING MODEL
A.
51 VDD
A7
o
Chlnnel
Stitul Regilt"
Chlnnel
Error Regilt.r
HD68450
Device
Control Aegiater
Operltion
Control Register
A,0/02
AII /0 3
A. 2/O,
Au/Os
2 AI,/O,
1 AIS/07
SeqUince
Control Regilter
DONE
I contC;:-':ittor I} On.
ACK.
Harmel
Int.fNptVtctor
p., DMAC
Error
InterNPtVtctor
Chinn"
Prloritv R......
Device
Function Codn
31
I
I
A,,/O,
A17 /O,
A.. /Olo
37 Ali/Oil
Az./On
Azl/OU
ACK.
7
Fe.
Fe. 31
Au/O ..
Fe. -,----__________r- AU /0 15
Suo
15
ACK.
ACK I
BEC,
BECI
"BEe.
Momory
Function Codtf
VII
A./Oo
At/O,
Function Coda
(Top View)
OeYice Add'... Reg",
BeIe Add,... Rtgil.er
752
INTRODUCTION OF
THE RELATED
DEVICES
MOS Memories
TTL HD74/HD74S/HD74LS Series
Advanced Low Power Schottky TTL
HD74ALS Series
CMOS Logic HD 14000B/ UB Series
Linear ICs
Interface Circuits
753
MOS Memories
TYPICAL CHARACTERISTICS OF MOS MEMORY
MOS RAM
Mode
Total
Bit
Type No.
Process
Organi
zation
( WO~d)
x bit
HM472114A1
HM472114A2
HM4721143
NMOS
1024x4
450
HM43344
450
640
300
460
450
640
HM6148L
HM4315
CMOS
1024x4
CMOS
1024x4
CMOS
4096x1
HM6147
HM61473
HM6147L
CMOS
4096x1
70
70
85
70
85
85
85
450
640
70
70
55
70
55
70
55
55
HM6147H35*
35
35
HM6147H-45*
45
45
35
CMOS
4096xl
HM6147HL45-
35
45
45
HM61162
120
120
HM61163
150
150
200
200
120
120
HM6116-4
HM6116L2
CMOS
2048x8
HM6116L3
150
150
HM6116L-4
200
200
HM61173HM6117-4*
HM6117L3*
CMOS
2048x8
HM6117L-4*
150
150
200
150
200
150
200
200
HM6167
70
70
HM6167-6
85
85
HM61678
100
100
70
70
HM6167L
CMOS
16384xl
HM6167L-6
85
85
HM6167L8
100
100
HM4716A1
120
320
Htv14715A-2
150
200
250
320
375
410
HM4816A3
100
235
HM4816A3E
105
200
120
270
HM4816A7
150
320
HM48642
150
270
200
335
120
230
HM4864A'15*
150
260
HM4864A20*
200
330
HM4716A3
HM4716A-4
HM4816A-4
NMOS
NMOS
16384xl
16384x1
HM48643
HM4864A12*
NMOS
65536x1
Supply
Voltage
70
HM6147L3
HM6147HL35-
64kbit
300
460
HM6148L6
Dynamic
300
300
HM61486
16kbit
150
200
450
HM6148
16kbit
150
200
HM43343
HM43344L
Static
Cycle
Time
(nsl
min
HM472114-4
HM43343L
4kbit
Access
Time
(nsl
max
* Preliminary
c, HM6116LP Series: 10/olW
** The package codes of P, G, C, and FP are applied to the package materials as follows.
P: Plastic DIP, G: Cerdip, C: Sidebrazed Ceramic DIP, FP: Small Sized Flat Package.
754
(VI
+5
Power
Oissi
pation
(WI
Pin
No.
0.2
18
Package- -
10/ol/20m
+5
18
10/ol/20m
0.1m/0.2
+5
18
5/01/0.2
+5
10/ol/20m
18
0.1m/75m
+5
18
5/o1/5m
0.1m/0.15
18
+5
5/01/0.15
0.lm/0.18
+5
24
c,
201-'/0.16
0.lm/O.2
24
+5
101-'/0.2
+5
0.35
2114L-4
HM6514
2148
21486
HM6504
2147
21473
2147H1
2147H2
2167
21676
21678
16
20m/0.275
16
20m/0.33
+5
2114L2
2114L3
20
11m/0.15 16
Replace
ment
51-'/0.15
+12,
+5,
-5
FP
25m/0.15
+5
C G P
MK41162
MK41163
MK4116-4
21183
21184
21187
Total
Bit
Type No.
32k-bit
HN46332
64k-bit
HN48364
Process
NMOS
HN43128
Mask
128k-bit
CMOS
HN613128*
256k-bit
HN61256
Access
Time
(ns)
max
4096x8
350
0.25
24
8192x8
350
0.225
24
16384x8
32768x4
6000
3m
28
16384x8
250
5/-1/0.1
28
32768x8
65536x4
3000
3m
28
HN462716
16k-bit
HN462716-1
NMOS
2048x8
~
~
HN462716-2
NMOS
HN462532-2
4096x8
HN462732
NMOS
4096x8
HN482732A-25* *
NMOS
4096x8
HN482732A-30* *
NMOS
8192x8
HN482764-4
16k-bit
HN48016*
24
+5
~
~
0.858
~
24
0.543
+5
0.788
+5
NMOS
2048x8
300
24
2716
2716-1
2716-2
TMS2532
TMS25L32
2732
24
+5
0.555
28
+5
0.3
24
450
350
300
HN482764*
HN482764-3*
~
390
HN482732A-20* *
64k-bit
0.555
Replacement
P
, 0 . 555
+5
450
HN462732-2
Electrically Erasable
HN462532L
32k-bit
+5
Package * **
Pin
C
G
No.
390
HN462532
U.V. Erasable
& Electrically
Supply Power
Voltage Dissipation
(V)
(W)
Organization
( WO~d)
X bit
2732A-2
2732A
2732A-3
2764
2764-3
* Preliminary
** Under development
*** The package codes of P, G, and C are applied to the package materials as follows.
P: Plastic DIP, G: Cerdip, C: Side-brazed Ceramic DIP
OUTLINE
DP-20
DP-16
DG-24B
DP-24
DP-28
I
FP24
HD74
Series
HD74S
Series
HD74LS
Series
Propagation
Delay Time
10ns
3ns
10ns
Power
Dissipation
10mW
20mW
2mW
Speed-Power
Product
100pJ
60pJ
20pJ
~-=::
Parameter
= -400/JA)
HD74 Series
HD74S Series
min.
max.
min.
max.
min.
max.
OAV
0.5V
O.5V
HD74LS Series
2.4V
2.7V
2.7V
V IL
0.8V
0.8V
0.8V
V IH
2V
2V
2V
IlL
IIH (V IH min)
-1.6mA
-2mA
40/JA
-O.4mA
V OH (l oH
50/JA
20/JA
SELECTION GUIDE
NAND/NOR/AND/OR GATES
Function
HD74 Series
02
03
04
05
06
07
08
09
05
05
10
10
11
12
12
13
14
08
09
10
11
12
13
14
15
15
20
20
21
22
23
25
26
27
30
32
37
22
38
40
40
125
126
132
133
134
140
756
16
17
20
HD74S Series
00
HD74LS Series
00
01
02
03
04
00
01
02
03
04
22
26
27
30
32
37
38
40
125A
126A
132
-
365A
366A
367A
368A
(to be continued)
HD74 Series
50
51
53
54
HD74S Series
HD74LS Series
51
54
64
65
HD74 Series
HD74S Series
HD74LS Series
HD74S Series
HD74LS Series
55
EXPANDER
Function
Dual 4-input Expanders
60
FLIP FLOPS
Function
HD74 Series
72
107
Monostable Multivibrator
Retriggerable Monostable Multivibrator
Dual Retriggerable Monostable Multivibrators
Hex D-type Flip Flops (with CLR)
Quad. D-type Flip Flops (with CLR)
Dual Monostable Multivibrators (with Schmitt Trigger)
Octal D-type Flip-Flops (with Common CK, and Single-Rail Outputs)
73
74
76
74
73
74A
76
78
112
113
107
109A
112
113
114
114
121
123
174
175
221
174
175
122
123
174
175
221
273
HD74 Series
HD74S Series
HD74LS Series
90
92
93
COUNTERS
Function
Decade Counter
Divide-by-Twelve Counter
4-bit Binary Counter
Presettable Decade Counter/Latch
4-bit Binary Counter/Latch
9qA
92A
93A
176
177
160
161
162
163
167
190
160
161
162
163
190
(to be continued)
- - - - - - - - - - - - - - - - - - - - T T L HD74/HD74S/HD74LS Series
Function
Synchronous 4-bit Binary Up/Down Counter
Synchronous Decade Up/Down Counter
Synchronous 4-bit Binary Up/Down Counter
Decade Counter
4-bit Binary Counter
Dual 4-bit Decade Counters
Dual 4-bit Binary Counters
Dual 4-bit Decade Counters
Synchronous Decade Up/Down Counter
Synchronous 4-bit Binary Up/Down Counter
HD74 Series
191
192
193
290
293
HD74S Series
HD74LS Series
191
192
193
290
293
390
393
490
668
669
HD74LS Series
95B
HD74 Series
95A
96
173
194
195
HD74S Series
194A
195A
HD74 Series
91A
164
166
198
199
HD74S Series
HD74LS Series
91
164
166
299
ENCODERS
Function
1O-line-to-4-line Priority Encoder
8-line-to-3-line Priority Encoder
HD74 Series
147
148
HD74S Series
HD74 Series
HD74S Series
HD74LS Series
148
DECODERS/DEMULTIPLEXERS
Function
BCD-to-Decimal Decoder
Excess 3-to-Decimal Decoder
Excess 3-Gray-to-Decimal Decoder
3-to-8-line Decoder
Dual 2-to-4-line Decoders/Demultiplexers
4-line-to-16-line DecoderiDemuitipiexer
Dual 2-line-to-4-line Decoders/Demultiplexers
Dual 2-line-to-4-line Decoders/Dem~ltiplexers (with Open Collector
Outputs)
4-line-to-16-line Decoder/Demultiplexer (with Open Collector Outputs)
758
42A
43A
44A
-
154
155
156
159
HD74LS Series
42
138
139
154
155
156
HD74 Series
45
145
46A
47A
141
HD74S Series
HD74LS Series
HD74 Series
HD74S Series
HD74LS Series
75
279
279
259
373
374
375
HD74 Series
HD74S Series
145
47
48
49
247
248
249
LATCHES
Function
Quad. Bistable Latches
4-bit Bistable Latch
Quad. SR Latches
8-bit Addressable Latch
Octal D-type Latches (with 3-state Out., Common Enable)
Octal D-type Latches (with 3-state Out., Common Clock)
4-bit Bistable Latch
75
77
HD74LS Series
HD74 Series
HD74S Series
HD74LS Series
83A
85
86
89
170
670
ARITHMETIC ELEMENTS
Function
4-bit Binary Full Adder
4-bit Magnitude Comparator
Quad. 2-input Exclusive-OR Gates
Quad. Exclusive-OR/NOR Gates
Quad. 2-input Exclusive-OR Gates (with Open Collector Outputs)
8-bit Odd/Even Parity Generator/Checker
4-bit Arithmetic Logic Unit/Function Generator
Look-Ahead Carry Generator (for ALU)
Dual Carry Save Full Adders
Quad. 2-input Exclusive-NOR Gates (with Open Collector Outputs)
9-bit Odd/Even Parity Generator/Checker
4-bit Binary Full Adder (with Fast Carry)
Quad. 2-input Exclusive-OR Gates
83A
85
86
86
135
136
--
180
182
H183
283
181
182
-
136
181
266
280
280
283
386
- - - - - - - - - - - - - - - - - - - - - T T L HD74/HD74S/HD74LS Series
DATA SELECTORS/MULTIPLEXERS
Function
16-bit Data Selector/Multiplexer
8-bit Data Selector/Multiplexer (with Strobe)
8-bit Data Selector/Multiplexer
Dual 4-line-to-l-line Data Selectors/Multiplexers
Quad. 2-line-to-1-line Data Selectors/Multiplexers
Quad. 2-line-to-1-line Data Selectors/Multiplexers
8-bit Data Selector/Multiplexer (with Stobe and 3-state Outputs)
Dual 4-line-to-1line Data Selectors/Multiplexers (with 3-state Outputs)
Quad. 2-line-to-1-line Data Selectors/Multiplexers (with 3-state Outputs)
Quad. 2-line-to-1-line Data Selectors/Multiplexers (with 3-state Outputs)
Quad. 2-input Multiplexers (with Storage)
HD74 Series
150
151A
153
157
HD74S Series
251
158
251
257
258
151
157
HD74 Series
HD74S Series
-
HD74LS Series
151
152
153
157
158
251
253
257
258
298
Function
Octal Buffers/Line Drivers/Line Receivers (Inverted 3-state Outputs)
Octal Buffers/Line Drivers/Line Receivers (Noninverted 3'state Outputs)
Quad. Bus Transceivers (Inverted 3-state Outputs)
Quad. Bus Transceivers (Noninverted 3-state Outputs)
Octal Buffers/Line Drivers/Line Receivers (Inverted 3-state Outputs)
Octal
Octal
Octal
Octal
Octal
Bus
Bus
Bus
Bus
Bus
Transceivers
Transceivers
Transceivers
Transceivers
Transceivers
HD74LS Series
240
241
242
243
244
245
640
641
642
645
OUTLINE
I DP-14 I
DP-24
DP20
DP16
~)~,
I
DG16
DG-16A
DG-20
~~
760
DG-24
DG14
making every effort to develop not only SSI but also MSI, to
meet your needs.
LINE-UP
Type No.
Function
LS Series
ALS Series
Propagation delay
10ns
4ns
HD74ALSOO
Power dissipation
2mW
lmW
HD74ALSOl
Speed-power product
20pJ
4pJ
HD74ALS03
HD74ALS04
Hex. Inverters
Performance
max
O.5V
2.7V
V,l
O.SV
V,H
2.0V
I,l
-O.4mA
20pA
Parameter
VOL (IOl
=SmA)
HD74ALS05
HD74ALSOS
HD74ALS09
HD74ALS20
HD74ALS21
HD74ALS22
HD74ALS74
HD74ALS109
HD74ALSl12*
HD74ALSl13*
HD74ALSl14 *
HD74ALS175*
* Preliminaly
OUTLINE
...
I
OP-14
OP-16
OG-14
~\)l
l
'
7R1
OG-16
FEATURES
Low Current Drain . . .. 0.5nA typ./Package (Voo = 5V)
High Noise Margin 45% typo of Voo, 30% min. of Voo
Wide Supply Voltage Range .......... Voo =3-18V
Wide Operating Temperature Range ....... -40-+85C
Capable of driving two lowpower TTL loads, one low
power Schottky TTL load, or two HTL loads over the rated
temperatu re range
Industry-standardized (EIA/JEDEC) family specification
Parameters specified at 5, 10, and 15V supply
Item
Symbol
Rating
DC Supply Voltage
Input Voltage (All inputs)
Voo
-0.5-+18
Unit
V
-0.5-Voo+0.5
Output Voltage
Vin
V out
lin
Operating Temperature
TA
-40-+85
Storage Temperature
T stg
-65-+150
Power Dissipation
Po
300
mW
-0.5-V oo+0.5
10
mA
c
SELECTION GUIDE
NAND Gates
Quad. 2-input NAND Gate
Quad. 2-input NAND Schmitt Trigger
Triple 3-input NAND Gate
Dual 4-input NAND Gate
8-input NAND Gate
HD14011B
HD14093B
HD14023B
HD14012B
HD14068B
NOR Gates
Quad. 2-input NOR Gate
Triple 3-input NOR Gate
Dual4-input NOR Gate
8-input NOR Gate
HD14001B
HD14025B
HD14002B
HD14078B
AND Gates
Quad. 2-input AND Gate
Triple 3-input AND Gate
Dual 4-input AND Gate
HD14081B
HD14073B
HD14082B
OR Gates
Quad. 2-input OR Gate
Triple 3-input OR Gate
Dual 4-input OR Gate
HD14071B
HD14075B
HD14072B
Complex Gates
Quad. Exclusive-OR Gate
Quad. Exclusive-NOR Gate
Triple Gate (Dual 4-input NAND and 2-input
NOR/OR or 8-input AND/NAND)
Dual Expandable AND-OR-INVERT Gate
4-bit AND/OR Selector (Quad. 2 channel
Data Seiector or Quad. Exclusive-NOR Gate)
Dual 5-input Majority Logic Gate
Hex Gate (Quad. Inverter plus 2-input
NOR plus 2-input NAND)
Inverters/Buffers/Level Translators
Dual Complementary Pair plus Inverter
Hex Inverter/Buffer
Hex Buffer
Hex Inverter
Strobed Hex Inverter/Buffer
Hex 3-5tate Buffer
Hex Schmitt Trigger
HD14070B
HD14077B
HD14501UB
HD14506B
HD14519B
HD14530B.
HD14572UB
HD14007UB
HD14049UB
HD14050B
HD14069UB
HD14502B
HD14503B
HD14584B
Decoders/Encoders
BCD-to-Decimal/Binaryto-Octal Decoder
4-bit Latch/4-to-16-line Decoder (high)
4-bit Latch/4-to-16-line Decoder (low)
8-bit Priority Encoder
Dual Binary-to-l-of-4 Decoder/Demultiplexer
Dual Binary-to-l-of-4 Decoder/Demultiplexer
( Inverting)
Display Decoders
BCD-to-Seven Segment Latch/Decoder/Driver
BCD-to-Seven Segment Latch/Decoder/Driver
HD14028B
HD14514B
HD14515B
HD14532B
HD14555B
HD14556B
HD14511B
HD14543B
Multiplexers/Demultiplexers/Bilateral Switches
HD14016B
Quad. Analog Switch/Quad. Multiplexer
HD14066B
Quad. Analog Switch/Quad. Multiplexer
Triple 2-channel Analog Multiplexer/
HD14053B
Demultiplexer
Dual 4-channel Analog Multiplexer/
HD14052B
Demultiplexer
HD14529B
Dual 4-channel Analog Data Selector
HD14539B
Dual 4-channel Data Selector/Multiplexer
8-channel Analog Multiplexer/Demultiplexer
HD14051B
HD14512B
8-channel Data Selector
HD14519B
4-bit AND/OR Selector
HD14558B
BCD-to-Seven Segment Decoder
Schmitt Triggers
Quad. 2-input NAND Schmitt Trigger
Dual Schmitt Trigger
Hex Schmitt Trigger
HD14093B
HD14583B
HD14584B
Flip-Flops/Latches
Dual Type D Flip-Flop
Dual J-,K Flip-Flop
Quad. Latch
Quad. NOR R-S Latch
Quad. NAND R-S Latch
Quad. D-Type Register
Quad. Type-D Flip-Flop
Dual 4-bit Latch
Hex Type-D Flip-Flop
HD14013B
HD14027B
HD14042B
HD14043B
HD14044B
HD14076B
HD14175B
HD14508B
HD14174B
(to be continued)
762
Shft Reg.sters
Phase-Locked Loops
Phase-Locked Loop
Phase Comparator and Programmable Counter
HD14035B
HD14l94B
HD140l5B
HD14014B
HD14021B
HD14034B
HD14006B
HD14557B
HD14517B
HD14562B
Multivibrators
Dual Precision Retriggerable/Resettable
Monostable Multivibrator
HD14024B
HD140l7B
HD14018B
HD14l60B
HD14l62B
HD145l0B
HD14522B
HD14040B
HD14020B
HD14022B
HD14161B
HD14163B
HD14516B
HD14526B
HD14518B
HD14520B
HD14569B
HD14553B
HD14534B
HD14566B
HD14521B
HD14536B
HD14541B
HD14046B
HD14568B
HD14538B
Adders/Comparators
4-bit Full Adder
Triple Serial Adder (Positive Logic)
Triple Serial Adder (Negative Logic)
NBCD Adder
9's Complementer
Look-Ahead Carry Block
4-bit Magnitude Comparator
HD14008B
HD14032B
HD14038B
HD14560B
HD14561B
HD14582B
HD14585B
HD14527B
HD14554B
HD14581B
Parity Checkers
l2-bit Parity Tree
HD14531B
Memories
4x4 Multiport Register
64-bit Static Random Access Memory
256-bit Static Random Access Memory
256-bit Static Random Access Memory
1024-bit Read Only Memory
HD14580B
HD14505B
HD14537B
HD14552B
HD14524B
HD14433B*
HD14443B
HD14447B
HD14549B
HD14559B
* Preliminary
OUTLINE
DP-14
DP16
i"
~
J,'
, l;
DP-24
DG-14
DG-18
Linear ICs
Line Up
Type No.
Functions
General Purpose
HA17741
High Speed
HA17715
Package Code
P
HA17747
Dual
JFET
Operational
Amplifiers
Voltage
Comparators
DG-14
DG-S
DP-S
DP-S
HA17301
DP-14
DG-14
HA17902
DP-14
DG-14
DP-S
Dual
HA170S2/A
HA170S3/A
DP-14
DG-14
Quad.
HA17084/A
DP-14
DG-14
Single
HA1S13
DP-S
Universal
HA1S12
DP-S
HA17903
DP-S
Dual
Fixed
DP-S
Cross-reference
Fairchild ~A741C
Fairchild ~A715C
DG-S
NS LM 145S
DG-S
NS LM 2904
Fairchild ~A74 7C
DG-14
HA170S0/A
Motorola MC3301
NS LM 2902
DG-S
Texas TLOSO/A
DG-S
Texas TLOS2/A
Texas TLOS3/A
Texas TLOS4/A
DG-S
DG-S
NS LM 2903
DG-14
HA1S07
HA17901
Quad.
A/D,D/A
Converters
DP-S
Single
Varieble
Voltage
Regulators
GS
DP-14
HA17904
Quad.
G
DG-14
HA1745S
Operational
Amplifiers
PS
DP-14
DG-14
DG-14
NS LM 2901
Fairchild ~A723C
2""'37V,150mA
HA17723
5V, 1A
HA17S05
T-220AB
Fairchild ~A7S05C
6V,1A
HA17S06
T-220AB
Fairchild
7V,1A
HA17S07
T-220AB
SV,1A
HA17S0S
T-220AB
Fairchild ~A7S0SC
12V,1A
HA17S12
T-220AB
Fairchild ~A7S12C
15V,1A
HA17S15
T-220AB
Fairchild ~A7S15C
1SV,1A
HA17S1S
T-220AB
Fairchild
24V,lA
HA17S24
T-220AB
Fairchild ~A7S24C
~A7S06C
~A7S1SC
5V,0.5A
HA17SM 05
T-220AB
Fairchild ~A7SM05C
6V,0.5A
HA17SM 06
T-220AB
Fairchild ~A7SM06C
7V,0.5A
HA17SM 07
T-220AB
SV,0.5A
HA17SM OS
T-220AB
Fairchild
~A7SMOSC
12V,0.5A
HA17SM 12
T-220AB
Fairchild
~A7SM12C
15V,0.5A
HA17SM 15
T-220AB
Fairchild ~A7SM15C
Fairchild ~A7SM1SC
1SV,0.5A
HA17SM 1S
T-220AB
20V,0.5A
HA17SM 20
T-220AB
Fairchild~A7SM20C
24V,0.5A
HA17SM 24
T-220AB
Fairchild ~A7SM24C
Switching Regulator
Controller
HA17494
DP-16
Texas TL494
HA17524
DP-16
HA16613A
DP-2S
HA1700S
DP-16
HA1740S
DP-16
AMDAM140S
8-bit D/A
12-bit D/A
HA17012
AMD AM6012
(to be continued)
764
linear
ICs-------------------------------------------------------------------Functions
Other
Function
Type No.
Package Code
P
PS
HAl7733
DG-14
5-Transistor Arrays
HAl127
DG-14
Precision Timers
HA17555
DP-8
HA1607
HA16503
DP-14
Light-measurement Amp.
for Camera
HA16506
DP-14
HA16564
DP-14
Coin Sensor
HA16603
DP-16
HA16604
SP-8
BUrner Controller
8-channel
Positive Supply
Fluorescent
Display Driver Negative Supply
HA16605W
DP-20
HA16617
DP-18
HA16619
Dp18
Cross-reference
Fairchild J.LA733C
RCA CA3045
DG-8
Signetics NE555
DP-8
Monostable Multivibrators
GS
OUTLINE
DP-8
DP14
DP16
DP20
DG14
DG-16
~
DP28
DG8
~
",.
DG20
I T220AB I
SP8
765
Interface Circuits
Line Up
Type
Functions
Dual
Driver
Triple
Dual
Receiver
DG14
Texas SN75109
DP14
DG14
Texas SN75110
DG16
HD75188
DP14
DG14
Texas SN75188
HD75107A
DP14
DG14
Texas SN75107A
HD75108A
DP14
DG14
Texas SN75108A
DG16
DG16
DP16
DG16
Texas SN75154
HD75189
DP14
DG14
Texas SN75189
HD75450A
DP14
DG14
Texas SN75450A
Dual AND
HD75451A
DP8
DG8
Texas SN75451A
Dual NAND
HD75452
Dp8
DG8
Texas SN75452
Dual OR
HD75453
DP8
DG8
Texas SN75453
Dual NOR
HD75454
Dp8
DG8
Texas SN75454
Texas SN7524
IC Memory
Other
DP14
HD75154
Core Memory
Memory
Support
HD75109
HD75110
HD2915
Quad.
Peripheral
Driver
HD2905
Triple
Cross Reference
HD2904
Quad.
Line Driver/
Receiver
Package CodE'
HD1902
DG16
HD2912
DG16
HD2916
DG16A
HD2922
DG16
HD2923
Printer Driver
HD2919
DG16A
Dp16
OUTLINE
DP-8
DG16
DP14
DG16A
DP16
766
DGS
DG14
CROSSREFERENCE
Function
2kB ROM
M
12SBRAM
C
4kB ROM
U
12SBRAM
M
P 128BRAM
U
1.1kB ROM
648 RAM
M 2kB ROM
968 RAM
4kB ROM
968 RAM
4kB ROM
C 96B RAM
4kBROM
96BRAM
Q.
1g>
iii
~
CIl
U 4kBROM
1288 RAM
M 128B RAM
P
U 1288 RAM
"S6BRAM
Hitaphi
Motorola
Fujitsu
MC6801
MC6S01-1
MB86801
Fairchild
HD6801S0
HD6S0155
HD6801VO
HD6801V5
HD6S03
HD6S03-1
F6801
MC6S03
MC6803-1
HD680551
MC6B05P2 MBSSS3
F3870
HD6805Ul
MC6805U2 MB8881
F3872
AMI
NEC
Intel
Toshiba
Mitsubishi
Matsushita
Others
Zilog;ZS
S6S01
!,PD7S01G
S051
!,PDS04S
S04S
TMPS048
M5L8048
!,PDS049
S049
TMP8049
M5LS049
!,PD8022
8022
MBS6803
56S05
Mostek;
MK3870/12
Mostek;
MK3870/22
Mostek;
MK3870/42
HD6805Vl
HD6805WO MC6805R2
HD6805XO MC6805P2
HD6301VO
HD63A01VO
HD63S01VO
HD6303
HD63A03
HD63B03
H06333
HD63A33
HD63B33
!'COM87L
H063L05
HD68P01SO
EPROM+
128B
RAM
C
HD68P01V05
HD68P01V07
U EPROM+
HD68P05V05
96BRAM
HD68P05V07
H06800
H06SAoo
M
H06SBoo
Internal
H06802
ClockS. RAM H06802W
P
H06809
HD68A09
HD68809
High-End
U
H06809E
H068A09E
H068B09E
H06821
PIA
HD6SA21
H06SB21
H06840
PTM
HD68A40
H068B40
H06843
Q.
:;: FOC
H068A43
9
.;:>
H06844
'5
~ DMAC
H068A44
H068B44
~
co
H068455
CRTC
H068A455
H0688455
COMBO
H06B46
.'"
ACIA
5S0A
AOU
RTC
a.
~
:e:0
MPU
:::E
.",
!e DMAC
H06850
H068A50
H06852
HD68A52
HD46508
HD46508-1
HD46508A
HD4650SA-l
Mostek;
MK3SP73/02
Mostek;
MK38P70/02
MC6800
MC68Aoo
MC68Boo
MC6802
MBB861
F6800
56800
!'POSOSOA
SOSOA
TMP90S0A M5LS080A
MB8870
F6802
56802
!,PD8085A
8054A
TMP8085A M5L8085A
MC6809
MC68A09
MC68B09
MC6809E
MC68A09E
MC68B09E
MC6S21
MC6SA21
MC68821
MC6840
MC68A40
MC68B40
MC6843
MBL6809
F6809
56809
!'P0780
MBSS74
F6S21
56S21
!,PDS255
S255
!,P08253
8253
MC6S44
MC68A44
MC68B44
MC6845*1
MC68A45*1
MC68845*1
M8S873
MB8876
MB8877
M8865
F6843
F6844
F6845
Zilog;Z80
TMP9555P M5LS255AF
M5L8253P
M5W1791-01P
8271
T3444A
!,P08257
8257
TMP9517C M5L8257P
!,PD3301
8275
MC6846
MBS872
MB8863
F6846
F6850
56846
56850
!'P08155
!,PD8251
8155
8251
TMP8155
MC6850
MC68A50
MC6852
MC68A52
MB8864
F6852
56852
!'PD8251
8251
TMP9551P M5UI251AP
M5L8155P MN6846
TMP9551P M5L8251AP
M58990P
HD146818
MC146818
H068000-4
HD68000-6
HD68000-8
H06800010
HD68450
MC68000L4
MC6aOOOL6
MC8aOOOL8
MCa8000110
MC68450
767
MN6802
WO;I771
Branch Offices:
Hitachi Electronic Components Europe GmbH
Veraufsburo Dusseldorf
K6nigsallee 6, Dusseldolf 1
Tel: 0211-8905-0
Telex: 8584536 (HIEC-D)
Hitachi, Ltd.
Nippon Bldg., 6-2, 2-chrome
Ohtemachi, Chiyoda-ku, Tokyo, 100, Japan
Tel: 270-2111
Telex: J22395, J22432
Fax: 03-246-0427
US SALES OFFICES
Hitachi America Ltd.
Electronic Devices
Sales and Service Division
1800 Bering Drive, San Jose, CA 95112
Tel: 408/292-6404
Telex: 17-1581
Twx: 910-338-2103
Fax: 408-2922133
EASTERN REGION
594 Marrett Rd., Suite 22
Lexington, MA 02173
617/861-1642
SOUTHERN REGION
6200 Savoy Dr., Suite 704
Houston, TX 77036
713-974;0534
Branch Office:
Hitachi Electronic Components (UK) Ltd.
Box 1062, 16311 Spanga, Stockholm, Sweden
Tel: 08-751-0035
Telex: 14106
NORTHWEST REGION
1800 Bering Dr.
San Jose, CA 95112
408/292-6404
SOUTHWEST REGION
9700 Reseda Blvd., Suite 208
Northridge, CA 91324
2131701-6606
Branch Offices:
Hitachi Semiconductor (Hong Kong) Ltd.
Taiwan Branch Office
No. 73 7th F1-1, Fu Shing N. RD.
Hsing Nan Bldg. Taipei, Taiwan
Tel: 02-773-2162-3
Telex: 23222 HISEKTWN
768
"'.:-,-,-,'~'"- - : - - - - -
'-----::-------~~------~~-
REGIONAL OFFICES
For further information, contact your Regional Sales Office:
North Central
500 Park Blvd.
Suite. 415
Itasca, IL 60143
312-773-4864
Northwest
1800 Bering Dr.
San Jose, CA 95112
408-292-6404
Southwest
Southern
6200 Savoy Drive, Suite 70
Houston, TX 77036
713-974-0534
(0)
HITACHI
A World Leader in Technology
Hitachi America, Ltd., Semiconductor and IC Sales and Service Division
1800 Bering Drive, San Jose, CA 95112 408- 292-6404
Printed~ U.SA