A Project Report On

Simulated Annealing for VLSI Cell Placement

Under guidance of

Dr. M S Bhat
By

Aamodh K (15VL01F)
Arjun S Kumar (15VL04F)
(M.Tech VLSI Design)
Submitted to

Dr. Rekha S Bhat

As a part of
VL897: Minor Project

Department of Electronics and Communication,

National Institute of Technology Karnataka
Surathkal
1st April 2016

VL897: Minor Project 2016

ABSTRACT
Simulated annealing is a general adaptive heuristic and belongs to the class
of non-deterministic algorithms. It has been applied to several combinatorial
problems from various fields of science and engineering.
This report discusses how simulated annealing can be applied to very largescale integration (VLSI) cell placement problem in order to minimize
wirelength and chip area. The algorithm is applied to full custom layout
design. Perl and Python coding languages have been used to implement the
algorithm.

Dept. of E&C, NITK Surathkal

Page 1

VL897: Minor Project 2016

CONTENTS
ABSTRACT

CONTENTS

LIST OF FIGURES

1. Problem Statement

1.1 Need for heuristic algorithm

1.2 Objective function

2. Simulated Annealing
2.1 Introduction

2.2 Brief description

2.3 Pseudo code

3. Simulated Annealing for Placement

3.1 Governing functions

4.

7
7

3.1.1 Initial configuration generation

3.1.2 Move generation function

3.1.3 Cost function

3.1.4 Annealing schedule function

10

Simulation Results

REFERENCES

Dept. of E&C, NITK Surathkal

11
13

Page 2

VL897: Minor Project 2016

LIST OF FIGURES
Figure 1: Typical graph of cost vs No. of configurations examined

Figure 2: Plot of total cost vs No. of configurations examined

11

Figure 3: Random initial placement of cells

11

Figure 4: Intermediate non optimal placement

12

Figure 5: Final optimal placement

12

Dept. of E&C, NITK Surathkal

Page 3

VL897: Minor Project 2016

1. Problem Statement
1.1 Need for heuristic algorithm
VLSI cell placement problems are known to be NP complete. Trying to get an
exact solution by evaluating every possible placement to determine the best
one would take time proportional to the factorial of the number of modules.
This method is, therefore, impossible to use for circuits with any reasonable
number of modules. A wide range of heuristic algorithms exist in the
literature for efficiently arranging the logic cells on VLSI chip. Simulated
annealing is once such method. A strong feature of simulated annealing
method is that it is both effective and robust.

1.2 Objective function

The main objective of simulated annealing placement algorithm is to

minimize the total chip area and the total estimated wire length for all the
cells.

Chip area usage needs to be optimized in order to fit more functionality into
a given chip area.

Wire length needs to be optimized in order to reduce the capacitive delays

associated with longer cells and speed up of the operation of the chip.
The

goals

are

closely

related

since

minimizing

the

chip

area

will

automatically reduce the total wirelength.

Dept. of E&C, NITK Surathkal

Page 4

VL897: Minor Project 2016

2. Simulated Annealing
2.1 Introduction

Simulated annealing is a general heuristic and belongs to the class of non

determininstic algorithms. It has been applied to several combinatorial
problems from various fields of science and engineering. These problems
include

travelling

salesman

problem,

graph

partitioning,

quadratic

assignment, matching, linear arrangement, and scheduling. In the area of

VLSI Design, simulated annealing has been applied to various physical
design steps like partitioning, floorplanning and cell placement[1].

2.2 Brief description

The goal of simulated annealing placement algorithm[2] is to determine a
placement with minimum possible cost. A cost function is defined such that it
consists of wire length and various penalties for module overlap, total chip
area, and so on.
The basic procedure in simulated annealing is to accept all moves that result
in a reduction in cost. Moves that result in a cost increase are accepted with
a probability that decreases with increase in cost. A parameter called T,
called the temperature, is used to control the acceptance probability of the
cost increasing moves. Higher values of T cause more such moves to be
accepted.
Acceptance probability is given by exp(C/T), where C is the cost increase.
In the beginning, the temperature is set to a very high value so most of the
moves are accepted. Then the temperature is gradually decreased so the
cost increasing moves have less chance of being accepted. Ultimately, the
temperature is reduced to a very low value so that only moves causing a

Dept. of E&C, NITK Surathkal

Page 5

VL897: Minor Project 2016

cost reduction are accepted, and the algorithm converges to a low cost
configuration.

2.3 Pseudo code

begin
T = initial_temperature;
P = initial_placement;
while (T > final_temperature) do
while (number_of_trials < trial_limit) do
new_P = PERTURB(P);
C = COST(new_P) COST(P);
if (C < 0) then
P = new_P;
elsif (random(0,1) > exp(C /T)) then
P = new_P;
T = SCHEDULE(T);
end

Dept. of E&C, NITK Surathkal

Page 6

VL897: Minor Project 2016

3. Simulated Annealing for Placement

3.1 Governing functions

The purpose of the algorithm is to find a placement of the standard cells

such that the total estimated interconnection and overlap costs are
minimized. We divide our algorithm into 4 principal components

Initial configuration generation

Move Generation function (PERTURB)

Cost Function (COST)

Annealing Schedule (SCHEDULE)

3.1.1 Initial configuration generation

We start our annealing procedure by placing the cells on the chip randomly.
We place the cells randomly so that the placement is not optimal. The initial
area occupied by the chip is calculated.
Since the cells are placed randomly thus, the distances between them and
the length of their interconnection will be huge. Next we will use the 3
different functions to get the optimal placement for the chip.

3.1.2 Move Generation function

This is the PERTURB function in pseudo code. To generate a new possible cell
placement, we use two strategies
a. Move single cell randomly to a new location on the chip.
b. Swap the position of two cells
c. Rotate single cell by 900

Dept. of E&C, NITK Surathkal

Page 7

VL897: Minor Project 2016

In our algorithm we use all three strategies randomly but with fixed
probability.

60% of the move generation is done through random move (a)

20% of the move generation is done through random move (b)

20% of the move generation is done through random move (c)

3.1.3 Cost function

This is the COST function in pseudo code. The cost function in our algorithm
is comprised of two components
= 1+ 2
c1 is a measure of the total estimated wire-length. For any cell, we find out
the wire-length by calculating the horizontal and the vertical distance
between it and its out cell.
Let Dh(i,j) be the horizontal distance between cell i and its jth out cell and
Dv(i,j) be the vertical distance between cell i and its jth out cell, therefore
the total wire length for the chip can be derived by the following
mathematical expression
( ( , ) +

1=

( , ))

where the summation is taken over all the n cells in a circuit.

When a cell is swapped or rotated it may so happen that two cells overlap
with each other. Let O(I,j) indicate the overlap between two cells. Clearly
this overlap is undesirable and should be minimized. In order to penalize the
overlap severely we square the overlap so that we get larger penalties for
overlaps. The overlap penalty c2 is given by
( ( , ))
!

Dept. of E&C, NITK Surathkal

Page 8

VL897: Minor Project 2016

Thus when we generate a new move we calculate the cost function for the
newly generated move. If we find that the new move has a cost lesser than
the previous best move, we accept it as the best move. But if we find a
solution that is not cost optimal, we do not reject it completely. We define an
Accept function which is the probabilistic acceptance function It determines
whether to accept a move or not. We have implemented an exponential
function for the accept method. We are accepting a non cost optimal solution
because we are giving the annealing schedule a chance to move out of a
local minimum which it may have hit.

Figure 1: Typical graph of cost vs No. of configurations examined[3]

For example, if a certain annealing schedule hits point B (local minima) and
if we do not accept a non cost optimal solution, then the annealing cannot
reach the global minima. By using the accept function we are giving the
annealing schedule a chance to get out of the local minima. As a nature of
the accept function used by us, the probability of accepting non cost optimal

Dept. of E&C, NITK Surathkal

Page 9

VL897: Minor Project 2016

solution is higher at the beginning of the annealing schedule. As temperature

decreases, so does the probability of accepting non-cost optimal solutions,
since the perturbations of a circuit is higher at higher temperatures than
lower temperatures.

3.1.4 Annealing schedule function

This is the schedule function in pseudo code. At first we start the annealing
procedure from a very high temperature 20,000K. We reduced our
temperature using
Tnew = T * T
T, the cooling rate is fixed by us. Initially we rapidly decreased the
temperature (T 0.8). In the middle portion of the annealing schedule we
reduced the temperature slowly (T 0.95), since this phase takes up the
maximum ( 75%) of the annealing schedule. In the low temperature, the
temperature is decreased rapidly again(T 0.8). The stopping condition is
when the temperature falls below 100K.
Within each temperature range we experimentally set the number of moves.
Once the number of moves is set, we fix it for the remainder of the
scheduling. For example in our code we have set the number of iterations for
the algorithm at 5*Number_of_Cells.

Dept. of E&C, NITK Surathkal

Page 10

VL897: Minor Project 2016

4. Simulation results

Figure 2: Plot of total cost vs No. of configurations examined.

Figure 3: Random initial placement of cells

Dept. of E&C, NITK Surathkal

Page 11

VL897: Minor Project 2016

Figure 4: Intermediate non optimal placement

Figure 5: Final optimal placement

Dept. of E&C, NITK Surathkal

Page 12

VL897: Minor Project 2016

REFERENCES
[1] C.Sechen and A.Sangiovanni-Vincentelli, The TimberWolf Placement and
Routing Package, IEEE Journal of Solid State Circuits, Vol. SC-20, No. 2,
April 1985.

[2] S. Kirkpatrick, C. Gelatt and M. Vecchi, Optimization by simulated

annealing IBM Computer Science/Engineering Technology Watson Res.
Center, Yofktown Heights, NY, Tech. Rep, 1982.

[3] K. Shahookar and P. Mazumder, VLSI Cell Placement Techniques,

Department of Electrical Engineering and Computer Science, University of
Michigan.

Dept. of E&C, NITK Surathkal

Page 13