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1
Layout Library
PNR tools generate hierarchical layouts
= Layouts in the library comprise the leaf
cells
= Shapes must be regularized to facilitate
PNR tools in placing cells and routing
wires among them
= Has to satisfy requirements imposed by
the tools used again, tool dependent
=
Requirements Imposed by
Tools
Functional completeness: usually must
include Flip-flop and Latch (both with
Async Set/Reset), tristate buffer, inverter,
either (AND and OR) or (NAND and NOR)
= Model library characterized for delay,
power dissipation, input capacitance, and
for tristate elements also output
capacitance
= VHDL/Verilog models and list of pins
showing pin directions (input, output,
inout)
=
Static complementary CMOS is slow and powerhungry at high voltages, but performs well at low VDD,
and robust toward noise and incorrect transistor
scaling
Dynamic logic styles are probably the fastest style,
small, and may consume less power at higher VDD,
but does not respond as well toward VDD reduction
and may preclude clock gating
Pass-transistor and transmission-gate based circuits
are often said to be fast and power-saving, but do not
function well at low supply voltages
8
10
Different-height cell in
one row
u
.
u
=Single-height
cells in
single Row
u
u
=Single-
and double- or
multiple-height cells
Most efficient, but most
complicated
u
11
Design Considerations
=
12
Cell arranged in
abutted rows
I/O pads placed
along the chip
perimeter
Cells in a row
may be abutted to
each other
A ring of power
and ground
connector is
placed between
pads and core
cells
metal2
corner
cell
corner
cell
Power
ring
core
cells
Pad
cells
corner
cell
metal1
Power
strip
corner
cell
13
Spacing
Closest
separation
Closest
separati on
Spacing
Spacing
Pitch
Pitch
Pitch
(a). line-to-line
pitch
(b). line-to-via
pitch
(c). via-to-via
pitch
14
metal3
metal2
=
metal1
smaller than
minimum
via or via2
pitch
unpromotable locations
(cannot be connected
with a via to the intended
upper metal location)
15
4
in absence of
obstruction,
possible to place
metal2 pin here
metal2 offset x = 0m
metal2 offset y = 1m
cell origin
= metal1 pin
8 coordinate in m
= metal2 pin
16
Use single-height
style
All sizes and shapes
have to be
regularized
All metal signal
tracks in a given
layer have to be the
same width
Power and ground
tracks must be the
same width
V DD rail
(metal pin)
row of
p-transistors
metal boundaries
(used as
cell boundary)
signal
pins
row of
n-transistors
Ground rail
(metal pin)
17
18
=
=
cell1 (flipped
horizontally)
cell2
19
cell2
=
cell overlap
=
may insert
filler cell
here
shared
cell4 (flipped
VDD/ground vertically)
rails
24
25
26
delay
delay
Dependence should
be almost linear
Hence, longer
rise/fall time at
input should
translate to longer
input-to-output
delay always
However, strongly
depends on how
rise/fall times are
defined
29
50 ps
t3 > 50 ps
t1 > 50 ps
t2 > t1
=
t4 = t3
hiv
op
ip
Cin
Cload
32
Timing Characterization
linear model
=
Parameters to characterize:
u
u
u
u
Intrinsic Delay
Slope Sensitivities quantifying delay
dependence on input rise/fall times
Output Resistance quantifying delay
dependence on load capacitance
Setup time of sequential cells
Input/Output Capacitances (used for both power
and delay estimation)
Timing Characterization
Nonlinear Model
Fully lookup-table based
= Synthesis tools perform interpolation
based on data on table
= The only model currently supported by
Cadence
= Offers the best accuracy
= Requires largest number of simulation to
perform
=
34
Linear Relationships:
Transition Delay =
Slope Delay
35
36
Power Characterization
Most simulation-based tools estimate
energy first, then divide by time to get
power
= Typical parameters to characterize:
=
u
u
u
37
38
Calculation Example
ip1
ip2
ip3
ip4
op
t (ns)
0
Dynamic Power
[(4 Erise(op)
4Efall(op))
8Eswitching] /
12
=
+
+
36ns
16
20
ip1
ip2
ip3
ip4
24
28
32
36
op
Cload
39