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Sebin Kollamana
DDR Evolution
DDR3 overview
DFI 3.1
Verification of DDR physical layer and
controller
DDR4 overview
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DDR evolution
SRAM Vs DRAM
Static Random Access Memory (SRAM) is a type of semiconductor memory where the word static
indicates that, unlike dynamic RAM (DRAM), it does not need to be periodically refreshed, as SRAM
uses bistable latching circuitry to store each bit.
SRAM is still volatile in the conventional sense that data is eventually lost when the memory is not
powered.
SRAM is more expensive, but faster and significantly less power hungry (especially idle) than
DRAM. It is therefore used where either bandwidth or low power, or both, are principal
considerations
SRAMs are used as the primary caches in CPUs, data buffers of HDD etc
DRAMs stores each bit of data in a separate capacitor within an integrated circuit. Since real
capacitors leak charge, the information eventually fades unless the capacitor charge is refreshed
periodically.
The advantage of DRAM is its structural simplicity: only one transistor and a capacitor are required
per bit, compared to six transistors in SRAM. This allows DRAM to reach very high density.
For economic reasons, the large memories(RAM) found in personal computers are DRAMs
DDR-DDR2-DDR3
Frequency supported : DDR - 100/133/166/200MHz
DDR2 - 100533MHz DDR3 - 300-1066MHz
Reduction in power consumption of 30% compared to DDR2 modules due to
DDR3's 1.5 V supply voltage, compared to DDR2's 1.8 V or DDR's 2.5 V.
Higher bandwidth made possible by DDR3's 8-bit wide prefetch buffer, in
contrast to DDR2's 4-bit prefetch buffer or DDR's 2-bit buffer.
Typical latencies for a DDR2 device were 5-5-5-15 where as 7-7-7-20(tCAStRCD-tRP-tRAS) for DDR3-1066 and 7-7-7-24 for DDR3-1333
DDR3 latencies are numerically higher because the clock cycles by which
they are measured are shorter
DDR3 1066 DDR3 working @533Mhz
LPDDR2 LPDDR3
Frequency supported: LPDDR - 0-200MHz
LPDDR2 - 0-533MHz
DDR3
Terminology and Commands
Interface signals
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DDR3 Commands
DDR2 commands are driven at single data rate, 1
command per clock
Control Signals - CKE, CS#, RAS#, CAS#, WE#
Address Signals - BA0-BA2, A0-An
Activate - Opens a particular row for Read/Write Access
Pre-charge - Closes an open row in a particular bank or all
banks
Refresh
Self Refresh
Powerdown
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CAS Latency
CAS Latency is the delay, in clock cycles, between the registration of
a READ command and the availability of the first bit of output data.
The CL can be set to 5-14 clocks, depending on the speed grade
option being used.
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Additive Latency
Delays the Read/Write commands internally by Additive latency
number of cycles
Additive Latency can be configured as zero, casl-1, casl-2
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Write Latency
The memory expects write data after write latency number of cycles
after the write command
Write latency can be configured in the range 5 to 12 depending on the
speed bin
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Burst Length
Read and write accesses to the DDR3 SDRAM are burst-oriented,
with the burst length being programmable to either four or eight.
The programmed burst length applies to both read and write bursts
Burst length can be programmed through the mode register or can be
controlled dynamically via a12
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Questions
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DDR3
Initialization
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Initialization
Assert reset for 200us
After de-asserting the reset, wait for 500us and then drive CKE high
Clocks (CK, CK#) need to be started and stabilized for at least 10 ns or 5
tCK (which is larger) before CKE goes active
Once the CKE is registered High after Reset, CKE needs to be
continuously registered High until the initialization sequence is finished
After CKE is being registered high, wait minimum of Reset CKE Exit time,
tXPR, before issuing the first MRS command to load mode register.
(tXPR=max (tXS ; 5 x tCK)
Issue MRS Command to load MR2 with all application settings
Issue MRS Command to load MR3 with all application settings
Issue MRS Command to load MR1 with all application settings and DLL
enabled
Issue MRS Command to load MR0 with all application settings and DLL
reset
Issue ZQCL command to starting ZQ calibration.
Wait for both tDLLK and tZQinit completed
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Initialization
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DDR3
Write and Read
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Write
A single write operation follows three steps Activate
Write - Precharge
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Write ck/dq/dqs
1 cycle preamble, dq/dqs relation, 0.5 cycle postamble
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Read
Activate Read Precharge
1 cycle read preamble, half cycle postamble
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Read timings
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Back-to-back reads
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Questions
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DDR3
Refresh, Self-Refresh, Powerdown
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Refresh
The DRAM requires REFRESH cycles at an average interval of 7.8s
(maximum when TC 85C or 3.9s maximum when TC > 85C).
(tREFI - maximum average periodic refresh, tRFC refresh to activate
period)
All banks must be precharged before entering the refresh.
A maximum of eight REFRESH commands can be posted to any
given DRAM, meaning that the maximum absolute interval between
any REFRESH command and the next REFRESH command is nine
times the maximum average interval refresh rate.
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Refresh
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Self-Refresh
The SELF REFRESH command is used to retain data in the DRAM,
even if the rest of the system is powered down. When in self refresh
mode, the DRAM retains data without external clocking.
Self refresh mode is also a convenient method used to enable/disable
the DLL as well as to change the clock frequency.
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Self-Refresh
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Power Down
Entering power-down disables the input and output buffers, excluding
CK, CK#, ODT, CKE, and RESET#.
NOP or DES commands are required until tCPDED has been
satisfied, at which time all specified input/output buffers are disabled.
(tCPDED Command pass disable delay)
During power-down entry, if any bank remains open after all inprogress commands are complete, the DRAM will be in active powerdown mode. If all banks are closed after all in-progress commands are
complete, the DRAM will be in precharge power-down mode.
DLL will be on during Active powerdown whereas in Precharge
powerdown mode, DLL can be turned off (slow powerdown entry/exit)
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Speed Bin
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Questions
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DDR3
Flyby topology and training
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Flyby Topology
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CS#[0]
CKE[0]
CS#[0]
CKE[0]
CS#[0]
CKE[0]
CS#[0]
CKE[0]
DQ[31:24]
, DQS[3]
DQ[23:16]
, DQS[2]
DQ[15:8],
DQS[1]
DQ[7:0],
DQS[0]
CS#[1]
CKE[1]
CS#[1]
CKE[1]
CS#[1]
CKE[1]
CS#[1]
CKE[1]
DQ[31:24]
, DQS[3]
DQ[23:16]
, DQS[2]
DQ[15:8],
DQS[1]
DQ[7:0],
DQS[0]
DQ[31:0]/DQS[3:0]
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CS#[2]
CKE[2]
CS#[2]
CKE[2]
CS#[2]
CKE[2]
CS#[2]
CKE[2]
DQ[31:24]
, DQS[3]
DQ[23:16]
, DQS[2]
DQ[15:8],
DQS[1]
DQ[7:0],
DQS[0]
CS#[3]
CKE[3]
CS#[3]
CKE[3]
CS#[3]
CKE[3]
CS#[3]
CKE[3]
DQ[31:24]
, DQS[3]
DQ[23:16]
, DQS[2]
DQ[15:8],
DQS[1]
DQ[7:0],
DQS[0]
Write Leveling
The goal is to delay the write DQS/DQS# to match the
CK/CK#. DDR3 has write leveling to achieve this.
1. Complete the initialization procedure
2. Enable write leveling mode using the mode register MR1
3. The phy/controller sends dqs pulse to the DRAM
4. DRAM samples the CK @ posedge of DQS and sends
the result through DQ bus.
5. Phy/controller samples the DQ bus, evaluates the result
and decides whether to delay the DQS further or not
6. Steps 3 to 6 are repeated until the proper delay is
determined
7. Exit write leveling using MR1
8. Resume operation
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Write Leveling
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Write Leveling
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Write Leveling
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Read DQ vs DQS
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Questions
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DFI 3.1
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What is DFI
Defines the connectivity between a DDR memory
controller (MC) and a DDR physical interface (PHY) for
memory devices.
Defines the signals, signal relationships, and timing
parameters required to transfer control information and
data to and from the DRAM devices over the DFI.
Supports an MC and PHY operating in either matched
frequency or a frequency ratio, or both.
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DFI Interfaces
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Control Interface
Write Data Interface
Read Data Interface
Update Interface
Status Interface
Training Interface
Low Power Control Interface
DFI Interfaces
CMD
PHY
Control Interface
Controller
Update interface
DFI
Interface
Status interface
Training interface
DATA
PHY
Leveling / Training Logic
DDR4 Features
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Control Interface
DFI
interface
DRAM
interface
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DFI
interface
DRAM
interface
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Update Interface
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Status Interface
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Status Interface
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Status Interface
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Training interface
Write leveling
Read gate training
Read data eye training
The MC or the PHY may initiate any training operation.
Training may be executed during initialization, frequency change or
during normal operation.
The PHY can request training by driving the dfi_rdlvl_gate_req or
dfi_rdlvl_req or dfi_wrlvl_req
The MC must respond to any of these requests by asserting the
appropriate enable (dfi_rdlvl_en, dfi_wrlvl_en or dfi_rdlvl_gate_en)
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Read gate
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Frequency Ratio
PHY transfers data at a higher data rate relative to the
DFI clock.
MC has the option to execute multiple commands in a
single DFI clock cycle.
Supports 1:1 or 1:2 or 1:4 MC to PHY frequency ratio.
The MC -> PHY interface works on DFI clock and the
PHY works on DFI PHY clock.
The frequency of DFI PHY clock and the memory clock
should always be the same.
The DFI clock and the DFI PHY clock should be phase
aligned.
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Ratio 1:2
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Ratio 1:2
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Ratio 1:4
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Ratio 1:4
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Ratio 1:4
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Questions
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DQ/DQS uncertainty
The DRAM specification allows some uncertainty on the read DQS and DQ
bits. Ensure that the DRAM model has this feature and that it is not turned off
by configuration. This is critical for training tests
DRAM initialization
The DRAM initialization typically takes long time to complete due to reset,
cke requirements. However after the initial sanity testing, these parameters
can be configured to a lower value to speed up the simulation
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The PHY might be having DLLs and slave delay lines to take care of the dqs, dqs gate delays.
Ensure that the delay lines support the highest and the lowest frequency of operation. Also
make sure that the delay line can support the maximum board/flyby delay. This becomes
significant while doing GLS at the best corner
During normal operation the DLL will be ON, however for low frequency applications such as
FPGA prototyping, the DRAM might be operated in DLL OFF mode.
This will test how fast the PHY can switch between READ/WRITE
Also tests the valid-highZ-valid switching in the DQS/DQ bus.
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Questions
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DDR4
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Training procedures
Write Leveling
DQ eye training
MPR settings
MPR Read
MPR Write
4 MPRs are available, controlled through MR3
ZQ Calibration
DQ Vref calibration
A MRS command to the mode register bits 5:0 of MR6 are used
to program the vref value. VrefDQ training mode is
enabled/disabled by A7 of MR6 and training range can be
selected by A6 of MR6
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4
Features
Per DRAM addressability
Allows programmability of a given device on a rank. As an
example, this feature can be used to program different ODT or
Vref values on DRAM devices on a given rank
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Features
Error Correction (CRC and Parity)
CRC
DDR4 supports CRC for write operation, and doesnt support
CRC for read operation
CRC Error mechanism shares the same Alert_n signal for
reporting errors on writes to DRAM. The controller has no way to
distinguish between CRC errors and Command/Address/Parity
errors other than to read the DRAM mode registers
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Features
Parity
Only for Command
[A2:A0] of MR5 are defined to enable or disable C/A Parity in the
DRAM
PAR signal is used to send the parity
Alert_n to flag error
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Features
Connectivity test
The DDR4 memory device supports a connectivity test (CT)
mode, which is designed to greatly speed up testing of electrical
continuity of pin interconnection on the PC boards between the
DDR4 memory devices and the memory controller on the SoC
Allows test patterns to be entered in parallel into the test input
pins and the test results extracted in parallel from the test output
pins of the DDR4 memory device at the same time
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Features
ODT
The ODT feature is designed to improve signal integrity of the memory channel by
allowing the DRAM controller to independently change termination resistance for
any or all DRAM devices.
Controller can control each RTT condition with WR/RD command and ODT pin
2.
3.
4.
if there is WRITE command along with ODT pin HIGH, then DRAM turns on
RTT_WR not RTT_NOM, and also if there is READ command, then DRAM
disables data termination regardless of ODT pin and goes into Driving mode.
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References
MT41J256M4 www.micron.com
JESD79-4 www.jedec.org
DFI 3.1 www.ddr-phy.org
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Thank You
Sebin Kollamana
Sebin.kollamana@wipro.com
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