Microprocessor Part1

Lecture One
Introduction to Computer &

Microcomputers
Assist.Prof. Dr. Hadeel Nasrat
University of Technology
Electrical Eng. Department
Microprocessor Engineering &
Microcontroller
INTRODUCTION TO COMPUTER & MICROCOMPUTERS
What is a Computer?
A computer is an electronic machine that accepts information, stores it until
the information is needed, processes the information according to the instructions
provided by the user, and finally returns the results to the user. The computer can
store and manipulate large quantities of data at very high speed, but a computer
cannot think. A computer makes decisions based on simple comparisons such as
one number being larger than another. Although the computer can help solve a
tremendous variety of problems, it is simply a machine. It cannot solve problems
on its own.
Computer Generations
From the 1950s, the computer age took off in full force. The years since
then have been divided into periods or generations based on the technology used.
1. First Generation Computers (1945-1954): Vacuum Tubes
The first computers used vacuum tubes for circuitry and magnetic drums for
memory, and were often enormous, taking up entire rooms. They were very expensive to
operate and in addition to using a great deal of electricity, generated a lot of heat, which
was often the cause of malfunctions.
First generation computers relied on machine language, the lowest-level
programming language understood by computers, to perform operations, and they could
only solve one problem at a time. Input was based on punched cards and paper tape,
and output was displayed on printouts.
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The UNIVAC and ENIAC computers are examples of first-generation computing

devices. The UNIVAC was the first commercial computer delivered to a business client,
the U.S. Census Bureau in 1951.
2. Second Generation (1955-1964): Transistors
Transistors replaced vacuum tubes and ushered in the second generation of
computers. The transistor was invented in 1947 but did not see widespread use in
computers until the late 1950s. The transistor was far superior to the vacuum tube,
allowing computers to become smaller, faster, cheaper, more energy-efficient and more
reliable than their first-generation predecessors. Though the transistor still generated a
great deal of heat that subjected the computer to damage, it was a vast improvement
over the vacuum tube. Second-generation computers still relied on punched cards for
input and printouts for output.
Second-generation computers moved from cryptic binary machine language to symbolic,
or assembly, languages, which allowed programmers to specify instructions in words.
High-level programming languages were also being developed at this time, such as early
versions of COBOL and FORTRAN. These were also the first computers that stored their
instructions in their memory, which moved from a magnetic drum to magnetic core
technology.
The first computers of this generation were developed for the atomic energy industry.
3. Third Generation (1965-1971): Integrated Circuits (ICs)
ICs were again smaller, cheaper, faster and more reliable than transistors.
Speeds went from the microsecond to the nanosecond (billionth) to the
picosecond (trillionth) range. ICs were used for main memory despite the
disadvantage of being volatile. Minicomputers were developed at this time.
Terminals replaced punched cards for data entry and disk packs became popular
for secondary storage. IBM introduced the idea of a compatible family of
computers, 360 family easing the problem of upgrading to a more powerful
machine. Operating systems were developed to manage and share the computing
resources and time-sharing operating systems were developed. These greatly
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improved the efficiency of computers. Computers had by now pervaded most

areas of business and administration. The number of transistors that be fabricated
on a chip is referred to as the scale of integration (SI). Early chips had SSI (small
SI) of tens to a few hundreds. Later chips were MSI (Medium SI): hundreds to a
few thousands. Then came LSI chips (Large SI) in the thousands range.
4. Fourth Generation (1971-Present) Microprocessors

The microprocessor brought the fourth generation of computers, as thousands of
integrated circuits were built onto a single silicon chip. What in the first generation filled
an entire room could now fit in the palm of the hand. The Intel 4004 chip, developed in
1971, located all the components of the computerfrom the central processing unit and
memory to input/output controlson a single chip.
In 1981 IBM introduced its first computer for the home user, and in 1984 Apple
introduced the Macintosh. Microprocessors also moved out of the realm of desktop
computers and into many areas of life as more and more everyday products began to
use microprocessors.
As these small computers became more powerful, they could be linked together to form
networks, which eventually led to the development of the Internet. Fourth generation
computers also saw the development of GUIs, the mouse and handheld devices.
5. Fifth Generation (Present and Beyond) Artificial Intelligence
Fifth generation computing devices, based on artificial intelligence, are still in
development, though there are some applications, such as voice recognition, that are
being used today. The use of parallel processing and superconductors is helping to
make artificial intelligence a reality. Quantum computation and molecular and
nanotechnology will radically change the face of computers in years to come. The goal of
fifth-generation computing is to develop devices that respond to natural language input
and are capable of learning and self-organization.
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Software &
Applications
Generation
Technology & Architecture
First
(1945-54)
Vacuum tubes, Relay memories,

CPU driven by PC and accumulator;
fixed point Arithmetic
Machine & Assembly

language, Single user
Basic I/O using
programmed and
Internet mode.
Second
(1955-64)
Discrete Transistors, Core Memories,

Floating point, Arithmetic I/O,
processors, Multiplexed memory
access
HLL used with

compilers, batch
processing, Monitoring,
Libraries
Third
(1965-71)
Integrated circuits,
Microprogramming, Pipelining,
Caching, Lookahead Processing
Multiprogramming, Time IBM 360/700

sharing OS, Multi-user CDC 6000
applications
TA-ASC PDP-8
Fourth
(1971Present)
LSI/VLSI and Semiconductor

memory, Microprocessors
technology, Multiprocessors, vector
super-computing, multi computer
Fifth
(present &
Beyond)
Multiprocessor OS,
languages, Compilers
parallel processing,
artificial intelligence and still in

development,
Systems
superconductors,
voice recognition
Applications
ENIAC TIFRAC
IBM 701 Princeton
IAS
IBM7099
CDC 1604
VAX 9800, Cray XMP, IBM 3600,

Pentium Processor
based systems
(PCs), Ultra SPARC
Cray/MPP, TMC/CM5, Intel paragon,
Fujitsu VP500
Types of Computers
Computer now comes in a variety of shapes and sizes, which could be roughly
classified according to their processing power into five sizes:
super large, large,
medium, small, and tiny.

Microcomputers are the type of computers that we are most likely to notice and use in
our everyday life. In fact there are other types of computers that you may use directly or
indirectly:
Supercomputers-super large computers: supercomputers are high- capacity
machines with hundreds of thousands of processors that can perform more than 1
trillion calculations per second. These are the most expensive but fastest
computers available. "Supers," as they are called, have been used for tasks
requiring the processing of enormous volumes of data, such as doing the U.S.
census count, forecasting weather, designing aircraft, modeling molecules,
breaking codes, and simulating explosion of nuclear bombs.
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Mainframe computers - large
computers:
The
only
type
of
computer
available until the late 1960s, mainframes are water- or air-cooled computers that
vary in size from small, to medium, to large, depending on their use. Small
mainframes are often called midsize computers;
they used to be called
minicomputers. Mainframes are used by large organizations such as

banks, airlines, insurance companies, and colleges-for processing millions of
transactions. Often users access a mainframe using a terminal, which has a
display screen and a keyboard and can input and output data but cannot by itself
process data.
Workstations - medium computer: Introduced in the early 1980s, workstations,
are expensive, powerful computers usually used for complex scientific,
mathematical, and engineering calculations and for computer-aided design and
computer-aided manufacturing. Providing
many capabilities comparable to
midsize mainframes, workstations are used for such tasks as designing airplane
fuselages, prescription drugs, and movie special effects. Workstations have
caught the eye of the public mainly for their graphics capabilities, which are used
to breathe three-dimensional life into movies such as Jurassic Park and Titanic.
The capabilities of low-end workstations overlap those of high-end desktop
microcomputers.
Microcomputer - small computers: Microcomputers, also called personal
computers (PC), can fit next to a desk or on a desktop, or can be carried around.
They are either stand-alone machines or are connected to a computer network,
such as a local area network. A local area network (LAN) connects, usually by
special cable, a group of desktop PCs and other devices, such as printers, in an
office or a building. Microcomputers are of several types:
Desktop PCs:
are those in which the case or main housing sits on a desk,
with keyboard in front and monitor (screen) often on top.

Tower PCs:
are those Microcomputer in which the case sits as a "tower,"
often on the floor beside a desk, thus freeing up desk surface space.
Laptop computers (also called notebook computers): are lightweight portable
computers with built-in monitor, keyboard, hard-disk drive, battery, and AC
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adapter that can be plugged into an electrical outlet; they weigh anywhere from
1.8 to 9 pounds.
Personal digital assistants (PDAs) (also called handheld computers or
palmtops) combine personal organization tools-schedule planners, address
books, to-do lists. Some are able to send e-mail and faxes. Some PDAs have
touch-sensitive screens. Some also connect to desktop computers for sending
or receiving information.
Microcontrollers-tiny computers: Microcontrollers, also called embedded
computers, are the tiny, specialized microprocessors installed in "smart"
appliances and automobiles. These microcontrollers enable PDAs microwave
ovens, for example, to store data about how long to cook your potatoes and at
what temperature.
Basic Blocks of a Microcomputer
All Microcomputers consist of (at least):
1. Microprocessor Unit (MPU) MPU is the brain of microcomputer
2. Program Memory (ROM)
3. Data Memory (RAM)
4. Input / Output ports
5. Bus System
Fig. (1): Basic Block of a Microcomputer

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Input Units -- "How to tell it what to do"

Devices allow us to enter information into the computer. A keyboard and
mouse are the standard way to interact with the computer. Other devices include
mice, scanners, microphones, joysticks and game pads used primarly for games.
Output Units -- "How it shows you what it is doing"

Devices are how the manipulated information is returned to us. They
commonly include video monitors, printers, and speakers.
Bus System
A Bus is a common communications pathway used to carry information
between the various elements of a computer system
The term BUS refers to a group of wires or conduction tracks on a printed
circuit board (PCB) though which binary information is transferred from one
part of the microcomputer to another
The individual subsystems of the digital computer are connected through an
interconnecting BUS system.
There are three main bus groups
ADDRESS BUS
DATA BUS
CONTROL BUS
Data Bus
The data bus consists of 8, 16, or 32 parallel signal lines. As indicated by the
double-ended arrows on the data bus line in Figure 1, the data bus lines are
bidirectional. This means that the CPU can read data in from memory or from a
port on these lines, or it can send data out to memory or to a port on these lines.
Many devices in a system will have their outputs connected to the data bus, but
only one device at a time will have its outputs enabled. Any device connected on
the data bus must have three-state outputs so that its outputs can be disabled
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when it is not being used to put data on the bus.

The Data Bus carries the data which is transferred throughout the system. (
bi-directional)
Examples of data transfers
Program instructions being read from memory into MPU.
Data being sent from MPU to I/O port
Data being read from I/O port going to MPU
Results from MPU sent to Memory
These are called read and write operations
Address Bus
The address bus consists of 16, 20, 24, or 32 parallel signal lines. On these lines the
CPU sends out the address of the memory location that is to be written to or read from.
The number of memory locations that the CPU can address is determined by the number
of address lines. If the CPU has N address lines, then it can directly address 2N memory
locations. For example, a CPU with 16 address lines can address 216 or 65,536 memory
locations, a CPU with 20 address lines can address 220 or 1,048,576 locations, and a
CPU with 24 address lines can address 224 or 16,777,216 locations. When the CPU
reads data from or writes data to a port, it sends the port address out on the address
bus.
An address is a binary number that identifies a specific memory storage
location or I/O port involved in a data transfer
The Address Bus is used to transmit the address of the location to the
memory or the I/O port.
The Address Bus is unidirectional ( one way ): addresses are always issued
by the MPU.
Control Bus
The control bus consists of 4 to 10 parallel signal lines. The CPU sends out
signals on the control bus to enable the outputs of addressed memory devices or
port devices. Typical control bus signals are Memory Read, Memory Write, I/O
Read, and l/O Write. To read a byte of data from a memory location, for example,
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the CPU sends out the memory address of the desired byte on the address bus and
then sends out a Memory Read signal on the control bus. The Memory Read signal
enables the addressed memory device to output a data word onto the data bus. The
data word from memory travels along the data bus to the CPU.
The Control Bus: is another group of signals whose functions are to provide
synchronization ( timing control ) between the MPU and the other system
components.
Control signals are unidirectional, and are mainly outputs from the MPU.
Example Control signals
RD: read signal asserted to read data into MPU
WR: write signal asserted to write data from MPU
Main memory
The memory section usually consists of a mixture of RAM (Random Access
Memory) and ROM (Read Only Memory). It may also have magnetic floppy disks,
magnetic hard disks, or optical disks (CDs, DVDs). Memory has two purposes. The
first purpose is to store the binary codes for the sequences of instructions you want
the computer to carry out. When you write a computer program, what you are really
doing is writing a sequential list of instructions for the computer. The second purpose
of the memory is to store the binary-coded data with which the computer is going to
be working. This data might be the inventory records of a supermarket, for example.
The duties of the memory are :
To store programs
To provide data to the MPU on request
To accept result from the MPU for storage
Main memory Types
ROM : read only memory. Contains program (Firmware). does not lose
its contents when power is removed (Non-volatile)
RAM: random access memory (read/write memory) used as variable
data, loses contents when power is removed volatile. When power up
will contain random data values
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Read-Only Memory
uP can read instructions from ROM quickly
Cannot write new data to the ROM
ROM remembers the data, even after power cycled
Typically, when the power is turned on, the microprocessor will start fetching
instructions from the still-remembered program in ROM (bootstrap )
Available ROMs
Masked ROM or just ROM
PROM or programmable ROM(once only)
EPROM (erasable via ultraviolet light)
Flash (can be erased and re-written about 10000 times, usually must write a
whole block not just 1 byte or 2 bytes, slow writing, fast reading)
EEPROM (electrically erasable read-only memory, also known as EEROM
both reading and writing are very slow but can program millions of
timesuseless for storing a program but good for say configuration
information.
A0
A1
ROM
m+1 bit
Addres
D0
D1
A2
m +1
D2
(n + 1)
Am
Dn
ROM
PROM
EEPROM
Capacity: 2m+1
OE : Output Enable connect to RD of uP
( )
CE , CS : Chip Enable to Address decoder

CE
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OE
n+1
bit
bit
Data
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RAM (Random Access Memory)

The uP can read the data from RAM quickly,
The uP can write new data quickly to RAM
RAM forgets its data if power is turned off
Two type of is available :
Static RAM(SRAM): ff base, fast, expensive, low cap/vol, applied for
cache , no refresh
Dynamic RAM (DRAM): cap base, slow , low cost high capacity/volume
, applied for main memory(pc) need refresh.
m+1 bit
Address
A0
A1
D0
D1
A2
D2
2
m +1
(n + 1)
Am
Capacity: 2m+1
n+1 bit
Data
Dn
Data bus is
Bidirectional
RAM
RD : Read signal connect to MemRD of uP
WR : Write signal connect to MemWR of uP

CS : Chip Select to Address decoder
CS
WR
RD
Central Processing Unit

The central processing unit or CPU controls the operation of the computer. In a
computer the CPU is a microprocessor. The CPU fetches binary-coded instructions
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from memory, decodes the instructions into a series of simple actions, and carries out
these actions in a sequence of steps. The CPU also contains an address counter or
instruction pointer register, which holds the address of the next instruction or data
item to be fetched from memory; general-purpose registers, which are used for
temporary storage of binary data; and circuitry, which generates the control bus
signals.
Computer Architecture
In computer engineering, computer architecture is the conceptual design and
fundamental operational structure of a computer system. It is a blueprint and functional
description of requirements (especially speeds and interconnections) and design
implementations for the various parts of a computer focusing largely on the way by
which the central processing unit (CPU) performs internally and accesses addresses in
memory.
Computer architecture comprises at least three main subcategories
Instruction set architecture, or ISA, is the abstract image of a computing
system that is seen by a machine language (or assembly language) programmer,
including the instruction set, memory address modes, processor registers, and
address and data formats.
Microarchitecture, also known as Computer organization is a lower level, more
concrete, description of the system that involves how the constituent parts of the
system are interconnected and how they interoperate in order to implement the
ISA. The size of a computer's cache for instance, is an organizational issue that
generally has nothing to do with the ISA.
System Design which includes all of the other hardware components within a
computing system such as:
system interconnects such as computer buses and switches
memory controllers and hierarchies
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CPU off-load mechanisms such as direct memory access issues like multiprocessing.
Once both ISA and microarchitecture has been specified, the actual device needs to be
designed into hardware. This design process is often called implementation.
Implementation is usually not considered architectural definition, but rather hardware
design engineering.
Computer Organization deals with the advances in computer architecture right from the
Von Neumann machines to the current day super scalar architectures.
Von Neumann Architecture
The earliest computing machines had fixed programs. Some very simple
computers still use this design, either for simplicity or training purposes. For example, a
desk calculator (in principle) is a fixed program computer. It can do basic mathematics,
but it cannot be used as a word processor or to run video games. To change the
program of such a machine, you have to re-wire, re-structure, or even re-design the
machine. Indeed, the earliest computers were not so much "programmed" as they were
"designed". "Reprogramming", when it was possible at all, was a very manual process,
starting with flow charts and paper notes, followed by detailed engineering designs, and
then the often-arduous process of implementing the physical changes.
The idea of the stored-program computer changed all that. By creating an
instruction set architecture and detailing the computation as a series of instructions (the
program), the machine becomes much more flexible. By treating those instructions in the
same way as data, a stored-program machine can easily change the program, and can
do so under program control.
The von Neumann architecture is a computer design model that uses a
processing unit and a single separate storage structure to hold both instructions and data
as shown in Fig. (2). It is named after mathematician and early computer scientist John
von Neumann. Such a computer implements a universal Turing machine, and the
common "referential model" of specifying sequential architectures, in contrast with
parallel architectures. The term "stored-program computer" is generally used to mean a
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computer of this design, although as modern computers are usually of this type, the term
has fallen into disuse. All general-purpose computers are now based on the key
concepts of the von Neumann architecture.
Though the von Neumann model is universal in general-purpose computing, it
suffers from one obvious problem. All information (instructions and data) must flow back
and forth between the processor and memory through a single channel, and this channel
will have finite bandwidth. When this bandwidth is fully used the processor can go no
faster. This performance limiting factor is called the von Neumann bottleneck.
Fig. (2): The Von-Neumann Architecture
Hardvard Architecture
A Harvard Architecture as shown in Fig. (3) has one memory for instructions and a
second for data. The name comes from the Harvard Mark 1, an electromechanical
computer which pre-dates the stored-program concept of von Neumann, as does the
architecture in this form. It is still used for applications which run fixed programs, in
areas such as digital signal processing, but not for general-purpose computing. The
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advantage is the increased bandwidth available due to having separate communication

channels for instructions and data; the disadvantage is that the storage is allocated to
code and data in a fixed ratio.
In Harvard architecture, there is no need to make the two memories share
characteristics. In particular, the word width, timing, implementation technology, and
memory address structure can differ. Instruction memory is often wider than data
memory. In some systems, instructions can be stored in read-only memory while data
memory generally requires read-write memory. In some systems, there is much more
instruction memory than data memory so instruction addresses are much wider than data
addresses.
Fig. (3): The Harvard architecture
A pure Harvard architecture computer suffers from the disadvantage that

mechanisms must be provided to separately load the program to be executed into
instruction memory and any data to be operated upon into data memory. Additionally,
modern Harvard architecture machines often use a read-only technology for the
instruction memory and read/write technology for the data memory. This allows the
computer to begin execution of a pre-loaded program as soon as power is applied. The
data memory will at this time be in an unknown state, so it is not possible to provide any
kind of pre-defined data values to the program.
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The solution is to provide a hardware pathway and machine language instructions

so that the contents of the instruction memory can be read as if they were data. Initial
data values can then be copied from the instruction memory into the data memory when
the program starts. If the data is not to be modified (for example, if it is a constant value,
such as pi, or a text string), it can be accessed by the running program directly from
instruction memory without taking up space in data memory (which is often at a
premium).
For instance each port may be supplied from its own local cache memory (fig.
(4)). The cache memories reduce the external bandwidth requirements sufficiently to
allow them both to be connected to the same main memory, giving the bandwidth
advantage of a Harvard architecture along with most of the flexibility of the simple von
Neumann architecture. (The flexibility may be somewhat reduced because of cache
consistency problems with self-modifying code).
Note that this type of Harvard
architecture is still a von Neumann machine.
Fig. (4): A modified Harvard Architecture
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Hardware, Software, and Firmware

When working around computers, you hear the terms hardware, software, and
firmware almost constantly. Hardware is the name given to the physical devices and
circuitry of the computer. Software refers to the programs written for the computer.
Firmware is the term given to programs stored in ROMs or in other devices which
permanently keep their stored information.
Peripheral Interface Categories:
We can classify the interface according to the specification of the peripherals
themselves.
Analogue/Digital Interface To interface two peripherals one of them is digital
and the other one is analog we have to add analog to digital converter (ADC) and
digital to analog converter (DAC). See figure 5.
Fig.(5): Analog Digital Interface

Synchronized/A synchronized Interface Two important categories of
interface are used to connect peripherals: the first one is the synchronized
interface which depends on a clock to order the data transfer. The second one is
the asynchronized interface which can be accomplished without clock. To
interface these peripherals together we need handshaking adaptor which
regulates the data exchange between them. See figure 6.
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Fig.(6): Synchronized/Asynchronized Interface
Serial/Parallel Interface To interface two peripherals one of them is parallel

and the second is serial we have to use parallelizing and serializing stages to
connect both of them. The parallelizing stage converts the serial pulses into
parallel data while the serializing stage converts the parallel data into serial
pulses. See figure 7.
Fig.(7): Parallel Serial Interface
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Microprocessor based Interface

The microprocessor can be interfaced with the peripherals via several techniques, they
are:
1. Memory space interface. This is the most common type. It is flexible and reliable
to be applied in any application. Moreover it supports data cash transfer. It can
also be accomplished by several data communication techniques. The drawback
of this technique is the complicated design and usage.
2. I/O ports interface such as serial and parallel ports. I/O port interface is simpler
but less efficient and than memory interface.
3. Interrupts (Hard interrupts)

4. Direct bus interface using internal buses such as ISA, EISA, PCI, USB, AGP, see
figure 8.
5. Indirect bus interface using external buses such as GPIB, SCSI, CAMAC, etc.,
see figure 8.
Fig. 8: Direct/Indirect Bus Interface

Bus
When referring to a computer, the bus also known as the address bus, data bus,
or local bus is a data connection between two or more devices connected together. For
example a bus enables a computer processor to communicate with the memory or a
video card to communicate with the memory.
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A bus is capable of being (parallel or a serial bus), (Synchronized or A

synchronized) and today all computers utilize two types of buses, an internal or
local bus and an external bus. An internal bus enables a communication between
internal components such as a computer video card and memory (e.g. ISA, EISA,
PCI, AGP, etc.) and an external bus is capable of communicating with external
components such as a SCSI bus, CAN, CAMAC, GPIB, etc.
A computer or devices bus speed or throughput is always measured in bits per
second or megabytes per second.
The bus is not only cable connection but also hardware (bus architecture),
protocol, software, and bus controller
BUS Basics
A computer bus is a method of transmitting data from one part of the computer to
another part of the computer. The computer bus connects all devices to the computer
CPU and main memory. The computer bus consists of three parts the address bus, a
data bus and control bus . The data bus transfers actual data whereas the address bus
transfers information about where the data should go. The control bus exchanges all
control signals. The following part contains a brief overview on each of the computer
buses.
Definitions:
1- PnP
Short for Plug and Play, PnP is an ability of a computer to detect and configure a
new piece of hardware automatically, without the requirement of the user to physically
configure the hardware device with jumpers or dipswitches. Plug and Play was
introduced on IBM compatible computers with the release of Microsoft Windows 95,
where Apple Macintosh computers have always supported the ability to automatically
detect and install hardware.
For Plug and Play to operate properly on IBM compatible computers the user must have
the following:
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BIOS supporting Plug and Play.

Operating systems supporting PnP.
Peripheral with PnP support.
Today all new computers have PnP capabilities. Computers running Microsoft Windows
XP no longer support non PnP devices.
2- Throughput (Baud-rate, Speed)
Also known as "communication speed", throughput is a numerical value used to
illustrate the total amount of data transferred being transferred through the computer or
device at that given time. This number is commonly represented in bits per second
(bps) or bytes per second (Bps).
3- Proprietary
Term used to describe a product that is only compatible with a specific type of
hardware, software, computer or manufacturer. When referring to computer hardware, it
is recommended that you do not choose a proprietary device as it reduces compatibility
and generally the capability of upgrading that product in the future.
ISA BUS
Introduced by IBM, ISA or Industry Standard Architecture was originally an 8-bit
bus that was later expanded to a 16-bit bus in 1984. When this BUS was originally
released it was a proprietary BUS, which allowed only IBM to create peripherals and the
actual interface. However in the early 1980's other manufacturers were creating the bus.
In 1993, Intel and Microsoft introduced a PnP ISA bus that allowed the computer to
automatically detect and setup computer ISA peripherals such as a modem or sound
card. Using the PnP technology an end-user would have the capability of connecting a
device and not having to configure the device using jumpers or dipswitches.
To determine if an ISA card is an 8-bit or 16-bit card physically look at the card. You will
notice that the first portion of the slot closest to the back of the card is used if the card is
an 8bit card. However, if both sections of the card are being utilized the card is a 16-bit
card.
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Many manufacturers are trying to eliminate the usage of the ISA slots however for
backwards compatibility you may find 1 or 2 ISA slots with additional PCI slots, AGP
slots, etc. However, today you may also have a motherboard that has no ISA slots. We
highly recommend when purchasing any new internal expansion card that you stay away
from ISA as it has for the most part disappeared.
EISA BUS
Short for Extended Industry Standard Architecture, EISA was announced
September of 1988. EISA is a computer bus designed by 9 competitors to compete with
IBM's MCA BUS. These competitors were AST Research, Compaq, Epson, Hewlett
Packard, NEC, Olivetti, Tandy, WYSE, and Zenith Data Systems.
The EISA Bus provided 32-bit slots at an 8.33 MHz cycle rate for the use with
386DX, or higher processors. In addition the EISA can accommodate a 16-bit ISA card in
the first row.
Unfortunately, while the EISA bus is backwards compatible and is not a
proprietary bus the EISA bus never became widely used and is no longer found in
computers today.
Page 22 of 27
Lecture One
Microcomputers
Microcontroller
MCA BUS
Short for Micro Channel Architecture, MCA was introduced by IBM in 1987,
MCA or the Micro Channel bus was a competition for ISA BUS. The MCA bus offered
several additional features over the ISA such as a 32-bit bus, automatically configure
cards (similar to what Plug and Play is today), and bus mastering for greater efficiency.
One of the major downfalls of the MCA bus was it being a proprietary BUS and because
of competing BUS designs. The MCA BUS never became widely used and has since
been fazed out of the desktop computers.
PCI BUS
Introduced by Intel in 1992, revised in 1993 to version 2.0, and later revised in
1995 to PCI 2.1. PCI is short for Peripheral Component Interconnect and is a 32-bit
computer bus that is also available as a 64-bit bus today. The PCI bus is the most
commonly used and found bus in computers today.
MINI PCI
Mini PCI is a new standard which measures at 2.75-inch x 1.81-inch x 0.22-inch is
a new standard developed by leading notebook manufactures. This technology could
allow manufactures to lower their price as the motherboards would be simpler to design.
Type I - Identical to Type II, except requires extra cables for connectors like the
RJ-11 and RJ-45. However, offers more flexibility to where it can be placed in the
computer.
Type II - Used when size is not important. Type II is able to integrate the RJ-11
and RJ-45 connectors and due away with extra cables.
Type III - SO-DIMM style connector that can be installed with a mere 5 mm overall
height above the system board. In addition cabling to the I/O connectors allow Type III
cards to be placed anywhere in the system.
PCI-X
PCI-X is a high performance bus that is designed to meet the increased I/O
demands of technologies such as Fiber Channel, Gigabit Ethernet and Ultra3 SCSI. PCIX capabilities include:
Page 23 of 27
Lecture One
Microcomputers
Microcontroller
Up to 133 MHz bus speed

64-Bit bandwidth
1GB/sec throughput
More efficient bus operation for easier interface.
Split Transactions allows an indicator device to make only one data request and
relinquish the bus. Instead of constantly needing to poll the bus for a response.
Byte Count that enables indicator to specify in advance the specific number of bytes
requested, eliminating the inefficiency of speculative prefetches.
Backwards compatibility
AGP
Introduced by Intel in 1997, AGP or Advanced Graphic Port is a 32-bit bus
designed for the high demands of 3-D graphics. AGP has a direct line to the computers
memory which allows 3-D elements to be stored in the system memory instead of the
video memory.
For AGP to work in a computer must have the AGP slot which comes with most Pentium
II and Pentium III machines. The computer also needs to be running Windows 95
OSR2.1, Windows 98, Windows 98 SE, Windows 2000, Windows ME or higher.
Page 24 of 27
Lecture One
Microcomputers
Microcontroller
USB Bus
USB (Universal Serial Bus) is a new external bus developed by Intel, Compaq,
DEC, IBM, Microsoft, NEC and Northern Telcom and released to the public in 1996 with
the Intel 430HX Triton II Mother Board. USB has the capability of transferring 12 Mbps,
supporting up to 127 devices and only utilizing one IRQ. For PC computers to take
advantage of USB the user must be running Windows 95 OSR2, Windows 98 or
Windows 2000. Linux users also have the capability of running USB with the proper
support drivers installed. To determine if your computer supports USB on the back, front
or sides of the computer look for a small connector with the following symbol.
USB cables are hot swappable which allows users to connect and disconnect the cable
while the computer is on without any physical damage to the cable.
The above illustration is an example of what the end of a USB connector looks like.
There are two standards of USB connectors. Type A connectors are found on the
computer and or USB hub and Type B connectors are found on the peripheral. All USB
cables should only be legally 5m (16ft) max as defined by the USB standard. When
Page 25 of 27
Lecture One
Microcomputers
Microcontroller
exceeding this length or utilizing extensions in the cables data loss will occur. The below
illustration is the slots used for each of the connectors shown in the above illustration.
USB VERSIONS
USB 1.0 - The original release of USB supports 127 devices transferring 12 Mbps.
USB 1.1 - Also known as full-speed USB, USB 1.1 is similar to the original release of
USB however minor modifications for the hardware and the specifications. This version
of USB still only supports a rate of 12 Mbps.
USB 2.0 - USB 2.0 also known as hi-speed USB was developed by Compaq, Hewlett
Packard, Intel, Lucent, Microsoft, NEC and Philips and was introduced in 2001. Hi-speed
USB is capable of supporting a transfer rate of up to 480 Mbps and is backwards
compatible meaning it is capable of supporting USB 1.0 and 1.1 devices and cables.
Page 26 of 27
Lecture One
Microcomputers
Microcontroller
Exercises:
1) Describe and draw the diagram of Von Neumann model.
2)
Define the following abbreviations CPU, RAM and ROM.
3)
Classify the system peripheral interface according to three different approaches.
4)
Define the following abbreviations ADC, DAC and I/O.
5)
Mention several techniques of microprocessor interface.
6)
Define and explain the following terms PnP, throughput and proprietary.
7)
What are the required conditions for applying PnP technique?
8)
Define the following abbreviations ISA, PnP, PCI, USB, AGP
9)
Compare the performance of the following buses, ISA, EISA, PCI, AGP and USB
10) Write some brief notes about the USB bus
Page 27 of 27
Lecture Two
Introduction to Microprocessors
Microprocessor Engineering & Microcontroller
INTRODUCTION TO MICROPROCESSORS
Microprocessor
Microprocessor: A silicon chip that contains a CPU. In the world of personal computers,
the terms microprocessor and CPU are used interchangeably.
A microprocessor (sometimes abbreviated P) is a digital electronic component with
miniaturized transistors on a single semiconductor integrated circuit (IC).
One or more microprocessors typically serve as a central processing unit (CPU) in a
computer system or handheld device.
Microprocessors made possible the advent of the microcomputer.
Three basic characteristics differentiate microprocessors:
Instruction set: The set of instructions that the microprocessor can execute.
Bandwidth: The number of bits processed in a single instruction.
Clock speed: Given in megahertz (MHz), the clock speed determines how
many instructions per second the processor can execute.
In both cases, the higher the value, the more powerful the CPU. For example, a 32 bit
microprocessor that runs at 50MHz is more powerful than a 16-bit microprocessor that
runs at 25MHz.
In addition to bandwidth and clock speed, microprocessors are classified as being either
RISC (reduced instruction set computer) or CISC (complex instruction set computer).
Evaluation of the Microprocessors

The evolution of microprocessors has been known to follow Moore's Law when it
comes to steadily increasing performance over the years. This law suggests that the
complexity of an integrated circuit, with respect to minimum component cost,
doubles every 18 months. This dictum has generally proven true since the early 1970s.
From their humble beginnings as the drivers for calculators, the continued increase in
Page 1 of 22
Lecture Two
power has led to the dominance of microprocessors over every other form of computer;
every system from the largest mainframes to the smallest handheld computers now uses
a microprocessor at its core.
The microprocessor has changed the way computers work by making them
faster. The microprocessor is often called the brain of the C.P.U.(or the central
processing unit) and without the microprocessor the computer is more or less
useless. Motorola and Intel have invented most of the microprocessors over the last
decade. Over the years their has been a constant battle over cutting edge
technology. In the 80's Motorola won the battle, but in the 90's it looks as Intel has won
the war. Table 1 lists some of types that belong to these companies (families) of
microprocessors.
Table 1: Some Types of Microprocessors
Company
4 bit
8 bit
16 bit
32 bit
64 bit
Intel
4004
4040
8008
8080
8085
8088/6
80186
80286
80386
80486
80860
pentium
Zilog
Z80
Z8000
Z8001
Z8002
Motorola
6800
6802
6809
68006
68008
68010
68020
68030
68040
The First 25 Years of Evolution

In 25 years, the number of transistors on a microprocessor chip grew from a
couple thousand to more than five million. By the turn of the century, the number
routinely exceeded 100 million on top-of-the-line chips.
Page 2 of 22
Page 3 of 22
Lecture Two
Lecture Two
Comparison between 8085 and Z80 Microprocessors

No.
8085 Microprocessor
Z80 Microprocessor
Data Lines are MULTIPLEXED
It has no MULTIPLEXED lines
74 instructions
158 Instructions
Operates at 3 to 5MHz
Operates at 4 to 20 MHz
It has 5 interrupts
It has two interrupts
No on board dynamic memory
It has on board logic to refresh

Dynamic memory
It contains no Index register
It has two Index register
It contains SIM & RIM
It contains no SIM & RIM
Comparison between 8085 and MC6800 Microprocessors

No.
8085 Microprocessor
MC6800 Microprocessor
It operates on Clock frequency

of 3 to 5 MHz.
It operates at 1 MHz frequency.
8085 has no Index register.
It has one index register.
8085 has on board clock logic

circuit.
No clock logic circuit.
8085 has one Accumulator

Register.
MC6800 has two Accumulator

Registers.
8085 has five interrupts.
MC 6800 have two interrupts.
It has total 674 Instructions.
MC6800 has total 72 instructions
Page 4 of 22
Lecture Two
Comparison between 8086 and 8088 Microprocessors

No.
8086 Microprocessor
8088 Microprocessor
The instruction Queue is 6 byte

long.
The instruction Queue is 4 byte

long.
In 8086 memory divides into two

banks, up to 1,048,576 bytes.
The memory in 8088 does not

divide in to two banks as 8086.
The data bus of 8086 is 16-bit

wide
The data bus of 8088 is 8-bit wide.
It has BHE signal on pin no. 34 &

there is no SSO signal.
It does not has BHE signal on pin

no. 34 & has only SSO signal. It
has no S7 pin.
The output signal is used to

select memory or I/O at M IO
but if M IO low or logic 0 it
selects I/O devices and if M IO
is high or logic 1it selects
memory.
The output signal is used to select

memory or I/O at M IO but
if M IO is low or at logic 0,it
selects Memory devices and if
M IO is high or at logic 1it
selects I/O.
It needs one machine cycle to

R/W signal if it is at even location
otherwise it needs two.
It needs one machine cycle to R/W

signal if it is at even location
otherwise it needs two.
In 8086, all address & data

Buses are multiplexed.
In 8088, address bus, AD7- AD0

buses are multiplexed.
It needs two IC 74343 for demultiplexing AD0-AD19.
It needs one IC 74343 for demultiplexing AD0-AD7.
Page 5 of 22
Lecture Two

No.
1
8086 Microprocessor
It is a 16 bit microprocessor and it
is first 16 bit microprocessor after
8085(8-bit).
It has pipelined architecture (not
highly) and high speed bus
interface on single chip.
80386 Microprocessor
It is a 32 bit microprocessor and it is
logical extension of the 80236.
It is highly pipelined architecture and
much faster speed bus than 8086.
It is upward compatible with

80386.It means all 8086
instructions are followed by 80386.
However, 80386 can support 8086

programming model & can also directly
run the programs written for 8086 in
virtual mode if VM=1(in protected mode)
It is housed on a 40 pin DIP

package.
The chip of 80836 contains 132 pins.
It is a built on a HMOS technology.
6
7
8
9
10
No special hardware is equipped

for task Switching.
The 8086 operates on a 5MHz.
Clock.
The address bus and data bus are
multiplexed.
It has a transistor package density
of 29,500 transistors.
It has a total of 117 instructions.
The 80386 using High-speed CHMOS III

technology.
It has a special hardware for task
switching.
The 80386 operate 33MHz clock
frequency maximum.
It has separate address and data bus for
time saving.
Transistor density and complexity further
increases 2,75,000.
It has total 129 instructions
The 80386 contains protection
mechanism paging which has instruction
two support them
It operate in three modes
a)Real
b)Virtual
c)Protected
It has instruction Queue as well as pre
fetch queue.
11
It has no mechanism protection,

paging.
12
It is operated in one mode only.
13
It has only instruction Queue.
14
In 8086, It is not necessity that all

operation are in parallel mode.
80386 all functional units are not parallel
15
8086 has nine flags.
It contains all nine flags of 8086 but other

flags named IOP,NT,RF,VM.
Page 6 of 22
Lecture Two

The 8086/8088 is a 16 bit processor running on a 16 bit (8086) or 8 bit (8088) bus
with a 20 bit address. It can address 1 MB of memory. Addressing consists of adding the
program's effective address to the (left shifted by 4) value of one of the segment
registers. Think of segments as multiple 64kb regions of memory, overlapping at a
distance of 16 bytes.
The 80286 is a 16 bit processor running on a 16 bit bus with a 24 bit address. It
can address 16mb of memory.
In real mode, it operates the same as an 8086. This is the power on reset state. In
protected mode, the segment register changes meaning. Instead of a segment address
(left shifted by 4 base address), the segment register is an index into a page descriptor
table, which is a table that supports virtual mode. Each element in the page descriptor
table also contains information about the protection status of that page, so that page
protection can be provided.
Unfortunately, since the meaning of the segment register changed, the 80286 was
not object code compatible with programs written for the 8086/8088. This is one of the
factors that made the 80286 unpopular.
Other microprocessors
80486: introduced in 1989
With 32-bit internal-external data bus and 32-bit address bus.
built in math co-processor in a single chip.
Introduction of cache memory (Static RAM with very fast access time).
Pentium :introduced in 1992 (Penta means five)
Thus the Pentium began as the fifth generation of the Intel x86
architecture.
The Pentium had an L2 cache from 256KB to 1MB, used a 50, 60 or 66MH
system bus and contained from 3.1 to 3.3 million transistors.
The Pentium uses a 32-bit expansion bus; however the data bus is 64-bits.
Page 7 of 22
Lecture Two
Pentium PRO :introduced in 1995
The Pro chip was the first chip to be offered in the AT or the ATX format.
The ATX format was preferred, as the Pro consumed more than 25 W of
power, which generated a fair amount of heat.
There were several major improvements of Pentium pro over Pentium, for
example:
It had a superscalar architecture (microprocessor architecture
containing more than one execution unit)
2-stage super pipeline
Internal micro-ops similar to RISC like instructions and internal
thermal protection.
This microprocessor could be clocked to 200.00 MHz and consisted of 5.5

million transistors.
Pentium II
Intel began by separating the processor, and cache of the Pentium Pro,
mounting them together on the circuit board with a big heat sink. Then by
dropping the whole assembly onto the system board, using a Single Edge
Contact (SEC) with 242 pins in the slot, and adding the 57 MMX (Multimedia
extension) micro-code instructions, then Intel had the Pentium II. This way,
defective cache modules don't force throwing out of a perfectly good CPU,
because of a bad cache. And to further improve cache yields, the Pentium II
ran cache at half the speed of the CPU.
Pentium II uses the Dynamic Execution Technology
Pentium II includes data integrity and reliability features such as Error

Correction Code (ECC), Fault Analysis, Recovery and Functional Redundancy
Checking for both system and L2 cache buses.
The pipelined Floating-Point Unit (FPU) supports the 32-bit and 64-bit formats
specified in IEEE standard 754, as well as an 80-bit format.
Page 8 of 22
Lecture Two
Parity protected address/request and response system bus signals with a retry
mechanism for high data integrity and reliability.
An on-die diode monitors the die temperature. A thermal sensor located on the
motherboard can monitor the die temperature of the Pentium II processor for
thermal management purposes.
This microprocessor could work at clock rates of 300MHz and is made up of

7.5 million transistors.
Pentium III
Similar to Pentium II, the Pentium III processor also uses a Dynamic Execution
micro-architecture: a unique combination of multiple branch prediction, data
flow analysis, and speculative execution.
The Pentium III has two major differences with Pentium II: Improved MMX and
Processor serial number feature. The improved MMX has totally 70
instructions enabling advanced imaging, 3D streaming audio and video, and
speech recognition for enhanced Internet Experience: technology instructions
for enhanced media and communication performance.
Additionally, Streaming SIMD (single-instruction, multiple data) Extensions for

enhanced floating point and 3-D application performance.
It also consisted of Internet Streaming SIMD Extensions which consisted of

70 instructions and includes single instruction, multiple data for floating-point,
additional SIMD integer and cacheability control instructions.
Data Pre-fetch Logic anticipates the data needed by the application programs
and pre-loads into the Advanced Transfer Cache increasing performance.
The processor has multiple low power states such as Sleep, and Deep to
conserve power during idle times. The system bus runs at 100MHz and
133MHz allowing for a 33% increase in available bandwidth to the processor.
The Processor Serial Number extends the concept of processor identification

by providing a 96-bit software accessible processor number that may be used
by applications to identify a system. Applications include membership
Page 9 of 22
Lecture Two
authentication, data backup/restore protection, removable storage data

protection, and managed access to files.
Pentium 4
The Pentium 4 processor is Intels microprocessor that was introduced at

1.5GHz in November of 2000.
It implements the new Intel Net Burst micro-architecture that features

significantly higher clock rates and world-class performance.
It includes several important new features and innovations that will allow the
Intel Pentium 4 processor to deliver industry-leading performance for the next
several years.
The Pentium 4 processor is designed to deliver performance across

applications where end users can truly appreciate and experience its
performance. For example, it allows a much better user experience in areas
such as Internet audio and streaming video, image processing, video content
creation, speech recognition, 3D applications and games, multi-media and
multi-tasking user environments.
The Pentium 4 processor enables real time MPEG2 video encoding and near
real-time MPEG4 encoding, allowing efficient video editing and video
conferencing.
It delivers world-class performance on 3D applications and games.
It adds 144 new 128-bit Single Instruction Multiple Data (SIMD) instructions
called SSE2 (Streaming SIMD Extension 2) that improves performance for
multi-media, content creation, scientific, and engineering applications.
Intel NetBurst micro-architecture of the Pentium 4 processor has four main

sections: the in-order front end, the out-of-order execution engine, the integer
and floating-point execution units, and the memory subsystem.
The Pentium 4 processor has a 20-stage misprediction pipeline while the P6

micro-architecture has a 10-stage misprediction
Page 10 of 22
Lecture Two
The Pentium 4 processor has a system bus with 3.2 G-bytes per second of
bandwidth. This bandwidth is achieved with a 64-bit wide bus capable of
transferring data at a rate of 400MHz.
Itanium
Intel, with partner Hewlett-Packard, developed a next generation 64-bit

processor architecture called IA-64 (the 80x86 design was renamed IA-32) the first implementation was named Itanium.
Itanium core processor is not binary compatible with X86 processors, instead it
has a separate compatibility unit in hardware to provide IA32 compatibility.
Itanium only allow memory operands in load and store operations.
As Itanium was a 64-bit processor so could address memory up to 4 GByte of

RAM.
The Itanium processor was specifically designed to provide a very high level of
parallel processing, to enable high performance without requiring very high
clock frequencies (which can lead to excessive power consumption and heat
generation).
Key strengths of the Itanium architecture include, Up to 6 instructions/cycle:

The Itanium processor can handle up to 6 simultaneous 64-bit instructions per
clock cycle
the dual-core version can support up to two software threads per core,
Extensive execution resources per core: 256 application registers (128 general
purpose, 128 floating point) and 64 predicate registers,
Large cache: 24MB in the dual-core version (12MB per core), providing data
to each core at up to 48GB/s,
Large address space: 50-bit physical / 64-bit virtual, Small, energy-efficient

core: Since Itanium relies on the compiler for scheduling instructions for
parallel throughput (other architectures rely on runtime optimization within the
processor itself),
Page 11 of 22
Lecture Two
it has fewer transistors in each core. This may be an advantage in current and
future multi-core designs.
Itanium 2
The Itanium 2 is an IA-64 microprocessor developed jointly by Hewlett Packard
(HP) and Intel, and introduced on July 8, 2002. The first Itanium 2 processor
(code-named McKinley) was substantially more powerful than the original Itanium
processor, roughly doubling performance, and providing competitive performance
across a range of data- and compute-intensive workloads. Several generations of
Itanium 2 processors have followed.
The Itanium 2 processor architecture is, dubbed Explicitly Parallel Instruction
Computing (EPIC). It is theoretically capable of performing roughly 8 times more
work per clock cycle than other CISC and RISC architectures due to its Parallel
Computing Micro-architecture. However, performance is heavily dependent on
software compilers and their ability to generate code which efficiently uses the
available execution units of the processor.
All Itanium 2 processors to date share a common cache hierarchy. They have 16
KB of Level 1 instruction cache and 16 KB of Level 1 data cache. The L2 cache is
unified (both instruction and data) and is 256 KB. The Level 3 cache is also
unified and varies in size from 1.5 MB to 24 MB. In an interesting design choice,
the L2 cache contains sufficient logic to handle semaphore operations without
disturbing the main ALU.
The latest Itanium processor, however, features a split L2 cache, adding a
dedicated 1MB L2 cache for instructions and thereby effectively growing the
original 256 KB L2 cache, which becomes a dedicated data cache.
Most systems sold by enterprise server vendors that contain 4 or more processor
sockets use proprietary Non-Uniform Memory Access (NUMA) architectures
that supersede the more limited front side bus of 1 and 2 CPU socket servers.
The Itanium 2 bus is occasionally referred to as the Scalability Port, but much
more frequently as the McKinley bus. It is a 200 MHz, 128-bit wide, double
Page 12 of 22
Lecture Two
pumped bus capable of 6.4 GB/s more than three times the bandwidth of the
original Itanium bus, known as the Merced bus.
In 2004, Intel released processors with a 266 MHz bus, increasing bandwidth to
8.5 GB/s. In early 2005, processors with a 10.6 GB/s, 333 MHz bus were
released.
Pentium D
The Pentium D is a series of microprocessors that was introduced by Intel at the

spring 2005 Intel Developer Forum.
A 9xx-series Pentium D package contains two Pentium 4 dies, unlike other multicore processors (including the Pentium D 8xx-series) that place both cores on a
single die.
The Pentium D was the first announced multi-core CPU (along with its more
expensive twin, the Pentium Extreme Edition) from any manufacturer intended for
desktop computers.
Intel underscored the significance of this introduction by predicting that by the end
of 2006 over 70% of its shipping desktop CPUs would be multi-core.
With heat rising incrementally faster than the rate at which signals move through
the processor, known as clock speed, an increase in performance can create an
even larger increase in heat. The answer is multi-core microprocessor. For
example, by moving from a single high-speed core, which generates a
corresponding increase in heat, to multiple slower cores, which produce a
corresponding reduction in heat, enterprises can potentially improve application
performance while reducing their thermal output.
A multi-core microprocessor is one which combines two or more independent

processors into a single package, often a single integrated circuit (IC); to be more
specific it has more than one execution unit with in a single integrated circuit.
A dual-core device contains only two independent microprocessor execution units,

as shown in the figure below.
Page 13 of 22
Lecture Two
In general, multi-core microprocessors allow a computing device to exhibit some

form of thread-level parallelism (TLP) without including multiple microprocessors
in separate physical packages. This form of TLP is often known as chip-level
multiprocessing, or CMP.
The Pentium D 820 runs in at 2.8GHz, is dual-core, its highlights are; it features
two 16KB data caches in addition to data cache, each core includes an Execution
Trace Cache that stores up to 12 K decoded micro-ops in the order of program
execution,
Microprocessor Fundamentals
Microprocessors are the "brains" of a computer. They direct the computer how to
perform the calculations and handle the data per user's instructions. Most of the logical
functionality resides in the central processing unit (CPU).
Components
A microprocessor contains an arithmetic logic unit (ALU) which processes any addition,
multiplication or Boolean operations that come through the device. It sends the results to the
control unit. The control unit processes any instructions and data and sends it to the registers for
temporary memory or through either the data, address or control bus.
Page 14 of 22
Lecture Two
Instruction Cycle
Each microprocessor model has a set of instructions such as add, move, branch
and jump. The microprocessor fetches each of these instructions from the memory. They
are stored in strings containing the number code of the instruction and the data relevant
to the instruction. Microprocessors follow an instruction cycle of fetch, decode and
execute.
Pipelining
Microprocessors pipeline instructions by overlapping the different parts of the
instruction cycle. Rather than wait for one cycle of fetch-decode-execute for one
instruction to complete, the microprocessor fetches the next instruction while it decodes
the previous instruction. This allows the microprocessor to process more instructions in a
given amount of time.
Cache
Cache is a small amount of memory that holds the most recently used data. This
memory allows a computer to get data quickly. This cuts the time it takes a computer to
access a recent program and computer data. Typically, the more cache memory
available, the faster the computer.
Clock Speed
Clock speed is the most recognized specification of a microprocessor. It is
typically measured in megahertz (MHz) or gigahertz (GHz). Generally speaking, the
faster your clock speed, the faster your computer can compute data. Also, be aware that
dual and quad core microprocessors are available. According to the Computer Shopper
website, a quad-core 2.5GHz Core 2 Quad Q9400 from Intel will outperform a 3GHz
Core 2 Duo E8400 in many computing tasks.
Bus Speed
Bus speed, typically called front-side bus (FBS), is the rate that a microprocessor
communicates with a motherboard's memory controller. High FSB speeds will increase
the performance of computer operations that are RAM-intensive, such as video and
audio editing and coding programs, or high-end 3D games.
Page 15 of 22
Lecture Two
The Microprocessor-Based Personal Computer System

Figure 1 shows the block diagram of the personal computer. The block diagram is
composed of four parts:
Fig. 1: shows the block diagram of the personal computer

1. Bus Architecture:- Three buses:
Address:
If I/O, a value between 0000H and FFFFH is issued.
If memory, it depends on the architecture:
20-bits (8086/8088)
24-bits (80286/80386SX)
25-bits (80386SL/SLC/EX)
32-bits (80386DX/80486/Pentium)
36-bits (Pentium Pro/II/III)
Data:
8-bits (8088)
16-bits (8086/80286/80386SX/SL/SLC/EX)
32-bits (80386DX/80486/Pentium)
64-bits (Pentium/Pro/II/III)
Page 16 of 22
Lecture Two
Control:
Most systems have at least 4 control bus connections (active low).
MRDC (Memory ReaD Control), MWRC, IORC (I/O Read Control), IOWC
Fig. 2: The block diagram of computer system showing the buses structure
Bus Standards:
ISA (Industry Standard Architecture): 8 MHz

8-bit (8086/8088)
16-bit (80286-Pentium)
EISA: 8 MHz
32-bit (older 386 and 486 machines).
PCI (Peripheral Component Interconnect): 33 MHz

32-bit or 64-bit (Pentiums)
New: PCI Express and PCI-X 533 MTS
VESA (Video Electronic Standards Association): Runs at processor

speed.
32-bit or 64-bit (Pentiums)
Page 17 of 22
Lecture Two
Only disk and video.Competes with the PCI but is not popular.
USB (Universal Serial Bus): 1.5 Mbps,12 Mbps and now 480 Mbps.
Newest systems.
Serial connection to microprocessor.
For keyboards, the mouse, modems and sound cards.
To reduce system cost through fewer wires.
AGP (Advanced Graphics Port): 66MHz

Newest systems.
Fast parallel connection: Across 64-bits for 533MB/sec.
For video cards.
To accommodate the new DVD (Digital Versatile Disk) players.
Latest AGP 3.0 with peak bandwidth of 2.1GB/s.
The memory
The memory structures of all Intel 80X86-Pentium 4 personal computer systems
are similar. This includes the first personal computers based upon the 8088 introduced in
1981 by IBM to the most powerful high-speed versions of today based on the Pentium 4.
The memory system is divided into three main parts: TPA (T ransient P rogram Area),
system area, and XMS (Extended Memory System). The type of microprocessor in
your computer determines whether an extended memory system exists. If the computer
is based upon an older 8086 or 8088 (a PC or XT), the TPA and system areas exist, but
there is no extended memory area. The PC and XT contain 640K bytes of TPA and 384K
bytes of system memory, for a total memory size of IM bytes. We often call the first IM
byte of memory the real or conventional memory system because each Intel
microprocessor is designed to function in this area by using its real mode of operation.
I/O Devices
Page 18 of 22
Lecture Two
8088
8086 (1MB only), 80286,

80386SX, 80386SL/SLC(32MB)
80386DX, 80486
Page 19 of 22
Lecture Two
Pentium/Pro/II/III
A List of the Types of Microprocessors

Computers can perform a number of complex operations that would normally
require days, years and sometimes decades for humans to calculate efficiently. A
microprocessor is the main component of any computer and is responsible for controlling
all of its operations. It manages the computer's instructions, which is a set of commands,
written in specific computer language, that the microprocessor uses to control other
devices and perform tasks. Depending on the purpose of a computer, there are several
types of microprocessors that are in use today.
Page 20 of 22
Lecture Two
1. Reduced Instruction Set Computer

An IBM Researcher, John Cocke, noticed that a computer uses only 20 percent of
its instructions, leaving 80 percent unused. In 1974, John Cocke developed the Reduced
Instruction Set Computer (RISC), a processor that used few instructions, required fewer
transistors and was cheaper to produce. RICS chips use less instruction but require
more lines of codes to perform some operations. RISC relies on the performance of
installed software, meaning that the software needs to be more complex. RISC are also
used in ovens, air conditioners and other kitchen appliances.
2. Complex Instruction Set Computer

The term Complex Instruction Set Computer (CISC) was defined retroactively to
distinguish this type of microprocessor from RISC microprocessors. These chips have a
larger number of different and complex instructions comparing to RISC. The main
principle of CISC microprocessor is that the computer's hardware is always faster than
software. Most laptops, desktops and servers use CISC microprocessors.
3. Very Long Instruction Word (VLIW)

Very Long Instruction Word (VLIW) introduced a completely new concept of
parallel instructions. It was designed to pack several independent instructions into a very
long instruction. To perform this kind of operation, the software needs to recognize
independent instructions. VLIW is similar to the process of executing multiple operations
in one clock cycle, the required time for an electrical signal to alternate from zero to one
and back to zero. The larger the number of clock cycles per second, the faster the
microprocessor is. This type of chip uses the computer compiler to compress an ordinary
sequential code into a very long instruction word.
4. Superscalar Processors
The architecture of Super-scalar Processors allows the computer to execute
several instructions simultaneously and independently. Super-scalar microprocessors
use pipe-lining to enable processing multiple instructions, but each instruction has to be
Page 21 of 22
Lecture Two
in a different pipeline stage at a given moment. The limitations of super-scalar

processors include: resource conflicts, when two or more instructions compete for the
same resource; control dependency, which occurs because the branches create
problems in maintaining an optimal parallelism; and data conflicts, which are produced
by data dependencies between instructions in the program.
Others
General Purpose Processor (GPP) is designed for a variety of tasks and not only
for one specific application or software. A Special Purpose Processor (SPP) has
functions similar to the microcomputer peripheral chip. The only difference is that SPP
has a specialized instruction set to control the functions independently, while a peripheral
chip is controlled by the CPU. Application-Specific Integrated Circuit (ASIC) is a type of
integrated circuit designed for a special purpose application. For example, an ASIC
created for a company's line of mobile phones only works on that specific line of mobile
phones. Digital Signal Processor (DSP) is a type of very fast microprocessor, mostly
used in math-intensive, signal-processing applications. It transforms analog signals into
digital data that is analyzed.
Page 22 of 22
Lecture Three
8085 Microprocessor
8085 Microprocessor
The main features of 8085 p are:
It is a 8 bit microprocessor.
It is manufactured with N-MOS technology.
It has 16-bit address bus and hence can address up to 216 = 65536 bytes
(64KB) memory locations through A0-A15
The first 8 lines of address bus and 8 lines of data bus are multiplexed AD0
AD7
Data bus is a group of 8 lines D0 D7
It supports external interrupt request.
A 16 bit program counter (PC)
A 16 bit stack pointer (SP)
Six 8-bit general purpose register arranged in pairs: BC, DE, HL.
It requires a signal +5V power supply and operates at 3.2 MHZ single phase
clock.
It is enclosed with 40 pins DIP (Dual in line package).
Page 1 of 18
Lecture Three
8085 Microprocessor
Pin Diagram of 8085 and Pin description of 8085
Fig. 1: Pin Diagram of 8085 microprocessor.
Page 2 of 18
Lecture Three
8085 Microprocessor
8085 is a 40 pin IC, DIP package. The signals from the pins can be grouped as
follows:
1. Power supply and clock signals
2. Address bus
3. Data bus
4. Control and status signals
5. Interrupts and externally initiated signals
6. Serial I/O ports
Fig. 2: Signal Groups of 8085

1. Power supply and Clock frequency signals:
Vcc
+ 5 volt power supply
Vss
Ground
X1, X2 :
Crystal or R/C network or LC network connections to set the frequency
of internal clock generator.
Page 3 of 18
Lecture Three
8085 Microprocessor
The frequency is internally divided by two. Since the basic operating timing
frequency is 3 MHz, a 6 MHz crystal is connected externally.
CLK (output)-Clock Output is used as the system clock for peripheral and devices
interfaced with the microprocessor.
2. Address Bus:
A8 - A15 (output; 3-state)
It carries the most significant 8 bits of the memory address or the 8 bits of the I/O
address;
3. Multiplexed Address / Data Bus:
AD0 - AD7 (input/output; 3-state)
These multiplexed set of lines used to carry the lower order 8 bit address as well
as data bus.
During the opcode fetch operation, in the first clock cycle, the lines deliver the
lower order address A0 - A7.
In the subsequent IO / memory, read / write clock cycle the lines are used as data
bus.
The CPU may read or write out data through these lines.
4. Control and Status signals:
ALE (output) - Address Latch Enable.
This signal helps to capture the lower order address presented on the multiplexed
address / data bus.
RD (output 3-state, active low) - Read memory or IO device.
This indicates that the selected memory location or I/O device is to be read and
that the data bus is ready for accepting data from the memory or I/O device.
WR (output 3-state, active low) - Write memory or IO device.
This indicates that the data on the data bus is to be written into the selected
memory location or I/O device.
IO M (output) - Select memory or an IO device.
This status signal indicates that the read / write operation relates to whether the
memory or I/O device.
Page 4 of 18
Lecture Three
8085 Microprocessor
It goes high to indicate an I/O operation.
It goes low for memory operations.
5. Status Signals:
It is used to know the type of current operation of the microprocessor.

Data Bus Status (output)
IO M
S0
S1
Halt
MEMORY WRITE
MEMORY READ
IO WRITE
IO READ
Opcode fetch
Interrupt Acknowledge
6. Interrupts and Externally initiated operations:
They are the signals initiated by an external device to request the microprocessor
to do a particular task or work.
There are five hardware interrupts called,

TRAP
RST 7.5
RST 6.5 ------ (inputs)
RST 5.5
INTR
INTRA (active low output)
On receipt of an interrupt, the microprocessor acknowledges the interrupt by the

active low INTA (Interrupt Acknowledge) signal.
RESETIN (Input, active low)
This signal is used to reset the microprocessor.
The program counter inside the microprocessor is set to zero.
The buses are tri-stated.
Page 5 of 18
Lecture Three
8085 Microprocessor
RESETOUT (Output)
It indicates CPU is being reset.
Used to reset all the connected devices when the microprocessor is reset.
7. Direct Memory Access (DMA):

Tri state devices:
3 output states are high & low states and additionally a high impedance state.
When enable E is high the gate is enabled and the output Q can be 1 or 0 (if A is
0, Q is 1, otherwise Q is 0). However, when E is low the gate is disabled and the
output Q enters into a high impedance state.
When 2 or more devices are connected to a common bus, to prevent the devices
from interfering with each other, the tristate gates are used to disconnect all
devices except the one that is communicating at a given instant.
The CPU controls the data transfer operation between memory and I/O device.
Direct Memory Access operation is used for large volume data transfer between
memory and an I/O device directly.
The CPU is disabled by tri-stating its buses and the transfer is effected directly by
external control circuits.
HOLD signal is generated by the DMA controller circuit. On receipt of this signal,
the microprocessor acknowledges the request by sending out HLDA signal and
leaves out the control of the buses. After the HLDA signal the DMA controller
starts the direct transfer of data.
Page 6 of 18
Lecture Three
8085 Microprocessor
READY (Output)
Memory and I/O devices will have slower response compared to microprocessors.
Before completing the present job such a slow peripheral may not be able to
handle further data or control signal from CPU.
The processor sets the READY signal after completing the present job to access
the data.
The microprocessor enters into WAIT state while the READY pin is disabled.
8. Single Bit Serial I/O ports:
SID (input)
- Serial input data line
SOD (output)
- Serial output data line
These signals are used for serial communication.
Architecture or Functional Block Diagram of 8085

The functional block diagram or architecture of 8085 Microprocessor is very important
as it gives the complete details about a Microprocessor. Fig.3 shows the Block diagram
of a Microprocessor
Page 7 of 18
Lecture Three
8085 Microprocessor
Fig. (2): Block diagram of the 8085 microprocessor architecture.
Page 8 of 18
Lecture Three
8085 Microprocessor
Registers of 8085:
The 8085 have six general-purpose registers to store 8-bit data during program
execution.
These registers are identified as B, C, D, E, H, and L.
They can be combined as register pairs BC, DE, and HL-to perform some 16-bit
operations.
Accumulator (A):
The accumulator is an 8-bit register that is part of the arithmetic/logic unit (ALU).
This register is used to store 8-bit data and to perform arithmetic and logical
operations.
The result of an operation is stored in the accumulator.
Flags:
The ALU includes five flip-flops that are set or reset according to the result of an
operation.
The microprocessor uses the flags for testing the data conditions.
They are Zero (Z), Carry (CY), Sign (S), Parity (P), and Auxiliary Carry (AC) flags.
The most commonly used flags are Sign, Zero, and Carry.
Page 9 of 18
Lecture Three
8085 Microprocessor
The bit position for the flags in flag register is
Arithmetic and Logic Unit (ALU):
It is used to perform the arithmetic operations like addition, subtraction,

multiplication, division, increment and decrement and logical operations like AND,
OR and EX-OR.
It receives the data from accumulator and registers.
According to the result it set or reset the flags.
Program Counter (PC):
This 16-bit register sequencing the execution of instructions.
It is a memory pointer. Memory locations have 16-bit addresses, and that is why
this is a 16-bit register.
The function of the program counter is to point to the memory address of the next
instruction to be executed.
When an op-code is being fetched, the program counter is incremented by one to

point to the next memory location.
Stack Pointer (Sp):
The stack pointer is also a 16-bit register used as a memory pointer.
It points to a memory location in R/W memory, called the stack.
The beginning of the stack is defined by loading a 16-bit address in the stack
pointer (register).
Temporary Register: It is used to hold the data during the arithmetic and logical
operations.
Instruction Register: When an instruction is fetched from the memory, it is loaded in
the instruction register.
Instruction Decoder: It gets the instruction from the instruction register and decodes the
instruction. It identifies the instruction to be performed.
Page 10 of 18
Lecture Three
8085 Microprocessor
Serial I/O Control: It has two control signals named SID and SOD for serial data
transmission.
Timing and Control unit:
It has three control signals ALE, RD , WR and three status signals IO M , S0

and S1.
ALE is used for provide control signal to synchronize the components of

microprocessor and timing for instruction to perform the operation.
RD
and WR
are used to indicate whether the operation is reading the data
from memory or writing the data into memory respectively.
IO M is used to indicate whether the operation is belongs to the memory or

peripherals.
ADDRESSING MODES OF 8085
Every instruction of a program has to operate on a data.
The method of specifying the data to be operated by the instruction is called

Addressing.
The 8085 has the following 5 different types of addressing.

1. Immediate Addressing
2. Direct Addressing
3. Register Addressing
4. Register Indirect Addressing
5. Implied Addressing
1. Immediate Addressing:
In immediate addressing mode, the data is specified in the instruction itself. The
data will be a part of the program instruction.
For Example:
MVI B, 3EH
;Move the data 3EH given in the instruction to B register;
LXI SP, 2700H.
Page 11 of 18
Lecture Three
8085 Microprocessor
2. Direct Addressing:
In direct addressing mode, the address of the data is specified in the instruction.
The data will be in memory. In this addressing mode, the program instructions and
data can be stored in different memory.
For Example:
; Load the data available in memory location 1050H in to Acc
LDA 1050H
SHLD 3000H
3. Register Addressing:
In register addressing mode, the instruction specifies the name of the register in
which the data is available.
For Example:
MOV A, B
; Move the content of B register to A register; SPHL; ADD C.
4. Register Indirect Addressing:
In register indirect addressing mode, the instruction specifies the name of the
register in which the address of the data is available. Here the data will be in
memory and the address will be in the register pair.
For Example:
MOV A, M
; the memory data addressed by HL pair is moved to A register.
LDAX B
5. Implied Addressing:
In implied addressing mode, the instruction itself specifies the data to be

operated.
For Example:
CMA
; Complement the content of accumulator; RAL
Page 12 of 18
Lecture Three
8085 Microprocessor
8085 INSTRUCTION SET CLASSIFICATION

The 8085 instruction set can be classified into the following five functional
headings.
1. DATA TRANSFER INSTRUCTIONS:

It includes the instructions that move (copies) data between registers or between
memory locations and registers. In all data transfer operations the content of source
register is not altered. Hence the data transfer is copying operation.
MOV A, B
MVI C, 45H
2. ARITHMETIC INSTRUCTIONS:
Includes the instructions, which performs the addition, subtraction, increment or
decrement operations. The flag conditions are altered after execution of an instruction in
this group.
ADD A,B
SUI B,05H
3. LOGICAL INSTRUCTIONS:
The instructions which performs the logical operations like AND, OR, EXCLUSIVEOR, complement, compare and rotate instructions are grouped under this heading. The
flag conditions are altered after execution of an instruction in this group.
ORA A
ANI B, 01H
4. BRANCHING INSTRUCTIONS:
The instructions that are used to transfer the program control from one memory
location to another memory location are grouped under this heading.
CALL
JMP 4100
Page 13 of 18
Lecture Three
8085 Microprocessor
5. MACHINE CONTROL INSTRUCTIONS:

It includes the instructions related to interrupts and the instruction used to stop the
program execution.
NOP
END
Opcode Sheet of 8085 Microprocessor with description

What is OPCODE? OPCODE is the machine language. ie, while we talk or write,
we do it in english; because we understand english. But a machine cannot understand
direct english. So, we translate english into its level to make a machine to understand.
For example, there is a translator inside all computers which translate our english into
Binary language for a computer to understand and perform the required operations.
Similarly, a machine language which a Microprocessor can understand is the HEXA
language. These hex codes are called OPCODES which makes a microprocessor to
work. As there is no translator inside a Microprocessor, we directly fnd the OPCODES for
each and every instruction and we feed it alone inside a trainer kit. Those opcodes with
its description are given below. The OPCODE sheet without description is also given in
the main page.
Page 14 of 18
Lecture Three
8085 Microprocessor
Page 15 of 18
Lecture Three
8085 Microprocessor
Page 16 of 18
Lecture Three
8085 Microprocessor
EXERCISE 1:
1.
What are the various registers in 8085?
2.
In 8085 name the 16 bit registers?
3.
What are the various flags used in 8085?
4.
What is Stack Pointer?
5.
What is Program counter?
6.
Which Stack is used in 8085?
7.
What happens when HLT instruction is executed in processor?
8.
What is meant by a bus?
9.
What is Tri-state logic?
10. Give an example of one address microprocessor?

11. In what way interrupts are classified in 8085?
12.
What are Hardware interrupts?
13. What are Software interrupts?

14.
Which interrupt has the highest priority?
15. Name 5 different addressing modes?

16. How many interrupts are there in 8085?
17. What is clock frequency for 8085?
18. What is the RST for the TRAP?
19. In 8085 which is called as High order / Low order Register?
20.
What are input & output devices?
21. Can an RC circuit be used as clock source for 8085?

22. Why crystal is a preferred clock source?
23. Which interrupt is not level-sensitive in 8085?
24. What does Quality factor mean?
25. What are level-triggering interrupt?
EXERCISE 2:
1.
Using LDA and STA instructions, write a program that will transfer five byte of
memory from location 3000H through 3004H to location 3200H through 3204H
Page 17 of 18
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
Lecture Three
8085 Microprocessor
Write a program to exchange the contents of HL register pair with DE register

pair using MOV instruction.
Write a program to swap lower 4 bit nibble with upper 4 bit nibble of 8 bit data
at memory location 2100H and place a result to location 2101H.
Write a program using the ADI instruction to add the two hexadecimal numbers
3AH and 48H and store the result in memory location 2100H.
Write a program to subtract the number in the D register from the number in
the E register. Store the result in register C.
Write an assembly language program that AND, OR and XOR together the
contents of register B, C and E and place the result into memory location
3000H, 3001H and 3002H.
Write a program that store 00H into memory location 2500H through 2510H.
Write an assembly language program to add two 8-bit numbers, the sum may
be of 16-bits.
Write an 8085 assembly language program using minimum number of
instructions to add the 16 bit number in BC, DE & HL. Store the 16 bit result in
DE.
Develop a program in assembly that subtracts the number in the DE register
pair from the number in the HL register. Place the result in BC register.
Sixteen bytes of data are stored in memory locations at 3150H to 315FH. Write
a program to transfer the entire block of data to new memory locations starting
at 3250H.
Write an 8085 assembly language program, which adds two three-byte
numbers. The first number is stored in memory locations 3800H, 3801H &
3802H and the second number is stored in memory location 3803H, 3804H &
3805H. Store the answer in memory locations 3810H upwards.
Write an 8085 assembly language program, which checks the number in
memory location 2800H. If the number is an even number, then put FF in
memory location 2810H, otherwise put 00.
Write a program to count the data byte in memory that equal to 55H starting at
memory location 2800H through 280FH. Place the count value in B register.
Write an 8085 assembly language program to find the smallest value between
two number in memory location 2800H and 2801. Store the value in memory
location 3000H.
Page 18 of 18
Lecture Four
8086 Microprocessor
8086 Microprocessor
The main features of 8086 p are:

It is a 16-bit Microprocessor (p). Its ALU, internal registers works with 16bit binary
word.
8086 has a 20 bit address bus can access up to 220= 1 MB memory locations.
8086 has a 16bit data bus. It can read or write data to a memory/port either 16bits
or 8 bit at a time.
It can support up to 64K I/O ports.
It provides 14, 16 -bit registers.
Frequency range of 8086 is 6-10 MHz
It has multiplexed address and data bus AD0- AD15 and A16 A19.
It requires single phase clock with 33% duty cycle to provide internal timing.
It can prefetch upto 6 instruction bytes from memory and queues them in order to
speed up instruction execution.
It requires +5V power supply.
A 40 pin dual in line package.
8086 is designed to operate in two modes, Minimum mode and Maximum mode.
o The minimum mode is selected by applying logic 1 to the MN / MX# input
pin. This is a single microprocessor configuration.
o The maximum mode is selected by applying logic 0 to the MN / MX# input
pin. This is a multi micro processors configuration.
Page 1 of 35
Lecture Four
8086 Microprocessor

Figure (1) shows the Pin diagram of 8086. The description follows it.
Fig. 1: Pin Diagram of 8086
The Microprocessor 8086 is a 16-bit CPU available in different clock rates and
packaged in a 40 pin CERDIP or plastic package.
The 8086 operates in single processor or multiprocessor configuration to achieve

high performance. The pins serve a particular function in minimum mode (single
processor
mode)
and
other
function
in
maximum
(multiprocessor mode).
The 8086 signals can be categorized in three groups.

Page 2 of 35
mode
configuration
Lecture Four
8086 Microprocessor
The first are the signal having common functions in minimum as well as
maximum mode.
The second are the signals which have special functions for minimum
mode
The third are the signals having special functions for maximum mode.
The following signal descriptions are common for both modes.
AD15-AD0:
o
These are the time multiplexed memory I/O address and data lines.
Contain the rightmost eight bits of the memory address or I/O port number
when ALE is active logic 1 or contain data whenever ALE is logic 0
(Multiplexed address(ALE=1)/data bus(ALE=0).
These pins are at their high impedance stste during a hold acknowledge
A19/S6, A18/S5, A17/S4, A16/S3:

o
The address/status bus bits are multiplexed to provide address signals

A19-A16 also status bits S6-S3.
These pins also attain a high impedance state during the hold
acknowledge.
The S4 and S3 show which segment register is accessed during the

current bus cycle, see table below.
S5 is the logic level of the internal interrupt enable flag,( Indicates condition
of IF flag bits)
S6 is always logic 0.
S4
S3
Function
Extra segment
Stack segment
Code or No segment
Data segment
BHE/S7: The bus high enable is used to Enables the most significant data bus
bits (D15 -D8 ) during a read or write operation. The state of S7 is always a logic 1.
Page 3 of 35
Lecture Four
8086 Microprocessor
RD Read: This signal on low indicates the peripheral that the processor is
performing memory or I/O read operation. The signal remains tristated (high
impedance state) during a hold acknowledge.
READY : This is the acknowledgement from the slow device or memory that they
have completed the data transfer. The signal made available by the devices is
synchronized by the 8284A clock generator to provide ready input to the 8086.
The signal is active high.
INTR-Interrupt Request : This is a triggered input. This is sampled during the last
clock cycles of each instruction to determine the availability of the request. If any
interrupt request is pending, the processor enters the interrupt acknowledge cycle.
This can be internally masked by resulting the interrupt enable flag. This signal is
active high and internally synchronized.
TEST :
o
An input that is tested by the WAIT instruction.
Commonly connected to the 8087 coprocessor.
This input is examined by a WAIT instruction. If the TEST pin goes low,
execution will continue, else the processor remains in an idle state. The
input is synchronized internally during each clock cycle on leading edge of
clock.
CLK- Clock Input: The clock input provides the basic timing for processor
operation and bus control activity. Its an asymmetric square wave with 33% duty
cycle.
NMI - Non-maskable interrupt: Similar to INTR except IF flag bit is not consulted
and interrupt is vector 2.
RESET:
o
Microprocessor resets if this pin is held high for 4 clock periods.
Instruction execution begins at FFFF0H and IF flag is cleared.
VCC/GND: Power supply (5V) and GND (0V).
MN MX - Minimum/Maximum mode: select either minimum mode or maximum

mode operation for the microprocessor.
Page 4 of 35
Lecture Four
8086 Microprocessor
8086 Minimum mode of operation:
In this mode, all the control signals are given out by the microprocessor chip itself.
There is a single microprocessor in the minimum mode system.
The microprocessor 8086 is operated in minimum mode by strapping its MN MX

pin to logic 1(connecting the MN MX pin directly to +5V).
Fig. 2: Minimum mode of 8086

The following signal descriptions are Minimum mode pins.
The following pin functions are for the minimum mode operation of 8086.
Page 5 of 35
Lecture Four
8086 Microprocessor
M IO : This is a status line logically equivalent to S2 in maximum mode. When it
is low, it indicates the CPU is having an I/O operation, and when it is high, it
indicates that the CPU is having a memory operation. It is tristated during local
bus hold acknowledge .
INTA Interrupt Acknowledge: This signal is used as a read strobe for interrupt
acknowledge cycles. i.e. when it goes low, the processor has accepted the
interrupt.
ALE Address Latch Enable: This output signal indicates the availability of the
valid address on the address/data lines, and is connected to latch enable input of
latches. This signal is active high and is never tristated.
DT R Data Transmit/Receive: This output is used to shows that the
microprocessor data bus is transmitting ( DT R =1) or receiving ( DT R =0) data.

This signal is used to enable external data bus buffer.
DEN Data Bus Enable: activates external data bus buffers.
HOLD :The hold input Requests a direct memory access (DMA). When the HOLD
signal is logic 1, the microprocessor stops execution software and places its
address, data and control bus at the high-impedance state.
HLDA- Hold Acknowledge: Indicates that the microprocessor has entered the
hold state.
8086 Maximum mode of operation:
In the maximum mode, the 8086 is operated by strapping the MN/MX pin to
ground.
In this mode, the processor derives the status signal S2, S1, S0. Another chip
called bus controller derives the control signal using this status information .
In the maximum mode, there may be more than one microprocessor in the system
configuration.
The microprocessor 8086 is operated in maximum mode by connecting its

MN MX pin to logic 0 (connecting the MN MX pin directly to GND).
Page 6 of 35
Lecture Four
8086 Microprocessor
Fig. 3: Maximum mode of 8086
The following pin functions are applicable for maximum mode operation of 8086.
RO GT 1 and RO GT 0 Request/Grant : These pins request direct memory
accesses (DMA) during maximum mode operation. These lines are bi-directional,
and are used to both request and grant a DMA operation.
S2 , S1 , S0 Status Lines: the status bits indicate the function of the current bus
cycle. These signals are normally decoded by the 8288 bus controller. Table (2)
shows the function of these three statues bits in the maximum mode.
Page 7 of 35
Lecture Four
8086 Microprocessor
Table (2): Bus control function generated by the bus controller using
Function
S2
S1
S0
Interrupt Acknowledge
Read I/O port
Write I/O port
Halt
Op-Code Fetch
Read Memory
Write Memory
Passive
LOCK: Lock output is used to lock peripherals off the system. Activated by using
the LOCK: prefix on any instruction.
QS1 and QS0- Queue statues bits: show the status of the internal instruction.
These pins are provides for access by the numeric coprocessor see table (3) for
the operation of the queue status bits.
Table (2): Queue status bits
QS1
QS0
Indication
No Operation (Queue is idel)
First Byte of opcode
Empty Queue
Subsequent Byte from the opcode
Page 8 of 35
Lecture Four
8086 Microprocessor
Fig. 4: Block diagram of the 8086 microprocessor architecture.
Page 9 of 35
Lecture Four
8086 Microprocessor
8086 has two blocks Bus Interfacing Unit (BIU) and Execution Unit (EU).
The BIU performs all bus operations such as instruction fetching, reading and
writing operands for memory and calculating the addresses of the memory
operands. The instruction bytes are transferred to the instruction queue.
EU executes instructions from the instruction system byte queue.
Both units operate asynchronously to give the 8086 an overlapping instruction

fetch and execution mechanism which is called as Pipelining. This results in
efficient use of the system bus and system performance.
BIU contains Instruction queue, Segment registers, Instruction pointer, Address

adder.
EU contains Control circuitry, Instruction decoder, ALU, Pointer and Index register
Flag register.
BUS INTERFACE UNIT:
It provides a full 16 bit bidirectional data bus and 20 bit address bus.
The bus interface unit is responsible for performing all external bus operations.
Specifically it has the following functions:
Instructions fetch, Instruction queuing, Operand fetch and storage, Address

relocation and Bus control.
The BIU uses a mechanism known as an instruction stream queue to implement a

pipeline architecture.
This queue permits prefetch of up to six bytes of instruction code. When ever the
queue of the BIU is not full, it has room for at least two more bytes and at the
same time the EU is not requesting it to read or write operands from memory, the
BIU is free to look ahead in the program by prefetching the next sequential
instruction.
These prefetching instructions are held in its FIFO queue. With its 16 bit data bus,
the BIU fetches two instruction bytes in a single memory cycle.
After a byte is loaded at the input end of the queue, it automatically shifts up
through the FIFO to the empty location nearest the output.
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Lecture Four
8086 Microprocessor
The EU accesses the queue from the output end. It reads one instruction byte
after the other from the output of the queue. If the queue is full and the EU is not
requesting access to operand in memory.
These intervals of no bus activity, which may occur between bus cycles are known
as Idle state.
If the BIU is already in the process of fetching an instruction when the EU request
it to read or write operands from memory or I/O, the BIU first completes the
instruction fetch bus cycle before initiating the operand read / write cycle.
The BIU also contains a dedicated adder which is used to generate the 20bit
physical address that is output on the address bus. This address is formed by
adding an appended 16 bit segment address and a 16 bit offset address.
For example: The physical address of the next instruction to be fetched is formed
by combining the current contents of the code segment CS register and the
current contents of the instruction pointer IP register.
The BIU is also responsible for generating bus control signals such as those for
memory read or write and I/O read or write.
EXECUTION UNIT
The Execution unit is responsible for decoding and executing all instructions.
The EU extracts instructions from the top of the queue in the BIU, decodes them,
generates operands if necessary, passes them to the BIU and requests it to
perform the read or write bys cycles to memory or I/O and perform the operation
specified by the instruction on the operands.
During the execution of the instruction, the EU tests the status and control flags
and updates them based on the results of executing the instruction.
If the queue is empty, the EU waits for the next instruction byte to be fetched and
shifted to top of the queue.
When the EU executes a branch or jump instruction, it transfers control to a

location corresponding to another set of sequential instructions.
Whenever this happens, the BIU automatically resets the queue and then begins
to fetch instructions from this new location to refill the queue.
Page 11 of 35
Lecture Four
8086 Microprocessor
Registers of 8086
The 8086 microprocessor has a total of fourteen registers that are accessible to the
programmer. It is divided into four groups. They are:
Four General purpose registers
Four Index/Pointer registers
Four Segment registers
Two Other registers
General purpose registers:

Accumulator register consists of two 8-bit registers AL and AH, which can be combined
together and used as a 16-bit register AX. AL in this case contains the loworder byte of
the word, and AH contains the high-order byte. Accumulator can be used for I/O
operations and string manipulation.
Base register consists of two 8-bit registers BL and BH, which can be combined
together and used as a 16-bit register BX. BL in this case contains the low-order byte of
the word, and BH contains the high-order byte. BX register usually contains a data
pointer used for based, based indexed or register indirect addressing.
Count register consists of two 8-bit registers CL and CH, which can be combined
together and used as a 16-bit register CX. When combined, CL register contains the
loworder byte of the word, and CH contains the high-order byte. Count register can be
used in Loop, shift/rotate instructions and as a counter in string manipulation
Data register consists of two 8-bit registers DL and DH, which can be combined together
and used as a 16-bit register DX. When combined, DL register contains the low order
byte of the word, and DH contains the high-order byte. Data register can be used as a
port number in I/O operations. In integer 32-bit multiply and divide instruction the DX
register contains high-order word of the initial or resulting number.
Index or Pointer Registers
These registers can also be called as Special Purpose registers.
Page 12 of 35
Lecture Four
8086 Microprocessor
Source Index (SI) is a 16-bit register. SI is used for indexed, based indexed and register
indirect addressing, as well as a source data address in string manipulation instructions.
Used in conjunction with the DS register to point to data locations in the data segment.
Destination Index (DI) is a 16-bit register. Used in conjunction with the ES register in
string operations.
DI is used for indexed, based indexed and register indirect
addressing, as well as a destination data address in string manipulation instructions. In

short, Destination Index and SI Source Index registers are used to hold address.
Stack Pointer (SP) is a 16-bit register pointing to program stack, ie it is used to hold the
address of the top of stack. The stack is maintained as a LIFO with its bottom at the start
of the stack segment (specified by the SS segment register).Unlike the SP register, the
BP can be used to specify the offset of other program segments.
Base Pointer (BP) is a 16-bit register pointing to data in stack segment. It is usually
used by subroutines to locate variables that were passed on the stack by a calling
program. BP register is usually used for based, based indexed or register indirect
addressing.
Segment Registers
Most of the registers contain data/instruction offsets within 64 KB memory segment.
There are four different 64 KB segments for instructions, stack, data and extra data. To
specify where in 1 MB of processor memory these 4 segments are located the processor
uses four segment registers.
Code segment (CS) is a 16-bit register containing address of 64 KB segment with
processor instructions. The processor uses CS segment for all accesses to instructions
referenced by instruction pointer (IP) register. CS register cannot be changed directly.
The CS register is automatically updated during far jump, far call and far return
instructions.
Stack segment (SS) is a 16-bit register containing address of 64KB segment with
program stack. By default, the processor assumes that all data referenced by the stack
pointer (SP) and base pointer (BP) registers is located in the stack segment. SS register
can be changed directly using POP instruction.
Data segment (DS) is a 16-bit register containing address of 64KB segment with
program data. By default, the processor assumes that all data referenced by general
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Lecture Four
8086 Microprocessor
registers (AX, BX, CX, DX) and index register (SI, DI) is located in the data segment. DS
register can be changed directly using POP and LDS instructions.
Extra segment (ES) used to hold the starting address of Extra segment. Extra segment
is provided for programs that need to access a second data segment. Segment registers
cannot be used in arithmetic operations.
Other registers of 8086

Instruction Pointer (IP) is a 16-bit register. This is a crucially important register which is
used to control which instruction the CPU executes. The ip, or program counter, is used
to store the memory location of the next instruction to be executed. The CPU checks the
program counter to ascertain which instruction to carry out next. It then updates the
program counter to point to the next instruction. Thus the program counter will always
point to the next instruction to be executed.
Flag Register determines the current state of the processor. They are modified
automatically by CPU after mathematical operations, this allows to determine the type of
the result, and to determine conditions to transfer control to other parts of the program.
8086 has 9 flags and they are divided into two categories:
1. Status Flags
Status Flags represent result of last arithmetic or logical instruction executed.
Conditional flags are as follows:
Carry Flag (CF):
arithmetic.
This flag indicates an overflow condition for unsigned integer
It is also used in multiple-precision arithmetic.
Auxiliary Flag (AF):
If an operation performed in ALU generates a carry/barrow from
lower nibble (i.e. D0 D3) to upper nibble (i.e. D4 D7), the AF flag is set i.e. carry given
by D3 bit to D4 is AF flag. This is not a general-purpose flag, it is used internally by the
processor to perform Binary to BCD conversion.
Parity Flag (PF): This flag is used to indicate the parity of result. If lower order 8-bits of
the result contains even number of 1s, the Parity Flag is set and for odd number of 1s,
the Parity Flag is reset.
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Lecture Four
8086 Microprocessor
Zero Flag (ZF): It is set; if the result of arithmetic or logical operation is zero else it is
reset.
Sign Flag (SF): In sign magnitude format the sign of number is indicated by MSB bit. If
the result of operation is negative, sign flag is set.
Overflow Flag (OF): It occurs when signed numbers are added or subtracted. An OF
indicates that the result has exceeded the capacity of machine.
2. Control Flags
Control flags are set or reset deliberately to control the operations of the execution unit.
Control flags are as follows:
1. Trap Flag (TP):

It is used for single step control.
It allows user to execute one instruction of a program at a time for
debugging.
When trap flag is set, program can be run in single step mode.
2. Interrupt Flag (IF):
It is an interrupt enable/disable flag.
If it is set, the maskable interrupt of 8086 is enabled and if it is reset, the
interrupt is disabled.
It can be set by executing instruction sit and can be cleared by executing

CLI
instruction.
3. Direction Flag (DF):

It is used in string operation.
If it is set, string bytes are accessed from higher memory address to lower
memory address.
When it is reset, the string bytes are accessed from lower memory address
to higher memory address.
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Lecture Four
8086 Microprocessor
8086 MEMORY MAP

Still another view of the 8086/88 memory space could be as 16 64K-byte blocks
beginning at hex address 000000h and ending at address 0FFFFFh. This division into
64K-byte blocks is an arbitrary but convenient choice. This is because the most
significant hex digit increments by 1 with each additional block. That is, address 20000h
is 65.536 bytes higher in memory than address 10000h. Be sure to note that five hex
digits are required to represent a memory address.
64 K
384 K ROM
A0000H
640 K RAM
1K
ROM BIOS
ROM BASIC
F0000H FFFFFH
Present in older computers
Reserved ROM
Video BIOS ROM
C0000H - C7FFFH
Video RAM
A0000H BFFFFH
User RAM
Resident portion of DOS
Varies between 12 K to 40 K
BIOS and DOS data area

Interrupt Vector Table
00400H - 005FFH
00000H - 003FFH
Page 16 of 35
Lecture Four
8086 Microprocessor
The diagram is called a memory map. This is because, like a road map, it is a guide
showing how the system memory is allocated. This type of information is vital to the
programmer, who must know exactly where his or her programs can be safely loaded.
Note that some memory locations are marked reserved and others dedicated. The
dedicated locations are used for processing specific system interrupts and the reset
function. Intel has also reserved several locations for future H/W and S/W products. If
you make use of these memory locations, you risk incompatibility with these future
products.
MEMORY SEGMENTATION
The Memory Address Space (MAS) is divided into 65,536 (i.e., 10,000H)
paragraphs. Each paragraph is 16 (i.e., 10H) consecutive bytes. Thus each paragraph
starts at a physical address whose rightmost hexadecimal digit is zero:
Addresses within a segment can range from address 00000h to address 0FFFFh. This
corresponds to the 64K-byte length of the segment. An address within a segment is
called an offset or logical address. A logical address gives the displacement from the
address base of the segment to the desired location within it, as opposed to its "real"
address, which maps directly anywhere into the 1 MB memory space. This "real" address
is called the physical address.
What is the difference between the physical and the logical address?
The physical address is 20 bits long and corresponds to the actual binary code output by
the BIU on the address bus lines. The logical address is an offset from location 0 of a
given segment.
When two segments overlap it is certainly possible for two different logical addresses to
map to the same physical address. This can have disastrous results when the data
begins to overwrite the subroutine stack area, or vice versa. For this reason you must be
very careful when segments are allowed to overlap.
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Lecture Four
8086 Microprocessor
You should also be careful when writing addresses on paper to do so clearly. To specify
the logical address XXXX in the stack segment, use the convention SS:XXXX, which is
equal to [SS] * 16 + XXXX.
FFFFFH
10H bytes
Paragraph
FFFFH
FFFF0H
FFFEFH
00030H
0002FH
10H bytes
00020H
0001FH
10H bytes
Paragraph 2H
Paragraph
1H
00010H
0000FH
10H bytes
Paragraph
0H
00000H
Physical Memory Segments

The address bus of the 8086/8088 is 20-bits.
Hence the microprocessor uses 20-bit memory addresses; but its registers are 16
bits.
The concept of memory segmentation is used to solve this problem of using 20-bit
addresses in a 16-bit microprocessor.
The 8086/8088 partitions its memory into 65,536 physical memory segments.
Page 18 of 35
Lecture Four
8086 Microprocessor
A physical memory segment is a block of 216 (i.e., 64K or 10,000H) consecutive bytes
starting at a paragraph boundary.
The segments overlap but they all begin at different paragraph boundaries.
All segments from the one starting at F0000h to the one starting at FFFF0h wrap
around and end at lower memory addresses.
Since each segment starts at a physical address whose leftmost hexadecimal digit is
zero, this digit need not be stored, hence a 16-bit segment register can be used to
store the remaining four digits of the 20-bit address.
Within a segment, a memory location is specified by giving an offset. This is the
number of bytes from the beginning of the segment.
Since a segment is 10,000H bytes, the first byte in a segment has offset 0000h and
the last byte has offset FFFFh (Note: Offsets are unsigned numbers).
Thus a memory location may be specified by providing the 16-bit segment base
address, and a 16-bit offset, written in the form segment:offset; this is known as a
logical address for the memory location.
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Lecture Four
8086 Microprocessor
For example, the logical address A4FB:4872h means offset 4872h within segment
A4FBh, that is, the segment starting at physical address A4FB0h. To obtain the
corresponding 20-bit physical (i.e., absolute) address, the 8086/8088 microprocessor
first shifts the segment base address 4 bits to the left (this is equivalent to multiplying
by 10H), and then adds the offset. Thus the physical address for A4FB:4872h is:
A4FB0h
+
4872h
A9822h
(20-bit physical address)
Because segments may overlap, the segment:offset form of an address is not unique
for a particular memory location as is the case for the physical address of that
memory location. For example consider the following:
Example:
A memory location has physical address 80FD2h. In what segment does it have offset
BFD2h ?
Solution:
physical address = segment * 10h
offset
segment * 10h = physical address - offset
Hence:
physical address = 80FD2h
-
offset =
BFD2h
75000h
Thus the segment is 7500h
Example:
For the memory location whose physical address is 1256Ah, give the address in
segment:offset form for segments 1256h and 1240h.
Solution:
Let X be the offset in segment 1256h and Y the offset in segment 1240h. We have:
Page 20 of 35
Lecture Four
8086 Microprocessor
(a) 1256Ah = 12560h + X X = 000Ah

hence 1256Ah = 1256:000Ah
(1)
(b) 1256Ah = 12400h + Y Y = 016Ah

hence 1256Ah = 1240:016Ah
(2)
(1) & (2) 1256:000AH = 1240:016AH
000Ah
1256h
016Ah
1240h
Program (or Logical) segments

A logical segment is part of a program that is loaded into memory beginning on a
paragraph boundary
(thus the base address of a logical segment has a rightmost hexadecimal digit of
zero).
A logical segment is contained within a particular physical segment. Since the size of
a physical segment is 64K, the maximum size of a logical segment is 64K.
Logical segments may or may not overlap.
There are four types of logical segments: Code segment, Data segment, Extra
segment, and Stack segment.
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Lecture Four
8086 Microprocessor
The Code segment contains the instructions of a program. The Data segment
provides a read/write memory in which the data of a program can be stored. The
Extra segment is usually used for data storage. Some string operations use the Extra
segment to handle memory addressing. The Stack segment is used for temporary
storage of addresses and data. It is in this segment that the values of the IP register,
the Flags register, and other registers are stored whenever an Interrupt or subroutine
call occurs.
Every 8086/8088 assembly language program must contain an explicitly defined
Code segment. An 8086/8088 assembly language program which generates an
executable file with extension .EXE must have an explicitly defined Stack segment.
Such a program may or may not contain the Data or the Extra segment. An
8086/8088 assembly language program which generates an executable file with
extension .COM has only one explicitly defined segment: the Code segment. The
Stack segment for such a program is implicit. Thus the maximum size for an
8086/8088 COM format Assembly language program is 64K.
An EXE format 8086/8088 Assembly language program may contain multiple
segments of a certain type; however only four logical segments can be active at a
time.
To keep track of the various logical segments, the 8086/8088 uses each of its four
segment registers to hold a 16-bit portion (called a segment number) of the 20-bit
starting address of a logical segment. The remaining four rightmost bits of the
address are implied 0000 because a logical segment starts at a paragraph boundary.
The CS, DS, SS, and ES registers contain the code, data, stack, and extra segment
numbers, respectively. The segment registers provide the segment base address part
of a logical memory address (i.e., segment:offset address):
CS:IP
is the segment:offset address of the next instruction to be executed.
DS:offset is the segment:offset address of the byte with the given offset in the data
segment.
SS:SP
is the segment:offset address of the top of the stack.
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SS:BP
Lecture Four
8086 Microprocessor
is the segment:offset address of the byte, in the stack, whose offset is in the
BP register.
DS:SI
is the segment offset:address of a byte in the data segment at which the

source operand of a string instruction starts.
ES:DI
is the segment:offset address of a byte in the extra segment at which the

destination operand of a string instruction starts.
The segment registers must be loaded with the segment numbers. Just what values are
loaded is dependent in part on how the linker and loader have assigned the logical
segments to memory locations, and on how the segment registers have been initialized
during the loading process. Typically, the CS register will be loaded with the proper code
segment number so that, in conjunction with the IP register, the programs first
executable instruction will be referenced. The SS and SP registers will also be properly
loaded if the stack segment is explicitly defined in the program. The other segment
registers, DS and ES, must be explicitly loaded by the programmer if they are
used by the program.
ADVANTAGES OF SEGMENTED MEMORY

Segmented memory can seem confusing at first. What you must remember is that
the program op-codes will be fetched from the code segment, while program data
variables will be stored in the data and extra segments. Stack operations use registers
BP or SP and the stack segment. As we begin writing programs the consequences of
these definitions will become clearer.
An immediate advantage of having separate data and code segments is that one
program can work on several different sets of data. This is done by reloading register DS
to point to the new data. Perhaps the greatest advantage of segmented memory is that
programs that reference logical addresses only can be loaded and run anywhere in
memory. This is because the logical addresses always range from 00000h to 0FFFFh,
independent of the code segment base. Such programs are said to be relocatable,
meaning that they will run at any location in memory. The requirements for writing
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Lecture Four
8086 Microprocessor
relocatable programs are that no references be made to physical addresses, and no

changes to the segment registers are allowed.
Addressing Modes of 8086 An overview

Definition: An instruction acts on any number of operands. The way an instruction
accesses its operands is called its Addressing modes.
Operands may be of three types:
o
Implicit
Explicit
Both Implicit and Explicit.
Implicit operands mean that the instruction by definition has some specific operands.
The programmers do NOT select these operands.
Example: Implicit operands
XLAT ; automatically takes AL and BX as operands
AAM ; it operates on the contents of AX.
Explicit operands mean the instruction operates on the operands specified by the
programmer.
Example: Explicit operands
MOV AX, BX; it takes AX and BX as operands
XCHG SI, DI; it takes SI and DI as operands
Implicit and explicit operands

Example: Implicit/Explicit operands
MUL BX;
automatically multiply BX explicitly times AX
The location of an operand value in memory space is called the Effective Address (EA)
We can classify the addressing modes of 8086 into four groups:
Page 24 of 35
Immediate addressing
Register addressing
Memory addressing
I/O port addressing
Lecture Four
8086 Microprocessor
The first three Addresssing modes are clearly explained.
Immediate Addressing Mode

In this addressing mode, the operand is stored as part of the instruction. The
immediate operand, which is stored along with the instruction, resides in the code
segment -- not in the data segment. This addressing mode is also faster to execute an
instruction because the operand is read with the instruction from memory. Here are some
examples:
Example: Immediate Operands
MOV AL, 20
; move the constant 20 into register AL
ADD AX, 5
; add constant 5 to register EAX
MOV DX, offset msg
; move the address of message to register DX
Register addressing mode

In this addressing mode, the operands may be:
reg16: 16-bit general registers: AX, BX, CX, DX, SI, DI, SP or BP.
reg8 : 8-bit general registers: AH, BH, CH, DH, AL, BL, CL, or DL.
Sreg : segment registers: CS, DS, ES, or SS. There is an exception: CS cannot
be a destination.
For register addressing modes, there is no need to compute the effective address. The
operand is in a register and to get the operand there is no memory access involved.
Example: Register Operands

MOV AX, BX
; mov reg16, reg16
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Lecture Four
8086 Microprocessor
ADD AX, SI
; add reg16, reg16
MOV DS, AX
; mov Sreg, reg16
Some rules in register addressing modes:

1. You may not specify CS as the destination operand.
Example: MOV CS, 02H > wrong
2. Only one of the operands can be a segment register. You cannot move data from one
segment register to another with a single MOV instruction. To copy the value of CS to
DS, you would have to use some sequence like:
MOV DS,CS -> wrong
MOV AX, CS
MOV DS, AX -> the way we do it
You should never use the segment registers as data registers to hold arbitrary values.
They should only contain segment addresses.
Memory Addressing Modes

Memory (RAM) is the main component of a computer to store temporary data and
machine instructions. In a program, programmers many times need to read from and
write into memory locations.
There are different forms of memory addressing modes
1. Direct Addressing
2. Register indirect addressing
3. Based addressing
4. Indexed addressing
5. Based indexed addressing
6. Based indexed with displacement
1. Direct Addressing Mode

The instruction MOV AL,DS:[8088H] loads the AL register with a copy of the byte
at memory location 8088h. Likewise, the instruction MOV DS:[1234H],DL stores the
value in the DL register to memory location 1234H. By default, all displacement-only
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Lecture Four
8086 Microprocessor
values provide offsets into the data segment. If you want to provide an offset into a
different segment, you must use a segment override prefix before your address. For
example, to access location 1234H in the extra segment (ES) you would use an
instruction of the form MOV AX,ES:[1234H]. Likewise, to access this location in the code
segment you would use the instruction MOV AX, CS:[1234H]. The DS: prefix in the
previous examples is not a segment override.
The instruction MOV AL,DS:[8088H] is same as MOV AL, [8088H]. If not mentioned DS
register is taken by default.
2. Register Indirect Addressing Mode

The 80x86 CPUs let you access memory indirectly through a register using the
register indirect addressing modes. There are four forms of this addressing mode on the
8086, best demonstrated by the following instructions:
MOV AL, [BX]
MOV AL, [BP]
MOV AL, [SI]
MOV AL, [DI]
The [BX], [SI], and [DI] modes use the DS

segment by default. The [BP] addressing
mode uses the stack segment (SS) by
default. You can use the segment override
prefix symbols if you wish to access data
in
different
segments.
The
following
instructions demonstrate the use of these

overrides:
MOV AL, CS:[BX]
MOV AL, DS:[BP]
MOV AL, SS:[SI]
MOV AL, ES:[DI]
Page 27 of 35
Lecture Four
8086 Microprocessor
Based Addressing Mode

8-bit or 16-bit instruction operand is added to the contents of a base register (BX or BP),
the resulting value is a pointer to location where data resides.
MOV AL, [BX],[SI]
MOV BL , [BP],[DI]
MOV CL , [BP],[DI]
IF BX=1000H , SI=0880H
MOV AL, [1000+880]
MOV AL,[1880]
Indexed Addressing Modes

The indexed addressing modes use the following syntax:
MOV AL, [BX+DISP]
MOV AL, [BP+DISP]
MOV AL, [SI+DISP]
MOV AL, [DI+DISP]
Code Example
MOV BX, 100H
MOV AL, [BX + 15]
MOV AL, [BX + 16]
If BX contains 1000h, then the instruction MOV CL, [BX+20H] will load CL from memory
location DS:1020H. Likewise, if BP contains 2020H, MOV DH, [BP+1000H] will load dh
from location SS:3020. The offsets generated by these addressing modes are the sum of
the constant and the specified register. The addressing modes involving BX, SI, and DI
all use the data segment, the [BP+disp] addressing mode uses the stack segment by
default. As with the register indirect addressing modes, you can use the segment
override prefixes to specify a different segment:
MOV AL, SS:[BX+Disp]
MOV AL, ES:[BP+disp]
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Lecture Four
8086 Microprocessor
MOV AL, CS:[SI+disp]

MOV AL, SS:[DI+Disp]
Example: MOV AX, [DI + 100]
Based Indexed Addressing Modes

The based indexed addressing modes are simply combinations of the register
indirect addressing modes. These addressing modes form the offset by adding together
a base register (BX or BP) and an index register (SI or DI). The allowable forms for these
addressing modes are:
MOV
AL, [BX][SI]
MOV
AL, [BX][DI]
MOV
AL, [BP][SI]
MOV
AL, [BP][DI]
Suppose that
BX = 1000H, SI = 880H.
Then the instruction
MOV
AL, [BX][SI]
would load AL from location DS:1880h.

Likewise, if
BP = 1598H
DI = 1004,
MOV AX,[BP+DI]
Will load the 16 bits in AX from locations SS:259C and SS:259D.
The addressing modes that do not involve BP use the data segment by default. Those
that have BP as an operand use the stack segment by default.
Based Indexed Plus Displacement Addressing Mode
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Lecture Four
8086 Microprocessor
These addressing modes are a slight modification of the base/indexed addressing

modes with the addition of an eight bit or sixteen bit constant. The following are some
examples of these addressing modes
MOV
AL, DISP[BX][SI]
MOV
AL, DISP[BX+DI]
MOV
AL, [BP+SI+DISP]
MOV
AL, [BP][DI][DISP]
Suppose
BP = 1000H,
BX =2000H,
SI = 120H, and DI = 5.
Then
MOV AL, 10H[BX+SI]
loads AL from
address DS:2130;
MOV CH, 125H[BP+DI] loads CH from location SS:112A;
MOV BX, CS:2[BX][DI] loads BX from location CS:2007.
8086 Instruction Set and its Classification

The instructions of 8086 are classified into SIX groups. They are:
1. DATA TRANSFER INSTRUCTIONS
2. ARITHMETIC INSTRUCTIONS
3. BIT MANIPULATION INSTRUCTIONS
4. STRING INSTRUCTIONS
5. PROGRAM EXECUTION TRANSFER INSTRUCTIONS
6. PROCESS CONTROL INSTRUCTIONS
1. DATA TRANSFER INSTRUCTIONS
Page 30 of 35
Lecture Four
8086 Microprocessor
The DATA TRANSFER INSTRUCTIONS are those, which transfers the DATA
from any one source to any one destination. The datas may be of any type. They are
again classified into four groups. They are:
General Purpose
Simple Input And
Special Address
Flag Transfer
Byte Or Word
Output Port
Transfer
Instructions
Transfer Instructions Transfer Instruction
Instruction
MOV
LEA
LAHF
PUSH
IN
LDS
SAHF
POP
OUT
LES
PUSHF
XCHG
POPF
XLAT
2. ARITHMETIC INSTRUCTIONS
These instructions are those which are useful to perform Arithmetic calculations,
such as addition, subtraction, multiplication and division. They are again classified into
four groups. They are:
Addition
Subtraction
Multiplication
Division
Instructions
Instructions
Instructions
Instructions
ADD
SUB
MUL
DIV
ADC
SBB
IMUL
IDIV
INC
DEC
AAM
AAD
AAA
NEG
CBW
DAA
CMP
CWD
AAS
DAS
3. BIT MANIPULATION INSTRUCTIONS

These instructions are used to perform Bit wise operations.
LOGICAL
SHIFT
Page 31 of 35
ROTATE
Lecture Four
8086 Microprocessor
INSTRUCTIONS INSTRUCTIONS INSTRUCTIONS

NOT
SHL / SAL
ROL
AND
SHR
ROR
OR
SAR
RCL
XOR
RCR
TEST
4. STRING INSTRUCTIONS
The string instructions function easily on blocks of memory. They are user friendly
instructions, which help for easy program writing and execution. They can speed up the
manipulating code. They are useful in array handling, tables and records.
STRING INSTRUCTIONS
REP
REPE
REPZ
REPNE
REPNZ
MOVS
MOVSB
MOVSW
COMPS / COMPSB / COMPSW

SCAS
SCASB
SCASW
LODS
LODSB
LODSW
STOS / STOSB / STOSW
5. PROGRAM EXECUTION TRANSFER INSTRUCTIONS

These instructions transfer the program control from one address to other
address. (Not in a sequence). They are again classified into four groups. They are:
Page 32 of 35
Unconditional
Transfer
Instructions
CALL
RET
JMP
Lecture Four
8086 Microprocessor
Conditional Transfer
Instructions
JA /
JNBE
JAE /
JNB
JB /
JNAE
JBE /
JNA
JC
JE / JZ
JG /
JNLE
JGE /
JNL
JL /
JNGE
Iteration Control
Instructions
LOOP
JLE / JNG
LOOPE / LOOPZ
JNC
LOOPNE
/ LOOPNZ
JNE / JNZ
JCXZ
JNO
JNP / JPO
JNS
JO
JP / JPE
JS
Interrupt
Instructions
INT
INTO
IRET
6. PROCESS CONTROL INSTRUCTIONS

These instructions are used to change the process of the Microprocessor. They
change the process with the stored information. They are again classified into Two
groups. They are:
Flag Set / Clear Instructions
External Hardware
Synchronization Instructions
STC
CLC
CMC
STD
CLD
STI
CLI
HLT
WAIT
ESC
LOCK
NOP
Page 33 of 35
Lecture Four
8086 Microprocessor
8086 Interview Questions

1. What are the flags in 8086?
2. What are the various interrupts in 8086?
3. What is meant by Maskable interrupts?
4. What is Non-Maskable interrupts?
5. Which interrupts are generally used for critical events?
6. Give examples for Maskable interrupts?
7. Give example for Non-Maskable interrupts?
8. What is the Maximum clock frequency in 8086?
9. What are the various segment registers in 8086?
10.
Which Stack is used in 8086?
11.
What are the address lines for the software interrupts?
12.
What is SIM and RIM instructions?
13.
Which is the tool used to connect the user and the computer?
14.
What is the position of the Stack Pointer after the PUSH instruction?
15.
What is the position of the Stack Pointer after the POP instruction?
16.
Logic calculations are done in which type of registers?
17.
What are the different functional units in 8086?
18.
What is meant by cross-compiler?
19.
What are the address lines for the hardware interrupts?

Page 34 of 35
Lecture Four
8086 Microprocessor
20.
Which Segment is used to store interrupt and subroutine return address registers?
21.
Which Flags can be set or reset by the programmer and also used to control the
operation of the processor?
22.
What does EU do?
23.
Which microprocessor accepts the program written for 8086 without any changes?
24.
What is the difference between 8086 and 8088?
Exercise
Write an 8086 Program to
1. Add two packed BCD numbers entered through keyboard.

2. Double digit addition, subtraction, multiplication and division program using 8086
microprocessor
3. Fibonacci series using 8086 microprocessor asseembly language

4. Right and Left shift a bit of data in 8086
5. Program to Interface Seven Segment Display with 8086 microprocessor
6. blink a digit of seven segment display
7. Interface a Dot Matrix Display with 8086 microprocessor
Page 35 of 35
Lecture Five
The third x86 generation of x86 microprocessors, Intel 80386 (i386) was a 32-bit
microprocessor backwards compatible with previous generations of 80x86 CPUs. Major
new feature in the i386 CPU was 80386 protected mode - this mode fixed many
shortcomings that existed in the 80286 processor and in the 80286 protected mode:
The 80386 mode included complete set of 32-bit registers and 32-bit instructions.
Although in this mode the CPU still used memory segment architecture similar to the one
present in earlier x86 microprocessors, the size of memory segments was increased to 4
GB. This simplified development of 32-bit software, and in most cases applications could
run without worrying about switching memory segments.
It became possible to switch from protected mode back to real-mode without simulating
processor reset.
Another new mode in the 80386 CPU was 8086 virtual mode. In this mode the CPU
could run old 8086 applications while providing necessary protection of memory and
other resources. Introduction of this mode and 80386 protected mode was very
significant step. All current 32-bit x86-based operating systems use these modes to run
legacy 16-bit and more modern 32-bit applications.
The Intel 80386 was produced at speeds up to 33 MHz, AMD produced even faster 40
MHz version.
There were a few different versions of the 80386 CPUs:
80386DX - this CPU could work with 16-bit and 32-bit external buses.
80386SX - low cost version of the 80386. This processor had 16 bit external
data bus and 24-bit external address bus.
80386SL - low-power microprocessor with power management features, with
16-bit external data bus and 24-bit external address bus. The processor
included ISA bus controller, memory controller and cache controller.
Embedded 80376 and 80386EX processors.
Page 1 of 43
Lecture Five

Figure (1) shows the Pin diagram of 80386. The description follows it.
Page 2 of 43
Lecture Five
Signal Descriptions of 80386

CLK2: Clock time 2;The input pin provides the basic system clock timing for the
operation of 80386.
D0 D31: Data Bus Connections, These 32 lines act as bidirectional data bus
during different access cycles. Transfer data between the microprocessor and its
memory and I/O system.
A31 A2: Address bus connection; these are upper 30 bit of the 32- bit address
bus. Address any of the 1GX32 memory locations found in the 80386 memory
system
BE0 to BE3 : Bank Enable Signals; The 32- bit data bus supported by 80386 and
the memory system of 80386 can be viewed as a 4 byte wide memory access
mechanism. The 4 byte enable lines BE0 to BE3 , may be used for enabling these 4
blanks. Using these 4 enable signal lines, the CPU may transfer 1 byte / 2 / 3 / 4 byte
of data simultaneously.
ADS : Address Data Strobe; The address status output pin indicates that the
address bus and bus cycle definition pins ( W/R , D/C , M/IO , BE0 to BE3 ) are
carrying the respective valid signals. The 80386 does not have any ALE signals and
so this signal may be used for latching the address to external latches.
READY : Ready; The ready signals indicates to the CPU that the previous bus cycle
has been terminated and the bus is ready for the next cycle. The signal is used to
insert WAIT states in a bus cycle and is useful for interfacing of slow devices with
CPU.
VCC: These are system power supply lines.
VSS: These return lines for the power supply.
BS16 : Bus Size 16 input pin allows the interfacing of 16 bit devices with the 32 bit
wide 80386 data bus. Select either a 32-bit data bus ( BS16 =1) or a 16 bit data bus
( BS16 =0)
HOLD: Hold requests a DMA action. The bus hold input pin enables the other bus
masters to gain control of the system bus if it is asserted.
Page 3 of 43
Lecture Five
HLDA: The bus Hold Acknowledge output indicates that a valid bus hold request
has been received and the bus has been relinquished by the CPU.
BUSY : The Busy input signal indicates to the CPU that the coprocessor is busy with
the allocated task.
ERROR : The error input pin indicates to the CPU that the coprocessor has
encountered an error while executing its instruction.
PEREQ: The coprocessor request asks the 80386 to relinquish control and is a
direct connection to the 80387 arithmetic coprocessor.
INTR: This interrupt request pin is a maskable interrupt, that can be masked using
the IF of the flag register.
NMI: A non Maskable Interrupt requests a non-maskable interrupt as it did on the
earlier versions of the microprocessor.
RESET: A high at this input pin suspends the current operation and restart the
execution from the starting location.
N/C: No connection pins are expected to be left open while connecting the 80386 in
the circuit.
M IO
: Memory / IO selects a memory device when a logic 1 or an I/O device
when a logic 0. During the I/O operation, the address bus contains a 16 bit I/O
address on address connections A15-A2.
W R : Write/ Read indicates that the current bus cycle is a write when a logic 1 or a
read when a logic 0.
LOCK : Lock becomes a logic 0 whenever an instruction is prefixed with the LOCK:
prefix. This is used most ofen during DMA accesses.
D C : Data/Control indicates that the data bus contains data for or from memory or
I/O when a logic 1. If D C is a logic 0, the microprocessor is halted or executes an
interrupt acknowledge.
NA : Next Address causes the 80386 to output the address of the next instruction or
data in the current bus cycle. This pin is often used for pipelining the address.
Page 4 of 43
Lecture Five
Figure (2) shows the Pin functions of 80386.
80386
Processor
Fig. 2: Signal Groups of 80386
Page 5 of 43
Lecture Five
Fig. 3: Block diagram of the 80386 microprocessor architecture.
Page 6 of 43
Lecture Five
The Internal Architecture of 80386 is divided into 3 sections.

It has basically six functional units:
1. Bus interface unit,

2. code prefetch unit,
3. instruction decode unit,
4. execution unit,
5. segmentation unit
6. paging unit.
Bus Interface Unit
Interface to the outside world
Responsible for
Fetching instruction
Operation to be executed
Reading and writing of data for memory
Input/output of data for input/output peripherals
Information transfers over the bus
De-multiplexed bus
386DX
32-bit data bus
Real-mode: 20-bit address, 1M-byte physical address space
Protected-mode: 32-bit address bus, 4G-byte physical address
space
Prefetch Unit
Instructions stored in FIFO queue
Holds code until ready for decoding
Whenever the queue is not full, prefetch the next sequential instructions
Time to fetch many of the instructions in a microcomputer program is
hidden.
Page 7 of 43
Lecture Five
Decode Unit
Offloads the responsibility of instruction decoding from the execution unit
Decodes instructions into the microcode instruction format used by the
execution unit
Contains another instruction queue that holds 3 fully decoded instructions
Decoded instructions are held until requested by the execution unit
Execution Unit
Responsible for executing instructions
Element of the EU
Arithmetic/logic unit (ALU)
Performs the operation identified by the instruction: ADD, SUB,
AND, etc.
Flags register
Holds status and control information
General-purpose registers
Holds address or data information
Control ROM
Contains microcode sequences that define operations performed by
machine instructions
Special multiply, shift, and barrel shift hardware
Accelerate multiply, divide, and rotate operations
Operations of the Execution Unit

Reads instructions from the instruction queue
Accesses data
General purpose registers if necessary
Generates memory address of data storage locations in memory if
necessary
Passes memory addresses to the segmentation and paging units and
requests the bus unit to perform read or write bus cycles to access data
operands in memory
Page 8 of 43
Lecture Five
Performs the operation defined by the instruction on the selected data

Tests the state of flags if necessary
Updates flag state based on instruction result
Segmentation and Paging Unit

Off-load memory-management and protection services from the bus unit
Segmentation unit
Implements real-mode and protected-mode segmentation model
Contains general registers, segment registers, and instruction pointer
Holds address and data operand information
Segmentation unit address generation logic
Real-mode address generation
CS:IP code
DS:SI data
Protected-mode address translation
Translates logical address to linear address
Protection checking
Paging unit
Implements protected-mode paging model
Contains translation look-aside buffer
Acts as a cache for recently used page directory entries and page
table entries
Translates linear address output of segmentation unit to a physical page
address
Not used in real mode
The Software Model

Programmers understanding the operation of the microcomputer from a software
point of view
Elements of the software model
Page 9 of 43
Lecture Five
Register set
Memory address space
Input/output address space
Could also consider operations processor can perform
What the programmer must know about the microprocessor
Registers available within the device
Purpose, operating capabilities of each
Size, organization of memory and I/O address spaces
Types of data
80386 Register Set:

General Purpose Data Registers
The 80386 has eight 32 - bit general purpose registers which may be used as
either 8 bit or 16 bit registers.
A 32 - bit register known as an extended register, is represented by the register
name with prefix E.
Example : A 32 bit register corresponding to AX is EAX, similarly BX is EBX etc.
The 16 bit registers BP, SP, SI and DI in 8086 are now available with their
extended size of 32 bit and are names as EBP,ESP,ESI and EDI.
AX represents the lower 16 bit of the 32 bit register EAX.
Page 10 of 43
Lecture Five
Pointers and Index Registers
two index registers (ESI, EDI) and two pointer registers (EBP, ESP);
contains offset addresses (16-bit in real mode: 64 KB)
ESP(extended stack pointer) and EBP(extended base pointer)
combined with the contents of the SS register to produce physical memory

address
TOS (top of stack) : SS:SP
BP : an offset relative to the SS register
ESI (extended source index register) and EDI (extended destination index
register)
automatically combined with the value in the DS register
Instruction Pointer
16-bit IP in real mode
next code address : CS:IP
Page 11 of 43
Lecture Five
FLAGS REGISTER
32-bit flags; just nine of its bits are active in the real mode
1. Statues Flag:
Carry flag(CF): carry-out, borrow-in
Parity flag (PF): set if even parity
Auxiliary carry flag (AF): carry-out from the low nibble
Zero flag(ZF): arithmetic or logic 0
Sign bit (SF): sign
Overflow flag (OF): the signed result is out of range
2. Control Flag:
Direction flag (DF): string operation; when set, the string ops automatically
decrements the address.
TF (Trap Flag): Setting TF puts the processor into single-step mode for
debugging. In
each
this mode, the CPU automatically generates an exception after
instruction, allowing a program to be inspected as it executes each
instruction. Single-stepping is just one of several debugging features of
the
80386.
IF (Interrupt-Enable Flag, bit 9): Setting IF allows the CPU to recognize external
(maskable) interrupt
effect on
requests. Clearing IF disables these interrupts. IF has no
either exceptions or nonmaskable external interrupts.
3. Systems Flags
Page 12 of 43
Lecture Five
NT (Nested Task, bit 14): The processor uses the nested task flag to control
chaining of
interrupted and called tasks. NT influences the operation of the IRET
instruction.
RF (Resume Flag, bit 16): The RF flag is used with the debug register
breakpoints. It is checked at the starting of every instruction cycle and if it is set,
any debug fault is ignored during the instruction cycle. The RF is automatically
reset after successful execution of every instruction, except for IRET and POPF
instructions.
VM (Virtual 8086 Mode, bit 17): If this flag is set, the 80386 enters the virtual
8086 mode within the protection mode. This is to be set only when the 80386 is in
protected mode. In this mode, if any privileged instruction is executed an exception
13 is generated. This bit can be set using IRET instruction or any task switch
operation only in the protected mode.
Systems Registers
The registers designed for use by systems programmers fall into these classes:
Memory-Management Registers
Control Registers
Debug Registers and Test Registers
Memory-Management Registers
Four registers of the 80386 locate the data structures that control segmented
memory management:
GDTR (Global Descriptor Table Register) / LDTR (Local Descriptor Table Register)
These registers point to the segment descriptor tables GDT and LDT.
IDTR (Interrupt Descriptor Table Register)
This register points to a table of entry points for interrupt handlers
TR
(the IDT).
(Task Register)
This register points to the information needed by the processor to define the current
task. Refer to Chapter 7 for a description of the
multitasking features of the 80386.
Page 13 of 43
Lecture Five
Control Registers
The 80386 has three 32 bit control registers CR0, CR2 and CR3 to hold global
machine status independent of the executed task. Load and store instructions are
available to access these registers.
Debug and Test Registers

Intel has provide a set of 8 debug registers for hardware debugging. Out of
these eight registers DR0 to DR7, two registers DR4 and DR5 are Intel
reserved.
The initial four registers DR0 to DR3 store four program controllable breakpoint
addresses, while DR6 and DR7 respectively hold breakpoint status and
breakpoint control information.
Two more test register are provided by 80386 for page caching namely test
control and test status register.
Memory and Input/Output

Architecture implements independent memory and input/output address spaces
Memory address space- 1,048,576 bytes long (1MB)
Input/output address space- 65,536 bytes long (64KB)
Address Space
Memory organized as individual bytes
Memory address space corresponds to the
1M addresses in the range 00000H to
FFFFFH
00000H= 000000000000000000002
FFFFFH= 111111111111111111112
220= 1,048,576 = 1M unique addresses
Data organization:
Byte: content of any individual byte
address
Page 14 of 43
Lecture Five
Word: contents of two contiguous byte addresses

Double-word: contents of 4 contiguous byte addresses
Dedicated and General Use of Memory

Memory address space is partitioned into general use and dedicated use areas
Dedicated (0H 3FFH):
Interrupt vector table
1st 1024 bytes
Addresses 0H 3FFH
256 4-byte pointers
16-bit segment base address
16-bit offset
General use:
400H FFFFFH
Used for stack, code, and data
Addressing Modes of 80386

The 80386 supports overall eleven addressing modes to facilitate efficient
execution of higher level language programs.
In case of all those modes, the 80386 can now have 32-bit immediate or 32- bit
register operands or displacements.
The 80386 has a family of scaled modes. In case of scaled modes, any of the
index register values can be multiplied by a valid scale factor to obtain the
displacement. The valid scale factor are 1, 2, 4 and 8.
The different scaled modes are as follows.
Scaled Indexed Mode: Contents of the index register are multiplied by a
scale factor that may be added further to get the operand offset.
Based Scaled Indexed Mode: Contents of the index register are multiplied
by a scale factor and then added to base register to obtain the offset.
Page 15 of 43
Lecture Five
Based Scaled Indexed Mode with Displacement: The Contents of the an

index register are multiplied by a scaling factor and the result is added to a
base register and a displacement to get the offset of an operand.
Real Address Mode of 80386

After reset, the 80386 starts from memory location FFFFFFF0H under the real
address mode. In the real mode, 80386 works as a fast 8086 with 32-bit registers
and data types.
In real mode, the default operand size is 16 bit but 32- bit operands and
addressing modes may be used with the help of override prefixes.
The segment size in real mode is 64k, hence the 32-bit effective addressing must
be less than 0000FFFFFH. The real mode initializes the 80386 and prepares it for
protected mode.
Memory Addressing in Real Mode

In the real mode, the 80386 can address at the most 1Mbytes of physical memory
using address lines A0-A19.
Paging unit is disabled in real addressing mode, and hence the real addresses are
the same as the physical addresses.
To form a physical memory address, appropriate segment registers contents (16bits) are shifted left by four positions and then added to the 16-bit offset address
formed using one of the addressing modes, in the same way as in the 80386 real
address modes.
The segment in 80386 real mode can be read, write or executed, i.e. no protection
is available.
Any fetch or access past the end of the segment limit generate exception 13 in real
address mode.
The segments in 80386 real mode may be overlapped or non-overlapped.
The interrupt vector table of 80386 has been allocated 1Kbyte space starting from
00000H to 003FFH.
Page 16 of 43
Lecture Five
Fig. (4):
Real-Mode Input/Output Address Space
Separate memory and Input/Output

address spaces
64KB I/O address space
page 0 : 0000H through 00FFH -->

direct I/O
indirect addressing: DX register
Page 17 of 43
Lecture Five
Protected Mode of 80386

All the capabilities of 80386 are available for utilization in its protected mode of
operation.
The 80386 in protected mode support all the software written for 80286 and 8086
to be executed under the control of memory management and protection abilities
of 80386.
The protected mode allows the use of additional instruction, addressing modes
and capabilities of 80386.
Addressing In Protected Mode

In this mode, the contents of segment registers are used as selectors to address
descriptors which contain the segment limit, base address and access rights byte
of the segment.
The effective address (offset) is added with segment base address to calculate
linear address. This linear address is further used as physical address, if the
paging unit is disabled, otherwise the paging unit converts the linear address into
physical address.
The paging unit is a memory management unit enabled only in protected mode.
The paging mechanism allows handling of large segments of memory in terms of
pages of 4Kbyte size.
The paging unit operates under the control of segmentation unit. The paging unit if
enabled converts linear addresses into physical address, in protected mode.
Page 18 of 43
Lecture Five
Fig. 5: Protected Mode Addressing without Paging Unit.
Virtual 8086 Mode

In its protected mode of operation, 80386DX provides a virtual 8086 operating
environment to execute the 8086 programs.
The real mode can also used to execute the 8086 programs along with the
capabilities of 80386, like protection and a few additional instructions.
Once the 80386 enters the protected mode from the real mode, it cannot return
back to the real mode without a reset operation.
Thus, the virtual 8086 mode of operation of 80386, offers an advantage of
executing 8086 programs while in protected mode.
The address forming mechanism in virtual 8086 mode is exactly identical with that
of 8086 real mode.
In virtual mode, 8086 can address 1Mbytes of physical memory that may be
anywhere in the 4Gbytes address space of the protected mode of 80386.
Like 80386 real mode, the addresses in virtual 8086 mode lie within 1Mbytes of
memory.
Page 19 of 43
Lecture Five
In virtual mode, the paging mechanism and protection capabilities are available at
the service of the programmers.
The 80386 supports multiprogramming, hence more than one programmer may be
using the CPU at a time.
Fig. 6: Memory Management in Virtual 8086.

Paging unit may not be necessarily enable in virtual mode, but may be needed
to run the 8086 programs which require more than 1Mbyts of memory for
memory management function.
In virtual mode, the paging unit allows only 256 pages, each of 4Kbytes size.
Each of the pages may be located anywhere in the maximum 4Gbytes physical
memory. The virtual mode allows the multiprogramming of 8086 applications.
The virtual 8086 mode executes all the programs at privilege level 3.Any of the
other programmes may deny access to the virtual mode programs or data.
Page 20 of 43
Lecture Five
However, the real mode programs are executed at the highest privilege level,
i.e. level 0.
The virtual mode may be entered using an IRET instruction at CPL=0 or a task
switch at any CPL, executing any task whose TSS is having a flag image with
VM flag set to 1.
The IRET instruction may be used to set the VM flag and consequently enter
the virtual mode.
The PUSHF and POPF instructions are unable to read or set the VM bit, as
they do not access it.
Even in the virtual mode, all the interrupts and exceptions are handled by the
protected mode interrupt handler.
To return to the protected mode from the virtual mode, any interrupt or
execution may be used.
As a part of interrupt service routine, the VM bit may be reset to zero to pull
back the 80386 into protected mode.
80386 INSTRUCTION SET CLASSIFICATION

The 80386 instruction set can be classified into the following functional headings.
1. Data movement instructions

2. Arithmetic instructions
3. Logical, shift, rotate, and bit instructions
4. I/O instructions
5. String instructions
6. Program flow control instructions
7. Miscellaneous instructions.
Page 21 of 43
Lecture Five
1. Data Movement Instructions:

These instructions provide convenient methods for moving bytes, words, or double
words of data between memory and the registers of the base architecture. They fall into
the following classes:
General-purpose data movement instructions.
Stack manipulation instructions.
Type-conversion instructions.
General-Purpose Data Movement Instructions

MOV (Move) transfers a byte, word, or double word from the source operand to the
destination operand. The MOV instruction is useful for transferring data along any of
these paths. There are also variants of MOV that operate on segment registers. These
are covered in a later section of this chapter:
To a register from memory
To memory from a register
Between general registers
Immediate data to a register
Immediate data to a memory
The MOV instruction cannot move from memory to memory or from segment register to
segment register are not allowed. Memory-to-memory moves can be performed,
however, by the string move instruction MOVS.
XCHG (Exchange) swaps the contents of two operands. This instruction takes the place
of three MOV instructions. It does not require a temporary location to save the contents
of one operand while load the other is being loaded. XCHG is especially useful for
implementing semaphores or similar data structures for process synchronization.
The XCHG instruction can swap two byte operands, two word operands, or two
doubleword operands. The operands for the XCHG instruction may be two register
operands, or a register operand with a memory operand. When used with a memory
operand, XCHG automatically activates the LOCK signal. (Refer to Chapter 11 for more
information on the bus lock.)
Page 22 of 43
Lecture Five
Stack Manipulation Instructions

PUSH (Push) decrements the stack pointer (ESP), then transfers the source operand to
the top of stack indicated by ESP (see Figure 31). PUSH is often used to place
parameters on the stack before calling a procedure; it is also the basic means of storing
temporary variables on the stack. The PUSH instruction operates on memory operands,
immediate operands, and register operands (including segment registers).
PUSHA (Push All Registers) saves the contents of the eight general registers on the
stack (see Figure 3-2). This instruction simplifies procedure calls by reducing the number
of instructions required to retain the contents of the general registers for use in a
procedure. The processor pushes the general registers on the stack in the following
order: EAX, ECX, EDX, EBX, the initial value of ESP before EAX was pushed, EBP, ESI,
and EDI. PUSHA is complemented by the POPA instruction.
POP (Pop) transfers the word or double word at the current top of stack (indicated by
ESP) to the destination operand, and then increments ESP to point to the new top of
stack. See Figure 3-3. POP moves information from the stack to a general register, or to
memory There are also a variant of POP that operates on segment registers. This is
covered in a later section of this chapter..
POPA (Pop All Registers) restores the registers saved on the stack by PUSHA, except
that it ignores the saved value of ESP. See Figure 3-4.
Type Conversion Instructions

The type conversion instructions convert bytes into words, words into double
words, and double words into 64-bit items (quad-words). These instructions are
especially useful for converting signed integers, because they automatically fill the extra
bits of the larger item with the value of the sign bit of the smaller item. This kind of
conversion, illustrated by Figure 3-5, is called sign extension.
There are two classes of type conversion instructions:
1. The forms CWD, CDQ, CBW, and CWDE which operate only on data in the
EAX
register.
2. The forms MOVSX and MOVZX, which permit one operand to be in any general
register while permitting the other operand to be in memory or in a register.
Page 23 of 43
Lecture Five
CWD (Convert Word to Double word) and CDQ (Convert Double word to Quad-Word)
double the size of the source operand. CWD extends the sign of the word in register AX
throughout register DX. CDQ extends the sign of the double word in EAX throughout
EDX. CWD can be used to produce a double word dividend from a word before a word
division, and CDQ can be used to produce a quad-word dividend from a double word
before double word division.
CBW (Convert Byte to Word) extends the sign of the byte in register AL throughout AX.
CWDE (Convert Word to Double word Extended) extends the sign of the word in
register AX throughout EAX.
MOVSX (Move with Sign Extension) sign-extends an 8-bit value to a 16-bit value and a
8- or 16-bit value to 32-bit value.
MOVZX (Move with Zero Extension) extends an 8-bit value to a 16-bit value and an 8or 16-bit value to 32-bit value by inserting high-order zeros.
2. Binary Arithmetic Instructions

The arithmetic instructions of the 80386 processor simplify the manipulation of
numeric data that is encoded in binary. Operations include the standard add, subtract,
multiply, and divide as well as increment, decrement, compare, and change sign. Both
signed and unsigned binary integers are supported. The binary arithmetic instructions
may also be used as one step in the process of performing arithmetic on decimal
integers.
Many of the arithmetic instructions operate on both signed and unsigned integers. These
instructions update the flags ZF, CF, SF, and OF in such a manner that subsequent
instructions can interpret the results of the arithmetic as either signed or unsigned. CF
contains information relevant to unsigned integers; SF and OF contain information
relevant to signed integers. ZF is relevant to both signed and unsigned integers; ZF is set
when all bits of the result are zero.
If the integer is unsigned, CF may be tested after one of these arithmetic operations to
determine whether the operation required a carry or borrow of a one-bit in the high-order
position of the destination operand. CF is set if a one-bit was carried out of the high-order
position (addition instructions ADD, ADC, AAA, and DAA) or if a one-bit was carried (i.e.
Page 24 of 43
Lecture Five
borrowed) into the high-order bit (subtraction instructions SUB, SBB, AAS, DAS, CMP,
and NEG).
If the integer is signed, both SF and OF should be tested. SF always has the same value
as the sign bit of the result. The most significant bit (MSB) of a signed integer is the bit
next to the sign--bit 6 of a byte, bit 14 of a word, or bit 30 of a doubleword. OF is set in
either of these cases:
A one-bit was carried out of the MSB into the sign bit but no one bit
was carried out
of the sign bit (addition instructions ADD, ADC, INC, AAA, and DAA). In other words, the
result was greater than the greatest positive number that could be contained in the
destination operand.
A one-bit was carried from the sign bit into the MSB but no one bit was carried into
the sign bit (subtraction instructions SUB, SBB, DEC, AAS, DAS, CMP, and NEG). In
other words, the result was smaller that the smallest negative number that could be
contained in the destination operand.
These status flags are tested by executing one of the two families of conditional
instructions: Jcc (jump on condition cc) or SETcc (byte set on condition).
Addition and Subtraction Instructions

ADD (Add Integers) replaces the destination operand with the sum of the source and
destination operands. Sets CF if overflow.
ADC (Add Integers with Carry) sums the operands, adds one if CF is set, and replaces
the destination operand with the result. If CF is cleared, ADC performs the same
operation as the ADD instruction. An ADD followed by multiple ADC instructions can be
used to add numbers longer than 32 bits.
INC (Increment) adds one to the destination operand. INC does not affect CF. Use ADD
with an immediate value of 1 if an increment that updates carry (CF) is needed.
SUB (Subtract Integers) subtracts the source operand from the destination operand
and replaces the destination operand with the result. If a borrow is required, the CF is
set. The operands may be signed or unsigned bytes, words, or double words.
SBB (Subtract Integers with Borrow) subtracts the source operand from the
destination operand, subtracts 1 if CF is set, and returns the result to the destination
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Lecture Five
operand. If CF is cleared, SBB performs the same operation as SUB. SUB followed by
multiple SBB instructions may be used to subtract numbers longer than 32 bits. If CF is
cleared, SBB performs the same operation as SUB.
DEC (Decrement) subtracts 1 from the destination operand. DEC does not update CF.
Use SUB with an immediate value of 1 to perform a decrement that affects carry.
Comparison and Sign Change Instruction

CMP (Compare) subtracts the source operand from the destination operand. It updates
OF, SF, ZF, AF, PF, and CF but does not alter the source and destination operands. A
subsequent Jcc or SETcc instruction can test the appropriate flags.
NEG (Negate) subtracts a signed integer operand from zero. The effect of NEG is to
reverse the sign of the operand from positive to negative or from negative to positive.
Multiplication Instructions
The 80386 has separate multiply instructions for unsigned and signed operands. MUL
operates on unsigned numbers, while IMUL operates on signed integers as well as
unsigned.
MUL (Unsigned Integer Multiply) performs an unsigned multiplication of the source
operand and the accumulator. If the source is a byte, the processor multiplies it by the
contents of AL and returns the double-length result to AH and AL. If the source operand
is a word, the processor multiplies it by the contents of AX and returns the double-length
result to DX and AX. If the source operand is a double word, the processor multiplies it
by the contents of EAX and returns the 64-bit result in EDX and EAX. MUL sets CF and
OF when the upper half of the result is nonzero; otherwise, they are cleared.
IMUL (Signed Integer Multiply) performs a signed multiplication operation. IMUL has
three variations:
1. A one-operand form. The operand may be a byte, word, or double word located in
memory or in a general register. This instruction uses EAX and EDX as implicit
operands in the same way as the MUL instruction.
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Lecture Five
2. A two-operand form. One of the source operands may be in any general

while the other may be either in memory or in a general
register
register. The product
replaces the general-register operand.
3. A three-operand form; two are source and one is the destination operand. One of
the source operands is an immediate value stored in the instruction; the second
may be in memory or in any general register. The product may be stored in any
general register. The immediate operand is treated as signed. If the immediate
operand is a byte, the processor automatically sign-extends it to the size of the
second operand before performing the multiplication.
The three forms are similar in most respects:
The length of the product is calculated to twice the length of the operands.
The CF and OF flags are set when significant bits are carried into the
high-order
half of the result. CF and OF are cleared when the high-order half of the result is the
sign-extension of the low-order half.
However, forms 2 and 3 differ in that the product is truncated to the length of the
operands before it is stored in the destination register. Because of this truncation, OF
should be tested to ensure that no significant bits are lost. (For ways to test OF, refer to
the INTO and PUSHF instructions)
Forms 2 and 3 of IMUL may also be used with unsigned operands because, whether the
operands are signed or unsigned, the low-order half of the product is the same.
Division Instructions
The 80386 has separate division instructions for unsigned and signed operands.
DIV operates on unsigned numbers, while IDIV operates on signed integers as well as
unsigned. In either case, an exception (interrupt zero) occurs if the divisor is zero or if the
quotient is too large for AL, AX, or EAX.
DIV (Unsigned Integer Divide) performs an unsigned division of the accumulator by the
source operand. The dividend (the accumulator) is twice the size of the divisor (the
source operand); the quotient and remainder have the same size as the divisor, as the
following table shows.
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Lecture Five
Size of Source Operand

(divisor)
Dividend
Quotient
Remainder
Byte
AX
AL
AH
Word
DX:AX
AX
DX
Double word
EDX:EAX
EAX
EDX
Non-integral quotients are truncated to integers toward 0. The remainder is always

less than the divisor. For unsigned byte division, the largest quotient is 255. For unsigned
word division, the largest quotient is 65,535. For unsigned doubleword division the
largest quotient is 2
IDIV (Signed Integer Divide) performs a signed division of the accumulator by the
source operand. IDIV uses the same registers as the DIV instruction.
For signed byte division, the maximum positive quotient is +127, and the minimum
negative quotient is -128. For signed word division, the maximum positive quotient is
+32,767, and the minimum negative quotient is -32,768. For signed doubleword division
the maximum positive quotient is 231-1, the minimum negative quotient is -231
. Non-integral results are truncated towards 0. The remainder always has the same sign
as the dividend and is less than the divisor in magnitude.
Decimal Arithmetic Instructions

Decimal arithmetic is performed by combining the binary arithmetic instructions (already
discussed in the prior section) with the decimal arithmetic instructions. The decimal
arithmetic instructions are used in one of the following ways:
To adjust the results of a previous binary arithmetic operation to
produce a valid
packed or unpacked decimal result.

To adjust the inputs to a subsequent binary arithmetic operation so
operation will produce a valid packed or unpacked decimal
that the
result.
These instructions operate only on the AL or AH registers. Most utilize the AF flag.
Packed BCD Adjustment Instructions

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Lecture Five
DAA (Decimal Adjust after Addition) adjusts the result of adding two valid packed
decimal operands in AL. DAA must always follow the addition of two pairs of packed
decimal numbers (one digit in each half-byte) to obtain a pair of valid packed decimal
digits as results. The carry flag is set if carry was needed.
DAS (Decimal Adjust after Subtraction) adjusts the result of subtracting two valid packed
decimal operands in AL. DAS must always follow the subtraction of one pair of packed
decimal numbers (one digit in each halfbyte) from another to obtain a pair of valid packed
decimal digits as results. The carry flag is set if a borrow was needed.
Unpacked BCD Adjustment Instructions

AAA (ASCII Adjust after Addition) changes the contents of register AL to a valid
unpacked decimal number, and zeros the top 4 bits. AAA must always follow the addition
of two unpacked decimal operands in AL. The carry flag is set and AH is incremented if a
carry is necessary.
AAS (ASCII Adjust after Subtraction) changes the contents of register AL to a valid
unpacked decimal number, and zeros the top 4 bits. AAS must always follow the
subtraction of one unpacked decimal operand from another in AL. The carry flag is set
and AH decremented if a borrow is necessary.
AAM (ASCII Adjust after Multiplication) corrects the result of a multiplication of two
valid unpacked decimal numbers. AAM must always follow the multiplication of two
decimal numbers to produce a valid decimal result. The high order digit is left in AH, the
low order digit in AL.
AAD (ASCII Adjust before Division) modifies the numerator in AH and AL to prepare
for the division of two valid unpacked decimal operands so that the quotient produced by
the division will be a valid unpacked decimal number. AH should contain the high-order
digit and AL the low-order digit. This instruction adjusts the value and places the result in
AL. AH will contain zero.
3. Logical Instructions
The group of logical instructions includes:
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Lecture Five
The Boolean operation instructions: they are AND, OR, XOR, and NOT.
Bit test and modify instructions
Bit scan instructions
Rotate and shift instructions
Byte set on condition
Bit Test and Modify Instructions
This group of instructions operates on a single bit which can be in memory or in a
general register. The location of the bit is specified as an offset from the low-order end of
the operand. The value of the offset either may be given by an immediate byte in the
instruction or may be contained in a general register.
These instructions first assign the value of the selected bit to CF, the carry flag. Then a
new value is assigned to the selected bit, as determined by the operation. OF, SF, ZF,
AF, PF are left in an undefined state. Table 1 defines these instructions.
Table 1. Bit Test and Modify Instructions

Instruction
Effect on CF
Effect on Selected Bit
Bit (Bit Test)
CF BIT
(none)
BTS(Bit Test and Set)
CF BIT
BTR (Bit Test and Reset)
CF BIT
BIT 0
BTC (Bit Test and Complement)
CF BIT
BIT NOT(BIT)
BIT 1
Bit Scan Instructions

These instructions scan a word or doubleword for a one-bit and store the index of
the first set bit into a register. The bit string being scanned may be either in a register or
in memory. The ZF flag is set if the entire word is zero (no set bits are found); ZF is
cleared if a one-bit is found. If no set bit is found, the value of the destination register is
undefined.
BSF (Bit Scan Forward) scans from low-order to high-order (starting from bit index
zero).
Page 30 of 43
Lecture Five
BSR (Bit Scan Reverse) scans from high-order to low-order (starting from bit index 15
of a word or index 31 of a doubleword).
Shift and Rotate Instructions

The shift and rotate instructions reposition the bits within the specified operand.
These instructions fall into the following classes:
Shift instructions
Rotate instructions
Double shift instructions
Shift Instructions
The bits in bytes, words, and doublewords may be shifted arithmetically or logically.
Depending on the value of a specified count, bits can be shifted up to 31 places.
A shift instruction can specify the count in one of three ways. One form of shift
instruction implicitly specifies the count as a single shift. The second form specifies
the count as an immediate value. The third form specifies the count as the value
contained in CL. This last form allows the shift count to be a variable that the program
supplies during execution. Only the low order 5 bits of CL are used.
SAL (Shift Arithmetic Left)/ SHL (Shift Logical Left): The SHL and SAL mnemonics
are synonyms. They represent the same instruction and use identical binary encodings.
These instructions move each bit in the destination operand one bit position to the left
the number of times specied by the count operand. Zeros ll vacated positions at the
L.O. bit; the H.O. bit shifts into the carry ag
SHR (Shift Logical Right) shifts the destination byte, word, or doubleword operand right
by one or by the number of bits specified in the count operand (an immediate value or
Page 31 of 43
Lecture Five
the value contained in CL). The processor shifts zeros in from the left side of the operand
as bits exit from the right side.
SAR (Shift Arithmetic Right) shifts the destination byte, word, or doubleword operand
to the right by one or by the number of bits specified in the count operand (an immediate
value or the value contained in CL). The processor preserves the sign of the operand by
shifting in zeros on the left (high-order) side if the value is positive or by shifting by ones
if the value is negative.
SHLD (Shift Left Double) shifts bits of the R/M field to the left, while shifting high-order
bits from the Reg field into the R/M field on the right (see Figure 3-10). The result is
stored back into the R/M operand. The Reg field is not modified.
SHRD (Shift Right Double) shifts bits of the R/M field to the right, while shifting loworder bits from the Reg field into the R/M field on the left (see Figure 3-11). The result is
stored back into the R/M operand. The Reg field is not modified.
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Lecture Five
Example:
Rotate Instructions
Rotate instructions allow bits in bytes, words, and doublewords to be rotated. Bits
rotated out of an operand are not lost as in a shift, but are "circled" back into the other
"end" of the operand.
ROL (Rotate Left) rotates the byte, word, or doubleword destination operand left by one
or by the number of bits specified in the count operand (an immediate value or the value
contained in CL).
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Lecture Five
ROR (Rotate Right) rotates the byte, word, or doubleword destination operand right by
one or by the number of bits specified in the count operand (an immediate value or the
value contained in CL).
RCL (Rotate Through Carry Left) rotates bits in the byte, word, or doubleword
destination operand left by one or by the number of bits specified in the count operand
(an immediate value or the value contained in CL).
RCR (Rotate Through Carry Right) rotates bits in the byte, word, or doubleword
destination operand right by one or by the number of bits specified in the count operand
(an immediate value or the value contained in CL).
Byte-Set-On-Condition Instructions
The set on condition (or setcc) instructions set a single byte operand (register or
memory location) to zero or one depending on the values in theags register. The
general formats for the setcc instructions are
Page 34 of 43
Lecture Five
SETcc reg8
SETcc mem8
SETcc represents a mnemonic appearing in the following tables. These instructions store
a zero into the corresponding operand if the condition is false, they store a one into the
eight bit operand if the condition is true.
Table 2: SETcc Instructions That Test Flags
The CMP instruction works synergistically with the SETcc instructions. Immediately
after a CMP operation the processor ags provide information concerning the relative
values of those operands. They allow you to see if one operand is less than, equal to,
greater than, or any combination of these.
There are two groups of SETcc instructions that are very useful after a CMP operation.
The rst group deals with the result of an unsigned comparison, the second group deals
with the result of a signed comparison.
Table 3: SETcc Instructions for Unsigned Comparisons
Page 35 of 43
Lecture Five
Table 4: SETcc Instructions for Signed Comparisons
Page 36 of 43
Lecture Five
4. Input/Output Instructions
The 80x86 supports two I/O instructions: in and out.They take the forms:
IN eax/ax/al, port
IN eax/ax/al, dx
OUT port, eax/ax/al
OUT dx, eax/ax/al
port is a value between 0 and 255. The 80x86 supports up to 65,536 different I/O
ports (requiring a 16 bit I/O address).
The port value above, however, is a single byte value. Therefore, you can only
directly address the rst 256 I/O ports in the 80x86s I/O address space. To address
all 65,536 different I/O ports, you must load the address of the desired port (assuming
its above 255) into the dx register and access the port indirectly.
The in instruction reads the data at the specied I/O port and copies it into the
accumulator. The out instruction writes the value in the accumulator to the speci
ed
I/O port.
5. String Instructions
The 80386 supports twelve string instructions:
MOVS (move string)
LODS (load string element into the accumulator)
STOS (store accumulator into string element)
SCAS (Scan string and check for match against the value in the accumulator)
CMPS (compare two strings)
INS (input a string from an I/O port)
OUTS (output a string to an I/O port
REP (repeat a string operation)
REPZ (repeat while zero)
REPE (repeat while equal)
REPNZ (repeat while not zero)
REPNE (repeat while not equal)
Page 37 of 43
Lecture Five
You can use the MOVS, STOS, SCAS, CMPS, INS and OUTS instructions to manipulate
a single element (byte, word, or double word) in a string, or to process an entire string.
Generally, you would only use the LODS instruction to manipulate a single item at a time.
These instructions can operate on strings of bytes, words, or double words. To specify
the object size, simply append a b, w, or d to the end of the instructions mnemonic, i.e.,
LODSB, MOVSW, CMPSD, etc. Of course, the double word forms are only available on
80386 and later processors
6. Control Transfer Instructions

The 80386 provides both conditional and unconditional control transfer
instructions to direct the flow of execution. Conditional control transfers depend on the
results of operations that affect the flag register. Unconditional control transfers are
always executed.
Unconditional Transfer Instructions

JMP, CALL, RET, INT and IRET instructions transfer control from one code
segment location to another. These locations can be within the same code segment
(near control transfers) or in different code segments (far control transfers). The variants
of these instructions that transfer control to other segments are discussed in a later
section of this chapter. If the model of memory organization used in a particular 80386
application does not make segments visible to applications programmers, intersegment
control transfers will not be used.
Jump Instruction
JMP (Jump) unconditionally transfers control to the target location. JMP is a oneway transfer of execution; it does not save a return address on the stack.
The JMP instruction always performs the same basic function of transferring control from
the current location to a new location. Its implementation varies depending on whether
the address is specified directly within the instruction or indirectly through a register or
memory.
Page 38 of 43
Lecture Five
A direct JMP instruction includes the destination address as part of the instruction. An
indirect JMP instruction obtains the destination address indirectly through a register or a
pointer variable.
Direct near JMP. A direct JMP uses a relative displacement value contained in the
instruction. The displacement is signed and the size of the displacement may be a byte,
word, or doubleword. The processor forms an effective address by adding this relative
displacement to the address contained in EIP. When the additions have been performed,
EIP refers to the next instruction to be executed.
Indirect near JMP. Indirect JMP instructions specify an absolute address in one of
several ways:
1. The program can JMP to a location specified by a general register
(any of EAX,
EDX, ECX, EBX, EBP, ESI, or EDI). The processor moves this 32-bit value into EIP and
resumes execution.
2. The processor can obtain the destination address from a memory operand specified
in the instruction.
3. A register can modify the address of the memory pointer to select a destination
address.
Call Instruction
CALL (Call Procedure) activates an out-of-line procedure, saving on the stack the
address of the instruction following the CALL for later use by a RET (Return) instruction.
CALL places the current value of EIP on the stack. The RET instruction in the called
procedure uses this address to transfer control back to the calling program.
CALL instructions, like JMP instructions have relative, direct, and indirect versions.
Indirect CALL instructions specify an absolute address in one of these ways:
1. The program can CALL a location specified by a general register (any of EAX, EDX,
ECX, EBX, EBP, ESI, or EDI). The processor moves this
32-bit value into EIP.
2. The processor can obtain the destination address from a memory operand specified
in the instruction.
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Lecture Five
Return and Return-From-Interrupt Instruction

RET (Return From Procedure) terminates the execution of a procedure and transfers
control through a back-link on the stack to the program that originally invoked the
procedure. RET restores the value of EIP that was saved on the stack by the previous
CALL instruction.
RET instructions may optionally specify an immediate operand. By adding this constant
to the new top-of-stack pointer, RET effectively removes any arguments that the calling
program pushed on the stack before the execution of the CALL instruction.
IRET (Return From Interrupt) returns control to an interrupted procedure. IRET differs
from RET in that it also pops the flags from the stack into the flags register. The flags are
stored on the stack by the interrupt mechanism.
Conditional Transfer Instructions

The conditional transfer instructions are jumps that may or may not transfer
control, depending on the state of the CPU flags when the instruction executes.
Conditional Jump Instructions

Although the JMP, CALL, and RET instructions provide transfer of control, they do not
allow you to make any serious decisions. The 80x86s conditional jump instructions
handle this task. The conditional jump instructions are the basic tool for creating loops
and other conditionally executable statements like the if..then statement.
The conditional jumps test one or more ags in the ags register to see if they match
some particular pattern (just like the SETcc instructions). If the pattern matches,
control transfers to the target location. If the match fails, the CPU ignores the
conditional jump and execution continues with the next instruction. Some instructions,
for example, test the conditions of the sign, carry, overow, and zero ags.
Note: Intels documentation denes various synonyms or instruction aliases for many
conditional jump instructions. The following tables list all the aliases for a particular
instruction. These tables also list out the opposite branches. Youll soon see the
purpose of the opposite branches.
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Lecture Five
Table 5: Jcc Instructions That Test Flags
Table 6: Jcc Instructions for Unsigned Comparisons
Page 41 of 43
Lecture Five
Table 7: Jcc Instructions for Signed Comparisons
Loop Instructions
The loop instructions are conditional jumps that use a value placed in ECX to
specify the number of repetitions of a software loop. All loop instructions automatically
decrement ECX and terminate the loop when ECX=0. Four of the five loop instructions
specify a condition involving ZF that terminates the loop before ECX reaches zero.
LOOP (Loop While ECX Not Zero) is a conditional transfer that automatically
decrements the ECX register before testing ECX for the branch condition. If ECX is nonzero, the program branches to the target label specified in the instruction. The LOOP
instruction causes the repetition of a code section
until the operation of the LOOP instruction decrements ECX to a value of zero. If LOOP
finds ECX=0, control transfers to the instruction immediately following the LOOP
instruction. If the value of ECX is initially zero, then the LOOP executes 232 times.
LOOPE (Loop While Equal) and LOOPZ (Loop While Zero) are synonyms for the same
instruction. These instructions automatically decrement the ECX register before testing
ECX and ZF for the branch conditions. If ECX is non-zero and ZF=1, the program
branches to the target label specified in the instruction. If LOOPE or LOOPZ finds that
Page 42 of 43
Lecture Five
ECX=0 or ZF=0, control transfers to the instruction immediately following the LOOPE or
LOOPZ instruction.
LOOPNE (Loop While Not Equal) and LOOPNZ (Loop While Not Zero) are synonyms
for the same instruction. These instructions automatically decrement the ECX register
before testing ECX and ZF for the branch conditions. If ECX is non-zero and ZF=0, the
program branches to the target label specified in the instruction. If LOOPNE or LOOPNZ
finds that ECX=0 or ZF=1, control transfers to the instruction immediately following the
LOOPNE or LOOPNZ instruction.
7. Miscellaneous Instructions
There are various miscellaneous instructions on the 80x86 that dont fall into any
category above. Generally these are instructions that manipulate individual ags, provide
special processor services, or handle privileged mode operations.
There are several instructions that directly manipulateags in the 80x86 ags register.
They are
clc Clears the carry ag
stc Sets the carry ag
cmc Complements the carry ag
cld Clears the direction ag
std Sets the direction ag
cli Clears the interrupt enable/disable ag
sti Sets the interrupt enable/disable ag
Note: you should be careful when using the cli instruction in your programs. Improper
use could lock up your machine until you cycle the power.
The nop instruction doesnt do anything except waste a few processor cycles and take
up a byte of memory. Programmers often use it as a place holder or a debugging aid. As
it turns out, this isnt a unique instruction, its just a synonym for the
instruction.
Page 43 of 43
xchg ax, ax

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Lecture One

Introduction to Computer &

INTRODUCTION TO COMPUTER & MICROCOMPUTERS

The UNIVAC and ENIAC computers are examples of first-generation computing

improved the efficiency of computers. Computers had by now pervaded most

4. Fourth Generation (1971-Present) Microprocessors

Technology & Architecture

Vacuum tubes, Relay memories,

Machine & Assembly

Discrete Transistors, Core Memories,

HLL used with

Multiprogramming, Time IBM 360/700

LSI/VLSI and Semiconductor

artificial intelligence and still in

VAX 9800, Cray XMP, IBM 3600,

super large, large,

medium, small, and tiny.

Mainframe computers - large

they used to be called

minicomputers. Mainframes are used by large organizations such as

many capabilities comparable to

are those in which the case or main housing sits on a desk,

with keyboard in front and monitor (screen) often on top.

are those Microcomputer in which the case sits as a "tower,"

Fig. (1): Basic Block of a Microcomputer

Input Units -- "How to tell it what to do"

Output Units -- "How it shows you what it is doing"

when it is not being used to put data on the bus.

OE : Output Enable connect to RD of uP

CE , CS : Chip Enable to Address decoder

RAM (Random Access Memory)

RD : Read signal connect to MemRD of uP

WR : Write signal connect to MemWR of uP

Central Processing Unit

system interconnects such as computer buses and switches

memory controllers and hierarchies

Fig. (2): The Von-Neumann Architecture

advantage is the increased bandwidth available due to having separate communication

Fig. (3): The Harvard architecture

A pure Harvard architecture computer suffers from the disadvantage that

The solution is to provide a hardware pathway and machine language instructions

Note that this type of Harvard

architecture is still a von Neumann machine.

Fig. (4): A modified Harvard Architecture

Hardware, Software, and Firmware

Fig.(5): Analog Digital Interface

Fig.(6): Synchronized/Asynchronized Interface

Serial/Parallel Interface To interface two peripherals one of them is parallel

Fig.(7): Parallel Serial Interface

Microprocessor based Interface

3. Interrupts (Hard interrupts)

Fig. 8: Direct/Indirect Bus Interface

A bus is capable of being (parallel or a serial bus), (Synchronized or A

BIOS supporting Plug and Play.

Up to 133 MHz bus speed

Define the following abbreviations CPU, RAM and ROM.

Classify the system peripheral interface according to three different approaches.

Define the following abbreviations ADC, DAC and I/O.

Mention several techniques of microprocessor interface.

What are the required conditions for applying PnP technique?

Define the following abbreviations ISA, PnP, PCI, USB, AGP

10) Write some brief notes about the USB bus

Evaluation of the Microprocessors