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ASIC Design (604202)

Miscellaneous Notes

Signal Integrity Effects:

The term Signal Integrity (SI) addresses two concerns in the electrical design aspects the timing and the quality
of the signal. Does the signal reach its destination when it is supposed to? And also, when it gets there, is it in
good condition.
Today, with the vast improvement of the chip fabrication technology, the silicon size is shrinking dramatically and
the transistor channel length is greatly reduced into sub-micron range. This trend leads to todays logic families
operating at much higher speed. Their rise and fall time are on the order of hundreds of picosecond.
As we move into deep-sub-micron regime, it will not be a surprise to see signals with even faster switching
characteristics. Since many SI problems are directly related to dV/dt or dI/dt, faster rise time significantly worsens
some of the noise phenomena such as ringing, crosstalk, and power/ground switching noise.
There are three mostly concerned noise problems:

Reflection: In chip packages, a trace with its reference plane constitutes a type of transmission line. Similarly, A
pair of parallel conducting paths separated by a uniform distance also form transmission lines. These transmission
lines serve the purpose of sending signals from one point to other.
In high-speed system, reflection noise increases time delay and produces overshoot, undershoot and ringing. The
root cause of reflection noise is the impedance discontinuity along the signal transmission path. When a signal
changes its routing layer and the impedance values are not consistent (manufacturing variations, design
considerations, etc.), reflection will occur at the discontinuity boundary. To minimize reflection noise, common
practices include controlling trace characteristic impedance (through trace geometry).

Crosstalk: Crosstalk is caused by EM coupling between multiple transmission lines running parallel.
It can cause noise pick up on the adjacent quiet signal lines that may lead to false logic switching. Crosstalk will
also impact the timing on the active lines if multiple lines are switching simultaneously. Depending on the
switching direction on each line (even mode switching, that is, all lines going either from low-to-high, or from
high-to-low, usually yields most delay), the extra delay introduced may significantly increase/decrease the
sampling window. The amount of crosstalk is related to the signal rise time, to the spacing between the lines, and
to how long these multiple lines run parallel to each other. To control the crosstalk, one can make the lines space
apart, add ground guarding band in between the signal lines, keep the parallelism to minimum, and keep the
traces close to the reference metal planes.

Power/Ground Noise: As digital circuitry speed increases, output-switching times decrease. Faster switching
times cause higher transient currents within the outputs as the load capacitors discharge. If a number of outputs
switch simultaneously from logic high to logic low, it causes the charge stored in the I/O load capacitances to flow
into the device. This sudden flow of current exits the device through internal inductances onto the board ground,
which develops a voltage. This voltage results in a voltage difference between the device and the board ground,
momentarily developing a low voltage signal on the I/O above the ground level. This low voltage signal is known
as ground bounce. The bounce effect can cause an output low to be seen as a high by other devices on the board.

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ASIC Design (604202)

Miscellaneous Notes

Practical Aspects of Mix Analog Digital Design

1. Long Design Cycles: Today, mixed-signal IC-design requires a long development cycle, complicated by the risk that
the design may not work the first time. An efficient design strongly relies on the availability of appropriate
powerful design tools to get insight into the circuit behavior but also into performance and yield degrading effects
such as temperature feedback, influence of fabrication tolerances, supply voltage variations etc.
For digital circuits, design tools are available with remarkable sophistication.
Tools for analog design are at a lower level, despite intensive activity by many researchers, users and vendors.
One reason for that is the difficulty of describing the process of analog design. The designer must take into
account numerous specifications, provide a good guess of quantities not specified, and choose from a large
variety of circuit topologies or, often, invent new ones. In addition, even if the topology is fixed, a complete
closed-form mathematical solution giving important quantities in terms of design variables almost never exists.
The variables involved are too many, and their possible range too wide, to allow for efficient optimization
procedures.
2. Difficulty in System Partitioning: Available technologies allow to integrate complete mixed analog digital systems
on a chip but the partitioning between analog and digital realization, circuit concepts and the design techniques
strongly depend on the underlying technology and system requirements.

3. Lack of Analog Synthesis Tools: Synthesis of analog circuits is mainly restricted to fundamental blocks such as
operational amplifiers, comparators and switched capacitor filters.
As in SC-techniques it is relatively easy to put together predefined blocks, synthesis is most successful for these
circuits. Synthesis of more complex blocks like A/D,D/A converters concentrates mostly on sigma delta
modulators.
The analog synthesis tools available today can be categorized into tools using fixed topologies and systems which
are open in the sense that everyone has to bring in his own synthesis rules. The first concept has the main
drawback that it is limited to a fixed set of topologies. On the other hand, it is very time consuming to develop
synthesis rules for the 2nd concept.
4. Difficulty in Testing: A further important point for a successful design of mixed analog-digital ICs is testability.
While digital test is difficult, analog test remains an art. Synthesis for test is key in that the designer will know that
the finished circuit is testable. Test structures and test loops have to be included for characterization and to make
sure that the testing time for the volume test is minimized by a maximum of fault coverage. Therefore, analog
fault modelling is a field of growing importance

5. Requirement of Isolation: Proper isolation of the analog circuits from the noisy digital circuits is a challenge in
mixed analog-digital ICs. Due to parasitic resistances and inductances associated with the power supply lines,
bonding wires and substrate, power supply noise voltage is created by the current spikes from the digital part. A
fraction of the noise inevitably propagates through the substrate to sensitive analog nodes it limits the achievable
accuracy.

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ASIC Design (604202)

Miscellaneous Notes

Pre-layout V/S Post Layout Simulation:

Simulations in ASIC design are used to check signal integrity, power integrity, electromagnetic compatibility, analog,
or even thermal simulations, they reveal information about design feasibility, margins, and limitations.
1. The main difference between pre-layout and post-layout is that pre-layout simulations take place before
completing the layout, while post-layout simulations use the completed layout as their basis. With signal-integrity
simulations, for example, that means exact lengths of interconnects can be used in the post-layout analysis.
2. In pre-layout and post-layout, we translate physical parameters into circuit elements and other mathematical
models for simulation. However, for pre-layout simulation, we must build up a circuit schematic to include all
elements of the simulation. For signal-integrity purposes, this includes IC buffer models, package models etc In terms
of power integrity, this includes capacitors, power sources, loads etc
Post-layout simulation involves extraction of physical information from the completed layout.

Pre-layout Simulation:
3. The main purpose of pre-layout simulation is to develop design constraints, while post-layout simulations main
goal is to verify compliance with those constraints.
Take, for example, a length constraint. Many different electrical constraints can drive the length constraints
perhaps meeting some timing requirement or the need to control the amount of loss for a signal. The effect of each
constraint on length can be studied in pre-layout simulation.
4. Pre-layout simulation also serves to prove out board-level design concepts. Suppose that a certain hardware
design calls for long-distance routing of a bus through several boards using several connectors. A pre-layout
simulation shows if such a configuration allows for a signal at the receiver that meets the design specifications. Also,
with pre-layout simulation, the engineer can understand the limitations of the buses in the design and create a plan
to successfully implement those buses.

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ASIC Design (604202)

Miscellaneous Notes

Post-Layout Confirmation:
5. Post-layout simulation, on the other hand, is mainly used to verify the completed design. It verifies all design
constraints after their creation. Post-layout simulation also comes in handy when comparing simulation versus
measurements. This is important to ensure that the constraints created by pre-layout simulation are based on sound
modeling of the PCB.
6. Troubleshooting is another useful application of post-layout simulation. When identifying a problem with a
prototype in the lab, post-layout simulation serves to investigate possible causes of the issue. Once identified,
exploratory simulation (usually performed in the same what-if environment as pre-layout simulation) can be used to
find a solution.

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ASIC Design (604202)

Miscellaneous Notes

Issues in ASIC Verification

Verification occurs at various stages in the ASIC development cycle. How much is enough at each stage is a problem
that needs to be addressed on a case to case basis. A sound knowledge of various techniques and awareness of
capabilities and limitations of each technique goes a long way in making decisions about when, where and what.
We shall discuss in detail the strengths and limitations of the various techniques, viz: ESL, Formal verification,
Dynamic simulation, FPGA prototyping and Emulation.
ESL or Electronic System Level testing is the newest trend. Supporters of ESL claim that it is a highly powerful system
level modeling tool. It enables fast software bring-up if combined with an emulation/FPGA prototyping platform. ESL
has been used successfully to validate systems for mobile applications where only one peripheral/application is
active on the processor bus. ESL does not seem suitable for systems where multiple processes and interfaces are
active simultaneously, like for example in a networking system.
Formal verification, a static verification technique which is mainly assertion based, is useful to check control paths. It
cannot be used to verify datapaths.
Dynamic simulation is a very effective way of verifying functionality of every block in the ASIC including the datapath.
Gate level simulations performed after the back annotated placement and routing data is available are used to
identify timing related issues or omissions/errors in stating multi-cycle paths.
The need to find hardware bugs as early as possible in the ASIC lifecycle drives the emulation and/or FPGA
prototyping effort. Both these techniques enable the testing of scenarios which are generally not possible to test in
dynamic functional verification, well before the actual silicon comes back from the fab. Emulation or prototyping also
accelerate fast software ramp up and the software team can get a development platform ready well before the
actual chip is available. Emulation involves running test cases on hardware accelerated platforms like Palladium from
Cadence and Veloce from Mentor. For FPGA prototyping, Single or multiple FPGAsare used to build a PCB system
targeted for the testing of the ASIC/SoC. The ASIC code is then fully or partially programmed on the FPGA/s and
functionality can thus be tested.
The FPGA prototype platform does enable longer test time, but the debugging available is limited. The hardware
accelerators are costly, and investing in them makes sense if a company has lot of ASIC programs running
simultaneously.
To ensure that a bug free product reaches the customer is a complex activity and poses multiple challenges.
Coverage, legacy code, repeatability are issues that need to be tackled. Ensuring that the coverage is at an
acceptable level is important.
Code coverage is run to find out if all the possibilities of a written code are exercised in a test suite. Simulators from
cadence (ius), synopsys(vcs) and mentor (modelsim) have their own code coverage analyzers. Functional coverage
means to find out if each feature listed in the specification for an ASIC/SoC is verified. It is essential that the
functional specification document has an individual numbered paragraph for each feature so that traceability is
easier.
Functional coverage is an activity that needs planning, reviews and careful test case designing. Methodologies like
eRM (e reuse methodology Specman based) and OVM (open verification methodology System verilog based) do
assist checking functional coverage, but the inputs provided need careful specification and reviews.

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Savitribai Phule PUNE UNIVERSITY

ASIC Design (604202)

Miscellaneous Notes

Reviews, not just for coverage, but at every stage in the ASIC cycle are extremely important. One of the challenges
encountered while designing an ASIC is that the hardware team interprets a certain behavior from software and the
software expects that certain things are taken care of in hardware. It is very important to involve members from
design team, verification team, architecture team, software & firmware team for verification review.
Finally, while choosing the verification flow for a certain ASIC, team needs to look at what is available in terms of
resources as well as time, understand the end user requirement, and make a decision on which technique to employ
at what stage.

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