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7 Engineering Essentials
Here are seven critical design strategies and tips, for beginners and gurus alike, to help
ensure successful PCBs.
24
MAY 2016
ELECTRONIC DESIGN
between traces is
properly secured to
Callouts
the board substrate.
Fig. 1
Proper
clearance
Fig. 2
Copper sliver risk
Fig. 3
Copper sliver short
2. TRUST THE
RATS
NEST
Copper
origin
sliver risk
Sometimes Copper
it just seems
like the schematic is a waste of time
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25
Engineering Essentials
Ive used an autorouter (admittedly, a 2. A very narrow, sliverhigh-end one) on every board Ive done
shaped region, such
(10+ years). If you have constraints like:
as this example in the
only on this layer; these two signals form original design file, can
a differential pair; must match lengths
peel off uncontrolled
on these nets, then you must tell it about
during manufacture,
them. Just ask yourself this as you concreating shorts and
template using the autorouter: By the
yield issues.
time I get the autorouter constraints set
up for my board, perhaps even going
trace-by-trace setting constraints in my schematic, how much
could I have manually hand-routed?
Veteran designers put a great deal of emphasis on the initial
component placement, spending as much as half the design
time getting the component placement optimized for the following:
Routing simplicityminimize rats-nest crossovers, etc.
Part proximityshorter routes mean better routes.
On the Sunstone Circuits user forum, one poster writes,
Take more care of component placement. Place them in a way
where they are easier to route. Component placement is 70% of
the job. Place [all components] before starting to route a single
trace ... use the rats nest (the lines which indicate connections
which are not routed yet) as a rough guide [for tracing complexities.]
Old timers often use a hybrid approach to routinghandrouting the critical routes, then locking them down. Non-critical traces can then be handled by the autorouter, autorouting
regions of the design to help manage runaway conditions in
the routing algorithms. This can sometimes be a good compromise between the control of hand-routing and the speed of
auto-routing.
Copper sliver
risk
Copper sliver
risk
5. UH-OH, SLIVER!
26
MAY 2016
ELECTRONIC DESIGN
Engineering Essentials
create a situation in which every DRC passes and yet the board
is still unbuildable or non-functional. Ive seen this happen
before. The team is all happy because the board passes DRC
and yet the first articles literally go up in smoke on the test
bench. Tracing the failure took the team back to the CAD
tools constraint manager. The constraint manager does not
have a design conscience; it will let you do anything, no matter
how bad.
At Sunstone Circuits, for example, its an almost daily occurrence to receive a quote request for a board design that we
could easily build, except for a critical area in which design
tolerances and clearances were compressed dramatically. This
situation puts the PCB fabs, such as Sunstone, in the position
of delivering the bad news: either we cant build the board at
all because of the tolerances that are beyond our capabilities,
or we can build the boards but at an increased price and at
a riskier yield. These customers would have benefited from
designing with a specific manufacturer in mind.
Baker adds, If your layout software allows you to waive the
DRC violations, then use that feature with caution. It is so easy
to temporarily waive DRCs, meaning to get back to them later,
and then forget them. Remember to review all waived DRC
errors prior to sending your design for fabrication.
Bob Tise, veteran PCB designer currently on staff with Sunstone Circuits, offers a counterpoint. You could also just resist
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