Kỹ Thuật Siêu Cao Tần: Báo Cáo Thí Nghiệm

TRNG I HC BCH KHOA NNG
KHOA IN T VIN THNG
BO CO TH NGHIM
K THUT SIU CAO TN

LAB 3: Transients on Transmission Lines
Student
: Nguyn Th Bo Trm
Group
09A
Class
06DT1
Nng 2010
dddDDDASARTETE
Bo co TN SIU CAO TN
Lab3
1. Introduction:
We have thus far focused on techniques for understanding transmission lines under sinusoidal
excitation. Powerful analytic insight is available here, permitting straightforward design of
interesting circuits.
In contrast, the analysis of transients is generally more difficult and less amenable to simple
closed-form analysis, especially when loads are reactive. This laboratory will explore the propagation
of transients on transmission lines with the aid of numerical experiments in SPICE.
2. Purely Resistive Termination:
First, let's use SPICE to investigate the propagation of pulses on a transmission line terminated
by purely resistive loads.
2.1 A step function, matched load
First, create a 50 transmission line with total length (time delay) of 25 ns, and excite it with a
Thevenin source 10u(t), with a source resistance Rg = 50 . With the load resistance RL = 50 ,
run the simulation.
Rg
Vg
T1
Vsource
Vload
50
TD = 25ns
Z0 = 50
Vg
RL
50
To create the voltage source, use the VPWL source. Using VPWL allows various times and the
voltages at those times to be specified using the T1, T2, T3, ... and V1, V2, V3, ... parameters. The
voltage source will be piece-wise linear, connecting each specified point. Using VPULSE allows
specification of the initial voltage, V1, the voltage of the pulse, V2, the delay time, TD, the rise time,
TR, the fall time, TF, the pulse width, PW, and the period, PER.
The VPWL source is piece-wise linear and allows the user to specify voltages at specific times
using T1, T2, T3 and the corresponding V1, V2, V3 parameters. Please note that the source will
connect each specified point in the most direct way. Additionally, two voltages cannot be specified
for the same time, so that instantaneous changes must be approximated.
For Example: to specify a VPWL source that produces a 10V square pulse starting at t=0 and
lasting for 10 ns, would have the following specified parameters: T1=0, V1=0, T2=0.001n, V2=10,
T3=10n, V3=10, T4=10.001n, V4=0. (Making V3=0 would form a sawtooth wave because of the
reasons stated above.)
Nguyn Th Bo Trm 06DT1
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Using VPULSE allows specification of an initial voltage, V1, the voltage of the pulse, V2, the delay
time, TD, the rise time, TR, the fall time, TF, the pulse width, PW, and the period, PER. Single
pulses can be formed with this source. More complex signals can be formed by combining multiple
sources.
Problem 1 Plot the voltage at the source and load ends of the transmission line for t = 050 ns.
Using your understanding of bounce diagrams, explain whether this plot makes sense and shows
what you would expect to see in the exact answer. Do the two agree? If not, why not? A full
credit answer will describe the bounce diagram until a reasonable (whatever you consider
reasonable) number of bounces, which can explain what exactly is happening in this situation.
Please do the same in any other bounce diagram questions that may follow.
Answer:
-
The voltage at the source and load ends of the transmission line for t = 050 ns
10V
5V
0V
0s
V(VG)
5ns
10ns
15ns
V(VSOURCE)
V(VLOAD)
20ns
25ns
30ns
35ns
40ns
45ns
50ns
Time
The reflection coefficient at the source is:

=
0 50 50
=
=0
+ 0 50 + 50
The reflection coefficient at the load is:

=
0 50 50
=
=0
+ 0 50 + 50
There is no reflection wave of voltage at the source and the load.

=

10 .50
=
= 5()
+ 50 + 50
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VL = 5 (V) after 25ns (time delay of the transmission line.)

The theory and the plot are the same.
2.2 A step function, mismatched load
Now, change the load impedance in the previous case to 20 .
Rg
Vg
T1
Vsource
Vload
50
TD = 25ns
Z0 = 50
Vg
RL
20
Problem 2 Plot the voltage at the source and load ends of the transmission line for t = 0100
ns. Using your understanding of bounce diagrams, compare this with what you would expect to
see in the exact answer. Do the two agree? If not, why not? How long does it take the answer to
settle to the final answer?
Answer:
-
10V
5V
0V
0s
V(VG)
10ns
20ns
30ns
V(VSOURCE)
V(VLOAD)
40ns
50ns
60ns
70ns
80ns
90ns
100ns
Time
The reflection coefficient at the source is:

=
0 50 50
=
=0
+ 0 50 50
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The reflection coefficient at the load is:
RL Z 0 20 50
3
RL Z 0 20 50
7
V1
Vg Z 0
Rg Z 0
10.50
5(V )
50 50
At t = T = 25ns, the wave reaches the load (receiving end) z = l, and because L
mismatch generates a reflected wave with the amplitude:
V1 L .V1
3
0 , the
7
15
(V)
7
So the voltage on line (in this case, the load voltage) is the sum of two waves:
VL V1 V1 5
15 20
2.86(V )
7
7
At t = 2T = 50ns, the wave reaches the sending end z = 0, and because g 0 , there is no
reflection wave in form of a wave with voltage amplitude V2+ = 0. Thus, the voltage on line (in this
case, the source voltage) is:
VS V1 V1 5
15 20
2.86(V )
7
7
At t = 3T = 75ns, the wave reaches the load (receiving end) z = l, and because L
3
0 , the
7
mismatch generates a reflected wave with the amplitude: V2 L .V2 0 (V)

VL = 2.86 (V)
Similarly, we also have: VS = 2.86 (V)
z=l
z=0
t=0
V1+
T
t=0
L V1+
2T
L g V1+
3T
Thus, after 50ns, the voltage at two ends of the transmission line have the same final answers.
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2.3 A step function, mismatched load and source

Now, change the load impedance in the previous case to RL=20 , and change the source
impedance to Rg=200 .
Rg
Vg
T1
Vsource
Vload
200
TD = 25ns
Z0 = 50
Vg
RL
20
Problem 3 Plot the voltage at the source and load ends of the transmission line for t = 0300
ns. Using your understanding of bounce diagrams, compare this to the exact answer. Do the two
agree? If not, why not? How long does it take the answer to settle down to the final answer?
Answer:
-
12V
8V
4V
0V
0s
V(VG)
50ns
V(VSOURCE)
100ns
150ns
200ns
250ns
300ns
V(VLOAD)
Time
Rg Z 0
Rg Z 0
200 50
0.6
200 50
RL Z 0 20 50
3
RL Z 0 20 50
7
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V1
Vg Z 0
Rg Z 0
Lab3
10.50
2(V )
200 50
At t = T = 25ns, the wave reaches the load (receiving end) z = l, and because L
mismatch generates a reflected wave with the amplitude:
3
0 , the
7
3
6
V1 L .V1 ( ) .2 0.86 (V)
7
7
So the voltage on line (in this case, the load voltage) is the sum of two waves:
VL V1 V1 2
6 8
1.14(V )
7 7
At t = 2T = 50ns, the wave reaches the sending end z = 0, and because g 0.6 , there is a
reflection wave in form of a wave with voltage amplitude V2+ = gV1 . Thus, the voltage on line (in
this case, the source voltage) is:
VS V1 V1 V2 (1 L L g ).V1 0.63(V )
At t = 3T = 75ns, the wave reaches the load (receiving end) z = l, and because L
3
0 , the
7
mismatch generates a reflected wave with the amplitude: V2 L .V2 (V)

VL = 0.85 (V)
L
V1+
z=0
t=0
t=0
z=l
T
+
L V1
2T
L g V1+
3T
L
2
4T
+
g V1
L g V1+
2
5T
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Calculate like the process above, we have the table:

Time
t = 0ns
V at sending end
VS = V1
t = T =25ns
t = 2T = 50ns
VS = V1
Vg Z 0
Rg Z 0
Vg Z 0
Rg Z 0
10.50
2(V )
200 50
VL 0(V )
10.50
2(V )
200 50
VL V1 V1 2
6 8
1.14(V )
7 7
VL V1 V1 2
6 8
1.14(V )
7 7
VS V1 V1 V2
(1 L L g ).V1 0.63(V )
t = 3T=75ns
V at receiving end
VS V1 V1 V2
VL (1 L L g L2g ).V1 0.85(V )
(1 L L g ).V1 0.63(V )
t = 4T=100ns
VS (1 L L g L2g L2g2 ).V1 0.98(V )VL (1 L L g L2g ).V1 0.85(V )
t = 5T =125ns
VS (1 L L g L2 g
VL (1 L L g L2 g L2 g2
L2 g2 ).V1 0.98(V )
L3g2 ).V1 0.92(V )
T = 6T =150ns
VS = 0.98 (V)
VL = 0.924(V)
T = 7T =175ns
VS = 0.89(V)
VL = 0.924(V)
T = 8T =200ns
VS = 0.89(V)
VL = 0.909(V)
T = 9T =225ns
VS = 0.913(V)
VL = 0.909(V)
Thus, the plot and the exact answer agree.
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The final voltage is: V
Vg Z L
Rg Z 0
10.20
0.909(V )
200 20
It takes 225ns to settle down to the final answer.

2.4 A short pulse
Now break the transmission line into two equal pieces, with total length 25 ns (you should now have
two different transmission lines, both with the same 50 characteristic impedance, but each with a
time delay of only 12.5 ns). This permits us to sample inside the transmission line. With the same
transmission line, and Rg=200 and RL=20 apply a pulse of duration 10 ns to the transmission
line, namely vg(t) = 10(u(t)- u(t-10ns)).
Rg
Vg
T1
T2
Vsource
Vmiddle
Vload
200
Z0 = 50
TD = 12.5ns
Vg
Z0 = 50
TD = 12.5ns
RL
20
Problem 4 Plot the voltage at the source, middle, and load ends of the transmission lines for t =
0100 ns. Sketch the bounce diagram; do you understand the voltage plots? How long before the
ghost pulse (the pulse you are seeing at the middle of the transmission line) arrives at the load
end? How large is the ghost pulse?
Answer:
-
The voltage at the source, middle, and load ends of the transmission lines for t = 0100ns
2.0V
1.0V
0V
-1.0V
-2.0V
0s
10ns
V(VSOURCE)
20ns
V(VMIDDLE)
30ns
40ns
V(VLOAD)
50ns
60ns
70ns
80ns
90ns
100ns
Time
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L
V1
Rg Z 0
Rg Z 0
Lab3
200 50
0.6
200 50
RL Z 0 20 50
3
RL Z 0 20 50
7
Vg Z 0
Rg Z 0
10.50
2(V )
200 50
The bounce diagram:
z l
2
V1+
z=0
z=l
t=0
+
L V1
L g V1+
2T
3T
L
2
+
g V1
4T
L g V1+
2
5T
-
We have the table of values (by calculating):
Time
t = 0+ ns
t = T/2
=12.5ns
V at sending end
VS V1
Vg Z 0
Rg Z 0
Vg Z 0
2(V )
0.50
VS
0
Rg Z 0 200 50
V middle
V at receiving end
Vm = 0 (V)
VL = 0 (V)
Vm = V1+ (t = 0ns) =
2(V)
VL = 0 (V)
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t = T = 25ns
VS = 0(V)
t = 3T/2 =
37.5ns
VS = 0(V)
t = 2T = 50ns
VS V1 V2
Lab3
Vm = VS (t = 12.5ns) =
0(V)
VL V1 V1
Vm V1 LV1
VL Vm Vm
6
0.86(V )
7
0(V )
Vm VL 0(V )
VL = 0 (V)
Vm V2 L gV1
VL = 0 (V)
6 8
1.14(V )
7 7
(Vm at t = 2T)
(L L g ).V1
1.37(V )
t = 5T/2 =
62.5ns
VS
t = 3T=75ns
Vg Z 0
Rg Z 0
0.50
0(V )
200 50
VS = 0(V)
t=
7T/2=82.5ns
VS = 0(V)
t = 4T =100ns
VS V2 V3
3
0.6 2 0.51(V )
7
Vm = VS (t = 12.5ns) =
0(V)
VL V2 V2
Vm V2 L gV1
VL = 0 (V)
(L g L2 g ).V1 0.29(V )
0.22(V )
Vm VL 0(V )
VL = 0 (V)
(L2 g L2 g2 ).V1
0.35(V )
It takes 12.5ns for the ghost pulse to get the load end. The ghost pulse has width of
12.5ns.
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2.5 A longer pulse

In the previous problem, the pulse was brief (10 ns) compared to the length of the transmission line
(25 ns). Now investigate a more complicated system.
Problem 5
Using the same transmission line and source impedance, define a new source for
which vg = +10 V for t = 0 20 ns, and vg V for t = 20 40ns. Plot the voltage at the
source, center, and load end of the transmission line for t = 0100 ns. Is the transition from high
to low perfectly clear at the load end?
Answer:
Rg
Vg
T1
T2
Vsource
Vmiddle
Vload
200
Z0 = 50
TD = 12.5ns
Vg
Z0 = 50
TD = 12.5ns
RL
20
The voltage at the source, center, and load end of the transmission line for t = 0100ns
2.0V
0V
-2.0V
-4.0V
0s
10ns
V(VSOURCE)
20ns
V(VMIDDLE)
30ns
40ns
V(VLOAD)
50ns
60ns
70ns
80ns
90ns
100ns
Time
From the graph, we can see that the transition from high to low is perfectly clear at the load
end.
2.6 An Impedance Bump

Transmission lines must be protected against damage, or their impedance properties could be
compromised. In this section well damage the transmission line by putting a weak load in the
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middle. In particular, at the center of the transmission line, add a shunt resistance of 50 (a shunt
resistance connects the node at the middle to ground).
Rg
Vg
T1
T2
Vsource
Vmiddle
Vload
200
Z0 = 50
TD = 12.5ns
Vg
Z0 = 50
TD = 12.5ns
Rshunt
RL
20
50
Problem 6 With the shunt resistance in place, repeat the previous problem. How did the
presence of the bump (break in the transition line) affect the voltage plots? Did any new ghosts
show up? Looking only at the source and end voltages, could you determine where the bump is?
Can you explain what you see in terms of a bounce diagram?
Answer:
2.0V
0V
-2.0V
-4.0V
0s
10ns
V(VSOURCE)
20ns
V(VMIDDLE)
30ns
40ns
V(VLOAD)
50ns
60ns
70ns
80ns
90ns
100ns
Time
The presence of the impedance bump (break in the transition line) reduced the magnitude
of the middle voltage.
3. Reactive Termination
As mentioned in class, it is frequently the case that the loads at the end of a data bus are reactive
(and often capacitive).
3.1 A step into a capacitive load
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For this exercise, again form a circuit with a source vg(t) = 10u(t), a source impedance Rg=25 ,
and a transmission line with characteristic impedance 50 and length 25ns.
Rg
Vg
T1
Vsource
Vg
Vload
25
TD = 25ns
Z0 = 50
CL
1n
Problem 7 Terminate the transmission line with a 1nF capacitor. Plot the voltage at the source
and load ends of the transmission line for t = 0400ns. If you see any exponential charging or
discharging, estimate the time constant, and solve for the R. You may use the following formulas.
15V
10V
5V
0V
0s
50ns
100ns
V(VSOURCE)
V(VLOAD)
150ns
200ns
250ns
300ns
350ns
400ns
Time
Vinitial = 0V
VFinal = 12.133V
V(t) = 8.4292V
t
= (75 25) = 50ns
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()

50. 109
= 4.214. 108
8.4292 12.133
0 12.133
4.214. 108
=
= 42.14()
109
Repeat the previous problem, but with a load capacitance of 100pF.
= =
Problem 8
Rg
T1
Vsource
Vg
Vload
25
Vg
TD = 25ns
Z0 = 50
CL
100pF
15V
10V
5V
0V
0s
50ns
100ns
V(VSOURCE)
V(VLOAD)
150ns
200ns
250ns
300ns
350ns
400ns
Time
Vinitial = 0V
VFinal = 13.33V
V(t) = 13.244V
t
= (50 25) = 25ns
25. 109
=
=
= 4.956. 109
()
13.244 13.33

0 13.33

9
= =
4.956. 10
=
= 49.56()
100.1012
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Problem 9
Lab3
Repeat the previous problem, but with a load capacitance of 10nF.

Rg
T1
Vsource
Vg
Vload
25
Vg
TD = 25ns
Z0 = 50
CL
10nF
10V
5V
0V
0s
50ns
100ns
V(VSOURCE)
V(VLOAD)
150ns
200ns
250ns
300ns
350ns
400ns
Time
Vinitial = 0V
VFinal = 10V
V(t) = 8.056V
t
= (400 25)= 375ns
375. 109
=
=
= 2.29. 107
()
8.056 10

0 10

7
2.29. 10
= = =
= 22.9()
10.109
Problem 10 Repeat the previous problem, but with a load inductance of 2.5H.
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Rg
T1
Vsource
Vg
Vload
1
25
Vg
TD = 25ns
Z0 = 50
2.5uH
0
2
15V
10V
5V
0V
0s
50ns
100ns
V(VSOURCE)
V(VLOAD)
150ns
200ns
250ns
300ns
350ns
400ns
Time
Vinitial = 13.202V
VFinal = 0V
V(t) = 4.8052V
t
= (75 25) = 50ns
50. 109
=
=
= 4.947. 108
()
4.8052 0
13.202 0

6
2.5. 10
= =
= 50.53()
4.947. 108
Problem 11 Repeat the previous problem, but with a load inductance of 0.25H.
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Rg
T1
Vsource
Vg
Vload
1
25
Vg
TD = 25ns
Z0 = 50
0.25uH
0
2
15V
10V
5V
0V
-5V
0s
50ns
100ns
V(VSOURCE)
V(VLOAD)
150ns
200ns
250ns
300ns
350ns
400ns
Time
Vinitial = 13.3V
VFinal = 0V
V(t) = 1.51V
t
= (36 25)ns
11. 109
=
=
= 5.056. 109
()
1.51 0
13.3 0

6
0.25. 10
=
= =
= 49.44()
5.056. 109
Problem 12 Repeat the previous problem, but with a load composed of a parallel combination of
RL=1000 , L = 1H and C = 100pF.
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Rg
Vg
T1
Vsource
Vg
Vload
1
25
TD = 25ns
Z0 = 50
RL
1k
1uH
100pF
0
2
10V
5V
0V
-5V
0s
50ns
100ns
V(VSOURCE)
V(VLOAD)
150ns
200ns
250ns
300ns
350ns
400ns
Time
Problem 13 How important is the value of Rg in these exercises?

Answer:
-
R is very important since it allows the system to reach steady state. The value of R helps us
g
to determine whether the circuit is matched or not at the input of transmission line.
4. Coupling
Many data buses are in parallel, in close proximity, such as the 32 bit and 64 bit buses found in
computers. These transmission lines will have mutual impedance which causes signals on one
transmission line to show up on another one.
In EE571 students analyze this coupling in great detail, but we can simulate a simplified model of a
two-wire data bus using SPICE1:
Note that your SPICE library contains a model for coupled lines; you could use this, but it does the modeling with an
explicit form of the Telegraphers Equation, and is painfully slow. I tried to use it, but realized that it would take about
one day to run every simulation!
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Here T1 and T4 represent the actual transmission lines, while T2 and T3 represent the cross
coupling. The coupling is slightly faster (95 ns instead of 100 ns) and has a higher characteristic
impedance.
Connect a Thevenin signal pulse (10 V, 50 ) to A and 50 loads to B, C and D2.
Z0 = 50
TD = 100ns
T1
A
R1
50
R3
Vg
Vg
50
Z0 = 200
TD = 95ns
T2
0
Z0 = 200
TD = 95ns
T3
0
Z0 = 50
TD = 100ns
T4
R4
R2
50
50
0
0
To make this model even closer to the real thing, the signal injected into T2 should have opposite sign of that injected
into T1. However, this lab will not require this.
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4.1 A simple pulse

Inject a 10ns pulse with the Thevenin source at A. Use a rise and fall time of 1ns.
Problem 14 Simulate the problem for 250 ns, and plot the voltage at A, B, C, and D. Describe
what you observe. How big is the VC compared to VD when the pulse arrives?
Which arrives first?
Answer:
-
Plot the voltage at A, B, C, and D
10V
5V
0V
-5V
0s
V(VG)
V(A)
50ns
V(B)
100ns
V(C)
150ns
200ns
250ns
V(D)
Time
V is about 4 times compared to the magnitude of V when the pulse arrives.
V arrives first.
Problem 15 When does a signal arrive at B? If you change the values of the load resistances at C
and D, can you eliminate the reflection? If so what value should the load have?
Answer:
-
A signal arrives at B at 195ns.

We cannot eliminate the reflection by changing the values of the load resistances at C and
D. We just can reduce VC and VD to zero.
The plot when the load resistances at C and D are 0.001:
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10V
5V
0V
-5V
0s
V(VG)
V(A)
50ns
V(B)
100ns
V(C)
150ns
200ns
250ns
V(D)
Time
5. Impedance Matching
5.1. Pre-lab Assignment
5.1. A. Design a quarter-wave transformer to match a 150 load to a source resistance of 75 .
State the length of your transmission line(s) in terms of the wavelength.
Answer:
= 150
= 75
The input impedance is:
= Z0
With
ZL + jZ0 tgl
Z0 + jZL tgl
= 4 =
2
.
4
We can divide the numerator and the denominator by tgl and take the limit as l
to get:
0 2
The characteristic impedance of the matching section is:

0 =
. = 150.75 = 106.066()
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5.1. B. Using the Smith Chart, if the characteristic impedance is given as 75 , design a stubmatching network to match a 150 load to a 75 source. Do this for both a shorted and an open
circuited stub. State the length of your transmission line(s) in terms of wavelength.
Answer:
0 = 75
= 75
= 150
ZL
The normalized load impedance is: =
Construct the appropriate SWR circle through point A. From the Smith chart, the normal load
admittance: yL = 0.5 (at point B l 0 )
The SWR circle intersects the 1+jb circle at two points, denoted as y1 , y2. Thus the distance
d, from the load to the stub, is given by either of these two intersections. Reading the WTG
scale, we obtain:
d2 = (0.348 0) = 0.348
At the two intersection points, the normalized admittances are:
y1 = 1 + j0.7
y2 = 1 j0.7
Thus, the first tuning solution requires a stub with a susceptance of j0.7. The length of an
open-circuited stub that gives this susceptance can be found on Smith chart by starting at y
= 0 (the open circuit) and moving along the outer edge of the chart (g=0) toward the
generator to the j0.7 point. The length is then:
lo1= 0.402
Similarly, the required open-circuited stub length for the second solution is:
lo2= 0.097
The length of an shorted-circuited stub that gives this susceptance can be found on Smith
chart by starting at y = (the shorted circuit) and moving along the outer edge of the chart
(g=0) toward the generator to the j0.7 point. The length is then:
ls1=(0.402 0.25) = 0.152
Similarly, the required shorted-circuited stub length for the second solution is:
ls2= (0.25 + 0.097) = 0.347
Z0
150
75
= 2 (point A on the Smith chart)
5.2. Lab Assignment

5.2.A. Find the actual length of the quarter-wave matching network you designed in part 5.1.A if up
= 2E+8 (m/s) and frequency = 1 GHz. Simulate the frequency response of the circuit by sweeping
the frequency from 1 MHz to 3 GHz using a 5Vpp sine wave source with a source resistance of 75 .
Plot the input and load voltage over frequency. Plot the magnitude of the reflection coefficient of
Page 23
Bo co TN SIU CAO TN
Lab3
the matching network and find the bandwidth where || is less than 0.2.
impedance of the matching network at 1 GHz?
What is the input
Answer:
up = 2.108
m
;
s
f = 1GHz
2.108

0.2(m)
f
10 9
up
TD
0.2
0.05 (m)
4
l
0.05 m
2.5.10 10 ( s) 0.25ns
8
u p 2.10 m / s
Rs
T1
Vload
Vinput
Vs
75
2.5Vac
0Vdc
TD = 0.25ns
Z0 = 106.066
RL
150
0
0
-
0
0
The input and load voltage over frequency:
Page 24
Bo co TN SIU CAO TN
Lab3
1.8V
1.6V
1.4V
1.2V
1.0MHz
3.0MHz
10MHz
V(VINPUT)
V(VLOAD)
30MHz
100MHz
300MHz
1.0GHz
3.0GHz
10GHz
Frequency
The magnitude of the reflection coefficient of the matching network:

400m
300m
200m
100m
0
1.0MHz
3.0MHz
10MHz
30MHz
(V(VINPUT)/ I(Rs)-75)/(V(VINPUT)/I(Rs)+75)
100MHz
300MHz
1.0GHz
3.0GHz
10GHz
Frequency
|| is less than 0.2 from 608.1 MHz to 1.388 GHz and frequencies from 2.607 GHz to 3 GHz
- The input impedance of the matching network at 1 GHz is 75.
Page 25
Bo co TN SIU CAO TN
Lab3
150
100
(1.0000G,75.000)
50
1.0MHz
3.0MHz
V(VINPUT)/ I(Rs)
10MHz
30MHz
100MHz
300MHz
1.0GHz
3.0GHz
10GHz
Frequency
5.2.B. Using the assumptions of section 5.2.A, simulate your pre-lab design in part 5.1.B and find
the bandwidth (the portion of the signal less than 0.2) of the matching network as well as the
input impedance at 1 GHz. Include the same plots as in section 5.2.A.
Answer:
up = 2.108
up
f
m
;
s
f = 1GHz
2.108
0.2(m)
10 9
d1 =0.152 = 0.1520.2 = 0.0304 (m) TD
d1 0.0304 m
1.52.10 10 ( s) 0.152ns
u p 2.108 m / s
lo1= 0.402 = 0.4020.2 = 0.0804 (m) TD
l o1 0.0804 m
4.02.10 10 ( s) 0.402ns
u p 2.108 m / s
ls1=0.152 = 0.1520.2 = 0.0304 (m) TD
l s1 0.0304 m
1.52.10 10 ( s) 0.152ns
u p 2.108 m / s
Open-circuited stub:
Page 26
Bo co TN SIU CAO TN
Lab3
Rs
T1
Vload
Vinput
Vs
75
2.5Vac
0Vdc
TD = 0.152ns
Z0 = 75
RL
150
0
T2
TD = 0.402ns
Z0 = 75
0
-
R1
1000G
2.0V
1.5V
1.0V
0.5V
0V
1.0MHz
3.0MHz
10MHz
V(VINPUT)
V(VLOAD)
30MHz
100MHz
300MHz
1.0GHz
3.0GHz
10GHz
Frequency

|| is less than 0.2 from 924 MHz to 1.11 GHz.
Page 27
Bo co TN SIU CAO TN
Lab3
1.0
0.5
0
1.0MHz
3.0MHz
10MHz
30MHz
(V(VINPUT)/I(Rs)-75)/(V(VINPUT)/I(Rs)+75)
100MHz
300MHz
1.0GHz
3.0GHz
10GHz
3.0GHz
10GHz
Frequency
The input impedance of the matching network at 1 GHz is 75.029.
150
100
(1.0000G,75.029)
50
0
1.0MHz
3.0MHz
V(VINPUT)/ I(Rs)
10MHz
30MHz
100MHz
300MHz
1.0GHz
Frequency
Shorted-circuited stub:
Page 28
Bo co TN SIU CAO TN
Lab3
Rs
T1
Vload
Vinput
Vs
75
2.5Vac
0Vdc
TD = 0.152ns
Z0 = 75
RL
150
0
T2
TD = 0.152ns
Z0 = 75
0
-
0
0
2.0V
1.5V
1.0V
0.5V
0V
1.0MHz
3.0MHz
10MHz
V(VINPUT)
V(VLOAD)
30MHz
100MHz
300MHz
1.0GHz
3.0GHz
10GHz
Frequency
Page 29
Bo co TN SIU CAO TN
Lab3
|| is less than 0.2 from 850 MHz to 1.21 GHz and from 2.07 GHz to 2.44 GHz
1.0
0.5
0
1.0MHz
3.0MHz
10MHz
30MHz
(V(VINPUT)/I(Rs)-75)/(V(VINPUT)/I(Rs)+75)
100MHz
300MHz
1.0GHz
3.0GHz
10GHz
3.0GHz
10GHz
Frequency
The input impedance of the matching network at 1 GHz is 75.029.
100
(1.0000G,75.029)
50
0
1.0MHz
3.0MHz
V(VINPUT)/ I(Rs)
10MHz
30MHz
100MHz
300MHz
1.0GHz
Frequency
Problem 16 Compare the results for the matching networks that you designed in the lab (quarter
wave, open and short stub). Which one is a better choice. Why?
Answer:
- Compare the results for the matching networks that we designed in the lab (quarter wave,
open and short stub), the quarter wave is the best choice among of these. Because: it has
the largest bandwidth (the portion of the signal less than 0.2) about 1.102GHz while the
open and short stubs are quite less than 1.0GHz. Besides, it also has an input impedance of
exactly 75 ohms.
Page 30
Bo co TN SIU CAO TN
Problem 17
shorted stub.
Lab3
For stub matching networks compare the performance of an open stub versus a
Answer:
- For stub matching networks compare the performance of an open stub versus a shorted
stub: bandwidth (the portion of the signal less than 0.2) about 0.186GHz and 0.73GHz
respectively. So the shorted stub circuit is the better one.
Problem 18 Suppose you had a lossless line terminated by a complex load, but wanted to carry
out the match using a quarter-wave transformer. How could you accomplish this?
Answer:
-
Suppose we had a lossless line terminated by a complex load, but wanted to carry out the
match using a quarter-wave transformer. To accomplish this we could use a transmission
line with a complex characteristic impedance.
Page 31

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TRNG I HC BCH KHOA NNG

KHOA IN T VIN THNG

K THUT SIU CAO TN

The reflection coefficient at the source is:

The reflection coefficient at the load is:

There is no reflection wave of voltage at the source and the load.

VL = 5 (V) after 25ns (time delay of the transmission line.)

The reflection coefficient at the source is:

The reflection coefficient at the load is:

mismatch generates a reflected wave with the amplitude: V2 L .V2 0 (V)

2.3 A step function, mismatched load and source

Nguyn Th Bo Trm 06DT1

this case, the source voltage) is:

mismatch generates a reflected wave with the amplitude: V2 L .V2 (V)

Nguyn Th Bo Trm 06DT1

Calculate like the process above, we have the table:

VL (1 L L g L2g ).V1 0.85(V )

VS (1 L L g L2g L2g2 ).V1 0.98(V )VL (1 L L g L2g ).V1 0.85(V )

L3g2 ).V1 0.92(V )

Thus, the plot and the exact answer agree.

Nguyn Th Bo Trm 06DT1

The final voltage is: V

It takes 225ns to settle down to the final answer.

Nguyn Th Bo Trm 06DT1

The bounce diagram:

We have the table of values (by calculating):

Nguyn Th Bo Trm 06DT1

Nguyn Th Bo Trm 06DT1

2.5 A longer pulse

2.6 An Impedance Bump

Nguyn Th Bo Trm 06DT1

Nguyn Th Bo Trm 06DT1

Repeat the previous problem, but with a load capacitance of 10nF.

Nguyn Th Bo Trm 06DT1

Nguyn Th Bo Trm 06DT1

Nguyn Th Bo Trm 06DT1

Problem 13 How important is the value of Rg in these exercises?

Nguyn Th Bo Trm 06DT1

Nguyn Th Bo Trm 06DT1

4.1 A simple pulse

Plot the voltage at A, B, C, and D

V is about 4 times compared to the magnitude of V when the pulse arrives.

A signal arrives at B at 195ns.

Nguyn Th Bo Trm 06DT1

The characteristic impedance of the matching section is:

Nguyn Th Bo Trm 06DT1

The normalized load impedance is: =

= 2 (point A on the Smith chart)

5.2. Lab Assignment

Nguyn Th Bo Trm 06DT1

What is the input

The input and load voltage over frequency:

Nguyn Th Bo Trm 06DT1

The magnitude of the reflection coefficient of the matching network:

Nguyn Th Bo Trm 06DT1

d1 =0.152 = 0.1520.2 = 0.0304 (m) TD

lo1= 0.402 = 0.4020.2 = 0.0804 (m) TD

ls1=0.152 = 0.1520.2 = 0.0304 (m) TD

Nguyn Th Bo Trm 06DT1

The input and load voltage over frequency:

The magnitude of the reflection coefficient of the matching network:

Nguyn Th Bo Trm 06DT1